diff --git a/.travis/script.sh b/.travis/script.sh
index d6060b13f..6a852a8b4 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -75,4 +75,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/regis
 echo -e "Testing Verilog generation with scan chain across an FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/scan_chain --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with routing mutliplexers implemented by tree structure";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/tree_structure --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing mutliplexers implemented by standard cell MUX2";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/stdcell_mux2 --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
index 59f493a13..660e9f003 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
@@ -82,13 +82,13 @@
          If your standard cell provider does not offer the exact truth table,
          you can simply swap the inputs as shown in the example below
       -->
-    <circuit_model type="gate" name="stdcell_mux2" prefix="stdcell_mux2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sc_mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sc_mux2.v">
+    <circuit_model type="gate" name="MUX2" prefix="MUX2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mux2.v">
       <design_technology type="cmos" topology="MUX2"/>
       <input_buffer exist="false"/>
       <output_buffer exist="false"/>
       <port type="input" prefix="in0" lib_name="B" size="1"/>
       <port type="input" prefix="in1" lib_name="A" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
+      <port type="input" prefix="sel" lib_name="S0" size="1"/>
       <port type="output" prefix="out" lib_name="Y" size="1"/>
     </circuit_model>
     <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
@@ -111,7 +111,7 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
@@ -120,7 +120,7 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
@@ -143,7 +143,7 @@
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
       <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
       <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
       <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
       <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
new file mode 100644
index 000000000..6ad9d0db0
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
new file mode 100644
index 000000000..658e328c0
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=