diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 617dcd952..2443abf5c 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -398,7 +398,7 @@ static void print_verilog_top_testbench_global_config_done_ports_stimuli(
                                                            module_global_port));
 
     BasicPort stimuli_config_done_port(
-      std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
+      std::string(TOP_TB_CONFIG_ALL_DONE_PORT_NAME), 1);
     /* Wire the port to the input stimuli:
      * The wiring will be inverted if the default value of the global port is 1
      * Otherwise, the wiring will not be inverted!
@@ -1695,8 +1695,15 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
   } else {
     VTR_ASSERT(num_prog_clocks > 1);
     for (size_t iclk = 0; iclk < num_prog_clocks; ++iclk) {
+      std::vector<size_t> curr_clk_ctrl_regions =
+        config_protocol.prog_clock_pin_ccff_head_indices(
+          config_protocol.prog_clock_pins()[iclk]);
+      size_t curr_regional_bitstream_max_size =
+        find_fabric_regional_bitstream_max_size(fabric_bitstream,
+                                                curr_clk_ctrl_regions);
       fp << "\t";
-      fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << iclk << " <= 0";
+      fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << iclk << " <= "
+         << regional_bitstream_max_size - curr_regional_bitstream_max_size;
       fp << ";";
       fp << std::endl;
     }
@@ -1905,9 +1912,12 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
   } else {
     VTR_ASSERT(num_prog_clocks > 1);
     for (size_t iclk = 0; iclk < num_prog_clocks; ++iclk) {
+      BasicPort curr_prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME),
+                                     iclk, iclk);
       fp << "always";
       fp << " @(negedge "
-         << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ")";
+         << generate_verilog_port(VERILOG_PORT_CONKT, curr_prog_clock_port)
+         << ")";
       fp << " begin";
       fp << std::endl;
 
diff --git a/openfpga/src/utils/fabric_bitstream_utils.cpp b/openfpga/src/utils/fabric_bitstream_utils.cpp
index d26eff686..eab11cb23 100644
--- a/openfpga/src/utils/fabric_bitstream_utils.cpp
+++ b/openfpga/src/utils/fabric_bitstream_utils.cpp
@@ -33,7 +33,7 @@ size_t find_fabric_regional_bitstream_max_size(
   for (const auto& region : fabric_bitstream.regions()) {
     if (!region_whitelist.empty() &&
         (std::find(region_whitelist.begin(), region_whitelist.end(),
-                   size_t(region)) != region_whitelist.end())) {
+                   size_t(region)) == region_whitelist.end())) {
       continue;
     }
     if (regional_bitstream_max_size <
@@ -65,7 +65,7 @@ size_t find_configuration_chain_fabric_bitstream_size_to_be_skipped(
   for (const auto& region : fabric_bitstream.regions()) {
     if (!region_whitelist.empty() &&
         (std::find(region_whitelist.begin(), region_whitelist.end(),
-                   size_t(region)) != region_whitelist.end())) {
+                   size_t(region)) == region_whitelist.end())) {
       continue;
     }
     size_t curr_region_num_bits_to_skip = 0;