riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

minor tuning on ini compilation

This commit is contained in:
tangxifan 2019-11-01 20:51:49 -06:00
parent a9c02cd2a5
commit f70f387f9f
3 changed files with 17 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
libs/external/libini/CMakeLists.txt vendored
View File

@ -8,5 +8,6 @@ files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
#Create the library #Create the library
add_library(libini STATIC add_library(libini STATIC
${LIB_HEADERS}) ${LIB_HEADERS})
target_include_directories(libini PUBLIC ${LIB_INCLUDE_DIRS}) target_include_directories(libini PUBLIC ${LIB_INCLUDE_DIRS})
set_target_properties(libini PROPERTIES PREFIX "" LINKER_LANGUAGE CXX) set_target_properties(libini PROPERTIES PREFIX "" LINKER_LANGUAGE CXX)

14
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp
View File

@ -22,13 +22,13 @@
* Top-level function to write an ini file which contains exchangeable * Top-level function to write an ini file which contains exchangeable
* information, in order to interface different Verilog simulators * information, in order to interface different Verilog simulators
********************************************************************/ ********************************************************************/
void print_verilog_simulation_info(const int &num_operating_clock_cycles, void print_verilog_simulation_info(const int& num_operating_clock_cycles,
const std::string &verilog_dir_formatted, const std::string& verilog_dir_formatted,
const std::string &chomped_circuit_name, const std::string& chomped_circuit_name,
const std::string &src_dir_path, const std::string& src_dir_path,
const size_t &num_program_clock_cycles, const size_t& num_program_clock_cycles,
const float &prog_clock_freq, const float& prog_clock_freq,
const float &op_clock_freq) { const float& op_clock_freq) {
mINI::INIStructure ini; mINI::INIStructure ini;
// std::map<char, int> units_map; // std::map<char, int> units_map;
// units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6;

14
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h
View File

@ -3,11 +3,11 @@
#include <string> #include <string>
void print_verilog_simulation_info(const int &num_operating_clock_cycles, void print_verilog_simulation_info(const int& num_operating_clock_cycles,
const std::string &verilog_dir_formatted, const std::string& verilog_dir_formatted,
const std::string &chomped_circuit_name, const std::string& chomped_circuit_name,
const std::string &src_dir_path, const std::string& src_dir_path,
const size_t &num_program_clock_cycles, const size_t& num_program_clock_cycles,
const float &prog_clock_freq, const float& prog_clock_freq,
const float &op_clock_freq); const float& op_clock_freq);
#endif #endif