From f6cea1e17c7b364e5c61908c993b947e5ad4713f Mon Sep 17 00:00:00 2001 From: CHARAS SAMY Date: Fri, 1 May 2020 10:55:23 -0600 Subject: [PATCH] Added test_mode_low benchmark --- .../test_mode_low/test_mode_low.act | 23 ++++++++ .../test_mode_low/test_mode_low.blif | 35 +++++++++++++ .../test_mode_low/test_mode_low.v | 52 +++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act create mode 100644 openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif create mode 100644 openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act new file mode 100644 index 000000000..44920c540 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act @@ -0,0 +1,23 @@ +a 0.5 0.2 +b 0.5 0.2 +clk 0.5 0.2 +out_0 0.5 0.2 +out_1 0.5 0.2 +out_2 0.5 0.2 +out_3 0.5 0.2 +sum_0 0.5 0.2 +sum_1 0.5 0.2 +sum_2 0.5 0.2 +sum_3 0.5 0.2 +sum_4 0.5 0.2 +sum_5 0.5 0.2 +sum_6 0.5 0.2 +sum_7 0.5 0.2 +pipe_a_0 0.5 0.2 +pipe_a_1 0.5 0.2 +pipe_b_0 0.5 0.2 +pipe_b_1 0.5 0.2 +pipe_sum_0 0.5 0.2 +pipe_sum_1 0.5 0.2 +pipe_sum_2 0.5 0.2 +pipe_sum_3 0.5 0.2 diff --git a/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif new file mode 100644 index 000000000..fd6a62c17 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif @@ -0,0 +1,35 @@ +.model test_mode_low +.inputs a b clk +.outputs out_0 out_1 out_2 out_3 + +#.subckt shift D=a clk=clk Q=pipe_a_0 +#.subckt shift D=pipe_a_0 clk=clk Q=pipe_a_1 +#.subckt shift D=b clk=clk Q=pipe_b_0 +#.subckt shift D=pipe_b_0 clk=clk Q=pipe_b_1 + + +.latch a pipe_a_0 re clk 0 +.latch pipe_a_0 pipe_a_1 re clk 0 +.latch b pipe_b_0 re clk 0 +.latch pipe_b_0 pipe_b_1 re clk 0 + +.latch sum_0 pipe_sum_0 re clk 0 +.latch sum_2 pipe_sum_1 re clk 0 +.latch sum_4 pipe_sum_2 re clk 0 +.latch sum_6 pipe_sum_3 re clk 0 + +.subckt adder a=pipe_a_1 b=pipe_b_1 cin=pipe_sum_3 cout=sum_1 sumout=sum_0 +.subckt adder a=pipe_sum_0 b=pipe_sum_2 cin=sum_1 cout=sum_3 sumout=sum_2 +.subckt adder a=pipe_sum_1 b=pipe_sum_3 cin=sum_3 cout=sum_5 sumout=sum_4 +.subckt adder a=pipe_sum_2 b=pipe_sum_0 cin=sum_5 cout=sum_7 sumout=sum_6 + +.names pipe_sum_0 out_0 +1 1 +.names pipe_sum_1 out_1 +1 1 +.names pipe_sum_2 out_2 +1 1 +.names pipe_sum_3 out_3 +1 1 + +.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v new file mode 100644 index 000000000..ac34e62f3 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v @@ -0,0 +1,52 @@ +////////////////////////////////////// +// // +// 2x2 Test-modes Low density // +// // +////////////////////////////////////// + + +module test_mode_low ( + a, + b, + clk, + reset, + out ); + + input wire a; + input wire b; + input wire clk; + input wire reset; + output wire[3:0] out; + + reg[1:0] pipe_a; + reg[1:0] pipe_b; + reg[3:0] pipe_sum; + wire[7:0] sum; + + assign sum[1:0] = pipe_a[1] + pipe_b[1] + pipe_sum[3]; + assign sum[3:2] = pipe_sum[0] + sum[1] + pipe_sum[2]; + assign sum[5:4] = pipe_sum[1] + sum[3] + pipe_sum[3]; + assign sum[7:6] = pipe_sum[2] + sum[5] + pipe_sum[0]; + assign out = pipe_sum; + + initial begin + pipe_a <= 2'b00; + pipe_b <= 2'b00; + pipe_sum <= 4'b0000; + end + + always @(posedge clk or posedge reset) begin + if(reset) begin + pipe_a <= 2'b00; + pipe_b <= 2'b00; + pipe_sum <= 4'b0000; + end else begin + pipe_a[0] <= a; + pipe_a[1] <= pipe_a[0]; + pipe_b[0] <= b; + pipe_b[1] <= pipe_b[0]; + pipe_sum <= {sum[6], sum[4], sum[2], sum[0]}; + end + end + +endmodule