From f6b645fd259586840c8571e160ebb020adfa05a7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 18 Sep 2024 17:44:55 -0700 Subject: [PATCH] [core] code format --- libs/libarchopenfpga/src/circuit_library.cpp | 4 +- libs/libarchopenfpga/src/circuit_library.h | 14 ++-- .../src/read_xml_circuit_library.cpp | 15 ++-- .../src/write_xml_circuit_library.cpp | 4 +- openfpga/src/fabric/build_mux_modules.cpp | 68 +++++++++++-------- 5 files changed, 63 insertions(+), 42 deletions(-) diff --git a/libs/libarchopenfpga/src/circuit_library.cpp b/libs/libarchopenfpga/src/circuit_library.cpp index e39366aec..28c00aa7b 100644 --- a/libs/libarchopenfpga/src/circuit_library.cpp +++ b/libs/libarchopenfpga/src/circuit_library.cpp @@ -1530,8 +1530,8 @@ void CircuitLibrary::set_model_pass_gate_logic(const CircuitModelId& model_id, } /* Set pass-gate logic information of a circuit model */ -void CircuitLibrary::set_model_last_stage_pass_gate_logic(const CircuitModelId& model_id, - const std::string& model_name) { +void CircuitLibrary::set_model_last_stage_pass_gate_logic( + const CircuitModelId& model_id, const std::string& model_name) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); last_stage_pass_gate_logic_model_names_[model_id] = model_name; diff --git a/libs/libarchopenfpga/src/circuit_library.h b/libs/libarchopenfpga/src/circuit_library.h index 58824d8da..2c511d59c 100644 --- a/libs/libarchopenfpga/src/circuit_library.h +++ b/libs/libarchopenfpga/src/circuit_library.h @@ -272,9 +272,11 @@ class CircuitLibrary { const CircuitModelId& model_id) const; /* Pass-gate-logic information */ CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const; - CircuitModelId last_stage_pass_gate_logic_model(const CircuitModelId& model_id) const; + CircuitModelId last_stage_pass_gate_logic_model( + const CircuitModelId& model_id) const; std::string pass_gate_logic_model_name(const CircuitModelId& model_id) const; - std::string last_stage_pass_gate_logic_model_name(const CircuitModelId& model_id) const; + std::string last_stage_pass_gate_logic_model_name( + const CircuitModelId& model_id) const; enum e_circuit_model_pass_gate_logic_type pass_gate_logic_type( const CircuitModelId& model_id) const; float pass_gate_logic_pmos_size(const CircuitModelId& model_id) const; @@ -451,7 +453,7 @@ class CircuitLibrary { void set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name); void set_model_last_stage_pass_gate_logic(const CircuitModelId& model_id, - const std::string& model_name); + const std::string& model_name); /* Port information */ CircuitPortId add_model_port(const CircuitModelId& model_id, const enum e_circuit_model_port_type& port_type); @@ -668,8 +670,10 @@ class CircuitLibrary { /* Pass-gate-related parameters */ vtr::vector pass_gate_logic_model_names_; vtr::vector pass_gate_logic_model_ids_; - vtr::vector last_stage_pass_gate_logic_model_names_; - vtr::vector last_stage_pass_gate_logic_model_ids_; + vtr::vector + last_stage_pass_gate_logic_model_names_; + vtr::vector + last_stage_pass_gate_logic_model_ids_; /* Port information */ vtr::vector port_ids_; diff --git a/libs/libarchopenfpga/src/read_xml_circuit_library.cpp b/libs/libarchopenfpga/src/read_xml_circuit_library.cpp index bd534779f..9fdc05265 100644 --- a/libs/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libs/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -833,18 +833,23 @@ static void read_xml_circuit_model(pugi::xml_node& xml_model, model, get_attribute(xml_pass_gate_logic, "circuit_model_name", loc_data) .as_string()); /* Last stage pass gate is optional */ - size_t num_last_stage_pgl = count_children(xml_model, "last_stage_pass_gate_logic", loc_data, pugiutil::ReqOpt::OPTIONAL); + size_t num_last_stage_pgl = + count_children(xml_model, "last_stage_pass_gate_logic", loc_data, + pugiutil::ReqOpt::OPTIONAL); if (0 < num_last_stage_pgl) { auto xml_last_stage_pass_gate_logic = get_single_child(xml_model, "last_stage_pass_gate_logic", loc_data); circuit_lib.set_model_last_stage_pass_gate_logic( - model, get_attribute(xml_last_stage_pass_gate_logic, "circuit_model_name", loc_data) + model, get_attribute(xml_last_stage_pass_gate_logic, + "circuit_model_name", loc_data) .as_string()); } else { - /* By default, assume the last stage circuit model is the same as others */ + /* By default, assume the last stage circuit model is the same as others + */ circuit_lib.set_model_last_stage_pass_gate_logic( - model, get_attribute(xml_pass_gate_logic, "circuit_model_name", loc_data) - .as_string()); + model, + get_attribute(xml_pass_gate_logic, "circuit_model_name", loc_data) + .as_string()); } } diff --git a/libs/libarchopenfpga/src/write_xml_circuit_library.cpp b/libs/libarchopenfpga/src/write_xml_circuit_library.cpp index 56da46d77..42e392685 100644 --- a/libs/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libs/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -597,7 +597,9 @@ static void write_xml_circuit_model(std::fstream& fp, const char* fname, << "" << "\n"; } diff --git a/openfpga/src/fabric/build_mux_modules.cpp b/openfpga/src/fabric/build_mux_modules.cpp index 0efd9a590..5d9fb93d7 100644 --- a/openfpga/src/fabric/build_mux_modules.cpp +++ b/openfpga/src/fabric/build_mux_modules.cpp @@ -461,7 +461,6 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( /* We must have one */ VTR_ASSERT(ModuleId::INVALID() != std_cell_module_id); - /* Find the module ports of the standard cell MUX2 module */ std::vector std_cell_module_inputs; std::vector std_cell_module_input_ports; @@ -498,8 +497,10 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( VTR_ASSERT(1 == std_cell_module_output_port.get_width()); /* Find module information of the standard cell MUX2 */ - CircuitModelId last_stage_std_cell_model = circuit_lib.last_stage_pass_gate_logic_model(mux_model); - std::string last_stage_std_cell_module_name = circuit_lib.model_name(last_stage_std_cell_model); + CircuitModelId last_stage_std_cell_model = + circuit_lib.last_stage_pass_gate_logic_model(mux_model); + std::string last_stage_std_cell_module_name = + circuit_lib.model_name(last_stage_std_cell_model); /* Get the moduleId for the submodule */ ModuleId last_stage_std_cell_module_id = module_manager.find_module(last_stage_std_cell_module_name); @@ -508,11 +509,11 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( /* Find the input ports and output ports of the standard cell */ std::vector last_stage_std_cell_input_ports = - circuit_lib.model_ports_by_type(last_stage_std_cell_model, CIRCUIT_MODEL_PORT_INPUT, - true); + circuit_lib.model_ports_by_type(last_stage_std_cell_model, + CIRCUIT_MODEL_PORT_INPUT, true); std::vector last_stage_std_cell_output_ports = - circuit_lib.model_ports_by_type(last_stage_std_cell_model, CIRCUIT_MODEL_PORT_OUTPUT, - true); + circuit_lib.model_ports_by_type(last_stage_std_cell_model, + CIRCUIT_MODEL_PORT_OUTPUT, true); /* Quick check the requirements on port map */ VTR_ASSERT(3 == last_stage_std_cell_input_ports.size()); VTR_ASSERT(1 == last_stage_std_cell_output_ports.size()); @@ -527,29 +528,37 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( last_stage_std_cell_module_id, circuit_lib.port_prefix(last_stage_std_cell_input_ports[port_id]))); VTR_ASSERT(true == module_manager.valid_module_port_id( - last_stage_std_cell_module_id, last_stage_std_cell_module_inputs[port_id])); - last_stage_std_cell_module_input_ports.push_back(module_manager.module_port( - last_stage_std_cell_module_id, last_stage_std_cell_module_inputs[port_id])); - VTR_ASSERT(1 == last_stage_std_cell_module_input_ports[port_id].get_width()); + last_stage_std_cell_module_id, + last_stage_std_cell_module_inputs[port_id])); + last_stage_std_cell_module_input_ports.push_back( + module_manager.module_port(last_stage_std_cell_module_id, + last_stage_std_cell_module_inputs[port_id])); + VTR_ASSERT(1 == + last_stage_std_cell_module_input_ports[port_id].get_width()); } /* Mem port is the memory of the standard cell MUX2, whose size must be 1 ! */ ModulePortId last_stage_std_cell_module_mem = module_manager.find_module_port( - last_stage_std_cell_module_id, circuit_lib.port_prefix(last_stage_std_cell_input_ports[2])); - VTR_ASSERT(true == module_manager.valid_module_port_id(last_stage_std_cell_module_id, - last_stage_std_cell_module_mem)); - BasicPort last_stage_std_cell_module_mem_port = - module_manager.module_port(last_stage_std_cell_module_id, last_stage_std_cell_module_mem); + last_stage_std_cell_module_id, + circuit_lib.port_prefix(last_stage_std_cell_input_ports[2])); + VTR_ASSERT(true == + module_manager.valid_module_port_id( + last_stage_std_cell_module_id, last_stage_std_cell_module_mem)); + BasicPort last_stage_std_cell_module_mem_port = module_manager.module_port( + last_stage_std_cell_module_id, last_stage_std_cell_module_mem); VTR_ASSERT(1 == last_stage_std_cell_module_mem_port.get_width()); /* Output port is the data path output of the standard cell MUX2, whose size * must be 1 ! */ - ModulePortId last_stage_std_cell_module_output = module_manager.find_module_port( - last_stage_std_cell_module_id, circuit_lib.port_prefix(last_stage_std_cell_output_ports[0])); + ModulePortId last_stage_std_cell_module_output = + module_manager.find_module_port( + last_stage_std_cell_module_id, + circuit_lib.port_prefix(last_stage_std_cell_output_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id( - last_stage_std_cell_module_id, last_stage_std_cell_module_output)); - BasicPort last_stage_std_cell_module_output_port = - module_manager.module_port(last_stage_std_cell_module_id, last_stage_std_cell_module_output); + last_stage_std_cell_module_id, + last_stage_std_cell_module_output)); + BasicPort last_stage_std_cell_module_output_port = module_manager.module_port( + last_stage_std_cell_module_id, last_stage_std_cell_module_output); VTR_ASSERT(1 == last_stage_std_cell_module_output_port.get_width()); /* Cache Net ids for each level of the multiplexer */ @@ -574,7 +583,6 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( /* To match the standard cell MUX2: We should have only 2 input_nodes */ VTR_ASSERT(2 == branch_size); - /* Last stage MUX model may have a different name */ ModuleId curr_stage_std_cell_module_id = std_cell_module_id; if (true == mux_graph.is_node_output(node)) { @@ -592,9 +600,9 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( /* Set a name for the instance */ std::string std_cell_instance_name = generate_mux_branch_instance_name( output_node_level, output_node_index_at_level, false); - module_manager.set_child_instance_name(mux_module, curr_stage_std_cell_module_id, - std_cell_instance_id, - std_cell_instance_name); + module_manager.set_child_instance_name( + mux_module, curr_stage_std_cell_module_id, std_cell_instance_id, + std_cell_instance_name); /* Add module nets to wire to next stage modules */ ModuleNetId branch_net; @@ -603,14 +611,16 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( MuxOutputId output_id = mux_graph.output_id(node); branch_net = mux_module_output_nets[output_id]; module_manager.add_module_net_source( - mux_module, branch_net, curr_stage_std_cell_module_id, std_cell_instance_id, - last_stage_std_cell_module_output, last_stage_std_cell_module_output_port.get_lsb()); + mux_module, branch_net, curr_stage_std_cell_module_id, + std_cell_instance_id, last_stage_std_cell_module_output, + last_stage_std_cell_module_output_port.get_lsb()); } else { VTR_ASSERT(false == mux_graph.is_node_output(node)); branch_net = module_manager.create_module_net(mux_module); module_manager.add_module_net_source( - mux_module, branch_net, curr_stage_std_cell_module_id, std_cell_instance_id, - std_cell_module_output, std_cell_module_output_port.get_lsb()); + mux_module, branch_net, curr_stage_std_cell_module_id, + std_cell_instance_id, std_cell_module_output, + std_cell_module_output_port.get_lsb()); } /* Record the module net id in the cache */