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bug fix in flagship vpr arch with frac mem and dsp

This commit is contained in:
tangxifan 2020-08-19 12:43:58 -06:00
parent af1c7c6f29
commit f64079641d
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
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@ -287,7 +287,7 @@
There are four 9x9 multipliers, each of which occupies part
of the input/output of the 36x36 multiplier
-->
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
<port name="a" physical_mode_port="a[0:8]" physical_mode_pin_rotate_offset="9"/>
<port name="b" physical_mode_port="b[0:8]" physical_mode_pin_rotate_offset="9"/>
<port name="out" physical_mode_port="out[0:17]" physical_mode_pin_rotate_offset="18"/>
@ -296,7 +296,7 @@
There are two 18x18 multipliers, each of which occupies part
of the input/output of the 36x36 multiplier
-->
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult_18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
<port name="a" physical_mode_port="a[0:17]" physical_mode_pin_rotate_offset="18"/>
<port name="b" physical_mode_port="b[0:17]" physical_mode_pin_rotate_offset="18"/>
<port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/>