diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp
index bca7b6709..433a05620 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp
@@ -172,6 +172,27 @@ int print_verilog_preconfig_top_module_connect_global_ports(
        */
       if ((false == pin_constraints.unconstrained_net(constrained_net_name)) &&
           (false == pin_constraints.unmapped_net(constrained_net_name))) {
+        /* The clock name must be a valid primary input. Otherwise, it could be
+         * a signal generated by internal logics, e.g., clb */
+        AtomBlockId atom_blk = atom_ctx.nlist.find_block(constrained_net_name);
+        if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))) {
+          VTR_LOG(
+            "Global net '%s' is not a primary input of the netlist (which "
+            "could a signal generated by internal logic). Will not wire it to "
+            "any FPGA primary input pin\n",
+            constrained_net_name.c_str());
+          continue;
+        }
+        /* The block may be renamed as it contains special characters which
+         * violate Verilog syntax */
+        if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+          VTR_LOG(
+            "Replace pin name '%s' with '%s' as it is renamed to comply "
+            "verilog syntax\n",
+            constrained_net_name.c_str(),
+            netlist_annotation.block_name(atom_blk).c_str());
+           constrained_net_name = netlist_annotation.block_name(atom_blk);
+        }
         BasicPort benchmark_pin(constrained_net_name, 1);
         print_verilog_wire_connection(fp, module_global_pin, benchmark_pin,
                                       false);