From f57fd273afb14d766ad77a8de495c60e648b89b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:28:06 -0600 Subject: [PATCH] [Documentation] Update documentation for smart fast configuration --- .../openfpga_shell/openfpga_commands/fpga_verilog_commands.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index c2044cf57..24dc3a603 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -33,6 +33,8 @@ write_verilog_testbench - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. + .. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration. + - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification