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Aded correct circuit models

This commit is contained in:
Ganesh Gore 2022-10-23 16:21:02 -06:00
parent ef78eac87b
commit f576eebe21
1 changed files with 16 additions and 14 deletions
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30
openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml
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@ -149,15 +149,20 @@
<port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFF" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model>
<circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="inout" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="DFF"/>
@ -181,15 +186,12 @@
<pb_type name="fpga_input" physical_mode_name="physical"/>
<pb_type name="fpga_output" physical_mode_name="physical"/>
<pb_type name="fpga_input[physical].iopad" circuit_model_name="GPIO" mode_bits="0">
<port name="inpad" physical_mode_port="inpad"/>
</pb_type>
<pb_type name="fpga_output[physical].iopad" circuit_model_name="GPIO" mode_bits="0">
<port name="outpad" physical_mode_port="outpad"/>
</pb_type>
<pb_type name="fpga_input[physical].iopad" circuit_model_name="GPIN"/>
<pb_type name="fpga_output[physical].iopad" circuit_model_name="GPOUT"/>
<pb_type name="fpga_input[inpad].inpad" physical_pb_type_name="fpga_input[physical].iopad"/>
<pb_type name="fpga_output[outpad].outpad" physical_pb_type_name="fpga_output[physical].iopad"/>
<pb_type name="fpga_input[inpad].inpad" physical_pb_type_name="fpga_input[physical].iopad" mode_bits="1"/>
<pb_type name="fpga_output[outpad].outpad" physical_pb_type_name="fpga_output[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->