diff --git a/.github/labeler.yml b/.github/labeler.yml index f2a30f198..dd1126d9f 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml @@ -1,103 +1,134 @@ # See https://github.com/actions/labeler#common-examples for defining patterns. -# The globs use "minimatch" syntax found at https://github.com/isaacs/minimatch +# The globs use minimatch syntax found at https://github.com/isaacs/minimatch # # WARNING: Due to this file being yaml, any string starting with `*` must be # wrapped in quotes. # Third-party tools ABC: - - abc/* - - abc/**/* +- changed-files: + - any-glob-to-any-file: 'abc/*' + - any-glob-to-any-file: 'abc/**/*' ACE2: - - ace2/* - - ace2/**/* +- changed-files: + - any-glob-to-any-file: 'ace2/*' + - any-glob-to-any-file: 'ace2/**/*' VPR: - - vpr/* - - vpr/**/* - - libs/**/* +- changed-files: + - any-glob-to-any-file: 'vpr/*' + - any-glob-to-any-file: 'vpr/**/*' + - any-glob-to-any-file: 'libs/**/*' # General areas documentation: - - docs/* - - docs/**/* - - "*README*" - - "*.md" - - tutorial - - "*.rst" - - ".readthedocs.yml" +- changed-files: + - any-glob-to-any-file: 'docs/*' + - any-glob-to-any-file: 'docs/**/*' + - any-glob-to-any-file: '*README*' + - any-glob-to-any-file: '*.md' + - any-glob-to-any-file: 'tutorial' + - any-glob-to-any-file: '*.rst' + - any-glob-to-any-file: '.readthedocs.yml' github: - - .github/* - - .github/**/* +- changed-files: + - any-glob-to-any-file: '.github/*' + - any-glob-to-any-file: '.github/**/*' docker: - - Dockerfile - - "*docker*" +- changed-files: + - any-glob-to-any-file: 'Dockerfile' + - any-glob-to-any-file: '*docker*' build: - - Makefile - - "*.make" - - CMakeLists.txt - - cmake +- changed-files: + - any-glob-to-any-file: 'Makefile' + - any-glob-to-any-file: '*.make' + - any-glob-to-any-file: 'CMakeLists.txt' + - any-glob-to-any-file: 'cmake' libopenfpga: - - "libopenfpga/**" +- changed-files: + - any-glob-to-any-file: 'libopenfpga/**' libopenfpga-bitstream: - - "libopenfpga/libfpgabitstream/**" +- changed-files: + - any-glob-to-any-file: 'libopenfpga/libfpgabitstream/**' libopenfpga-arch-parser: - - "libopenfpga/libarchopenfpga/**" +- changed-files: + - any-glob-to-any-file: 'libopenfpga/libarchopenfpga/**' libopenfpga-fabric-key: - - "libopenfpga/libfabrickey/**" +- changed-files: + - any-glob-to-any-file: 'libopenfpga/libfabrickey/**' libopenfpga-shell: - - "libopenfpga/libopenfpgashell/**" +- changed-files: + - any-glob-to-any-file: 'libopenfpga/libopenfpgashell/**' libopenfpga-utils: - - "libopenfpga/libopenfpgautil/**" +- changed-files: + - any-glob-to-any-file: 'libopenfpga/libopenfpgautil/**' openfpga-tools: - - "openfpga/**" +- changed-files: + - any-glob-to-any-file: 'openfpga/**' openfpga-verilog: - - "openfpga/*/fpga_verilog/**" +- changed-files: + - any-glob-to-any-file: 'openfpga/*/fpga_verilog/**' openfpga-sdc: - - "openfpga/*/fpga_sdc/**" +- changed-files: + - any-glob-to-any-file: 'openfpga/*/fpga_sdc/**' openfpga-bitstream: - - "openfpga/*/fpga_bitstream/**" +- changed-files: + - any-glob-to-any-file: 'openfpga/*/fpga_bitstream/**' openfpga-spice: - - "openfpga/*/fpga_spice/**" +- changed-files: + - any-glob-to-any-file: 'openfpga/*/fpga_spice/**' flow-scripts: - - "openfpga_flow/scripts/**" - - "openfpga_flow/openfpga_shell_scripts/**" - - "openfpga_flow/openfpga_simulation_settings/**" - - "openfpga_flow/misc/**" +- changed-files: + - any-glob-to-any-file: 'openfpga_flow/scripts/**' + - any-glob-to-any-file: 'openfpga_flow/openfpga_shell_scripts/**' + - any-glob-to-any-file: 'openfpga_flow/openfpga_simulation_settings/**' + - any-glob-to-any-file: 'openfpga_flow/misc/**' architecture-description: - - "openfpga_flow/vpr_arch/**" - - "openfpga_flow/openfpga_arch/**" - - "openfpga_flow/fabric_keys/**" +- changed-files: + - any-glob-to-any-file: 'openfpga_flow/vpr_arch/**' + - any-glob-to-any-file: 'openfpga_flow/openfpga_arch/**' + - any-glob-to-any-file: 'openfpga_flow/fabric_keys/**' bitstream: - - "openfpga_flow/fabric_keys/**" +- changed-files: + - any-glob-to-any-file: 'openfpga_flow/fabric_keys/**' cell-library: - - "openfpga_flow/openfpga_cell_library/**" - - "openfpga_flow/tech/**" +- changed-files: + - any-glob-to-any-file: 'openfpga_flow/openfpga_cell_library/**' + - any-glob-to-any-file: 'openfpga_flow/tech/**' benchmarks: - - "openfpga_flow/benchmarks/**" +- changed-files: + - any-glob-to-any-file: 'openfpga_flow/benchmarks/**' tests: - - "openfpga_flow/tasks/**" +- changed-files: + - any-glob-to-any-file: 'openfpga_flow/tasks/**' # Tag pull requests with the languages used to make it easy to see what is # being used. lang-hdl: - - "*.v" - - "*.sv" +- changed-files: + - any-glob-to-any-file: '*.v' + - any-glob-to-any-file: '*.sv' lang-cpp: - - "*.c*" - - "*.h" +- changed-files: + - any-glob-to-any-file: '*.c*' + - any-glob-to-any-file: '*.h' lang-perl: - - "*.pl" - - "*perl*" +- changed-files: + - any-glob-to-any-file: '*.pl' + - any-glob-to-any-file: '*perl*' lang-python: - - "*.py" +- changed-files: + - any-glob-to-any-file: '*.py' lang-shell: - - "*.sh" +- changed-files: + - any-glob-to-any-file: '*.sh' lang-netlist: - - "*.blif" - - "*.eblif" - - "*.edif" - - "*.vqm" +- changed-files: + - any-glob-to-any-file: '*.blif' + - any-glob-to-any-file: '*.eblif' + - any-glob-to-any-file: '*.edif' + - any-glob-to-any-file: '*.vqm' lang-make: - - "*.make" - - Makefile - - CMakeLists.txt \ No newline at end of file +- changed-files: + - any-glob-to-any-file: '*.make' + - any-glob-to-any-file: 'Makefile' + - any-glob-to-any-file: 'CMakeLists.txt' diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 2e8a8246c..e97ead79f 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -1,13 +1,19 @@ name: Test # Run CI on push, PR, and weekly. - on: - push: + workflow_dispatch: pull_request: + push: + branches: + - 'master' schedule: - cron: "0 0 * * 0 " # weekly +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + # Environment variables env: # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.) @@ -22,7 +28,7 @@ env: jobs: change_detect: name: "Detect code changes" - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 outputs: # this is output as string, see https://docs.github.com/en/actions/reference/workflow-syntax-for-github-actions#jobsjob_idoutputs source_modified: ${{ steps.changes.outputs.status_code == '1' }} @@ -31,12 +37,12 @@ jobs: docker_repo: ${{ steps.changes.outputs.docker_repo }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: fetch-depth: 0 @@ -67,7 +73,7 @@ jobs: needs: change_detect if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }} name: ${{ matrix.config.name }} - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 # Note: dependencies are installed in the container. See details about dependency list in docker/Dockerfile.master # Comment the line out when base image is built again #container: ghcr.io/${{ needs.change_detect.outputs.docker_repo }}/openfpga-build-${{ matrix.config.cc}} @@ -76,45 +82,53 @@ jobs: fail-fast: false matrix: config: - - name: "Build Compatibility: GCC-8 (Ubuntu 20.04)" - cc: gcc-8 - cxx: g++-8 - - name: "Build Compatibility: GCC-9 (Ubuntu 20.04)" + - name: "Build Compatibility: GCC-9 (Ubuntu 22.04)" cc: gcc-9 cxx: g++-9 - - name: "Build Compatibility: GCC-10 (Ubuntu 20.04)" + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: GCC-10 (Ubuntu 22.04)" cc: gcc-10 cxx: g++-10 - - name: "Build Compatibility: GCC-11 (Ubuntu 20.04)" + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: GCC-11 (Ubuntu 22.04)" cc: gcc-11 cxx: g++-11 - - name: "Build Compatibility: Clang-6 (Ubuntu 20.04)" - cc: clang-6.0 - cxx: clang++-6.0 - - name: "Build Compatibility: Clang-7 (Ubuntu 20.04)" - cc: clang-7 - cxx: clang++-7 - - name: "Build Compatibility: Clang-8 (Ubuntu 20.04)" - cc: clang-8 - cxx: clang++-8 - - name: "Build Compatibility: Clang-10 (Ubuntu 20.04)" - cc: clang-10 - cxx: clang++-10 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: GCC-12 (Ubuntu 22.04)" + cc: gcc-12 + cxx: g++-12 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: Clang-11 (Ubuntu 22.04)" + cc: clang-11 + cxx: clang++-11 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: Clang-12 (Ubuntu 22.04)" + cc: clang-12 + cxx: clang++-12 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: Clang-13 (Ubuntu 22.04)" + cc: clang-13 + cxx: clang++-13 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: Clang-14 (Ubuntu 22.04)" + cc: clang-14 + cxx: clang++-14 + dependency_version: "ubuntu22p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies - run: sudo bash ./.github/workflows/install_dependencies_build.sh + run: sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh - name: Dump tool versions run: | @@ -129,12 +143,18 @@ jobs: run: | make all BUILD_TYPE=$BUILD_TYPE + - name: Clear error log + if: ${{ failure() }} + shell: bash + run: | + make all BUILD_TYPE=$BUILD_TYPE -j1 + # Check the cache size and see if it is over the limit - name: Check ccache size run: ccache -s - name: Upload artifact - uses: actions/upload-artifact@v2 - if: ${{ matrix.config.cc == 'gcc-9'}} + uses: actions/upload-artifact@v4 + if: ${{ matrix.config.cc == 'gcc-11'}} with: name: openfpga path: | @@ -151,11 +171,12 @@ jobs: openfpga_flow openfpga.sh + linux_build_opt: needs: change_detect if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }} name: ${{ matrix.config.name }} - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 # Note: dependencies are installed in the container. See details about dependency list in docker/Dockerfile.master # Comment the line out when base image is built again #container: ghcr.io/${{ needs.change_detect.outputs.docker_repo }}/openfpga-build-${{ matrix.config.cc}} @@ -164,41 +185,46 @@ jobs: fail-fast: false matrix: config: - - name: "Build w/o Yosys (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + - name: "Build w/o Yosys (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_YOSYS=OFF" - - name: "Build w/o Yosys plugin (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + dependency_version: "ubuntu22p04" + - name: "Build w/o Yosys plugin (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_YOSYS_PLUGIN=OFF" - - name: "Build w/o test (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + dependency_version: "ubuntu22p04" + - name: "Build w/o test (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_TEST=OFF" - - name: "Build w/o version number (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + dependency_version: "ubuntu22p04" + - name: "Build w/o version number (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_VERSION=OFF" - - name: "Build w/o SWIG support (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + dependency_version: "ubuntu22p04" + - name: "Build w/o SWIG support (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_SWIG=OFF" + dependency_version: "ubuntu22p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies - run: sudo bash ./.github/workflows/install_dependencies_build.sh + run: sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh - name: Dump tool versions run: | @@ -217,29 +243,34 @@ jobs: needs: change_detect if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }} name: ${{ matrix.config.name }} - runs-on: ubuntu-22.04 + runs-on: ubuntu-20.04 strategy: fail-fast: false matrix: config: - - name: "Build (Ubuntu 22.04)" + - name: "Build (GCC-11 on Ubuntu 20.04)" cc: gcc-11 cxx: g++-11 + dependency_version: "ubuntu20p04" + - name: "Build (Clang-10 on Ubuntu 20.04)" + cc: clang-10 + cxx: clang++-10 + dependency_version: "ubuntu20p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies - run: sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh + run: sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh - name: Dump tool versions run: | @@ -270,23 +301,24 @@ jobs: cxx: g++-11 build_type: debug cores: 4 + dependency_version: "ubuntu22p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies run: | - sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh - sudo bash ./.github/workflows/install_dependencies_run_ubuntu22p04.sh + sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh + sudo bash ./.github/workflows/install_dependencies_run_${{ matrix.config.dependency_version }}.sh sudo python3 -m pip install -r requirements.txt - name: Dump tool versions @@ -321,23 +353,24 @@ jobs: cxx: g++-11 build_type: release cores: 4 + dependency_version: "ubuntu22p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies run: | - sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh - sudo bash ./.github/workflows/install_dependencies_run_ubuntu22p04.sh + sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh + sudo bash ./.github/workflows/install_dependencies_run_${{ matrix.config.dependency_version }}.sh sudo python3 -m pip install -r requirements.txt - name: Dump tool versions @@ -360,18 +393,18 @@ jobs: docker_distribution: name: Build docker image for distribution - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 needs: [linux_build, change_detect] steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Download a built artifacts - uses: actions/download-artifact@v2 + uses: actions/download-artifact@v4 with: name: openfpga - name: Set up QEMU @@ -397,7 +430,7 @@ jobs: linux_regression_tests: name: linux_regression_tests - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 needs: [linux_build, change_detect] container: ghcr.io/${{ needs.change_detect.outputs.docker_repo }}/openfpga-env strategy: @@ -417,14 +450,14 @@ jobs: - name: tcl_reg_test steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Download a built artifacts - uses: actions/download-artifact@v2 + uses: actions/download-artifact@v4 with: name: openfpga - name: chmod @@ -438,11 +471,11 @@ jobs: chmod +x build/yosys/bin/yosys-config chmod +x build/yosys/bin/yosys-filterlib chmod +x build/yosys/bin/yosys-smtbmc - - name: ${{matrix.config.name}}_GCC-9_(Ubuntu 20.04) + - name: ${{matrix.config.name}}_GCC-11_(Ubuntu 22.04) shell: bash run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs - name: Upload artifact - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 if: ${{ failure() }} with: name: failed_${{matrix.config.name}}_regression_log @@ -454,7 +487,7 @@ jobs: needs: change_detect if: ${{ !fromJSON(needs.change_detect.outputs.source_modified) }} name: docker_regression_tests - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 container: image: ghcr.io/${{ needs.change_detect.outputs.docker_repo }}/openfpga-master:latest options: --user root --workdir /home/openfpga_user @@ -475,23 +508,23 @@ jobs: - name: tcl_reg_test steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - - name: ${{matrix.config.name}}_GCC-9_(Ubuntu 20.04) + - name: ${{matrix.config.name}}_GCC-11_(Ubuntu 22.04) shell: bash run: | - bash .github/workflows/install_dependencies_run.sh + bash .github/workflows/install_dependencies_run_ubuntu22p04.sh ${PYTHON_EXEC} -m pip install -r requirements.txt rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. . unset OPENFPGA_PATH source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs - name: Upload artifact - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 if: ${{ failure() }} with: name: failed_${{matrix.config.name}}_regression_log diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 7d5b08984..feaa28a3e 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -1,13 +1,19 @@ name: Cell Library Tests # Run CI on push, PR, and weekly. - on: - push: + workflow_dispatch: pull_request: + push: + branches: + - 'master' schedule: - cron: "0 0 * * 0 " # weekly +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + # Multiple job to tests jobs: # Test the RTL compilation compatibility @@ -16,7 +22,7 @@ jobs: runs-on: ubuntu-22.04 steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} diff --git a/.github/workflows/docker.yml b/.github/workflows/docker.yml index f29dbd883..ef77be6ed 100644 --- a/.github/workflows/docker.yml +++ b/.github/workflows/docker.yml @@ -7,10 +7,14 @@ env: DOCKER_REPO: ${{ secrets.DOCKER_REPO }} REPO_OWNER: ${{ github.repository_owner }} +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + jobs: change_detect: name: "Detect code changes" - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 outputs: docker_repo: ${{ steps.changes.outputs.docker_repo }} steps: @@ -31,7 +35,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout - uses: actions/checkout@v2 + uses: actions/checkout@v4 - name: Set up QEMU uses: docker/setup-qemu-action@v1 - name: Set up Docker Buildx @@ -64,18 +68,17 @@ jobs: strategy: matrix: compiler: - - gcc-7 - - gcc-8 - gcc-9 - gcc-10 - gcc-11 - - clang-6.0 - - clang-7 - - clang-8 - - clang-10 + - gcc-12 + - clang-11 + - clang-12 + - clang-13 + - clang-14 steps: - name: Checkout - uses: actions/checkout@v2 + uses: actions/checkout@v4 - name: Set up QEMU uses: docker/setup-qemu-action@v1 - name: Set up Docker Buildx diff --git a/.github/workflows/format.yaml b/.github/workflows/format.yaml index fd1365272..2a4fd8bbb 100644 --- a/.github/workflows/format.yaml +++ b/.github/workflows/format.yaml @@ -3,29 +3,39 @@ name: Code Format # Run CI on push, PR, and weekly. on: - push: + workflow_dispatch: pull_request: + push: + branches: + - 'master' schedule: - cron: "0 0 * * 0 " # weekly +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + # Multiple job to tests jobs: change_detect: name: "Check" - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 strategy: fail-fast: false matrix: config: - name: "C/C++" code_type: "-cpp" + dependency_version: "ubuntu22p04" - name: "XML" code_type: "-xml" + dependency_version: "ubuntu22p04" - name: "Python" code_type: "-py" + dependency_version: "ubuntu22p04" steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} @@ -34,12 +44,12 @@ jobs: - name: Install dependencies run: | - sudo bash ./.github/workflows/install_dependencies_build.sh + sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh sudo python3 -m pip install -r requirements.txt - name: Dump tool versions run: | - clang-format-10 --version + clang-format-14 --version black --version - name: Check format diff --git a/.github/workflows/install_dependencies_build.sh b/.github/workflows/install_dependencies_build_ubuntu20p04.sh similarity index 100% rename from .github/workflows/install_dependencies_build.sh rename to .github/workflows/install_dependencies_build_ubuntu20p04.sh diff --git a/.github/workflows/install_dependencies_build_ubuntu22p04.sh b/.github/workflows/install_dependencies_build_ubuntu22p04.sh index e49f0b9d4..19d806add 100755 --- a/.github/workflows/install_dependencies_build_ubuntu22p04.sh +++ b/.github/workflows/install_dependencies_build_ubuntu22p04.sh @@ -53,6 +53,9 @@ apt-get install -y \ gcc-10 \ g++-11 \ gcc-11 \ + clang-11 \ clang-12 \ - clang-format-12 \ + clang-13 \ + clang-14 \ + clang-format-14 \ libxml2-utils diff --git a/.github/workflows/install_dependencies_run.sh b/.github/workflows/install_dependencies_run_ubuntu20p04.sh similarity index 100% rename from .github/workflows/install_dependencies_run.sh rename to .github/workflows/install_dependencies_run_ubuntu20p04.sh diff --git a/.github/workflows/labeler.yml b/.github/workflows/labeler.yml index 808aaa18b..65abffb8b 100644 --- a/.github/workflows/labeler.yml +++ b/.github/workflows/labeler.yml @@ -4,9 +4,12 @@ on: jobs: triage: + permissions: + contents: read + pull-requests: write runs-on: ubuntu-latest steps: - - uses: actions/labeler@main + - uses: actions/labeler@v5 with: repo-token: "${{ secrets.GITHUB_TOKEN }}" configuration-path: ".github/labeler.yml" diff --git a/.github/workflows/patch_updater.yml b/.github/workflows/patch_updater.yml index 7a579acf9..38c406e98 100644 --- a/.github/workflows/patch_updater.yml +++ b/.github/workflows/patch_updater.yml @@ -1,8 +1,9 @@ name: Count Patches on: workflow_dispatch: - schedule: - - cron: '0 0 * * *' + push: + branches: + - 'master' env: TAG_COMMIT: 8ee3fb8.. @@ -41,6 +42,7 @@ jobs: with: github_token: ${{ secrets.GITHUB_TOKEN }} branch: ${{env.BRANCH_NAME}} + force: true - name: Create Auto PR if: "!contains(steps.log.outputs.message, 'Updated Patch Count') && contains(steps.repo.outputs.message, 'lnis-uofu/OpenFPGA')" diff --git a/.readthedocs.yml b/.readthedocs.yml index 2b28d0df4..28647ec7e 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -17,7 +17,9 @@ sphinx: configuration: docs/source/conf.py # Optionally build your docs in additional formats such as PDF and ePub -formats: all +formats: + - pdf + - epub # Optionally set the version of Python and requirements required to build your docs python: diff --git a/CMakeLists.txt b/CMakeLists.txt index 100351184..76e27b7e9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -320,7 +320,9 @@ if (OPENFPGA_WITH_YOSYS) else () # run makefile provided, we pass-on the options to the local make file add_custom_target( - yosys ALL + yosys ALL + # add step to remove the 'built-in' quicklogic plugins code in yosys + COMMAND rm -rf techlibs/quicklogic COMMAND $(MAKE) config-gcc COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_BINARY_DIR}/yosys/ WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys diff --git a/Makefile b/Makefile index 23c2cdab6..9f39d6c22 100644 --- a/Makefile +++ b/Makefile @@ -42,7 +42,7 @@ endif # Define executables PYTHON_EXEC ?= python3 -CLANG_FORMAT_EXEC ?= clang-format-10 +CLANG_FORMAT_EXEC ?= clang-format-14 XML_FORMAT_EXEC ?= xmllint PYTHON_FORMAT_EXEC ?= black diff --git a/README.md b/README.md index 0b4bb8fd6..a66ddc216 100644 --- a/README.md +++ b/README.md @@ -11,16 +11,19 @@ Version: see [`VERSION.md`](VERSION.md) The award-winning OpenFPGA framework is the **first open-source FPGA IP generator with silicon proofs** supporting highly-customizable FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. -**If this is your first time working with OpenFPGA, we strongly **recommend you watch the** [introduction video about OpenFPGA](https://youtu.be/ocODUGcYGqo)** +> [!TIP] +> If this is your first time working with OpenFPGA, we strongly recommend you watch the [introduction video about OpenFPGA](https://youtu.be/ocODUGcYGqo) A quick overview of OpenFPGA tools can be found [**here**](https://openfpga.readthedocs.io/en/master/tutorials/getting_started/tools/). We also recommend potential users check out the summary of [**technical capabilities**](https://openfpga.readthedocs.io/en/master/overview/tech_highlights/#) before compiling. -**Before asking for help, please checkout the** [Frequently Asked Questions](https://github.com/lnis-uofu/OpenFPGA/discussions/937) +> [!TIP] +> Before asking for help, please checkout the [Frequently Asked Questions](https://github.com/lnis-uofu/OpenFPGA/discussions/937) ## Compilation -**A tutorial **video about **how to compile** can be** found [here](https://youtu.be/F9sMRmDewM0)** +> [!NOTE] +> A tutorial video about how to compile can be found [here](https://youtu.be/F9sMRmDewM0) Detailed guidelines are available at [**compilation guidelines**](https://openfpga.readthedocs.io/en/master/tutorials/getting_started/compile/). Before starting, we strongly recommend you read the required dependencies and ensure that they are correctly installed. @@ -36,7 +39,7 @@ You can find a set of [tutorials](https://openfpga.readthedocs.io/en/master/tuto ## Backward Compatibility -If you were using an old version of OpenFPGA and are now interested to move to the latest version, please check out the [developer guidelines](https://openfpga.readthedocs.io/en/master/dev_manual/back_compatibile). +If you were using an old version of OpenFPGA and are now interested to move to the latest version, please check out the [developer guidelines](https://openfpga.readthedocs.io/en/master/dev_manual/back_compatible/). ## License @@ -54,8 +57,8 @@ Bibtex: @ARTICLE{9098028, author={Tang, Xifan and Giacomin, Edouard and Chauviere, Baudouin and Alacchi, Aurélien and Gaillardon, Pierre-Emmanuel}, journal={IEEE Micro}, title={OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs}, year={2020}, volume={40}, number={4}, pages={41-48}, doi={10.1109/MM.2020.2995854}} ``` -A list of related publications can be found [here](https://openfpga.readthedocs.io/en/master/reference/). +A list of related publications can be found [here](https://openfpga.readthedocs.io/en/master/appendix/reference/). ## Contributing to OpenFPGA -Please read the [contributor guidelines](https://openfpga.readthedocs.io/en/master/dev_manual/contributor_guide) if you would like to contribute to OpenFPGA. +Please read the [contributor guidelines](https://openfpga.readthedocs.io/en/master/dev_manual/contributor_guide/) if you would like to contribute to OpenFPGA. diff --git a/VERSION.md b/VERSION.md index 992c7c678..21c2b9b13 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.1795 +1.2.2938 diff --git a/cmake/modules/FindTBB.cmake b/cmake/modules/FindTBB.cmake deleted file mode 100644 index 0a1a5bb77..000000000 --- a/cmake/modules/FindTBB.cmake +++ /dev/null @@ -1,303 +0,0 @@ -# The MIT License (MIT) -# -# Copyright (c) 2015 Justus Calvin -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all -# copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -# SOFTWARE. - -# -# FindTBB -# ------- -# -# Find TBB include directories and libraries. -# -# Usage: -# -# find_package(TBB [major[.minor]] [EXACT] -# [QUIET] [REQUIRED] -# [[COMPONENTS] [components...]] -# [OPTIONAL_COMPONENTS components...]) -# -# where the allowed components are tbbmalloc and tbb_preview. Users may modify -# the behavior of this module with the following variables: -# -# * TBB_ROOT_DIR - The base directory the of TBB installation. -# * TBB_INCLUDE_DIR - The directory that contains the TBB headers files. -# * TBB_LIBRARY - The directory that contains the TBB library files. -# * TBB__LIBRARY - The path of the TBB the corresponding TBB library. -# These libraries, if specified, override the -# corresponding library search results, where -# may be tbb, tbb_debug, tbbmalloc, tbbmalloc_debug, -# tbb_preview, or tbb_preview_debug. -# * TBB_USE_DEBUG_BUILD - The debug version of tbb libraries, if present, will -# be used instead of the release version. -# -# Users may modify the behavior of this module with the following environment -# variables: -# -# * TBB_INSTALL_DIR -# * TBBROOT -# * LIBRARY_PATH -# -# This module will set the following variables: -# -# * TBB_FOUND - Set to false, or undefined, if we haven’t found, or -# don’t want to use TBB. -# * TBB__FOUND - If False, optional part of TBB sytem is -# not available. -# * TBB_VERSION - The full version string -# * TBB_VERSION_MAJOR - The major version -# * TBB_VERSION_MINOR - The minor version -# * TBB_INTERFACE_VERSION - The interface version number defined in -# tbb/tbb_stddef.h. -# * TBB__LIBRARY_RELEASE - The path of the TBB release version of -# , where may be tbb, tbb_debug, -# tbbmalloc, tbbmalloc_debug, tbb_preview, or -# tbb_preview_debug. -# * TBB__LIBRARY_DEGUG - The path of the TBB release version of -# , where may be tbb, tbb_debug, -# tbbmalloc, tbbmalloc_debug, tbb_preview, or -# tbb_preview_debug. -# -# The following varibles should be used to build and link with TBB: -# -# * TBB_INCLUDE_DIRS - The include directory for TBB. -# * TBB_LIBRARIES - The libraries to link against to use TBB. -# * TBB_LIBRARIES_RELEASE - The release libraries to link against to use TBB. -# * TBB_LIBRARIES_DEBUG - The debug libraries to link against to use TBB. -# * TBB_DEFINITIONS - Definitions to use when compiling code that uses -# TBB. -# * TBB_DEFINITIONS_RELEASE - Definitions to use when compiling release code that -# uses TBB. -# * TBB_DEFINITIONS_DEBUG - Definitions to use when compiling debug code that -# uses TBB. -# -# This module will also create the "tbb" target that may be used when building -# executables and libraries. - -include(FindPackageHandleStandardArgs) - -if(NOT TBB_FOUND) - - ################################## - # Check the build type - ################################## - - if(NOT DEFINED TBB_USE_DEBUG_BUILD) - if(CMAKE_BUILD_TYPE MATCHES "(Debug|DEBUG|debug|RelWithDebInfo|RELWITHDEBINFO|relwithdebinfo)") - set(TBB_BUILD_TYPE DEBUG) - else() - set(TBB_BUILD_TYPE RELEASE) - endif() - elseif(TBB_USE_DEBUG_BUILD) - set(TBB_BUILD_TYPE DEBUG) - else() - set(TBB_BUILD_TYPE RELEASE) - endif() - - ################################## - # Set the TBB search directories - ################################## - - # Define search paths based on user input and environment variables - set(TBB_SEARCH_DIR ${TBB_ROOT_DIR} $ENV{TBB_INSTALL_DIR} $ENV{TBBROOT}) - - # Define the search directories based on the current platform - if(CMAKE_SYSTEM_NAME STREQUAL "Windows") - set(TBB_DEFAULT_SEARCH_DIR "C:/Program Files/Intel/TBB" - "C:/Program Files (x86)/Intel/TBB") - - # Set the target architecture - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - set(TBB_ARCHITECTURE "intel64") - else() - set(TBB_ARCHITECTURE "ia32") - endif() - - # Set the TBB search library path search suffix based on the version of VC - if(WINDOWS_STORE) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11_ui") - elseif(MSVC14) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc14") - elseif(MSVC12) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc12") - elseif(MSVC11) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11") - elseif(MSVC10) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc10") - endif() - - # Add the library path search suffix for the VC independent version of TBB - list(APPEND TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc_mt") - - elseif(CMAKE_SYSTEM_NAME STREQUAL "Darwin") - # OS X - set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") - - # TODO: Check to see which C++ library is being used by the compiler. - if(NOT ${CMAKE_SYSTEM_VERSION} VERSION_LESS 13.0) - # The default C++ library on OS X 10.9 and later is libc++ - set(TBB_LIB_PATH_SUFFIX "lib/libc++" "lib") - else() - set(TBB_LIB_PATH_SUFFIX "lib") - endif() - elseif(CMAKE_SYSTEM_NAME STREQUAL "Linux") - # Linux - set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") - - # TODO: Check compiler version to see the suffix should be /gcc4.1 or - # /gcc4.1. For now, assume that the compiler is more recent than - # gcc 4.4.x or later. - if(CMAKE_SYSTEM_PROCESSOR STREQUAL "x86_64") - set(TBB_LIB_PATH_SUFFIX "lib/intel64/gcc4.4") - elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^i.86$") - set(TBB_LIB_PATH_SUFFIX "lib/ia32/gcc4.4") - endif() - endif() - - ################################## - # Find the TBB include dir - ################################## - - find_path(TBB_INCLUDE_DIRS tbb/tbb.h - HINTS ${TBB_INCLUDE_DIR} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} - PATH_SUFFIXES include) - - ################################## - # Set version strings - ################################## - - if(TBB_INCLUDE_DIRS) - file(READ "${TBB_INCLUDE_DIRS}/tbb/tbb_stddef.h" _tbb_version_file) - string(REGEX REPLACE ".*#define TBB_VERSION_MAJOR ([0-9]+).*" "\\1" - TBB_VERSION_MAJOR "${_tbb_version_file}") - string(REGEX REPLACE ".*#define TBB_VERSION_MINOR ([0-9]+).*" "\\1" - TBB_VERSION_MINOR "${_tbb_version_file}") - string(REGEX REPLACE ".*#define TBB_INTERFACE_VERSION ([0-9]+).*" "\\1" - TBB_INTERFACE_VERSION "${_tbb_version_file}") - set(TBB_VERSION "${TBB_VERSION_MAJOR}.${TBB_VERSION_MINOR}") - endif() - - ################################## - # Find TBB components - ################################## - - if(TBB_VERSION VERSION_LESS 4.3) - set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc tbb) - else() - set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc_proxy tbbmalloc tbb) - endif() - - # Find each component - foreach(_comp ${TBB_SEARCH_COMPOMPONENTS}) - if(";${TBB_FIND_COMPONENTS};tbb;" MATCHES ";${_comp};") - - # Search for the libraries - find_library(TBB_${_comp}_LIBRARY_RELEASE ${_comp} - HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH - PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX}) - - find_library(TBB_${_comp}_LIBRARY_DEBUG ${_comp}_debug - HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH - PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX}) - - if(TBB_${_comp}_LIBRARY_DEBUG) - list(APPEND TBB_LIBRARIES_DEBUG "${TBB_${_comp}_LIBRARY_DEBUG}") - endif() - if(TBB_${_comp}_LIBRARY_RELEASE) - list(APPEND TBB_LIBRARIES_RELEASE "${TBB_${_comp}_LIBRARY_RELEASE}") - endif() - if(TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE} AND NOT TBB_${_comp}_LIBRARY) - set(TBB_${_comp}_LIBRARY "${TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE}}") - endif() - - if(TBB_${_comp}_LIBRARY AND EXISTS "${TBB_${_comp}_LIBRARY}") - set(TBB_${_comp}_FOUND TRUE) - else() - set(TBB_${_comp}_FOUND FALSE) - endif() - - # Mark internal variables as advanced - mark_as_advanced(TBB_${_comp}_LIBRARY_RELEASE) - mark_as_advanced(TBB_${_comp}_LIBRARY_DEBUG) - mark_as_advanced(TBB_${_comp}_LIBRARY) - - endif() - endforeach() - - ################################## - # Set compile flags and libraries - ################################## - - set(TBB_DEFINITIONS_RELEASE "") - set(TBB_DEFINITIONS_DEBUG "-DTBB_USE_DEBUG=1") - - if(TBB_LIBRARIES_${TBB_BUILD_TYPE}) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_${TBB_BUILD_TYPE}}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_${TBB_BUILD_TYPE}}") - elseif(TBB_LIBRARIES_RELEASE) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_RELEASE}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_RELEASE}") - elseif(TBB_LIBRARIES_DEBUG) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_DEBUG}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_DEBUG}") - endif() - - find_package_handle_standard_args(TBB - REQUIRED_VARS TBB_INCLUDE_DIRS TBB_LIBRARIES - HANDLE_COMPONENTS - VERSION_VAR TBB_VERSION) - - ################################## - # Create targets - ################################## - - if(NOT CMAKE_VERSION VERSION_LESS 3.0 AND TBB_FOUND) - add_library(tbb SHARED IMPORTED) - set_target_properties(tbb PROPERTIES - INTERFACE_INCLUDE_DIRECTORIES ${TBB_INCLUDE_DIRS} - IMPORTED_LOCATION ${TBB_LIBRARIES}) - if(TBB_LIBRARIES_RELEASE AND TBB_LIBRARIES_DEBUG) - set_target_properties(tbb PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "$<$,$>:TBB_USE_DEBUG=1>" - IMPORTED_LOCATION_DEBUG ${TBB_LIBRARIES_DEBUG} - IMPORTED_LOCATION_RELWITHDEBINFO ${TBB_LIBRARIES_DEBUG} - IMPORTED_LOCATION_RELEASE ${TBB_LIBRARIES_RELEASE} - IMPORTED_LOCATION_MINSIZEREL ${TBB_LIBRARIES_RELEASE} - ) - elseif(TBB_LIBRARIES_RELEASE) - set_target_properties(tbb PROPERTIES IMPORTED_LOCATION ${TBB_LIBRARIES_RELEASE}) - else() - set_target_properties(tbb PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "${TBB_DEFINITIONS_DEBUG}" - IMPORTED_LOCATION ${TBB_LIBRARIES_DEBUG} - ) - endif() - endif() - - mark_as_advanced(TBB_INCLUDE_DIRS TBB_LIBRARIES) - - unset(TBB_ARCHITECTURE) - unset(TBB_BUILD_TYPE) - unset(TBB_LIB_PATH_SUFFIX) - unset(TBB_DEFAULT_SEARCH_DIR) - -endif() diff --git a/docker/Dockerfile.base b/docker/Dockerfile.base index fafef66d3..bffd33166 100755 --- a/docker/Dockerfile.base +++ b/docker/Dockerfile.base @@ -1,9 +1,9 @@ -FROM ubuntu:20.04 +FROM ubuntu:22.04 ENV DEBIAN_FRONTEND=noninteractive RUN apt-get update && apt-get install software-properties-common -y # 18.04 includes 2.17 but github requires 2.18+ to support submodules. RUN add-apt-repository ppa:git-core/ppa -ADD .github/workflows/install_dependencies_build.sh install_dependencies_build.sh +ADD .github/workflows/install_dependencies_build_ubuntu22p04.sh install_dependencies_build.sh RUN bash install_dependencies_build.sh ADD requirements.txt requirements.txt RUN python3 -m pip install -r requirements.txt diff --git a/docker/Dockerfile.clang-10 b/docker/Dockerfile.clang-10 deleted file mode 100644 index 447c5fc81..000000000 --- a/docker/Dockerfile.clang-10 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y clang-format-7 clang-10 diff --git a/docker/Dockerfile.clang-11 b/docker/Dockerfile.clang-11 new file mode 100644 index 000000000..4ba9ad201 --- /dev/null +++ b/docker/Dockerfile.clang-11 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN apt-get update && apt-get install -y clang-format-14 clang-11 diff --git a/docker/Dockerfile.clang-12 b/docker/Dockerfile.clang-12 new file mode 100644 index 000000000..57a8dbd0d --- /dev/null +++ b/docker/Dockerfile.clang-12 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN apt-get update && apt-get install -y clang-format-14 clang-12 diff --git a/docker/Dockerfile.clang-13 b/docker/Dockerfile.clang-13 new file mode 100644 index 000000000..902e8f29f --- /dev/null +++ b/docker/Dockerfile.clang-13 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN apt-get update && apt-get install -y clang-format-14 clang-13 diff --git a/docker/Dockerfile.clang-14 b/docker/Dockerfile.clang-14 new file mode 100644 index 000000000..bad23c8b0 --- /dev/null +++ b/docker/Dockerfile.clang-14 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN apt-get update && apt-get install -y clang-format-14 clang-14 diff --git a/docker/Dockerfile.clang-6.0 b/docker/Dockerfile.clang-6.0 deleted file mode 100644 index 6d7c36b3e..000000000 --- a/docker/Dockerfile.clang-6.0 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y clang-format-7 clang-6.0 diff --git a/docker/Dockerfile.clang-7 b/docker/Dockerfile.clang-7 deleted file mode 100644 index 485a61318..000000000 --- a/docker/Dockerfile.clang-7 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y clang-format-7 clang-7 diff --git a/docker/Dockerfile.clang-8 b/docker/Dockerfile.clang-8 deleted file mode 100644 index 5a4a5f4ef..000000000 --- a/docker/Dockerfile.clang-8 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y clang-format-7 clang-8 diff --git a/docker/Dockerfile.env b/docker/Dockerfile.env index b2ca7c202..642d8589b 100644 --- a/docker/Dockerfile.env +++ b/docker/Dockerfile.env @@ -1,15 +1,13 @@ -FROM ubuntu:20.04 +FROM ubuntu:22.04 ENV DEBIAN_FRONTEND=noninteractive RUN apt-get update && apt-get install --no-install-recommends software-properties-common -y # 18.04 includes 2.17 but github requires 2.18+ to support submodules. #RUN add-apt-repository ppa:git-core/ppa -ADD .github/workflows/install_dependencies_run.sh install_dependencies_run.sh +ADD .github/workflows/install_dependencies_run_ubuntu22p04.sh install_dependencies_run.sh RUN bash install_dependencies_run.sh RUN curl https://bootstrap.pypa.io/get-pip.py -o get-pip.py -RUN python3.8 get-pip.py && rm get-pip.py -RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.8 2 -# Comment out this line since Ubuntu 20.04 does not support it -# RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.6 1 +RUN python3.10 get-pip.py && rm get-pip.py +RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.10 2 ADD requirements.txt requirements.txt -ENV PYTHON_EXEC=python3.8 +ENV PYTHON_EXEC=python3.10 RUN ${PYTHON_EXEC} -m pip install -r requirements.txt diff --git a/docker/Dockerfile.gcc-12 b/docker/Dockerfile.gcc-12 new file mode 100644 index 000000000..d21a8e1ed --- /dev/null +++ b/docker/Dockerfile.gcc-12 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN add-apt-repository -y ppa:ubuntu-toolchain-r/test && apt-get update && apt-get install -y gcc-12 g++-12 diff --git a/docker/Dockerfile.gcc-7 b/docker/Dockerfile.gcc-7 deleted file mode 100644 index d7638677b..000000000 --- a/docker/Dockerfile.gcc-7 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y gcc-7 g++-7 diff --git a/docker/Dockerfile.gcc-8 b/docker/Dockerfile.gcc-8 deleted file mode 100644 index 187a47623..000000000 --- a/docker/Dockerfile.gcc-8 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y gcc-8 g++-8 diff --git a/docs/source/dev_manual/cicd_setup.rst b/docs/source/dev_manual/ci.rst similarity index 62% rename from docs/source/dev_manual/cicd_setup.rst rename to docs/source/dev_manual/ci.rst index 92609ccd3..043edb1db 100644 --- a/docs/source/dev_manual/cicd_setup.rst +++ b/docs/source/dev_manual/ci.rst @@ -1,4 +1,64 @@ -.. dev_manual_cicd_setup:: +.. _developer_ci: + +Continous Integration +===================== + +Motivation +---------- + +Continous Integration (CI) systems are built to ensure that input and output files of each teams are + +- Correct +- Reproducable +- Consistent with other teams + +CI system is automatically triggered on + +- Main branch: the master branch of the codebase +- A pull request on main branch + +Workflows +--------- + +Principles +^^^^^^^^^^ + +Continous Integration system consists a number of workflows, each of which is designed to validate a specific aspect of the codebase. +For the work of each team, there is at least 1 dedicated workflow. + +Workflows can categorized in two types + +.. option:: Generation flow + + Such type of workflow is designed to ensure that golden files (netlists, bitstreams, etc.) are reproduciable. + A generation workflow consists of three steps: + + - Detect changes on input files, e.g., architecture files, IPs and related scripts. + + - If no changes detected, the workflow ends, since the golden outputs are not changed in a pull request + - If any changes are detected, the workflow will continue to the next steps + + - Regenerate golden files by calling scripts. By the end of this step, it will compare the newly generated files with the golden reference (current branch) + - If there are no changes, the workflow ends. + - If any changes on golden reference are detected, this will error out. It means that the current golden reference are not reproduciable. + + .. warning:: If any changes on golden references are detected, code review has to be enforced. Ensure that all the teams impacted agree on the changes. + +.. option:: Validation flow + + Such type of workflow is designed to verify the correctness of golden files + A validation workflow consists of three steps: + + - Detect changes on golden reference (some pull requests update golden references) + + - If no changes detected, the workflow ends. There is no need to validate the correctness of the golden reference (previous pull request should already do so). + - If any changes are detected, the workflow will continue to the next steps + + - Run validation by calling scripts. For example, verification may call HDL simulations to verify the correctness of netlists. + - If the new golden reference passes all the tests, this will end. + - If the new golden reference fails any test, this will error out. It means that the current golden reference can not meet basic requirements. + + .. warning:: If any validation flow failed, the pull request cannot be merged in general. CI/CD setup ----------- diff --git a/docs/source/dev_manual/contributor_guidelines/general_rules.rst b/docs/source/dev_manual/contributor_guidelines/general_rules.rst new file mode 100644 index 000000000..3df8e658b --- /dev/null +++ b/docs/source/dev_manual/contributor_guidelines/general_rules.rst @@ -0,0 +1,44 @@ +.. _developer_contributor_guidelines_general_rules: + +General Rules +============= + +Motivation +---------- +Github projects involve many parties with different interests. +It is necessary to establish rules to + +- guarantee the quality of each pull request by establishing a standard +- code review for each pull request is straightforward +- contributors have confidence when submitting changes + +Create Pull requests +-------------------- + +- Contributors should state clearly their motivation and the principles of code changes in each pull request +- Contributors should be active in resolving conflicts with other contributors as well as maintainers. In principle, all the maintainers want every pull request in and are looking for reasons to approve it. +- Each pull request should pass all the existing tests in CI (See :ref:`developer_contributor_guidelines_checkin_system` for details). Otherwise, it should not be merged unless you get a waiver from all the maintainers. +- Contributors should not modify any codes/tests which are unrelated to the scope of their pull requests. +- The size of each pull request should be small. Large pull request takes weeks to be merged. The recommend size of pull request is up to 500 lines of codes changes. If you have one large file, this can be waived. However, the number of files to be changed should be as small as possible. + + .. note:: For large pull requests, it is strongly recommended that contributors should talk to maintainers first or create an issue on the Github. Contributors should clearly define the motivation, detailed technical plan as well as deliverables. Through discussions, the technical plan may be requested to change. Please do not start code changes blindly before the technical plan is approved. + +- For any new feature/functionality to be added, there should be + + - Dedicated test cases in CI which validates its correctness + - An update on the documentation, if it changes user interface + - Provide sufficient code comments to ease the maintenance + +.. _developer_contributor_guidelines_checkin_system: + +Check-in System +--------------- + +.. seealso:: The check-in system is based on continous integration (CI). See details in :ref:`developer_ci` + +The check-in system aims to offer a standardized way to + +- ensure quailty of each contribution +- resolve conflicts between teams + +It is designed for efficient communication between teams. diff --git a/docs/source/dev_manual/contributor_guidelines/index.rst b/docs/source/dev_manual/contributor_guidelines/index.rst new file mode 100644 index 000000000..0fa7b108b --- /dev/null +++ b/docs/source/dev_manual/contributor_guidelines/index.rst @@ -0,0 +1,11 @@ +.. _developer_contributor_guidelines: + +Contributor Guidelines +====================== + +.. toctree:: + :maxdepth: 2 + + general_rules + + naming_convention diff --git a/docs/source/dev_manual/contributor_guidelines/naming_convention.rst b/docs/source/dev_manual/contributor_guidelines/naming_convention.rst new file mode 100644 index 000000000..34b775654 --- /dev/null +++ b/docs/source/dev_manual/contributor_guidelines/naming_convention.rst @@ -0,0 +1,224 @@ +.. _developer_naming_convention: + +Naming Convention +================= + +.. _developer_naming_convention_cell_names: + +Cell Names +---------- + +.. warning:: This is a different concept than the cell names in :ref:`developer_naming_convention_ff_model_names`! + +.. note:: we refer to standard cell wrapper here. Wrappers are built to make netlists portable between PDKs as well as across standard cell libraries in a PDK. + +For code readability, the cell name should follow the convention +:: + _ + +.. option:: Cell_Function + + Name of logic function, e.g., AND2, XNOR3, etc. + +.. option:: Set_Features + + This is mainly for sequential cells, e.g., D-type flip-flops. If a cell contains a set signal, its existence and polarity must be inferreable by the cell name. The available options are + + - S: Asynchronous active-high set + - SYNS: Synchronous active-hight set + - SN: Asynchronous active-low set + - SYNSN: Synchronous active-low set + + .. note:: For cells without set, this keyword should be empty + +.. option:: Reset_Features + + This is mainly for sequential cells, e.g., D-type flip-flops. If a cell contains a reset signal, its existence and polarity must be inferreable by the cell name. The available options are + + - R: Asynchronous active-high reset + - SYNR: Synchronous active-hight reset + - RN: Asynchronous active-low reset + - SYNRN: Synchronous active-low reset + + .. note:: For cells without reset, this keyword should be empty + +.. option:: Output_Features + + This is mainly for sequential cells, e.g., D-type flip-flops. + + - If not specified, the sequential cell contains a pair of differential outputs, e.g., ``Q`` and ``QN`` + - If specified, the sequential cell only contains single output, e.g., ``Q`` + + The available options are + + - Q: single output which is positive + - QN: single ouput which is negative + + .. note:: For cells without reset, this keyword should be empty + +.. option:: Drive_Strength + + This is to specify the drive strength of a cell + + - If not specified, we assume minimum drive strength, i.e., ``D0``. + - If specified, we expect a format of ``D``, where the integer indicates the drive strength + +.. option:: Wrapper + + This is to specify if the cell is a wrapper of an existing standard cell + + - If not specified, we assume this cell contains RTL + - If specified, we assume this cell is a wrapper of an existing standard cell + +A quick example +:: + NAND2D4_WRAPPER + +represents a wrapper for a standard cell that is a 2-input NAND gate with a drive strength of 4 + +Another example +:: + SDFFSSYNRNQ + +represents a scan-chain flip-flop which contains + + - Asynchronous active-high set + - Synchronous active-low reset + - Single output + +Pin Names +--------- + +.. note:: Please use lowercase as much as you can + +For code readability, the pin name should follow the convention +:: + _ + + +.. option:: Pin_Name + + Represents the pin name + +.. option:: Polarity + + Represents polarity of the pin, it can be + + - ``n`` denotes a negative-enable (active_low) signal + + .. note:: When not specified, by default we assume this is a postive-enable (active-high) signal + +.. option:: Direction + + Represents the direction of a pin, it can be + + - ``i`` denotes an input signal + - ``o`` denotes an output signal + +A quick example +:: + clk_ni + +represents an input clock signal which is negative-enable + +Another example +:: + q_no + +represents an output Q signal which is negative to the input + +.. _developer_naming_convention_ff_model_names: + +Flip-flop Model Names +--------------------- + +.. warning:: This is a different concept than the cell names in :ref:`developer_naming_convention_cell_names`! + +.. note:: we refer to virtual cell model (used by VPR and Yosys for cell mapping) here. + +For code readability, D-type flip-flop model names should follow the convention +:: + dff + +.. option:: Sync_Features + + Represents if the reset/set is synchronous or asynchronous to the clock, it can be + + - ``s`` denotes a synchronous behavior + - an empty string "" denotes an asynchronous behavior, e.g., ``ffr`` + +.. option:: Trigger_Type + + Represents if the flip-flop is triggered by rising edge or falling edge of a clock, it can be + + - ``n`` means triggered by failling edge + - an empty string "" means triggered by rising edge, e.g., ``ff`` + +.. option:: Set_Type + + Represents if the flip-flop has a set and the polarity of the set, it can be + + - ``s`` means that the flip-flop has an active-high set pin + - ``sn`` means that the flip-flop has an active-low set pin + - an empty string "" means the flip-flop does not have a set pin, e.g., ``ff`` + +.. option:: Reset_Type + + Represents if the flip-flop has a reset and the polarity of the reset, it can be + + - ``r`` means that the flip-flop has an active-high reset pin + - ``rn`` means that the flip-flop has an active-low reset pin + - an empty string "" means the flip-flop does not have a reset pin, e.g., ``ff`` + + +A quick example +:: + ffnrn + +represents a flip-flop + +- triggered by falling edge +- with an asynchronous active-low reset + +Another example +:: + sffs + +represents a flip-flop + +- triggered by rising edge +- with a synchronous active-high set + +.. _developer_naming_convention_mux_model_names: + +Multiplexer Model Names +----------------------- + +.. warning:: This is a different concept than the cell names in :ref:`developer_naming_convention_cell_names`! + +.. note:: Here, we refer to the circuit model name used in OpenFPGA architecture file. + +For code readability, a routing multiplexer circuit model name should follow the convention +:: + _mux_ + +.. option:: Location + + Represents the location of the routing multiplexers, it can be + + - ``cb`` denotes a routing multiplexer in a connection block + - ``sb`` denotes a routing multiplexer in a switch block + - ``pb`` denotes a routing multiplexer in a programmable block + +.. option:: Load + + Represents the output load condition of the routing multiplexers, it can be + + - ``highload`` means that the routing multiplexer has to drive a very high capacitive load, which potentially requires a big buffer at output + - an empty string "" means the routing multiplexer requires only a typical buffer size. + +A quick example +:: + pb_mux_highload + +represents a routing multiplexer used in a programmable block which drives a high capacitive load diff --git a/docs/source/dev_manual/index.rst b/docs/source/dev_manual/index.rst index 6f5fd58ba..0a86d4b12 100644 --- a/docs/source/dev_manual/index.rst +++ b/docs/source/dev_manual/index.rst @@ -1,16 +1,22 @@ +.. _developer: + Developer Guidelines .. toctree:: - :maxdepth: 1 + :maxdepth: 2 version_number back_compatible - contributor_guidelines - - cicd_setup + ci regression_tests tcl_api + +.. toctree:: + :maxdepth: 2 + :caption: Contributor Guidelines + + contributor_guidelines/index diff --git a/docs/source/manual/arch_lang/addon_vpr_syntax.rst b/docs/source/manual/arch_lang/addon_vpr_syntax.rst index b2c88992c..95a8eec64 100644 --- a/docs/source/manual/arch_lang/addon_vpr_syntax.rst +++ b/docs/source/manual/arch_lang/addon_vpr_syntax.rst @@ -88,6 +88,23 @@ Layout .. warning:: Do NOT enable ``shrink_boundary`` if you are not using the tileable routing resource graph generator! +.. option:: perimeter_cb="" + + Allow connection blocks to appear around the perimeter programmable block (mainly I/Os). This is designed to enhance routability of I/Os on perimeter. Also strongly recommended when programmable clock network is required to touch clock pins on I/Os. As illustrated in :numref:`fig_perimeter_cb`, routing tracks can access three sides of each I/O when perimeter connection blocks are created. + By default, it is ``false``. + +.. warning:: When enabled, please only place outputs at one side of I/Os. For example, outputs of an I/O on the top side can only occur on the bottom side of the I/O tile. Otherwise, routability loss may be expected, leading to some pins cannot be reachable. Enable the ``opin2all_sides`` to recover routability loss. + + .. _fig_perimeter_cb: + + .. figure:: ./figures/perimeter_cb.png + :width: 100% + :alt: Impact of perimeter_cb + + Impact on routing architecture when perimeter connection blocks are : (a) disabled; (b) enabled. + + .. warning:: Do NOT enable ``perimeter_cb`` if you are not using the tileable routing resource graph generator! + .. option:: opin2all_sides="" Allow each output pin of a programmable block to drive the routing tracks on all the sides of its adjacent switch block (see an illustrative example in :numref:`fig_opin2all_sides`). This can improve the routability of an FPGA fabric with an increase in the sizes of routing multiplexers in each switch block. diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst index 9fd1024a7..cd119f69a 100644 --- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst +++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst @@ -79,6 +79,7 @@ For subtile port merge support (see an illustrative example in :numref:`fig_subt .. note:: When defined, the given port of all the subtiles of a tile will be merged into one port. For example, a tile consists of 8 subtile ``A`` and 6 subtile ``B`` and all the subtiles have a port ``clk``, in the FPGA fabric, all the ``clk`` of the subtiles ``A`` and ``B`` will be wired to a common port ``clk`` at tile level. +.. note:: Note that when a dedicated clock network is defined, the size of the global port will follow the ``global_port`` defined in the clock network description file (See details in :ref:`file_formats_clock_network`) .. note:: When merged, the port will have a default side of ``TOP`` and index of ``0`` on all the attributes, such as width, height etc. @@ -99,6 +100,8 @@ For global port support: - ``clock_arch_tree_name=""`` defines the name of the programmable clock network, which the global port will drive. The name of the programmable clock network must be a valid name (See details in :ref:`file_formats_clock_network`) +.. note:: ``clock_arch_tree_name`` is applicable to clock, reset and set signals. + - ``is_reset=""`` define if the global port is a reset port at the top-level FPGA fabric. An operating reset port will be driven by proper signals in testbenches. - ``is_set=""`` define if the global port is a set port at the top-level FPGA fabric. An operating set port will be driven by proper signals in testbenches. diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 4ec803f99..0e515b84b 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -53,6 +53,7 @@ Here, we focus these common syntax and we will detail special syntax in :ref:`ci + @@ -129,12 +130,16 @@ Input and Output Buffers Pass Gate Logic ^^^^^^^^^^^^^^^ +.. note:: pass-gate logic are used in building multiplexers and LUTs. + .. option:: - ``circuit_model_name=""`` Specify the name of the circuit model which is used to implement pass-gate logic, the type of specified circuit model should be ``pass_gate``. -.. note:: pass-gate logic are used in building multiplexers and LUTs. +.. option:: + + - ``circuit_model_name=""`` Specify the name of the circuit model which is used to implement the pass-gate logic at last stage of multiplexer, the type of specified circuit model should be ``pass_gate``. The type of the pass-gate logic circuit model must be a standard cell MUX2! .. _circuit_library_circuit_port: diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index 94f1d5e02..5bc928c6c 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -619,6 +619,14 @@ This example shows: Standard Cell Multiplexer ````````````````````````` +.. _fig_stdcellmux: + +.. figure:: ./figures/stdcellmux.png + :width: 100% + :alt: Examples of MUX built with standard cells + + An example of a multiplexer built with standard cells: (a) all the MUX2 are the same; (b) the MUX2 at the last stage is a different one + .. code-block:: xml @@ -631,12 +639,34 @@ Standard Cell Multiplexer -This example shows: +This example shows (see an illustative example in :numref:`fig_stdcellmux` (a)): - A tree-like 4-input CMOS multiplexer built by the standard cell ``MUX2`` - All the inputs will be buffered using the circuit model ``inv1x`` - All the outputs will be buffered using the circuit model ``tapbuf4`` - The multiplexer will have 4 inputs and 3 SRAMs to control which datapath to propagate +Alternatively, user can specify a different standard cell MUX2 at the last stage. + +.. code-block:: xml + + + + + + + + + + + + +This example shows (see an illustative example in :numref:`fig_stdcellmux` (b)): + - A tree-like 4-input CMOS multiplexer built by the standard cell ``MUX2`` + - The last stage A tree-like 4-input CMOS multiplexer built by the standard cell ``MUX2`` + - All the inputs will be buffered using the circuit model ``inv1x`` + - All the outputs will be buffered using the circuit model ``tapbuf4`` + - The multiplexer will have 4 inputs and 3 SRAMs to control which datapath to propagate + .. _circuit_model_mux_multilevel_example: Multi-level Multiplexer diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst index d4d4d052e..f1a816eb3 100644 --- a/docs/source/manual/arch_lang/config_protocol.rst +++ b/docs/source/manual/arch_lang/config_protocol.rst @@ -7,6 +7,17 @@ Configuration protocol is the circuitry designed to program an FPGA. As an interface, configuration protocol could be really different in FPGAs, depending on the application context. OpenFPGA supports versatile configuration protocol, providing different trade-offs between speed and area. +Under configuration protocol, if the configuration is QL Memory Bank with flatten BL/WL protocol, there might be +optional configuration setting call . +In QL Memory Bank configuration protocol, configuration bits are organized as BitLine (BL) x WordLine (WL) +By default, OpenFPGA will keep BL and WL in square shape if possible where BL might be one bit longer than WL in some cases + For example: + - If the configuration bits of a PB is 9 bits, then BL=3 and WL=3 + - If the configuration bits of a PB is 11 bits, then BL=4 and WL=3 (where there is one extra bit as phantom bit) + - If the configuration bits of a PB is 14 bits, then BL=4 and WL=4 (where there is two extra bits as phantom bits) + +This QL Memory Bank configuration setting allow OpenFPGA to use a fixed WL size, instead of default approach + Template ~~~~~~~~ @@ -14,6 +25,9 @@ Template + + + .. option:: type="scan_chain|memory_bank|standalone|frame_based|ql_memory_bank" @@ -54,6 +68,29 @@ Template .. note:: For ``ql_memory_bank`` configuration protocol when BL/WL protocol ``shift_register`` is selected, different configuration regions **cannot** share any WLs on the same row! In such case, the default fabric key may not work. Strongly recommend to craft your own fabric key based on your configuration region plannning! +.. option:: name="" + + Specify the name of PB type, for example: clb, dsp, bram and etc + +.. option:: num_wl="" + + Fix the size of WL + + For example: + Considered that the configuration bits of a PB is 400 bits. + + If num_wl is not defined, then + - BL will be 20 [=ceiling(square_root(400))] + - WL will be 20 [=ceiling(400/20)] + + If num_wl is defined as 10, then + - WL will be fixed as 10 + - BL will be 40 [=ceiling(400/10)] + + If num_wl is defined as 32, then + - WL will be fixed as 32 + - BL will be 13 [=ceiling(400/32)] + - There will be 16 bits [=(32x13)-400] as phantom bits. Configuration Chain Example ~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/source/manual/arch_lang/direct_interconnect.rst b/docs/source/manual/arch_lang/direct_interconnect.rst index 21b91b74b..5024171cb 100644 --- a/docs/source/manual/arch_lang/direct_interconnect.rst +++ b/docs/source/manual/arch_lang/direct_interconnect.rst @@ -1,12 +1,12 @@ .. _direct_interconnect: -Inter-Tile Direct Interconnection extensions --------------------------------------------- +Direct Interconnect +------------------- -This section introduces extensions on the architecture description file about existing interconnection description. +This section introduces extensions on the architecture description file about direct connections between programmable blocks. -Directlist -~~~~~~~~~~ +Syntax +~~~~~~ The original direct connections in the directlist section are documented here_. Its description is given below: @@ -20,20 +20,26 @@ The original direct connections in the directlist section are documented here_. .. note:: These options are required -Our extension include three more options: +In the OpenFPGA architecture file, you may define additional attributes for each VPR's direct connection: .. code-block:: xml - - + + -.. note:: these options are optional. However, if `interconnection_type` is set `x_dir` and `y_dir` are required. +.. note:: these options are optional. However, if ``interconnection_type`` is set to ``inter_column`` or ``inter_row``, then ``x_dir`` and ``y_dir`` are required. .. option:: interconnection_type="" - the type of interconnection should be a string. - Available types are ``NONE`` | ``column`` | ``row``, specifies if it applies on a column or a row ot if it doesn't apply. + Available types are ``inner_column_or_row`` | ``part_of_cb`` | ``inter_column`` | ``inter_row`` + + - ``inner_column_or_row`` indicates the direct connections are between tiles in the same column or row. This is the default value. + - ``part_of_cb`` indicates the direct connections will drive routing multiplexers in connection blocks. Therefore, it is no longer a strict point-to-point direct connection. + - ``inter_column`` indicates the direct connections are between tiles in two columns + - ``inter_row`` indicates the direct connections are between tiles in two rows + +.. note:: The following syntax is only applicable to ``inter_column`` and ``inter_row`` .. option:: x_dir="" @@ -42,15 +48,15 @@ Our extension include three more options: - x_dir="positive": - - interconnection_type="column": a column will be connected to a column on the ``right``, if it exists. + - interconnection_type="inter_column": a column will be connected to a column on the ``right``, if it exists. - - interconnection_type="row": the most on the ``right`` cell from a row connection will connect the most on the ``left`` cell of next row, if it exists. + - interconnection_type="inter_row": the most on the ``right`` cell from a row connection will connect the most on the ``left`` cell of next row, if it exists. - x_dir="negative": - - interconnection_type="column": a column will be connected to a column on the ``left``, if it exists. + - interconnection_type="inter_column": a column will be connected to a column on the ``left``, if it exists. - - interconnection_type="row": the most on the ``left`` cell from a row connection will connect the most on the ``right`` cell of next row, if it exists. + - interconnection_type="inter_row": the most on the ``left`` cell from a row connection will connect the most on the ``right`` cell of next row, if it exists. .. option:: y_dir="" @@ -59,27 +65,96 @@ Our extension include three more options: - y_dir="positive": - - interconnection_type="column": the ``bottom`` cell of a column will be connected to the next column ``top`` cell, if it exists. + - interconnection_type="inter_column": the ``bottom`` cell of a column will be connected to the next column ``top`` cell, if it exists. - - interconnection_type="row": a row will be connected on an ``above`` row, if it exists. + - interconnection_type="inter_row": a row will be connected on an ``above`` row, if it exists. - y_dir="negative": - - interconnection_type="column": the ``top`` cell of a column will be connected to the next column ``bottom`` cell, if it exists. + - interconnection_type="inter_column": the ``top`` cell of a column will be connected to the next column ``bottom`` cell, if it exists. - - interconnection_type="row": a row will be connected on a row ``below``, if it exists. + - interconnection_type="inter_row": a row will be connected on a row ``below``, if it exists. -Example -~~~~~~~ +Enhanced Connection Block +~~~~~~~~~~~~~~~~~~~~~~~~~ -For this example, we will study a scan-chain implementation. The description could be: +The direct connection can also drive routing multiplexers of connection blocks. When such connection occures in a connection block, it is called enhanced connection block. +:numref:`fig_ecb` illustrates the difference between a regular connection block and an enhanced connection block. + +.. _fig_ecb: + +.. figure:: ./figures/ecb.png + + Enhanced connection block vs. Regular connection block + +In such scenario, the type ``part_of_cb`` is required. + +.. warning:: Restrictions may be applied when building the direct connections as part of a connection block. + +Direct connections can be inside a tile or across two tiles. Currently, across more than two tiles are not supported! +:numref:`fig_ecb_allowed_direct_connection` illustrates the region (in red) where any input pin is allowed to be driven by any output pin. + +.. _fig_ecb_allowed_direct_connection: + +.. figure:: ./figures/ecb_allowed_direct_connection.png + + Allowed connections inside a tile for enhanced connection block (see the highlighted region) + +:numref:`fig_ecb_allowed_direct_connection_inner_tile_example` shows a few feedback connections which can be built inside connection blocks. Note that feedback connections are fully allowed between any pins on the same side of a programmable block. + +.. _fig_ecb_allowed_direct_connection_inner_tile_example: + +.. figure:: ./figures/ecb_allowed_direct_connection_inner_tile_example.png + + Example of feedback connections inside a tile for enhanced connection block + +For instance, VPR architecture defines feedback connections like: .. code-block:: xml - + + + +:numref:`fig_ecb_allowed_direct_connection_inter_tile_example` shows a few inter-tile connections which can be built inside connection blocks. Note that inter-tile connections are subjected to the restrictions depicted in :numref:`fig_ecb_allowed_direct_connection` + +.. _fig_ecb_allowed_direct_connection_inter_tile_example: + +.. figure:: ./figures/ecb_allowed_direct_connection_inter_tile_example.png + + Example of connections across two tiles for enhanced connection block + +:numref:`fig_ecb_forbid_direct_connection_example` illustrates some inner-tile and inter-tile connections which are not allowed. Note that feedback connections across different sides are restricted! + +.. _fig_ecb_forbid_direct_connection_example: + +.. figure:: ./figures/ecb_forbid_direct_connection_example.png + + Restrictions on building direct connections as part of a connection block + +Inter-tile Connections +~~~~~~~~~~~~~~~~~~~~~~ + +For this example, we will study a scan-chain implementation. The description could be: + +In VPR architecture: + +.. code-block:: xml + + + + + +In OpenFPGA architecture: + +.. code-block:: xml + + + + + :numref:`fig_p2p_exple` is the graphical representation of the above scan-chain description on a 4x4 FPGA. .. _fig_p2p_exple: @@ -91,9 +166,6 @@ For this example, we will study a scan-chain implementation. The description cou In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB. -Truth table -~~~~~~~~~~~ - A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below. :numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate. diff --git a/docs/source/manual/arch_lang/figures/ecb.png b/docs/source/manual/arch_lang/figures/ecb.png new file mode 100644 index 000000000..5a6afd99c Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb.png differ diff --git a/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png new file mode 100644 index 000000000..35dddf336 Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png differ diff --git a/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inner_tile_example.png b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inner_tile_example.png new file mode 100644 index 000000000..30db9d640 Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inner_tile_example.png differ diff --git a/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inter_tile_example.png b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inter_tile_example.png new file mode 100644 index 000000000..d3baa9ee3 Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inter_tile_example.png differ diff --git a/docs/source/manual/arch_lang/figures/ecb_forbid_direct_connection_example.png b/docs/source/manual/arch_lang/figures/ecb_forbid_direct_connection_example.png new file mode 100644 index 000000000..ba936335a Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb_forbid_direct_connection_example.png differ diff --git a/docs/source/manual/arch_lang/figures/perimeter_cb.png b/docs/source/manual/arch_lang/figures/perimeter_cb.png new file mode 100644 index 000000000..e3a658338 Binary files /dev/null and b/docs/source/manual/arch_lang/figures/perimeter_cb.png differ diff --git a/docs/source/manual/arch_lang/figures/stdcellmux.png b/docs/source/manual/arch_lang/figures/stdcellmux.png new file mode 100644 index 000000000..d2d08c7b1 Binary files /dev/null and b/docs/source/manual/arch_lang/figures/stdcellmux.png differ diff --git a/docs/source/manual/file_formats/bitstream_setting.rst b/docs/source/manual/file_formats/bitstream_setting.rst index 764bf0c87..d46751a14 100644 --- a/docs/source/manual/file_formats/bitstream_setting.rst +++ b/docs/source/manual/file_formats/bitstream_setting.rst @@ -13,6 +13,12 @@ This can define a hard-coded bitstream for a reconfigurable resource in FPGA fab + + + + + + pb_type-related Settings @@ -39,7 +45,6 @@ The following syntax are applicable to the XML definition tagged by ``pb_type`` .. option:: content="" The content of the ``pb_type`` bitstream, which could be a keyword in a ``.eblif`` file. For example, ``content=".attr LUT"`` means that the bitstream will be extracted from the ``.attr LUT`` line which is defined under the ``.blif model`` (that is defined under the ``pb_type`` in VPR architecture file). - .. option:: is_mode_select_bitstream="" @@ -71,3 +76,72 @@ The following syntax are applicable to the XML definition tagged by ``interconne The default path can be either ``iopad.inpad`` or ``ff.Q`` which corresponds to the first input and the second input respectively. + +non_fabric-related Settings +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This is special syntax to extract PB defined parameter or attribute and save the data into dedicated JSON file outside of fabric bitstream + +The following syntax are applicable to the XML definition tagged by ``non_fabric`` in bitstream setting files. + +.. option:: name="" + + The ``pb_type`` top level name that the data to be extracted. For example, + + .. code-block:: xml + + name="bram" + +.. option:: file="" + + The filepath the data is saved to. For example, + + .. code-block:: xml + + file="bram.json" + +.. option:: pb child element name="" + + Together with ``pb_type`` top level name, that is the source of the ``pb_type`` bitstream + + The final ``pb_type`` name is "" + "" + + For example, + + .. code-block:: xml + + + + + The final ``pb_type`` name is "bram.bram_lr[mem_36K_tdp].mem_36K" + +.. option:: pb child element content="" + + The content of the ``pb_type`` data to be extracted. For example, ``content=".param INIT_i"`` means that the data will be extracted from the ``.param INIT_i`` line defined under the ``.blif model``. + +overwrite_bitstream-related Settings +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This is to allow user to set value of a list of bits which is represented using full path in the hierarchy of FPGA fabric + +This ``overwrite_bitstream`` settings has the highest priority than loading any external bitstream file + +Each bit to overwrite is represented by one ``bit`` child node/tag + +The following syntax are applicable to the XML definition tagged by ``bit`` node under ``overwrite_bitstream`` setting. + +.. option:: value="<0 or 1>" + + The boolean ``0`` or ``1`` that will be set. For example, + + .. code-block:: xml + + value="0" + +.. option:: path="" + + ``path`` represents the location of this block in FPGA fabric, i.e., the full path in the hierarchy of FPGA fabric. + + .. code-block:: xml + + path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5[0]" diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index 9d6baad98..c1fa9c695 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -14,6 +14,8 @@ Using the clock network description language, users can define multiple clock ne - A number of switch points which interconnects clock spines using programmable routing switches. See details in :ref:`file_formats_clock_network_switch_point`. - A number of tap points which connect the clock spines to programmable blocks, e.g., CLBs. See details in :ref:`file_formats_clock_network_tap_point`. +The entry point of a clock tree must be at a valid connection block. + .. note:: Please note that the levels of a clock network will be automatically inferred from the clock spines and switch points. Clock network will be **only** built based on the width and the number of levels, as well as the tap points. .. note:: The switch points and clock spines will be used to route a clock network. The switch points will not impact the physical clock network but only impact the configuration of the programmable routing switches in the physical clock network. @@ -22,17 +24,43 @@ Using the clock network description language, users can define multiple clock ne .. code-block:: xml - - + + - + + + + + + - + + + +.. _fig_prog_clock_network_example_2x2: + +.. figure:: figures/prog_clk_network_example_2x2.png + :width: 100% + :alt: An example of programmable clock network considering a 2x2 FPGA fabric + + An example of programmable clock network considering a 2x2 FPGA fabric + +Note that when the ``perimeter_cb`` is enabled for routing architecture (See details in :ref:`addon_vpr_syntax`), clock entry point can be indeed at the fringe of FPGA fabrics. See example in :numref:`prog_clock_network_example_2x2_perimeter_cb`. + +.. _fig_prog_clock_network_example_2x2_perimeter_cb: + +.. figure:: figures/prog_clk_network_example_2x2_perimeter_cb.png + :width: 100% + :alt: An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb + + An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb + + General Settings ^^^^^^^^^^^^^^^^ @@ -40,7 +68,7 @@ The following syntax are applicable to the XML definition under the root node `` .. option:: default_segment="" - Define the default routing segment to be used when building the routing tracks for the clock network. Must be a valid routing segment defined in the VPR architecture file. For example, + Define the default routing segment to be used when building the routing tracks for the clock network. The routing segments are used to build the spines of clock networks as shown in :numref:`fig_prog_clock_network_example_2x2`. Must be a valid routing segment defined in the VPR architecture file. For example, .. code-block:: xml @@ -56,23 +84,30 @@ where the segment is defined in the VPR architecture file: .. note:: Currently, clock network requires only length-1 wire segment to be used! -.. option:: default_switch="" +.. option:: default_tap_switch="" - Define the default routing switch to be used when interconnects the routing tracks in the clock network. Must be a valid routing switch defined in the VPR architecture file. For example, + Define the default routing switch to be used when interconnects the routing tracks to the input pins of programmable blocks in the clock network. The tap switches are used to build the taps of clock networks as shown in :numref:`fig_prog_clock_network_example_2x2`. Must be a valid routing switch defined in the VPR architecture file. See the example in the ``default_driver_switch``. + +.. option:: default_driver_switch="" + + .. note:: For internal drivers, suggest to use the same driver switch for the output pins of a programmable block as defined in VPR architecture. + + Define the default routing switch to be used when interconnects the routing tracks in the clock network. The driver switches are used to build the switch points of clock networks as shown in :numref:`fig_prog_clock_network_example_2x2`. Must be a valid routing switch defined in the VPR architecture file. For example, .. code-block:: xml - default_switch="clk_mux" + default_tap_switch="cb_mux" default_driver_switch="sb_clk_mux" where the switch is defined in the VPR architecture file: .. code-block:: xml - + + -.. note:: Currently, clock network only supports one type of routing switch, which means all the programmable routing switch in the clock network will be in the same type and circuit design topology. +.. note:: Currently, clock network only supports the default types of routing switch, which means all the programmable routing switch in the clock network will be in the same type and circuit design topology. Clock Network Settings ^^^^^^^^^^^^^^^^^^^^^^ @@ -94,13 +129,18 @@ where the clock network is used to drive the global clock pin ``clk0`` in OpenFP - -.. option:: width="" +.. option:: global_port="" - The maximum number of clock pins that a clock network can drive. + .. note:: When programmable clock network is specified for a global port in OpenFPGA architecure description file, the width of clock tree will be the final size of the global port. + + Define the source port of the clock network. For example, ``clk[0:7]``. Note that the global port name should match + + - the ``from_pin`` when defining the tap points (See details in :ref:`file_formats_clock_network_clock_tap_point`). + - the ``name`` of global port definition in OpenFPGA architecture description file .. _file_formats_clock_network_clock_spine: @@ -110,6 +150,8 @@ Clock Spine Settings The following syntax are applicable to the XML definition tagged by ``spine``. Note that a number of clock spines can be defined under the node ``clock_network``. +.. note:: Use coordinates of connection blocks to define the starting and ending points of clock spines. + .. option:: name="" The unique name of the clock spine. It will be used to build switch points between other clock spines. @@ -136,10 +178,66 @@ For example, -where a horizental clock spine ``spine0`` is defined which spans from (1, 1) to (2, 1) +where a horizental clock spine ``spine0`` is defined which spans from (1, 1) to (2, 1), as highlighted in orange in the :numref:`fig_prog_clock_network_example_2x2` .. note:: We only support clock spines in horizental and vertical directions. Diagonal clock spine is not supported! +.. _file_formats_clock_network_intermediate_driver: + +Intermediate Driver +^^^^^^^^^^^^^^^^^^^ + +The following syntax are applicable to the XML definition tagged by ``intermediate_driver`` +Note that a number of intermediate drivers can be defined under each clock spine ``spine``. + +.. option:: x="" + + The coordinate X where the intermediate driver should occur on the spine. Must be a valid coordinate within the range of the current clock spine and the clock spine to be tapped. + +.. option:: y="" + + The coordinate Y where the intermediate driver should occur on the spine. Must be a valid coordinate within the range of the current clock spine and the clock spine to be tapped. + +.. note:: The intermeidate driver is different than the internal driver (see details in :ref:`file_formats_clock_network_switch_point`). Intermediate driver may occur in any mid points of a spine, while internal driver occurs **ONLY** on the switch points between spines. + +Under each intermediate driver, a number of tap points can be specified. +For each tap point, outputs of neighbouring programmable blocks are allowed to drive the spine through syntax ``tap``. + +.. option:: from_pin="" + + Define the pin of a programmable block as an internal driver to a clock network. The pin must be a valid pin defined in the VPR architecture description file. + +.. option:: to_pin="" + + Define the source pin of a clock network. The pin must be a valid pin of the global ports defined in the tile_annotation part of OpenFPGA architecture description file. + +For example, + +.. code-block:: xml + + + + + + + + + + + +where clock spine ``spine0`` will be driven by other programmable blocks at (1, 1), as highlighted in purple in the :numref:`fig_prog_clock_network_example_2x2_perimeter_cb` + +To be specific, the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file: + +.. code-block:: xml + + + + + + + + .. _file_formats_clock_network_switch_point: Switch Point Settings @@ -148,6 +246,8 @@ Switch Point Settings The following syntax are applicable to the XML definition tagged by ``switch_point``. Note that a number of switch points can be defined under each clock spine ``spine``. +.. note:: Use the coordinate of switch block to define switching points! + .. option:: tap="" Define which clock spine will be tapped from the current clock spine. @@ -168,40 +268,126 @@ For example, -where clock spine ``spine0`` will drive another clock spine ``spine1`` at (1, 1). +where clock spine ``spine0`` will drive another clock spine ``spine1`` at (1, 1), as highlighted in blue in the :numref:`fig_prog_clock_network_example_2x2` + +For each switch point, outputs of neighbouring programmable blocks are allowed to drive the spine at next level, through syntax ``internal_driver``. + +.. option:: from_pin="" + + Define the pin of a programmable block as an internal driver to a clock network. The pin must be a valid pin defined in the VPR architecture description file. + +.. option:: to_pin="" + + Define the source pin of a clock network. The pin must be a valid pin of the global ports defined in the tile_annotation part of OpenFPGA architecture description file. + +For example, + +.. code-block:: xml + + + + + + + + + + +where the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file: + +.. code-block:: xml + + + + + + + .. _file_formats_clock_network_tap_point: Tap Point Settings ^^^^^^^^^^^^^^^^^^ -The following syntax are applicable to the XML definition tagged by ``tap``. +The following syntax are applicable to the XML definition tagged by ``all``, ``region`` and ``single``. Note that a number of tap points can be defined under the node ``taps``. -.. option:: tile_pin="" +.. option:: from_pin="" - Define the pin of a programmable block to be tapped by a clock network. The pin must be a valid pin defined in the VPR architecture description file. + Define the source pin of a programmable block to be tapped by a clock network. The pin must be a valid pin of the global ports defined in the tile_annotation part of OpenFPGA architecture description file. + +.. option:: to_pin="" + + Define the destination pin of a programmable block to be tapped by a clock network. The pin must be a valid pin defined in the VPR architecture description file. .. note:: Only the leaf clock spine (not switch points to drive other clock spine) can tap pins of programmable blocks. +.. note:: Each coordinate must be a valid integer within the device height and width that are defined in VPR architecture!!! + +.. warning:: The following syntax are only applicable to ``single`` tap mode. + +.. option:: x="" + + Define the x coordinate of the tap point, which is applied to the destination pin ``to_pin`` + +.. option:: y="" + + Define the y coordinate of the tap point, which is applied to the destination pin ``to_pin`` + +.. warning:: The following syntax are only applicable to ``region`` tap mode. + +.. option:: start_x="" + + Define the starting x coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: start_y="" + + Define the starting y coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: end_x="" + + Define the ending x coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: end_y="" + + Define the ending y coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: repeat_x="" + + Define the repeating factor on x coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: repeat_y="" + + Define the repeating factor on y coordinate of the tap region, which is applied to the destination pin ``to_pin`` + For example, .. code-block:: xml - + - + + + where all the clock spines of the clock network ``clk_tree_0`` tap the clock pins ``clk`` of tile ``clb`` in a VPR architecture description file: +.. note:: Use the name of ``tile`` in the ``to_pin`` when there are a number of subtiles in your tile! Use the absolute index for the subtile in the tile. + .. code-block:: xml - - + + + + + + + + diff --git a/docs/source/manual/file_formats/fabric_hierarchy_file.rst b/docs/source/manual/file_formats/fabric_hierarchy_file.rst new file mode 100644 index 000000000..0d717afd3 --- /dev/null +++ b/docs/source/manual/file_formats/fabric_hierarchy_file.rst @@ -0,0 +1,62 @@ +.. _file_format_fabric_hierarchy_file: + +Fabric Hierarchy File (.yaml) +---------------------------------------- + +This file is generated by command :ref:`openfpga_setup_commands_write_fabric_hierarchy` + + +The fabric hierarchy file aims to show module trees of a number of given roots + +This file is created for netlist manipulation and detailed floorplanning during physical design steps + +By using the options of the command :ref:`openfpga_setup_commands_write_fabric_hierarchy`, user can selectively output the module tree on their needs. + +An example of the file is shown as follows. + +.. code-block:: yaml + + fpga_top: + tile_0__2_: + sb_0__1_: + mux_tree_tapbuf_size2: + INVTX1 + const1 + tap_buf4 + mux_tree_tapbuf_basis_input2_mem1: + - TGATE + mux_tree_tapbuf_size2_feedthrough_mem + sb_1__config_group_mem_size40: + mux_tree_tapbuf_size2_mem: + - DFF + tile_1__2_: + grid_io_top: + logical_tile_io_mode_io_: + logical_tile_io_mode_physical__iopad: + - GPIO + - GPIO_feedthrough_DFF_mem + direct_interc + +In this example, the root module is ``fpga_top``. +The child modules under ``fpga_top`` are ``tile_0__2_`` and ``tile_1__2_``. +Note that the leaf nodes are shown as a list, e.g., ``GPIO`` and ``GPIO_feedthrough_DFF_mem``. + +When multiple root modules are defined, the output could be + +.. code-block:: yaml + + sb_0__1_: + - mux_tree_tapbuf_size2 + sb_1__0_: + - mux_tree_tapbuf_size2 + sb_1__1_: + - mux_tree_tapbuf_size2 + cbx_1__0_: + - mux_tree_tapbuf_size4 + cbx_1__1_: + - mux_tree_tapbuf_size4 + cby_0__1_: + - mux_tree_tapbuf_size2 + - mux_tree_tapbuf_size4 + cby_1__1_: + - mux_tree_tapbuf_size4 diff --git a/docs/source/manual/file_formats/fabric_pin_physical_location_file.rst b/docs/source/manual/file_formats/fabric_pin_physical_location_file.rst new file mode 100644 index 000000000..ee24916e7 --- /dev/null +++ b/docs/source/manual/file_formats/fabric_pin_physical_location_file.rst @@ -0,0 +1,109 @@ +.. _file_format_fabric_pin_physical_location_file: + +Fabric Pin Physical Location File (.xml) +---------------------------------------- + +This file is generated by command :ref:`openfpga_setup_commands_write_fabric_pin_physical_location` + + +The fabric pin physical location file aims to show + +- Pin names of each module in an eFPGA fabric +- Preferred physical side of each pin on its module + +This file is created for pin guidelines during physical design steps + +An example of the file is shown as follows. + +.. code-block:: xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +.. option:: name="" + + The module name in FPGA fabric, which should be a valid module defined in output Verilog netlist. + + .. note:: You should be find the exact module in the FPGA fabric if you output the Verilog netlists. + +.. option:: pin="" + + The name of the pin in FPGA fabric. Note that all the bus port will be flatten in this file. + + .. note:: You should be find the exact pin in the module if you output the Verilog netlists. + +.. option:: side="" + + The physical side of the pin should appear on the perimeter of the module. diff --git a/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2.png b/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2.png new file mode 100644 index 000000000..eae255144 Binary files /dev/null and b/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2.png differ diff --git a/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png b/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png new file mode 100644 index 000000000..4ec057d1c Binary files /dev/null and b/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png differ diff --git a/docs/source/manual/file_formats/figures/tile_style_bottom_left.png b/docs/source/manual/file_formats/figures/tile_style_bottom_left.png new file mode 100644 index 000000000..393eab862 Binary files /dev/null and b/docs/source/manual/file_formats/figures/tile_style_bottom_left.png differ diff --git a/docs/source/manual/file_formats/index.rst b/docs/source/manual/file_formats/index.rst index 6ec94c3b9..e7151f99b 100644 --- a/docs/source/manual/file_formats/index.rst +++ b/docs/source/manual/file_formats/index.rst @@ -41,3 +41,11 @@ OpenFPGA widely uses XML format for interchangeable files module_naming_file tile_config_file + + fabric_pin_physical_location_file + + fabric_hierarchy_file + + reference_file + + unique_blocks diff --git a/docs/source/manual/file_formats/reference_file.rst b/docs/source/manual/file_formats/reference_file.rst new file mode 100644 index 000000000..1a57939a8 --- /dev/null +++ b/docs/source/manual/file_formats/reference_file.rst @@ -0,0 +1,80 @@ +.. _file_format_reference_file: + +Reference File (.yaml) +---------------------------------------- + +This file is generated by command :ref:`openfpga_setup_commands_report_reference` + + +The reference file aims to the show reference number of each child module of given parent module + +By using the options of the command :ref:`openfpga_setup_commands_report_reference`, user can selectively output the reference info under the given parent module on their needs. + +An example of the file is shown as follows. + +.. code-block:: yaml + + Date: Mon Sep 9 16:41:53 2024 + + #the instance names are given during netlist generation + + references: + - module: grid_io_top + count: 1 + instances: + - grid_io_top_1__2_ + - module: grid_io_right + count: 1 + instances: + - grid_io_right_2__1_ + - module: grid_io_bottom + count: 1 + instances: + - grid_io_bottom_1__0_ + - module: grid_io_left + count: 1 + instances: + - grid_io_left_0__1_ + - module: grid_clb + count: 1 + instances: + - grid_clb_1__1_ + - module: sb_0__0_ + count: 1 + instances: + - sb_0__0_ + - module: sb_0__1_ + count: 1 + instances: + - sb_0__1_ + - module: sb_1__0_ + count: 1 + instances: + - sb_1__0_ + - module: sb_1__1_ + count: 1 + instances: + - sb_1__1_ + - module: cbx_1__0_ + count: 1 + instances: + - cbx_1__0_ + - module: cbx_1__1_ + count: 1 + instances: + - cbx_1__1_ + - module: cby_0__1_ + count: 1 + instances: + - cby_0__1_ + - module: cby_1__1_ + count: 1 + instances: + - cby_1__1_ + +In this example, the parent module is ``fpga_top``. +The child modules under ``fpga_top`` are ``grid_io_top``, ``grid_io_right``, and etc. + +The instance of the child module ``grid_io_top`` is shown as a list as below: + - grid_io_top_1__2_ + diff --git a/docs/source/manual/file_formats/tile_config_file.rst b/docs/source/manual/file_formats/tile_config_file.rst index c3dfcbbce..f9c94664f 100644 --- a/docs/source/manual/file_formats/tile_config_file.rst +++ b/docs/source/manual/file_formats/tile_config_file.rst @@ -24,10 +24,12 @@ Detailed syntax are presented as follows. Specify the style of tile organization. Can be [``top_left`` | ``top_right`` | ``bottom_left`` | ``bottom_right`` | ``custom``] - .. warning:: Currently, only ``top_left`` is supported! + .. warning:: Currently, only ``top_left`` and ``bottom_left`` are supported! The ``top_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_top_left` shows an example of tiles in the top-left sytle, where the programmable block locates in the top-left corner of all the tiles, surrounded by two connection blocks and one switch blocks. + The ``bottom_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_bottom_left` shows an example of tiles in the bottom-left sytle, where the programmable block locates in the bottom-left corner of all the tiles, surrounded by two connection blocks and one switch blocks. + .. _fig_tile_style_top_left: .. figure:: ./figures/tile_style_top_left.png @@ -37,3 +39,12 @@ Detailed syntax are presented as follows. An example of top-left style of a tile in FPGA fabric +.. _fig_tile_style_bottom_left: + +.. figure:: ./figures/tile_style_bottom_left.png + :width: 100% + :alt: An example of bottom-left style of tile + + An example of bottom-left style of a tile in FPGA fabric + + diff --git a/docs/source/manual/file_formats/unique_blocks.rst b/docs/source/manual/file_formats/unique_blocks.rst new file mode 100644 index 000000000..ace724cc4 --- /dev/null +++ b/docs/source/manual/file_formats/unique_blocks.rst @@ -0,0 +1,50 @@ +.. _file_formats_unique_blocks: + +Unique Blocks (.xml) +-------------------- + +A unique blocks file is formatted in XML. The unique blocks can be of type ``cbx``, ``cby``, or ``sb``. As illustrated by the XML code below, the file includes the type and coordinates of these unique blocks, as well as the coordinates of their corresponding instances. + +Configurable Block +~~~~~~~~~~~~~~~~~~ + +Unique blocks can be applied to various blocks, each of which can be of type ``cbx``, ``cby``, or ``sb``, and may have different coordinates. + +.. note:: + + For each block, a set of keys can be defined. For unique blocks, both keys and instances can be specified. However, if a unique block does not have an instance, only keys are permitted. + + - ``type`` specifies the type of the unique block in the FPGA fabric. Valid values for ``type`` are ``cbx``, ``cby``, or ``sb``. + - ``x`` represents the x-coordinate of the unique block. + - ``y`` represents the y-coordinate of the unique block. + +Configurable Instance +~~~~~~~~~~~~~~~~~~~~~ + +A specific unique block can have multiple instances, where each instance is a mirrored version of the unique block. Each instance shares the same type as its parent block and includes information about its coordinates. + +.. note:: + + - ``x`` specifies the x-coordinate of the instance. + - ``y`` specifies the y-coordinate of the instance. + +The following content provides an example of a unique block file: + +.. code-block:: xml + + + + + + + + + + + + + + + + + diff --git a/docs/source/manual/openfpga_flow/run_fpga_task.rst b/docs/source/manual/openfpga_flow/run_fpga_task.rst index 366e9bd23..094b3038c 100644 --- a/docs/source/manual/openfpga_flow/run_fpga_task.rst +++ b/docs/source/manual/openfpga_flow/run_fpga_task.rst @@ -29,9 +29,9 @@ Similarly ``regression/regression_quick`` expect following structure:: Running OpenFPGA Task: ~~~~~~~~~~~~~~~~~~~~~~ -At a minimum ``open_fpga_flow.py`` requires following command-line arguments:: +At a minimum ``run_fpga_task.py`` requires following command-line arguments:: - open_fpga_flow.py ... [] + run_fpga_task.py ... [] where: @@ -58,6 +58,12 @@ Command-line Options if any threads fail to execute successfully. It is mainly used to while performing regression test. +.. option:: --default_tool_path + + Specify the paths to tools as well as the keywords to extract QoR results from log files, when running this task. By default, the script will use the ``openfpga_flow/misc/fpgaflow_default_tool_path.conf``. + + .. note:: Please use absolute path!!! + .. option:: --test_run This option allows to debug OpenFPGA Task script diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index d3497cd98..d518bc9fc 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -14,6 +14,14 @@ write_fabric_verilog Specify the output directory for the Verilog netlists. For example, ``--file /temp/fabric_netlist/`` + .. option:: --constant_undriven_inputs + + .. note:: This option is automatically enabled and set to ``bus0`` when the option ``perimeter_cb`` of tileable routing resource graph is enabled (see details in :ref`addon_vpr_syntax`). + + .. note:: Enable this option may shadow issues in your FPGA architecture, which causes them difficult to be found in design verification. + + Can be [``none`` | ``bus0`` | ``bus1`` | ``bit0`` | ``bit1`` ]. Use constant 0 or 1 for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric. When ``bus0`` or ``bus1`` are set, the constant wiring will be done in a bus format. When ``bit0`` or ``bit1`` are set, the constant wiring will be done in a bit-blast style. Suggest to use bit-blast style only when downstream Verilog parsers do not support bus format. By default, it is ``none``. + .. option:: --default_net_type Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. @@ -61,6 +69,10 @@ write_full_testbench The bitstream file to be loaded to the full testbench, which should be in the same file format that OpenFPGA can outputs (See detailes in :ref:`file_formats_fabric_bitstream_plain_text`). For example, ``--bitstream and2.bit`` + .. option:: --simulator + + Specify the type of simulator which the full testbench will be used for. Currently support ``iverilog`` | ``vcs``. By default, assume the simulator is iverilog. For example, ``--simulator iverilog``. For different types of simulator, some syntax in the testbench may differ to help fast convergence. + .. option:: --fabric_netlist_file_path Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v`` @@ -172,6 +184,10 @@ __ iverilog_website_ .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable. + .. option:: --dump_waveform + + Enable waveform output when runnign HDL simulation on the preconfigured wrapper. When enabled, waveform files can be outputted in two formats: ``fsdb`` and ``vcd`` through preprocessing flags ``DUMP_FSDB`` and ``DUMP_VCD`` respectively. For example, when using VCS,. the flag can be activiated by ``+define+DUMP_FSDB=1``. + .. option:: --no_time_stamp Do not print time stamp in Verilog netlists diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 9ea4b2145..e955592c6 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -130,8 +130,17 @@ Clock signals will be auto-detected and routed based on pin constraints which ar .. option:: --pin_constraints_file or -pcf - Specify the *Pin Constraints File* (PCF) when the clock network contains multiple clock pins. For example, ``-pin_constraints_file pin_constraints.xml`` - Strongly recommend for multi-clock network. See detailed file format about :ref:`file_format_pin_constraints_file`. + Specify the *Pin Constraints File* (PCF) when the clock network contains multiple clock pins. For example, ``-pin_constraints_file pin_constraints.xml``. Strongly recommend for multi-clock network. See detailed file format about :ref:`file_format_pin_constraints_file`. + + .. note:: If there is a global net, e.g., ``clk`` or ``reset``, which will be driven by an internal resource, it should also be defined in the PCF file. + + .. option:: --disable_unused_trees + + Disable entire clock trees when they are not used by any clock nets. Useful to reduce clock power + + .. option:: --disable_unused_spines + + Disable part of the clock tree which are used by clock nets. Useful to reduce clock power .. option:: --verbose @@ -226,6 +235,10 @@ pb_pin_fixup .. warning:: This feature has been integrated into VPR to provide accurate timing analysis results at post-routing stage. However, this command provides a light fix-up (not as thorough as the one in VPR) but bring more flexibility in support some architecture without local routing. Suggest to enable it when your architecture does not have local routing for *Look-Up Tables* (LUTs) but you want to enable logic equivalent for input pins of LUTs .. warning:: This command may be deprecated in future + + .. option:: --map_global_net_to_msb + + If specified, any global net including clock, reset etc, will be mapped to a best-fit Most Significant Bit (MSB) of input ports of programmable blocks. If not specified, a best-fit Least Significant Bit (LSB) will be the default choice. For example, when ``--clock_modeling ideal`` is selected when running VPR, global nets will not be routed and their pin mapping on programmable blocks may be revoked by other nets due to optimization. Therefore, this command will restore the pin mapping for the global nets and pick a spare pin on programmable blocks. This option is to set a preference when mapping the global nets to spare pins. .. option:: --verbose @@ -359,20 +372,33 @@ add_fpga_core_to_fabric Show verbose log +.. _openfpga_setup_commands_write_fabric_hierarchy: write_fabric_hierarchy ~~~~~~~~~~~~~~~~~~~~~~ - Write the hierarchy of FPGA fabric graph to a plain-text file + Write the hierarchy of FPGA fabric graph to a YAML file .. option:: --file or -f - Specify the file name to write the hierarchy. + Specify the file name to write the hierarchy. See details in :ref:`file_format_fabric_hierarchy_file`. .. option:: --depth Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1. + .. option:: --module + + Specify the root module name(s) which should be considered. By default, it is ``fpga_top``. Note that regular expression is supported. For example, ``grid_*`` will output all the modules with a prefix of ``grid_`` + + .. option:: --filter + + Specify the filter which allows user to select modules to appear under each root module tree. By default, it is ``*``. Regular expression is supported. For example, ``*mux*`` will output all the modules which contains ``mux``. In the other words, the filter defines a white list. + + .. option:: --exclude_empty_modules + + Exclude modules with no qualified children (match the names defined through filter) from the output file + .. option:: --verbose Show verbose log @@ -392,7 +418,7 @@ write_fabric_io_info .. option:: --no_time_stamp - Do not print time stamp in bitstream files + Do not print time stamp in output files .. option:: --verbose @@ -433,7 +459,7 @@ pcf2place .. option:: --no_time_stamp - Do not print time stamp in bitstream files + Do not print time stamp in output files .. option:: --verbose @@ -467,8 +493,98 @@ write_module_naming_rules .. option:: --no_time_stamp - Do not print time stamp in bitstream files + Do not print time stamp in output files .. option:: --verbose Show verbose log + +.. _openfpga_setup_commands_write_fabric_pin_physical_location: + +write_fabric_pin_physical_location +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Output the physical location of each pin for each module of an FPGA fabric to a given file + + .. option:: --file + + Specify the file path to be written to. See details in :ref:`file_format_fabric_pin_physical_location_file`. + + .. option:: --module + + Specify the name of modules to be considered. Support regular expression, e.g., ``tile*``. When provided, only pins of selected modules will be outputted. By default, a wildcard ``*`` is considered, which means all the modules will be considered. + + .. option:: --show_invalid_side + + Show sides for each pin, even these pin does not have a specific valid side. This is mainly used for debugging. + + .. option:: --no_time_stamp + + Do not print time stamp in output files + + .. option:: --verbose + + Show verbose log + +.. _openfpga_setup_commands_report_reference: + +report_reference +~~~~~~~~~~~~~~~~~~~~ + + Write reference information of each child module under a given parent module to a YAML file + + .. option:: --file or -f + + Specify the file name to write the reference information. See details in :ref:`file_format_reference_file`. + + .. option:: --module + + Specify the parent module name, under which the references of each child module will be reported. + + .. option:: --no_time_stamp + + Do not print time stamp in output files + + .. option:: --verbose + + Show verbose info + + +.. _openfpga_setup_commands_read_unique_blocks: + +read_unique_blocks +~~~~~~~~~~~~~~~~~~~~ + + Read information of unique blocks from a given file. + + .. option:: --file + + Specify the file which contains unique block information. See details in :ref:`file_formats_unique_blocks`. + + .. option:: --type + + Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML. + + .. option:: --verbose + + Show verbose info + +.. _openfpga_setup_commands_write_unique_blocks: + +write_unique_blocks +~~~~~~~~~~~~~~~~~~~~~ + + Write information of unique blocks from internal data structure to a given file. + + .. option:: --file + + Specify the file which we will write unique block information to. See details in :ref:`file_formats_unique_blocks`. + + .. option:: --type + + Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML. + + .. option:: --verbose + + Show verbose info + diff --git a/docs/source/tutorials/getting_started/compile.rst b/docs/source/tutorials/getting_started/compile.rst index 1a1cc89c0..fe7f0b5d6 100644 --- a/docs/source/tutorials/getting_started/compile.rst +++ b/docs/source/tutorials/getting_started/compile.rst @@ -12,7 +12,7 @@ How to Compile Supported Operating Systems ~~~~~~~~~~~~~~~~~~~~~~~~~~~ -OpenFPGA is continously tested with Ubuntu 20.04 and partially on Ubuntu 22.04 +OpenFPGA is continously tested with Ubuntu 22.04 and partially on Ubuntu 20.04 It might work with earlier versions and other distributions. In addition to continous integration, our community users have tested OpenFPGA on their local machines using the following operating systems: @@ -21,7 +21,6 @@ In addition to continous integration, our community users have tested OpenFPGA o - CentOS 8 - Ubuntu 18.04 - Ubuntu 21.04 -- Ubuntu 22.04 Build Steps ~~~~~~~~~~~ @@ -34,7 +33,7 @@ In general, please follow the steps to compile cd OpenFPGA make all -.. note:: OpenFPGA requires gcc/g++ version > 7 and clang version > 6. +.. note:: OpenFPGA requires gcc/g++ version > 9 and clang version > 10. .. note:: cmake3.12+ is recommended to compile OpenFPGA with GUI @@ -111,7 +110,7 @@ Ubuntu 20.04 - Dependencies required to run regression tests -.. include:: regtest_dependencies.sh +.. include:: ubuntu20p04_regtest_dependencies.sh :code: shell .. note:: Python packages are also required @@ -135,7 +134,7 @@ Ubuntu 22.04 - Dependencies required to run regression tests -.. include:: regtest_dependencies.sh +.. include:: ubuntu22p04_regtest_dependencies.sh :code: shell .. note:: Python packages are also required diff --git a/docs/source/tutorials/getting_started/regtest_dependencies.sh b/docs/source/tutorials/getting_started/regtest_dependencies.sh index 39fb7c71f..9454e026f 120000 --- a/docs/source/tutorials/getting_started/regtest_dependencies.sh +++ b/docs/source/tutorials/getting_started/regtest_dependencies.sh @@ -1 +1 @@ -../../../../.github/workflows/install_dependencies_run.sh \ No newline at end of file +../../../../.github/workflows/install_dependencies_run_ubuntu22p04.sh \ No newline at end of file diff --git a/docs/source/tutorials/getting_started/ubuntu20p04_dependencies.sh b/docs/source/tutorials/getting_started/ubuntu20p04_dependencies.sh index 326a04511..b5c829840 120000 --- a/docs/source/tutorials/getting_started/ubuntu20p04_dependencies.sh +++ b/docs/source/tutorials/getting_started/ubuntu20p04_dependencies.sh @@ -1 +1 @@ -../../../../.github/workflows/install_dependencies_build.sh \ No newline at end of file +../../../../.github/workflows/install_dependencies_build_ubuntu20p04.sh \ No newline at end of file diff --git a/docs/source/tutorials/getting_started/ubuntu20p04_regtest_dependencies.sh b/docs/source/tutorials/getting_started/ubuntu20p04_regtest_dependencies.sh new file mode 120000 index 000000000..67a110927 --- /dev/null +++ b/docs/source/tutorials/getting_started/ubuntu20p04_regtest_dependencies.sh @@ -0,0 +1 @@ +../../../../.github/workflows/install_dependencies_run_ubuntu20p04.sh \ No newline at end of file diff --git a/docs/source/tutorials/getting_started/ubuntu22p04_regtest_dependencies.sh b/docs/source/tutorials/getting_started/ubuntu22p04_regtest_dependencies.sh new file mode 120000 index 000000000..9454e026f --- /dev/null +++ b/docs/source/tutorials/getting_started/ubuntu22p04_regtest_dependencies.sh @@ -0,0 +1 @@ +../../../../.github/workflows/install_dependencies_run_ubuntu22p04.sh \ No newline at end of file diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index 537a46357..de555d3af 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -10,3 +10,4 @@ add_subdirectory(libpcf) add_subdirectory(libbusgroup) add_subdirectory(libnamemanager) add_subdirectory(libtileconfig) +add_subdirectory(libopenfpgacapnproto) diff --git a/libs/libarchopenfpga/src/arch_direct.cpp b/libs/libarchopenfpga/src/arch_direct.cpp index 33565deeb..41ed809b6 100644 --- a/libs/libarchopenfpga/src/arch_direct.cpp +++ b/libs/libarchopenfpga/src/arch_direct.cpp @@ -71,7 +71,7 @@ ArchDirectId ArchDirect::add_direct(const std::string& name) { direct_ids_.push_back(direct); names_.push_back(name); circuit_models_.push_back(CircuitModelId::INVALID()); - types_.emplace_back(NUM_DIRECT_TYPES); + types_.emplace_back(e_direct_type::NUM_DIRECT_TYPES); directions_.emplace_back(vtr::Point( NUM_DIRECT_DIRECTIONS, NUM_DIRECT_DIRECTIONS)); diff --git a/libs/libarchopenfpga/src/arch_direct.h b/libs/libarchopenfpga/src/arch_direct.h index 5508095eb..2dbe6fce8 100644 --- a/libs/libarchopenfpga/src/arch_direct.h +++ b/libs/libarchopenfpga/src/arch_direct.h @@ -14,15 +14,16 @@ * These types are supplementary to the original VPR direct connections * Here we extend to the cross-row and cross-column connections ********************************************************************/ -enum e_direct_type { - INNER_COLUMN, - INNER_ROW, +enum class e_direct_type { + INNER_COLUMN_OR_ROW, + PART_OF_CB, INTER_COLUMN, INTER_ROW, NUM_DIRECT_TYPES }; -constexpr std::array DIRECT_TYPE_STRING = { - {"inner_column", "inner_row", "inter_column", "inter_row"}}; +constexpr std::array + DIRECT_TYPE_STRING = { + {"inner_column_or_row", "part_of_cb", "inter_column", "inter_row"}}; enum e_direct_direction { POSITIVE_DIR, NEGATIVE_DIR, NUM_DIRECT_DIRECTIONS }; constexpr std::array diff --git a/libs/libarchopenfpga/src/bitstream_setting.cpp b/libs/libarchopenfpga/src/bitstream_setting.cpp index c04eeba87..6092bd91e 100644 --- a/libs/libarchopenfpga/src/bitstream_setting.cpp +++ b/libs/libarchopenfpga/src/bitstream_setting.cpp @@ -24,6 +24,12 @@ BitstreamSetting::interconnect_settings() const { interconnect_setting_ids_.end()); } +BitstreamSetting::overwrite_bitstream_range +BitstreamSetting::overwrite_bitstreams() const { + return vtr::make_range(overwrite_bitstream_ids_.begin(), + overwrite_bitstream_ids_.end()); +} + /************************************************************************ * Constructors ***********************************************************************/ @@ -102,6 +108,22 @@ std::string BitstreamSetting::default_path( return interconnect_default_paths_[interconnect_setting_id]; } +std::vector BitstreamSetting::non_fabric() const { + return non_fabric_; +} + +std::string BitstreamSetting::overwrite_bitstream_path( + const OverwriteBitstreamId& id) const { + VTR_ASSERT(true == valid_overwrite_bitstream_id(id)); + return overwrite_bitstream_paths_[id]; +} + +bool BitstreamSetting::overwrite_bitstream_value( + const OverwriteBitstreamId& id) const { + VTR_ASSERT(true == valid_overwrite_bitstream_id(id)); + return overwrite_bitstream_values_[id]; +} + /************************************************************************ * Public Mutators ***********************************************************************/ @@ -154,6 +176,41 @@ BitstreamSetting::add_bitstream_interconnect_setting( return interc_setting_id; } +void BitstreamSetting::add_non_fabric(const std::string& name, + const std::string& file) { + VTR_ASSERT(name.size()); + VTR_ASSERT(file.size()); + non_fabric_.push_back(NonFabricBitstreamSetting(name, file)); +} + +void BitstreamSetting::add_non_fabric_pb(const std::string& pb, + const std::string& content) { + VTR_ASSERT(non_fabric_.size()); + VTR_ASSERT(content.find(".param ") == 0 || content.find(".attr ") == 0); + if (content.find(".param ") == 0) { + VTR_ASSERT(content.size() > 7); + non_fabric_.back().add_pb(pb, "param", content.substr(7)); + } else { + VTR_ASSERT(content.size() > 6); + non_fabric_.back().add_pb(pb, "attr", content.substr(6)); + } +} + +OverwriteBitstreamId BitstreamSetting::add_overwrite_bitstream( + const std::string& path, const bool& value) { + VTR_ASSERT(path.size()); + VTR_ASSERT(overwrite_bitstream_ids_.size() == + overwrite_bitstream_paths_.size()); + VTR_ASSERT(overwrite_bitstream_paths_.size() == + overwrite_bitstream_values_.size()); + OverwriteBitstreamId id = + OverwriteBitstreamId(overwrite_bitstream_ids_.size()); + overwrite_bitstream_ids_.push_back(id); + overwrite_bitstream_paths_.push_back(path); + overwrite_bitstream_values_.push_back(value); + return id; +} + /************************************************************************ * Public Validators ***********************************************************************/ @@ -170,4 +227,14 @@ bool BitstreamSetting::valid_bitstream_interconnect_setting_id( interconnect_setting_ids_[interconnect_setting_id]); } +bool BitstreamSetting::valid_overwrite_bitstream_id( + const OverwriteBitstreamId& id) const { + VTR_ASSERT(overwrite_bitstream_ids_.size() == + overwrite_bitstream_paths_.size()); + VTR_ASSERT(overwrite_bitstream_paths_.size() == + overwrite_bitstream_values_.size()); + return (size_t(id) < overwrite_bitstream_ids_.size()) && + (id == overwrite_bitstream_ids_[id]); +} + } // namespace openfpga diff --git a/libs/libarchopenfpga/src/bitstream_setting.h b/libs/libarchopenfpga/src/bitstream_setting.h index 7963942a0..042e850e0 100644 --- a/libs/libarchopenfpga/src/bitstream_setting.h +++ b/libs/libarchopenfpga/src/bitstream_setting.h @@ -6,6 +6,7 @@ * which are used by OpenFPGA *******************************************************************/ #include +#include #include "bitstream_setting_fwd.h" #include "vtr_vector.h" @@ -13,6 +14,29 @@ /* namespace openfpga begins */ namespace openfpga { +struct NonFabricBitstreamPBSetting { + NonFabricBitstreamPBSetting(const std::string& p = "", + const std::string& t = "", + const std::string& c = "") + : pb(p), type(t), content(c) {} + const std::string pb = ""; + const std::string type = ""; + const std::string content = ""; +}; + +struct NonFabricBitstreamSetting { + NonFabricBitstreamSetting(const std::string& n = "", + const std::string& f = "") + : name(n), file(f) {} + void add_pb(const std::string& p, const std::string& t, + const std::string& c) { + pbs.push_back(NonFabricBitstreamPBSetting(p, t, c)); + } + const std::string name = ""; + const std::string file = ""; + std::vector pbs; +}; + /******************************************************************** * A data structure to describe bitstream settings * @@ -37,11 +61,15 @@ class BitstreamSetting { typedef vtr::vector::const_iterator bitstream_interconnect_setting_iterator; + typedef vtr::vector::const_iterator + overwrite_bitstream_iterator; /* Create range */ typedef vtr::Range bitstream_pb_type_setting_range; typedef vtr::Range bitstream_interconnect_setting_range; + typedef vtr::Range overwrite_bitstream_range; public: /* Constructors */ BitstreamSetting(); @@ -49,6 +77,7 @@ class BitstreamSetting { public: /* Accessors: aggregates */ bitstream_pb_type_setting_range pb_type_settings() const; bitstream_interconnect_setting_range interconnect_settings() const; + overwrite_bitstream_range overwrite_bitstreams() const; public: /* Public Accessors */ std::string pb_type_name( @@ -73,6 +102,9 @@ class BitstreamSetting { const BitstreamInterconnectSettingId& interconnect_setting_id) const; std::string default_path( const BitstreamInterconnectSettingId& interconnect_setting_id) const; + std::vector non_fabric() const; + std::string overwrite_bitstream_path(const OverwriteBitstreamId& id) const; + bool overwrite_bitstream_value(const OverwriteBitstreamId& id) const; public: /* Public Mutators */ BitstreamPbTypeSettingId add_bitstream_pb_type_setting( @@ -92,11 +124,18 @@ class BitstreamSetting { const std::vector& parent_mode_names, const std::string& default_path); + void add_non_fabric(const std::string& name, const std::string& file); + void add_non_fabric_pb(const std::string& pb, const std::string& content); + + OverwriteBitstreamId add_overwrite_bitstream(const std::string& path, + const bool& value); + public: /* Public Validators */ bool valid_bitstream_pb_type_setting_id( const BitstreamPbTypeSettingId& pb_type_setting_id) const; bool valid_bitstream_interconnect_setting_id( const BitstreamInterconnectSettingId& interconnect_setting_id) const; + bool valid_overwrite_bitstream_id(const OverwriteBitstreamId& id) const; private: /* Internal data */ /* Pb type -related settings @@ -133,6 +172,11 @@ class BitstreamSetting { interconnect_parent_mode_names_; vtr::vector interconnect_default_paths_; + std::vector non_fabric_; + vtr::vector + overwrite_bitstream_ids_; + vtr::vector overwrite_bitstream_paths_; + vtr::vector overwrite_bitstream_values_; }; } // namespace openfpga diff --git a/libs/libarchopenfpga/src/bitstream_setting_fwd.h b/libs/libarchopenfpga/src/bitstream_setting_fwd.h index bc5c2ab88..dbcc70553 100644 --- a/libs/libarchopenfpga/src/bitstream_setting_fwd.h +++ b/libs/libarchopenfpga/src/bitstream_setting_fwd.h @@ -15,11 +15,13 @@ struct bitstream_pb_type_setting_id_tag; struct bitstream_interconnect_setting_id_tag; +struct overwrite_bitstream_id_tag; typedef vtr::StrongId BitstreamPbTypeSettingId; typedef vtr::StrongId BitstreamInterconnectSettingId; +typedef vtr::StrongId OverwriteBitstreamId; /* Short declaration of class */ class BitstreamSetting; diff --git a/libs/libarchopenfpga/src/check_circuit_library.cpp b/libs/libarchopenfpga/src/check_circuit_library.cpp index 62a71a3a1..a9852a7e5 100644 --- a/libs/libarchopenfpga/src/check_circuit_library.cpp +++ b/libs/libarchopenfpga/src/check_circuit_library.cpp @@ -800,6 +800,60 @@ static size_t check_io_circuit_model(const CircuitLibrary& circuit_lib) { return num_err; } +/************************************************************************ + * Check the last stage pass gate logic model is the same type as default + ***********************************************************************/ +static size_t check_pass_gate_circuit_model_consistency( + const CircuitLibrary& circuit_lib) { + size_t num_err = 0; + + for (const CircuitModelId& mux_model : + circuit_lib.models_by_type(CIRCUIT_MODEL_MUX)) { + CircuitModelId pgl_model = circuit_lib.pass_gate_logic_model(mux_model); + CircuitModelId last_stage_pgl_model = + circuit_lib.last_stage_pass_gate_logic_model(mux_model); + if (!circuit_lib.valid_model_id(pgl_model)) { + VTR_LOGF_ERROR( + __FILE__, __LINE__, + "The pass-gate logic circuit model '%s' of '%s' is not valid!\n", + circuit_lib.pass_gate_logic_model_name(mux_model).c_str(), + circuit_lib.model_name(mux_model).c_str()); + num_err++; + } + if (!circuit_lib.valid_model_id(last_stage_pgl_model)) { + VTR_LOGF_ERROR( + __FILE__, __LINE__, + "The last stage pass-gate logic circuit model '%s' of '%s' is not " + "valid!\n", + circuit_lib.last_stage_pass_gate_logic_model_name(mux_model).c_str(), + circuit_lib.model_name(mux_model).c_str()); + num_err++; + } + if (circuit_lib.model_type(pgl_model) != + circuit_lib.model_type(last_stage_pgl_model)) { + VTR_LOGF_ERROR( + __FILE__, __LINE__, + "The last stage pass-gate logic circuit model '%s' of '%s' should be " + "the same type as its regular pass-gate logic model '%s'!\n", + circuit_lib.model_name(last_stage_pgl_model).c_str(), + circuit_lib.model_name(mux_model).c_str(), + circuit_lib.model_name(pgl_model).c_str()); + num_err++; + } + if (pgl_model != last_stage_pgl_model && + circuit_lib.gate_type(pgl_model) != CIRCUIT_MODEL_GATE_MUX2) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "The last stage pass-gate logic circuit model '%s' of " + "'%s' should be a MUX2 gate!\n", + circuit_lib.model_name(last_stage_pgl_model).c_str(), + circuit_lib.model_name(mux_model).c_str()); + num_err++; + } + } + + return num_err; +} + /************************************************************************ * Check points to make sure we have a valid circuit library * Detailed checkpoints: @@ -920,6 +974,9 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) { /* 11. Check power-gated inverter/buffer models */ num_err += check_power_gated_circuit_models(circuit_lib); + /* 12. Check pass-gate logic model consistency */ + num_err += check_pass_gate_circuit_model_consistency(circuit_lib); + /* If we have any errors, exit */ if (0 < num_err) { diff --git a/libs/libarchopenfpga/src/circuit_library.cpp b/libs/libarchopenfpga/src/circuit_library.cpp index 241f63c7a..28c00aa7b 100644 --- a/libs/libarchopenfpga/src/circuit_library.cpp +++ b/libs/libarchopenfpga/src/circuit_library.cpp @@ -259,6 +259,28 @@ CircuitModelId CircuitLibrary::pass_gate_logic_model( return pgl_model_id; } +/* Find the id of pass-gate circuit model + * Two cases to be considered: + * 1. this is a pass-gate circuit model, just find the data and return + * 2. this circuit model includes a pass-gate, find the link to pass-gate + * circuit model and go recursively + */ +CircuitModelId CircuitLibrary::last_stage_pass_gate_logic_model( + const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + + /* Return the data if this is a pass-gate circuit model */ + if (CIRCUIT_MODEL_PASSGATE == model_type(model_id)) { + return model_ids_[model_id]; + } + + /* Otherwise, we need to make sure this circuit model contains a pass-gate */ + CircuitModelId pgl_model_id = last_stage_pass_gate_logic_model_ids_[model_id]; + VTR_ASSERT(CircuitModelId::INVALID() != pgl_model_id); + return pgl_model_id; +} + /* Find the name of pass-gate circuit model * Two cases to be considered: * 1. this is a pass-gate circuit model, just find the data and return @@ -279,6 +301,26 @@ std::string CircuitLibrary::pass_gate_logic_model_name( return pass_gate_logic_model_names_[model_id]; } +/* Find the name of pass-gate circuit model + * Two cases to be considered: + * 1. this is a pass-gate circuit model, just find the data and return + * 2. this circuit model includes a pass-gate, find the link to pass-gate + * circuit model and go recursively + */ +std::string CircuitLibrary::last_stage_pass_gate_logic_model_name( + const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + + /* Return the data if this is a pass-gate circuit model */ + if (CIRCUIT_MODEL_PASSGATE == model_type(model_id)) { + return model_names_[model_id]; + } + + /* Otherwise, we need to make sure this circuit model contains a pass-gate */ + return last_stage_pass_gate_logic_model_names_[model_id]; +} + /* Return the type of pass gate logic module, only applicable to circuit model * whose type is pass-gate logic */ enum e_circuit_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type( @@ -1262,6 +1304,8 @@ CircuitModelId CircuitLibrary::add_model( /* Pass-gate-related parameters */ pass_gate_logic_model_names_.emplace_back(); pass_gate_logic_model_ids_.emplace_back(CircuitModelId::INVALID()); + last_stage_pass_gate_logic_model_names_.emplace_back(); + last_stage_pass_gate_logic_model_ids_.emplace_back(CircuitModelId::INVALID()); /* Delay information */ delay_types_.emplace_back(); @@ -1485,6 +1529,15 @@ void CircuitLibrary::set_model_pass_gate_logic(const CircuitModelId& model_id, return; } +/* Set pass-gate logic information of a circuit model */ +void CircuitLibrary::set_model_last_stage_pass_gate_logic( + const CircuitModelId& model_id, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + last_stage_pass_gate_logic_model_names_[model_id] = model_name; + return; +} + /* Add a port to a circuit model */ CircuitPortId CircuitLibrary::add_model_port( const CircuitModelId& model_id, @@ -2174,6 +2227,12 @@ void CircuitLibrary::link_pass_gate_logic_model( } pass_gate_logic_model_ids_[model_id] = model(pass_gate_logic_model_names_[model_id]); + /* Get the circuit model id by name, skip those with empty names*/ + if (true == last_stage_pass_gate_logic_model_names_[model_id].empty()) { + return; + } + last_stage_pass_gate_logic_model_ids_[model_id] = + model(last_stage_pass_gate_logic_model_names_[model_id]); return; } diff --git a/libs/libarchopenfpga/src/circuit_library.h b/libs/libarchopenfpga/src/circuit_library.h index 30caef09c..2c511d59c 100644 --- a/libs/libarchopenfpga/src/circuit_library.h +++ b/libs/libarchopenfpga/src/circuit_library.h @@ -272,7 +272,11 @@ class CircuitLibrary { const CircuitModelId& model_id) const; /* Pass-gate-logic information */ CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const; + CircuitModelId last_stage_pass_gate_logic_model( + const CircuitModelId& model_id) const; std::string pass_gate_logic_model_name(const CircuitModelId& model_id) const; + std::string last_stage_pass_gate_logic_model_name( + const CircuitModelId& model_id) const; enum e_circuit_model_pass_gate_logic_type pass_gate_logic_type( const CircuitModelId& model_id) const; float pass_gate_logic_pmos_size(const CircuitModelId& model_id) const; @@ -448,6 +452,8 @@ class CircuitLibrary { /* Pass-gate-related parameters */ void set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name); + void set_model_last_stage_pass_gate_logic(const CircuitModelId& model_id, + const std::string& model_name); /* Port information */ CircuitPortId add_model_port(const CircuitModelId& model_id, const enum e_circuit_model_port_type& port_type); @@ -664,6 +670,10 @@ class CircuitLibrary { /* Pass-gate-related parameters */ vtr::vector pass_gate_logic_model_names_; vtr::vector pass_gate_logic_model_ids_; + vtr::vector + last_stage_pass_gate_logic_model_names_; + vtr::vector + last_stage_pass_gate_logic_model_ids_; /* Port information */ vtr::vector port_ids_; diff --git a/libs/libarchopenfpga/src/config_protocol.cpp b/libs/libarchopenfpga/src/config_protocol.cpp index 00de87a41..d4a40833c 100644 --- a/libs/libarchopenfpga/src/config_protocol.cpp +++ b/libs/libarchopenfpga/src/config_protocol.cpp @@ -116,6 +116,11 @@ CircuitModelId ConfigProtocol::wl_memory_model() const { size_t ConfigProtocol::wl_num_banks() const { return wl_num_banks_; } +const QLMemoryBankConfigSetting* ConfigProtocol::ql_memory_bank_config_setting() + const { + return &ql_memory_bank_config_setting_; +} + /************************************************************************ * Public Mutators ***********************************************************************/ @@ -256,6 +261,10 @@ void ConfigProtocol::set_wl_num_banks(const size_t& num_banks) { wl_num_banks_ = num_banks; } +QLMemoryBankConfigSetting* ConfigProtocol::get_ql_memory_bank_config_setting() { + return &ql_memory_bank_config_setting_; +} + /************************************************************************ * Private Validators ***********************************************************************/ diff --git a/libs/libarchopenfpga/src/config_protocol.h b/libs/libarchopenfpga/src/config_protocol.h index 42ca982c4..7805d3c36 100644 --- a/libs/libarchopenfpga/src/config_protocol.h +++ b/libs/libarchopenfpga/src/config_protocol.h @@ -7,6 +7,7 @@ #include "circuit_library_fwd.h" #include "circuit_types.h" #include "openfpga_port.h" +#include "ql_memory_bank_config_setting.h" /* Data type to define the protocol through which BL/WL can be manipulated */ enum e_blwl_protocol_type { @@ -54,6 +55,9 @@ class ConfigProtocol { CircuitModelId wl_memory_model() const; size_t wl_num_banks() const; + /* QL Memory Bank Config Setting */ + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting() const; + public: /* Public Mutators */ void set_type(const e_config_protocol_type& type); void set_memory_model_name(const std::string& memory_model_name); @@ -76,6 +80,9 @@ class ConfigProtocol { void set_wl_memory_model(const CircuitModelId& memory_model); void set_wl_num_banks(const size_t& num_banks); + /* QL Memory Bank Config Setting */ + QLMemoryBankConfigSetting* get_ql_memory_bank_config_setting(); + public: /* Public validators */ /* Check if internal data has any conflicts to each other. Return number of * errors detected */ @@ -131,6 +138,9 @@ class ConfigProtocol { std::string wl_memory_model_name_; CircuitModelId wl_memory_model_; size_t wl_num_banks_; + + /* QL Memory Bank Config Setting */ + QLMemoryBankConfigSetting ql_memory_bank_config_setting_; }; #endif diff --git a/libs/libarchopenfpga/src/ql_memory_bank_config_setting.cpp b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.cpp new file mode 100644 index 000000000..87318adc2 --- /dev/null +++ b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.cpp @@ -0,0 +1,34 @@ +#include "ql_memory_bank_config_setting.h" + +#include "openfpga_tokenizer.h" +#include "vtr_assert.h" +#include "vtr_log.h" + +/************************************************************************ + * Member functions for class QLMemoryBankConfigSetting + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ +QLMemoryBankConfigSetting::QLMemoryBankConfigSetting() {} + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +QLMemoryBankPBSetting QLMemoryBankConfigSetting::pb_setting( + const std::string& name) const { + if (settings_.find(name) != settings_.end()) { + return settings_.at(name); + } + return QLMemoryBankPBSetting(); +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void QLMemoryBankConfigSetting::add_pb_setting(const std::string& name, + uint32_t num_wl) { + VTR_ASSERT(settings_.find(name) == settings_.end()); + settings_[name] = QLMemoryBankPBSetting(num_wl); +} diff --git a/libs/libarchopenfpga/src/ql_memory_bank_config_setting.h b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.h new file mode 100644 index 000000000..82dcd4989 --- /dev/null +++ b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.h @@ -0,0 +1,30 @@ +#ifndef QL_MEMORY_BANK_CONFIG_SETTING_H +#define QL_MEMORY_BANK_CONFIG_SETTING_H + +#include +#include +#include + +struct QLMemoryBankPBSetting { + QLMemoryBankPBSetting(uint32_t n = 0) : num_wl(n) {} + uint32_t num_wl = 0; +}; + +/******************************************************************** + * A data structure to store QL Memory Bank configuration setting + *******************************************************************/ +class QLMemoryBankConfigSetting { + public: /* Constructors */ + QLMemoryBankConfigSetting(); + + public: /* Public Accessors */ + QLMemoryBankPBSetting pb_setting(const std::string& name) const; + + public: /* Public Mutators */ + void add_pb_setting(const std::string& name, uint32_t num_wl); + + private: /* Internal data */ + std::map settings_; +}; + +#endif diff --git a/libs/libarchopenfpga/src/read_xml_bitstream_setting.cpp b/libs/libarchopenfpga/src/read_xml_bitstream_setting.cpp index 7447bec2a..244703fc1 100644 --- a/libs/libarchopenfpga/src/read_xml_bitstream_setting.cpp +++ b/libs/libarchopenfpga/src/read_xml_bitstream_setting.cpp @@ -76,6 +76,56 @@ static void read_xml_bitstream_interconnect_setting( operating_pb_parser.modes(), default_path_attr); } +/******************************************************************** + * Parse XML description for a non_fabric annotation under a XML + *node + *******************************************************************/ +static void read_xml_non_fabric_bitstream_setting( + pugi::xml_node& xml_non_fabric, const pugiutil::loc_data& loc_data, + openfpga::BitstreamSetting& bitstream_setting) { + const std::string& name_attr = + get_attribute(xml_non_fabric, "name", loc_data).as_string(); + const std::string& file_attr = + get_attribute(xml_non_fabric, "file", loc_data).as_string(); + /* Add to non-fabric */ + bitstream_setting.add_non_fabric(name_attr, file_attr); + for (pugi::xml_node xml_child : xml_non_fabric.children()) { + if (xml_child.name() != std::string("pb")) { + bad_tag(xml_child, loc_data, xml_non_fabric, {"pb"}); + } + const std::string& pb_name_attr = + get_attribute(xml_child, "name", loc_data).as_string(); + const std::string& content_attr = + get_attribute(xml_child, "content", loc_data).as_string(); + /* Add PB to non-fabric */ + bitstream_setting.add_non_fabric_pb(pb_name_attr, content_attr); + } +} + +/******************************************************************** + * Parse XML description for a bit setting under a XML node + *******************************************************************/ +static void read_xml_overwrite_bitstream_setting( + pugi::xml_node& xml_overwrite_bitstream, const pugiutil::loc_data& loc_data, + openfpga::BitstreamSetting& bitstream_setting) { + // Loopthrough bit + for (pugi::xml_node xml_bit : xml_overwrite_bitstream.children()) { + if (xml_bit.name() != std::string("bit")) { + bad_tag(xml_bit, loc_data, xml_overwrite_bitstream, {"bit"}); + } + const std::string& path_attr = + get_attribute(xml_bit, "path", loc_data).as_string(); + const std::string& value_attr = + get_attribute(xml_bit, "value", loc_data).as_string(); + if (value_attr != "0" && value_attr != "1") { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_bit), + "Invalid value of overwrite_bitstream bit. Expect [0|1]"); + } + /* Add to bit */ + bitstream_setting.add_overwrite_bitstream(path_attr, value_attr == "1"); + } +} + /******************************************************************** * Parse XML codes about to an object *******************************************************************/ @@ -89,17 +139,26 @@ openfpga::BitstreamSetting read_xml_bitstream_setting( for (pugi::xml_node xml_child : Node.children()) { /* Error out if the XML child has an invalid name! */ if ((xml_child.name() != std::string("pb_type")) && - (xml_child.name() != std::string("interconnect"))) { - bad_tag(xml_child, loc_data, Node, {"pb_type | interconnect"}); + (xml_child.name() != std::string("interconnect")) && + (xml_child.name() != std::string("non_fabric")) && + (xml_child.name() != std::string("overwrite_bitstream"))) { + bad_tag(xml_child, loc_data, Node, + {"pb_type | interconnect | non_fabric | overwrite_bitstream"}); } if (xml_child.name() == std::string("pb_type")) { read_xml_bitstream_pb_type_setting(xml_child, loc_data, bitstream_setting); - } else { - VTR_ASSERT_SAFE(xml_child.name() == std::string("interconnect")); + } else if (xml_child.name() == std::string("interconnect")) { read_xml_bitstream_interconnect_setting(xml_child, loc_data, bitstream_setting); + } else if (xml_child.name() == std::string("non_fabric")) { + read_xml_non_fabric_bitstream_setting(xml_child, loc_data, + bitstream_setting); + } else { + VTR_ASSERT_SAFE(xml_child.name() == std::string("overwrite_bitstream")); + read_xml_overwrite_bitstream_setting(xml_child, loc_data, + bitstream_setting); } } diff --git a/libs/libarchopenfpga/src/read_xml_circuit_library.cpp b/libs/libarchopenfpga/src/read_xml_circuit_library.cpp index 13ff84800..9fdc05265 100644 --- a/libs/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libs/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -832,6 +832,25 @@ static void read_xml_circuit_model(pugi::xml_node& xml_model, circuit_lib.set_model_pass_gate_logic( model, get_attribute(xml_pass_gate_logic, "circuit_model_name", loc_data) .as_string()); + /* Last stage pass gate is optional */ + size_t num_last_stage_pgl = + count_children(xml_model, "last_stage_pass_gate_logic", loc_data, + pugiutil::ReqOpt::OPTIONAL); + if (0 < num_last_stage_pgl) { + auto xml_last_stage_pass_gate_logic = + get_single_child(xml_model, "last_stage_pass_gate_logic", loc_data); + circuit_lib.set_model_last_stage_pass_gate_logic( + model, get_attribute(xml_last_stage_pass_gate_logic, + "circuit_model_name", loc_data) + .as_string()); + } else { + /* By default, assume the last stage circuit model is the same as others + */ + circuit_lib.set_model_last_stage_pass_gate_logic( + model, + get_attribute(xml_pass_gate_logic, "circuit_model_name", loc_data) + .as_string()); + } } /* Parse all the ports belonging to this circuit model diff --git a/libs/libarchopenfpga/src/read_xml_config_protocol.cpp b/libs/libarchopenfpga/src/read_xml_config_protocol.cpp index b51d9f237..d93ff131e 100644 --- a/libs/libarchopenfpga/src/read_xml_config_protocol.cpp +++ b/libs/libarchopenfpga/src/read_xml_config_protocol.cpp @@ -249,6 +249,32 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz, } } +/******************************************************************** + * Parse XML codes about to + *QLMemoryBankConfigSetting + *******************************************************************/ +static void read_xml_ql_memory_bank_config_setting( + QLMemoryBankConfigSetting* setting, pugi::xml_node& Node, + const pugiutil::loc_data& loc_data) { + /* Parse configuration protocol root node */ + pugi::xml_node config_setting = + get_single_child(Node, "ql_memory_bank_config_setting", loc_data, + pugiutil::ReqOpt::OPTIONAL); + + if (config_setting) { + /* Add to ql_memory_bank_config_setting_ */ + for (pugi::xml_node xml_child : config_setting.children()) { + if (xml_child.name() != std::string("pb_type")) { + bad_tag(xml_child, loc_data, config_setting, {"pb_type"}); + } + const std::string& name_attr = + get_attribute(xml_child, "name", loc_data).as_string(); + uint32_t num_wl = get_attribute(xml_child, "num_wl", loc_data).as_uint(); + setting->add_pb_setting(name_attr, num_wl); + } + } +} + /******************************************************************** * Parse XML codes about to an object of ConfigProtocol *******************************************************************/ @@ -264,5 +290,14 @@ ConfigProtocol read_xml_config_protocol(pugi::xml_node& Node, get_single_child(xml_config, "organization", loc_data); read_xml_config_organization(xml_config_orgz, loc_data, config_protocol); + /* Parse QL Memory Bank configuration setting */ + if (config_protocol.type() == CONFIG_MEM_QL_MEMORY_BANK && + config_protocol.bl_protocol_type() == BLWL_PROTOCOL_FLATTEN && + config_protocol.wl_protocol_type() == BLWL_PROTOCOL_FLATTEN) { + read_xml_ql_memory_bank_config_setting( + config_protocol.get_ql_memory_bank_config_setting(), xml_config, + loc_data); + } + return config_protocol; } diff --git a/libs/libarchopenfpga/src/read_xml_routing_circuit.cpp b/libs/libarchopenfpga/src/read_xml_routing_circuit.cpp index 1ac6675b8..0a48531c0 100644 --- a/libs/libarchopenfpga/src/read_xml_routing_circuit.cpp +++ b/libs/libarchopenfpga/src/read_xml_routing_circuit.cpp @@ -11,6 +11,7 @@ /* Headers from vtr util library */ #include "vtr_assert.h" +#include "vtr_log.h" /* Headers from libarchfpga */ #include "arch_error.h" @@ -198,15 +199,20 @@ std::map read_xml_routing_segment_circuit( * Convert string to the enumerate of direct type *******************************************************************/ static e_direct_type string_to_direct_type(const std::string& type_string) { - if (std::string("column") == type_string) { - return INTER_COLUMN; + if (std::string("part_of_cb") == type_string) { + return e_direct_type::PART_OF_CB; + } + if (std::string("inner_column_or_row") == type_string) { + return e_direct_type::INNER_COLUMN_OR_ROW; + } + if (std::string("inter_column") == type_string) { + return e_direct_type::INTER_COLUMN; + } + if (std::string("inter_row") == type_string) { + return e_direct_type::INTER_ROW; } - if (std::string("row") == type_string) { - return INTER_ROW; - } - - return NUM_DIRECT_TYPES; + return e_direct_type::NUM_DIRECT_TYPES; } /******************************************************************** @@ -255,13 +261,6 @@ ArchDirect read_xml_direct_circuit(pugi::xml_node& Node, std::string direct_name = get_attribute(xml_direct, "name", loc_data).as_string(); - /* Get the routing segment circuit model name */ - std::string direct_model_name = - get_attribute(xml_direct, "circuit_model_name", loc_data).as_string(); - - CircuitModelId direct_model = find_routing_circuit_model( - xml_direct, loc_data, circuit_lib, direct_model_name, CIRCUIT_MODEL_WIRE); - /* Add to the Arch direct database */ ArchDirectId direct = arch_direct.add_direct(direct_name); if (false == arch_direct.valid_direct_id(direct)) { @@ -269,28 +268,48 @@ ArchDirect read_xml_direct_circuit(pugi::xml_node& Node, "Direct name '%s' has been defined more than once!\n", direct_name.c_str()); } - arch_direct.set_circuit_model(direct, direct_model); /* Add more information*/ std::string direct_type_name = get_attribute(xml_direct, "type", loc_data, pugiutil::ReqOpt::OPTIONAL) - .as_string("none"); - /* If not defined, we go to the next */ - if (std::string("none") == direct_type_name) { - continue; - } + .as_string( + DIRECT_TYPE_STRING[size_t(e_direct_type::INNER_COLUMN_OR_ROW)]); e_direct_type direct_type = string_to_direct_type(direct_type_name); - if (NUM_DIRECT_TYPES == direct_type) { + if (e_direct_type::NUM_DIRECT_TYPES == direct_type) { archfpga_throw( loc_data.filename_c_str(), loc_data.line(xml_direct), - "Direct type '%s' is not support! Acceptable values are [column|row]\n", + "Direct type '%s' is not support! Acceptable values are " + "[inner_column_or_row|part_of_cb|inter_column|inter_row]\n", direct_type_name.c_str()); } arch_direct.set_type(direct, direct_type); + /* Get the routing segment circuit model name */ + std::string direct_model_name = + get_attribute(xml_direct, "circuit_model_name", loc_data).as_string(); + + /* If a direct connection is part of a connection block, the circuit model + * should be a MUX */ + e_circuit_model_type expected_circuit_model_type = CIRCUIT_MODEL_WIRE; + if (arch_direct.type(direct) == e_direct_type::PART_OF_CB) { + VTR_LOG("Direct '%s' will modelled as part of a connection block.\n", + direct_name.c_str()); + expected_circuit_model_type = CIRCUIT_MODEL_MUX; + } + CircuitModelId direct_model = find_routing_circuit_model( + xml_direct, loc_data, circuit_lib, direct_model_name, + expected_circuit_model_type); + arch_direct.set_circuit_model(direct, direct_model); + + /* The following syntax is only available for inter-column/row */ + if (arch_direct.type(direct) != e_direct_type::INTER_COLUMN && + arch_direct.type(direct) != e_direct_type::INTER_ROW) { + continue; + } + std::string x_dir_name = get_attribute(xml_direct, "x_dir", loc_data).as_string(); std::string y_dir_name = diff --git a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp index 135e38361..960f9352d 100644 --- a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp +++ b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp @@ -89,14 +89,6 @@ static void read_xml_tile_global_port_annotation( get_attribute(xml_tile, "is_clock", loc_data, pugiutil::ReqOpt::OPTIONAL) .as_bool(false)); - /* Get clock tree attributes if this is a clock */ - if (tile_annotation.global_port_is_clock(tile_global_port_id)) { - tile_annotation.set_global_port_clock_arch_tree_name( - tile_global_port_id, get_attribute(xml_tile, "clock_arch_tree_name", - loc_data, pugiutil::ReqOpt::OPTIONAL) - .as_string()); - } - /* Get is_set attributes */ tile_annotation.set_global_port_is_set( tile_global_port_id, @@ -109,6 +101,16 @@ static void read_xml_tile_global_port_annotation( get_attribute(xml_tile, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL) .as_bool(false)); + /* Get clock tree attributes if this is a clock, reset or set */ + if (tile_annotation.global_port_is_clock(tile_global_port_id) || + tile_annotation.global_port_is_reset(tile_global_port_id) || + tile_annotation.global_port_is_set(tile_global_port_id)) { + tile_annotation.set_global_port_clock_arch_tree_name( + tile_global_port_id, get_attribute(xml_tile, "clock_arch_tree_name", + loc_data, pugiutil::ReqOpt::OPTIONAL) + .as_string()); + } + /* Get default_value attributes */ tile_annotation.set_global_port_default_value( tile_global_port_id, diff --git a/libs/libarchopenfpga/src/tile_annotation.cpp b/libs/libarchopenfpga/src/tile_annotation.cpp index 2ffacd1d0..77adcff18 100644 --- a/libs/libarchopenfpga/src/tile_annotation.cpp +++ b/libs/libarchopenfpga/src/tile_annotation.cpp @@ -96,6 +96,11 @@ size_t TileAnnotation::global_port_default_value( return global_port_default_values_[global_port_id]; } +bool TileAnnotation::global_port_thru_dedicated_network( + const TileGlobalPortId& global_port_id) const { + return !global_port_clock_arch_tree_name(global_port_id).empty(); +} + std::string TileAnnotation::global_port_clock_arch_tree_name( const TileGlobalPortId& global_port_id) const { VTR_ASSERT(valid_global_port_id(global_port_id)); diff --git a/libs/libarchopenfpga/src/tile_annotation.h b/libs/libarchopenfpga/src/tile_annotation.h index 36af8a9b4..f2f3f3d75 100644 --- a/libs/libarchopenfpga/src/tile_annotation.h +++ b/libs/libarchopenfpga/src/tile_annotation.h @@ -54,6 +54,8 @@ class TileAnnotation { bool global_port_is_clock(const TileGlobalPortId& global_port_id) const; bool global_port_is_set(const TileGlobalPortId& global_port_id) const; bool global_port_is_reset(const TileGlobalPortId& global_port_id) const; + bool global_port_thru_dedicated_network( + const TileGlobalPortId& global_port_id) const; std::string global_port_clock_arch_tree_name( const TileGlobalPortId& global_port_id) const; size_t global_port_default_value( diff --git a/libs/libarchopenfpga/src/write_xml_circuit_library.cpp b/libs/libarchopenfpga/src/write_xml_circuit_library.cpp index ac6867cea..42e392685 100644 --- a/libs/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libs/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -593,6 +593,15 @@ static void write_xml_circuit_model(std::fstream& fp, const char* fname, circuit_lib.model_name(circuit_lib.pass_gate_logic_model(model)).c_str()); fp << "/>" << "\n"; + fp << "\t\t\t" + << "" + << "\n"; } /* Write the ports of circuit model */ diff --git a/libs/libarchopenfpga/src/write_xml_routing_circuit.cpp b/libs/libarchopenfpga/src/write_xml_routing_circuit.cpp index 74eb8beac..691bfff6d 100644 --- a/libs/libarchopenfpga/src/write_xml_routing_circuit.cpp +++ b/libs/libarchopenfpga/src/write_xml_routing_circuit.cpp @@ -57,7 +57,7 @@ static void write_xml_direct_component_circuit( fp, "circuit_model_name", circuit_lib.model_name(arch_direct.circuit_model(direct_id)).c_str()); write_xml_attribute(fp, "type", - DIRECT_TYPE_STRING[arch_direct.type(direct_id)]); + DIRECT_TYPE_STRING[size_t(arch_direct.type(direct_id))]); write_xml_attribute(fp, "x_dir", DIRECT_DIRECTION_STRING[arch_direct.x_dir(direct_id)]); write_xml_attribute(fp, "y_dir", diff --git a/libs/libclkarchopenfpga/arch/example.xml b/libs/libclkarchopenfpga/arch/example.xml index ac6e722dd..9ba53a2f7 100644 --- a/libs/libclkarchopenfpga/arch/example.xml +++ b/libs/libclkarchopenfpga/arch/example.xml @@ -1,5 +1,5 @@ - - + + @@ -17,10 +17,10 @@ - - - - + + + + diff --git a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml new file mode 100644 index 000000000..6332695a0 --- /dev/null +++ b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index ee562bfd5..a1c16709c 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -18,7 +18,10 @@ namespace openfpga { // Begin namespace openfpga ***********************************************************************/ ClockNetwork::ClockNetwork() { default_segment_id_ = RRSegmentId::INVALID(); - default_switch_id_ = RRSwitchId::INVALID(); + default_tap_switch_id_ = RRSwitchId::INVALID(); + default_driver_switch_id_ = RRSwitchId::INVALID(); + /* Set a default invalid bounding box */ + empty_tap_bb_ = vtr::Rect(1, 0, 1, 0); is_dirty_ = true; } @@ -31,6 +34,12 @@ ClockNetwork::clock_tree_range ClockNetwork::trees() const { return vtr::make_range(tree_ids_.begin(), tree_ids_.end()); } +ClockNetwork::clock_internal_driver_range ClockNetwork::internal_drivers() + const { + return vtr::make_range(internal_driver_ids_.begin(), + internal_driver_ids_.end()); +} + std::vector ClockNetwork::levels( const ClockTreeId& tree_id) const { std::vector ret; @@ -172,11 +181,20 @@ RRSegmentId ClockNetwork::default_segment() const { return default_segment_id_; } -std::string ClockNetwork::default_switch_name() const { - return default_switch_name_; +std::string ClockNetwork::default_tap_switch_name() const { + return default_tap_switch_name_; } -RRSwitchId ClockNetwork::default_switch() const { return default_switch_id_; } +std::string ClockNetwork::default_driver_switch_name() const { + return default_driver_switch_name_; +} + +RRSwitchId ClockNetwork::default_tap_switch() const { + return default_tap_switch_id_; +} +RRSwitchId ClockNetwork::default_driver_switch() const { + return default_driver_switch_id_; +} std::string ClockNetwork::tree_name(const ClockTreeId& tree_id) const { VTR_ASSERT(valid_tree_id(tree_id)); @@ -199,9 +217,14 @@ size_t ClockNetwork::max_tree_depth() const { return max_size; } +BasicPort ClockNetwork::tree_global_port(const ClockTreeId& tree_id) const { + VTR_ASSERT(valid_tree_id(tree_id)); + return tree_global_ports_[tree_id]; +} + size_t ClockNetwork::tree_width(const ClockTreeId& tree_id) const { VTR_ASSERT(valid_tree_id(tree_id)); - return tree_widths_[tree_id]; + return tree_global_ports_[tree_id].get_width(); } size_t ClockNetwork::tree_depth(const ClockTreeId& tree_id) const { @@ -247,6 +270,54 @@ vtr::Point ClockNetwork::spine_end_point( return spine_end_points_[spine_id]; } +std::vector ClockNetwork::spine_intermediate_drivers( + const ClockSpineId& spine_id, const vtr::Point& coord) const { + VTR_ASSERT(valid_spine_id(spine_id)); + /* Convert coord to a unique string */ + std::string coord_str = + std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); + auto result = spine_intermediate_drivers_[spine_id].find(coord_str); + if (result == spine_intermediate_drivers_[spine_id].end()) { + return std::vector(); + } + return result->second; +} + +vtr::Point ClockNetwork::spine_intermediate_driver_routing_track_coord( + const ClockSpineId& spine_id, const vtr::Point& coord) const { + vtr::Point des_coord(coord.x(), coord.y()); + Direction des_spine_direction = spine_direction(spine_id); + /* des node depends on the type of routing track and direction. But it + * should be a starting point at the current SB[x][y] */ + if (des_spine_direction == Direction::INC && + spine_track_type(spine_id) == CHANX) { + des_coord.set_x(coord.x() + 1); + } + if (des_spine_direction == Direction::INC && + spine_track_type(spine_id) == CHANY) { + des_coord.set_y(coord.y() + 1); + } + return des_coord; +} + +std::vector +ClockNetwork::spine_intermediate_drivers_by_routing_track( + const ClockSpineId& spine_id, const vtr::Point& track_coord) const { + vtr::Point des_coord(track_coord.x(), track_coord.y()); + Direction des_spine_direction = spine_direction(spine_id); + /* des node depends on the type of routing track and direction. But it + * should be a starting point at the current SB[x][y] */ + if (des_spine_direction == Direction::INC && + spine_track_type(spine_id) == CHANX) { + des_coord.set_x(track_coord.x() - 1); + } + if (des_spine_direction == Direction::INC && + spine_track_type(spine_id) == CHANY) { + des_coord.set_y(track_coord.y() - 1); + } + return spine_intermediate_drivers(spine_id, des_coord); +} + ClockLevelId ClockNetwork::spine_level(const ClockSpineId& spine_id) const { VTR_ASSERT(valid_spine_id(spine_id)); if (is_dirty_) { @@ -315,17 +386,163 @@ vtr::Point ClockNetwork::spine_switch_point( return spine_switch_coords_[spine_id][size_t(switch_point_id)]; } -std::vector ClockNetwork::tree_taps( +std::vector +ClockNetwork::find_spine_switch_points_with_coord( + const ClockSpineId& spine_id, const vtr::Point& coord) const { + VTR_ASSERT(valid_spine_id(spine_id)); + std::vector ret; + for (size_t i = 0; i < spine_switch_points_[spine_id].size(); ++i) { + if (spine_switch_coords_[spine_id][i] == coord) { + ret.push_back(ClockSwitchPointId(i)); + } + } + + return ret; +} + +std::vector +ClockNetwork::spine_switch_point_internal_drivers( + const ClockSpineId& spine_id, + const ClockSwitchPointId& switch_point_id) const { + VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id)); + return spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)]; +} + +std::string ClockNetwork::internal_driver_from_pin( + const ClockInternalDriverId& int_driver_id) const { + VTR_ASSERT(valid_internal_driver_id(int_driver_id)); + return internal_driver_from_pins_[int_driver_id]; +} + +BasicPort ClockNetwork::internal_driver_to_pin( + const ClockInternalDriverId& int_driver_id) const { + VTR_ASSERT(valid_internal_driver_id(int_driver_id)); + return internal_driver_to_pins_[int_driver_id]; +} + +std::vector ClockNetwork::tree_taps( const ClockTreeId& tree_id) const { VTR_ASSERT(valid_tree_id(tree_id)); return tree_taps_[tree_id]; } -std::vector ClockNetwork::tree_flatten_taps( - const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const { +BasicPort ClockNetwork::tap_from_port(const ClockTapId& tap_id) const { + VTR_ASSERT(valid_tap_id(tap_id)); + return tap_from_ports_[tap_id]; +} + +std::string ClockNetwork::tap_to_port(const ClockTapId& tap_id) const { + VTR_ASSERT(valid_tap_id(tap_id)); + return tap_to_ports_[tap_id]; +} + +ClockNetwork::e_tap_type ClockNetwork::tap_type( + const ClockTapId& tap_id) const { + VTR_ASSERT(valid_tap_id(tap_id)); + /* If not a region, it is a default type covering all the coordinates*/ + if (tap_bbs_[tap_id] == empty_tap_bb_) { + return ClockNetwork::e_tap_type::ALL; + } + /* Now check if this a single point */ + if (tap_bbs_[tap_id].height() == 0 && tap_bbs_[tap_id].width() == 0) { + return ClockNetwork::e_tap_type::SINGLE; + } + return ClockNetwork::e_tap_type::REGION; +} + +size_t ClockNetwork::tap_x(const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE); + return tap_bbs_[tap_id].xmin(); +} + +size_t ClockNetwork::tap_y(const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE); + return tap_bbs_[tap_id].ymin(); +} + +vtr::Rect ClockNetwork::tap_bounding_box( + const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION); + return tap_bbs_[tap_id]; +} + +size_t ClockNetwork::tap_step_x(const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION); + return tap_bb_steps_[tap_id].x(); +} + +size_t ClockNetwork::tap_step_y(const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION); + return tap_bb_steps_[tap_id].y(); +} + +bool ClockNetwork::valid_tap_coord_in_bb( + const ClockTapId& tap_id, const vtr::Point& tap_coord) const { + VTR_ASSERT(valid_tap_id(tap_id)); + if (tap_type(tap_id) == ClockNetwork::e_tap_type::ALL) { + return true; + } + if (tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE && + tap_bbs_[tap_id].coincident(tap_coord)) { + return true; + } + if (tap_type(tap_id) == ClockNetwork::e_tap_type::REGION && + tap_bbs_[tap_id].coincident(tap_coord)) { + /* Check if steps are considered, coords still matches */ + bool x_in_bb = false; + for (size_t ix = tap_bbs_[tap_id].xmin(); ix <= tap_bbs_[tap_id].xmax(); + ix = ix + tap_bb_steps_[tap_id].x()) { + if (tap_coord.x() == ix) { + x_in_bb = true; + break; + } + } + /* Early exit */ + if (!x_in_bb) { + return false; + } + bool y_in_bb = false; + for (size_t iy = tap_bbs_[tap_id].ymin(); iy <= tap_bbs_[tap_id].ymax(); + iy = iy + tap_bb_steps_[tap_id].y()) { + if (tap_coord.y() == iy) { + y_in_bb = true; + break; + } + } + if (y_in_bb && x_in_bb) { + return true; + } + } + return false; +} + +std::vector ClockNetwork::tree_flatten_tap_to_ports( + const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, + const vtr::Point& tap_coord) const { VTR_ASSERT(valid_tree_id(tree_id)); std::vector flatten_taps; - for (const std::string& tap_name : tree_taps_[tree_id]) { + for (ClockTapId tap_id : tree_taps_[tree_id]) { + VTR_ASSERT(valid_tap_id(tap_id)); + /* Filter out unmatched from ports. Expect [clk_pin_id:clk_pin_id] */ + BasicPort from_port = tap_from_ports_[tap_id]; + if (!from_port.is_valid()) { + VTR_LOG_ERROR("Invalid from port name '%s' whose index is not valid\n", + from_port.to_verilog_string().c_str()); + exit(1); + } + if (from_port.get_width() != 1) { + VTR_LOG_ERROR("Invalid from port name '%s' whose width is not 1\n", + from_port.to_verilog_string().c_str()); + exit(1); + } + if (from_port.get_lsb() != size_t(clk_pin_id)) { + continue; + } + /* Filter out unmatched coordinates */ + if (!valid_tap_coord_in_bb(tap_id, tap_coord)) { + continue; + } + std::string tap_name = tap_to_ports_[tap_id]; StringToken tokenizer(tap_name); std::vector pin_tokens = tokenizer.split("."); if (pin_tokens.size() != 2) { @@ -351,9 +568,6 @@ std::vector ClockNetwork::tree_flatten_taps( std::string flatten_tile_str = tile_info.get_name() + "[" + std::to_string(tile_idx) + "]"; for (size_t& pin_idx : pin_info.pins()) { - if (pin_idx != size_t(clk_pin_id)) { - continue; - } std::string flatten_pin_str = pin_info.get_name() + "[" + std::to_string(pin_idx) + "]"; flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str); @@ -363,6 +577,63 @@ std::vector ClockNetwork::tree_flatten_taps( return flatten_taps; } +std::vector ClockNetwork::flatten_internal_driver_from_pin( + const ClockInternalDriverId& int_driver_id, + const ClockTreePinId& clk_pin_id) const { + std::vector flatten_taps; + BasicPort des_pin = internal_driver_to_pin(int_driver_id); + if (!des_pin.is_valid()) { + VTR_LOG_ERROR( + "Invalid internal driver destination port name '%s' whose index is not " + "valid\n", + des_pin.to_verilog_string().c_str()); + exit(1); + } + if (des_pin.get_width() != 1) { + VTR_LOG_ERROR( + "Invalid internal driver destination port name '%s' whose width is not " + "1\n", + des_pin.to_verilog_string().c_str()); + exit(1); + } + if (des_pin.get_lsb() != size_t(clk_pin_id)) { + return flatten_taps; + } + + std::string tap_name = internal_driver_from_pin(int_driver_id); + StringToken tokenizer(tap_name); + std::vector pin_tokens = tokenizer.split("."); + if (pin_tokens.size() != 2) { + VTR_LOG_ERROR("Invalid pin name '%s'. Expect .\n", + tap_name.c_str()); + exit(1); + } + PortParser tile_parser(pin_tokens[0]); + BasicPort tile_info = tile_parser.port(); + PortParser pin_parser(pin_tokens[1]); + BasicPort pin_info = pin_parser.port(); + if (!tile_info.is_valid()) { + VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n", + tap_name.c_str()); + exit(1); + } + if (!pin_info.is_valid()) { + VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n", + tap_name.c_str()); + exit(1); + } + for (size_t& tile_idx : tile_info.pins()) { + std::string flatten_tile_str = + tile_info.get_name() + "[" + std::to_string(tile_idx) + "]"; + for (size_t& pin_idx : pin_info.pins()) { + std::string flatten_pin_str = + pin_info.get_name() + "[" + std::to_string(pin_idx) + "]"; + flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str); + } + } + return flatten_taps; +} + ClockTreeId ClockNetwork::find_tree(const std::string& name) const { auto result = tree_name2id_map_.find(name); if (result == tree_name2id_map_.end()) { @@ -400,6 +671,8 @@ void ClockNetwork::reserve_spines(const size_t& num_spines) { spine_track_types_.reserve(num_spines); spine_switch_points_.reserve(num_spines); spine_switch_coords_.reserve(num_spines); + spine_switch_internal_drivers_.reserve(num_spines); + spine_intermediate_drivers_.reserve(num_spines); spine_parents_.reserve(num_spines); spine_children_.reserve(num_spines); spine_parent_trees_.reserve(num_spines); @@ -408,7 +681,7 @@ void ClockNetwork::reserve_spines(const size_t& num_spines) { void ClockNetwork::reserve_trees(const size_t& num_trees) { tree_ids_.reserve(num_trees); tree_names_.reserve(num_trees); - tree_widths_.reserve(num_trees); + tree_global_ports_.reserve(num_trees); tree_top_spines_.reserve(num_trees); tree_taps_.reserve(num_trees); } @@ -417,25 +690,40 @@ void ClockNetwork::set_default_segment(const RRSegmentId& seg_id) { default_segment_id_ = seg_id; } -void ClockNetwork::set_default_switch(const RRSwitchId& switch_id) { - default_switch_id_ = switch_id; +void ClockNetwork::set_default_tap_switch(const RRSwitchId& switch_id) { + default_tap_switch_id_ = switch_id; +} + +void ClockNetwork::set_default_driver_switch(const RRSwitchId& switch_id) { + default_driver_switch_id_ = switch_id; } void ClockNetwork::set_default_segment_name(const std::string& name) { default_segment_name_ = name; } -void ClockNetwork::set_default_switch_name(const std::string& name) { - default_switch_name_ = name; +void ClockNetwork::set_default_tap_switch_name(const std::string& name) { + default_tap_switch_name_ = name; } -ClockTreeId ClockNetwork::create_tree(const std::string& name, size_t width) { +void ClockNetwork::set_default_driver_switch_name(const std::string& name) { + default_driver_switch_name_ = name; +} + +ClockTreeId ClockNetwork::create_tree(const std::string& name, + const BasicPort& global_port) { + /* Sanity checks */ + if (!global_port.is_valid()) { + VTR_LOG_ERROR("Invalid global port '%s' for clock tree name '%s'\n", + global_port.to_verilog_string().c_str(), name.c_str()); + exit(1); + } /* Create a new id */ ClockTreeId tree_id = ClockTreeId(tree_ids_.size()); tree_ids_.push_back(tree_id); tree_names_.push_back(name); - tree_widths_.push_back(width); + tree_global_ports_.push_back(global_port); tree_depths_.emplace_back(); tree_taps_.emplace_back(); tree_top_spines_.emplace_back(); @@ -476,6 +764,8 @@ ClockSpineId ClockNetwork::create_spine(const std::string& name) { spine_track_types_.emplace_back(NUM_RR_TYPES); spine_switch_points_.emplace_back(); spine_switch_coords_.emplace_back(); + spine_switch_internal_drivers_.emplace_back(); + spine_intermediate_drivers_.emplace_back(); spine_parents_.emplace_back(); spine_children_.emplace_back(); spine_parent_trees_.emplace_back(); @@ -526,13 +816,14 @@ void ClockNetwork::set_spine_track_type(const ClockSpineId& spine_id, spine_track_types_[spine_id] = type; } -void ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id, - const ClockSpineId& drive_spine_id, - const vtr::Point& coord) { +ClockSwitchPointId ClockNetwork::add_spine_switch_point( + const ClockSpineId& spine_id, const ClockSpineId& drive_spine_id, + const vtr::Point& coord) { VTR_ASSERT(valid_spine_id(spine_id)); VTR_ASSERT(valid_spine_id(drive_spine_id)); spine_switch_points_[spine_id].push_back(drive_spine_id); spine_switch_coords_[spine_id].push_back(coord); + spine_switch_internal_drivers_[spine_id].emplace_back(); /* Do not allow any spine has different parents */ if (spine_parents_[drive_spine_id]) { VTR_LOG_ERROR( @@ -545,12 +836,143 @@ void ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id, } spine_parents_[drive_spine_id] = spine_id; spine_children_[spine_id].push_back(drive_spine_id); + return ClockSwitchPointId(spine_switch_points_[spine_id].size() - 1); } -void ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, - const std::string& pin_name) { +ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( + const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, + const std::string& int_driver_from_port, + const std::string& int_driver_to_port) { + VTR_ASSERT(valid_spine_id(spine_id)); + VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id)); + /* Parse ports */ + PortParser to_pin_parser(int_driver_to_port); + /* Find any existing id for the driver port */ + for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { + if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port && + internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) { + spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)] + .push_back(int_driver_id); + return int_driver_id; + } + } + /* Reaching here, no existing id can be reused, create a new one */ + ClockInternalDriverId int_driver_id = + ClockInternalDriverId(internal_driver_ids_.size()); + internal_driver_ids_.push_back(int_driver_id); + internal_driver_from_pins_.push_back(int_driver_from_port); + internal_driver_to_pins_.push_back(to_pin_parser.port()); + spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back( + int_driver_id); + return int_driver_id; +} + +ClockInternalDriverId ClockNetwork::add_spine_intermediate_driver( + const ClockSpineId& spine_id, const vtr::Point& coord, + const std::string& int_driver_from_port, + const std::string& int_driver_to_port) { + VTR_ASSERT(valid_spine_id(spine_id)); + /* Convert coord to a unique string */ + std::string coord_str = + std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); + /* Parse ports */ + PortParser to_pin_parser(int_driver_to_port); + /* Find any existing id for the driver port */ + ClockInternalDriverId int_driver_id_to_add = + ClockInternalDriverId(internal_driver_ids_.size()); + for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { + if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port && + internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) { + int_driver_id_to_add = int_driver_id; + break; + } + } + /* Reaching here, no existing id can be reused, create a new one */ + if (int_driver_id_to_add == + ClockInternalDriverId(internal_driver_ids_.size())) { + internal_driver_ids_.push_back(int_driver_id_to_add); + internal_driver_from_pins_.push_back(int_driver_from_port); + internal_driver_to_pins_.push_back(to_pin_parser.port()); + } + /* Add it to existing map, avoid duplicated id */ + auto result = spine_intermediate_drivers_[spine_id].find(coord_str); + if (result == spine_intermediate_drivers_[spine_id].end()) { + spine_intermediate_drivers_[spine_id][coord_str].push_back( + int_driver_id_to_add); + } else { + if (std::find(result->second.begin(), result->second.end(), + int_driver_id_to_add) == result->second.end()) { + result->second.push_back(int_driver_id_to_add); + } else { + VTR_LOG_WARN( + "Skip intermediate driver (from_port='%s', to_port='%s') at (%s) as it " + "is duplicated in the clock architecture description file!\n", + int_driver_from_port.c_str(), int_driver_to_port.c_str(), + coord_str.c_str()); + } + } + return int_driver_id_to_add; +} + +ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, + const BasicPort& from_port, + const std::string& to_port) { VTR_ASSERT(valid_tree_id(tree_id)); - tree_taps_[tree_id].push_back(pin_name); + /* TODO: Consider find existing tap template and avoid duplication in storage + */ + ClockTapId tap_id = ClockTapId(tap_ids_.size()); + tap_ids_.push_back(tap_id); + tap_from_ports_.push_back(from_port); + tap_to_ports_.push_back(to_port); + tap_bbs_.emplace_back(empty_tap_bb_); + tap_bb_steps_.emplace_back(vtr::Point(0, 0)); + tree_taps_[tree_id].push_back(tap_id); + return tap_id; +} + +bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, + const vtr::Rect& bb) { + VTR_ASSERT(valid_tap_id(tap_id)); + /* Check the bounding box, ensure it must be valid */ + if (bb.xmax() < bb.xmin() || bb.ymax() < bb.ymin()) { + VTR_LOG_ERROR( + "Invalid bounding box (xlow=%lu, ylow=%lu) -> (xhigh=%lu, yhigh=%lu)! " + "Must follow: xlow <= xhigh, ylow <= yhigh!\n", + bb.xmin(), bb.ymin(), bb.xmax(), bb.ymax()); + return false; + } + tap_bbs_[tap_id] = bb; + return true; +} + +bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id, + const size_t& step) { + VTR_ASSERT(valid_tap_id(tap_id)); + /* Must be a valid step >= 1 */ + if (step == 0) { + VTR_LOG_ERROR( + "Invalid x-direction step (=%lu) for any bounding box! Expect an integer " + ">= 1!\n", + step); + return false; + } + tap_bb_steps_[tap_id].set_x(step); + return true; +} + +bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id, + const size_t& step) { + VTR_ASSERT(valid_tap_id(tap_id)); + /* Must be a valid step >= 1 */ + if (step == 0) { + VTR_LOG_ERROR( + "Invalid y-direction step (=%lu) for any bounding box! Expect an integer " + ">= 1!\n", + step); + return false; + } + tap_bb_steps_[tap_id].set_y(step); + return true; } bool ClockNetwork::link() { @@ -562,6 +984,25 @@ bool ClockNetwork::link() { return true; } +bool ClockNetwork::validate_tree_taps() const { + for (ClockTreeId tree_id : trees()) { + for (ClockTapId tap_id : tree_taps(tree_id)) { + /* The from pin name should match the global port */ + if (!tree_global_port(tree_id).mergeable(tap_from_port(tap_id)) || + !tree_global_port(tree_id).contained(tap_from_port(tap_id))) { + VTR_LOG_ERROR( + "Tap point from_port '%s' is not part of the global port '%s' of " + "tree '%s'\n", + tap_from_port(tap_id).to_verilog_string().c_str(), + tree_global_port(tree_id).to_verilog_string().c_str(), + tree_name(tree_id).c_str()); + return false; + } + } + } + return true; +} + bool ClockNetwork::validate_tree() const { for (ClockTreeId tree_id : trees()) { for (ClockSpineId spine_id : spines(tree_id)) { @@ -622,7 +1063,8 @@ bool ClockNetwork::validate_tree() const { bool ClockNetwork::validate() const { is_dirty_ = true; - if (default_segment_id_ && default_switch_id_ && validate_tree()) { + if (default_segment_id_ && default_tap_switch_id_ && + default_driver_switch_id_ && validate_tree() && validate_tree_taps()) { is_dirty_ = false; } return true; @@ -698,6 +1140,16 @@ bool ClockNetwork::valid_tree_id(const ClockTreeId& tree_id) const { (tree_id == tree_ids_[tree_id]); } +bool ClockNetwork::valid_internal_driver_id( + const ClockInternalDriverId& int_driver_id) const { + return (size_t(int_driver_id) < internal_driver_ids_.size()) && + (int_driver_id == internal_driver_ids_[int_driver_id]); +} + +bool ClockNetwork::valid_tap_id(const ClockTapId& tap_id) const { + return (size_t(tap_id) < tap_ids_.size()) && (tap_id == tap_ids_[tap_id]); +} + bool ClockNetwork::valid_level_id(const ClockTreeId& tree_id, const ClockLevelId& lvl_id) const { return valid_tree_id(tree_id) && (size_t(lvl_id) < tree_depth(tree_id)); diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 0b9b8a42b..9f7fe0fcb 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -14,6 +14,7 @@ /* Headers from openfpgautil library */ #include "clock_network_fwd.h" +#include "openfpga_port.h" #include "rr_graph_fwd.h" #include "rr_node_types.h" @@ -42,6 +43,14 @@ class ClockNetwork { clock_tree_iterator; /* Create range */ typedef vtr::Range clock_tree_range; + typedef vtr::vector::const_iterator + clock_internal_driver_iterator; + /* Create range */ + typedef vtr::Range + clock_internal_driver_range; + /* Type of tap points */ + enum class e_tap_type : unsigned char { ALL = 0, SINGLE, REGION, NUM_TYPES }; public: /* Constructors */ ClockNetwork(); @@ -49,6 +58,7 @@ class ClockNetwork { public: /* Accessors: aggregates */ size_t num_trees() const; clock_tree_range trees() const; + clock_internal_driver_range internal_drivers() const; /* Return the range of clock levels */ std::vector levels(const ClockTreeId& tree_id) const; /* Return a list of spine id under a clock tree */ @@ -73,9 +83,12 @@ class ClockNetwork { * information from RRGraph */ RRSegmentId default_segment() const; std::string default_segment_name() const; - RRSwitchId default_switch() const; - std::string default_switch_name() const; + RRSwitchId default_tap_switch() const; + std::string default_tap_switch_name() const; + RRSwitchId default_driver_switch() const; + std::string default_driver_switch_name() const; std::string tree_name(const ClockTreeId& tree_id) const; + BasicPort tree_global_port(const ClockTreeId& tree_id) const; size_t tree_width(const ClockTreeId& tree_id) const; size_t tree_depth(const ClockTreeId& tree_id) const; size_t max_tree_width() const; @@ -84,6 +97,27 @@ class ClockNetwork { std::string spine_name(const ClockSpineId& spine_id) const; vtr::Point spine_start_point(const ClockSpineId& spine_id) const; vtr::Point spine_end_point(const ClockSpineId& spine_id) const; + /* Find the intermediate drivers by the SB coordinate */ + std::vector spine_intermediate_drivers( + const ClockSpineId& spine_id, const vtr::Point& coord) const; + /* Find the coordinate of routing track which the intermediate driver will + * driver. Note that the coordinate may be different than the coordinate of + * intermeidate driver. One of the exceptions lies in the CHANX with INC + * direction, which starts actually on the routing tracks on the right side of + * a SB, resulting in x -> x + 1. Another exception is on the CHANY with INC + * direction, which starts actually on the routing tracks on the top side of a + * SB, resulting in y - > y + 1. This function is to provide an official + * conversion the coordinates. */ + vtr::Point spine_intermediate_driver_routing_track_coord( + const ClockSpineId& spine_id, const vtr::Point& coord) const; + /* Find the intermediate drivers by the routing track starting point. Note + * that the routing track starting point may be different from the SB + * coordinate. See the exceptions in the + * spine_intermediate_driver_track_coord() */ + std::vector + spine_intermediate_drivers_by_routing_track( + const ClockSpineId& spine_id, const vtr::Point& track_coord) const; + /* Return the level where the spine locates in the multi-layer clock tree * structure */ ClockLevelId spine_level(const ClockSpineId& spine_id) const; @@ -114,15 +148,51 @@ class ClockNetwork { vtr::Point spine_switch_point( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const; + + /* Find all the switching points at a given coordinate */ + std::vector find_spine_switch_points_with_coord( + const ClockSpineId& spine_id, const vtr::Point& coord) const; + + std::vector spine_switch_point_internal_drivers( + const ClockSpineId& spine_id, + const ClockSwitchPointId& switch_point_id) const; + std::string internal_driver_from_pin( + const ClockInternalDriverId& int_driver_id) const; + std::vector flatten_internal_driver_from_pin( + const ClockInternalDriverId& int_driver_id, + const ClockTreePinId& clk_pin_id) const; + BasicPort internal_driver_to_pin( + const ClockInternalDriverId& int_driver_id) const; + /* Return the original list of tap pins that is in storage; useful for parsers */ - std::vector tree_taps(const ClockTreeId& tree_id) const; + std::vector tree_taps(const ClockTreeId& tree_id) const; + /* Return the source ports for a given tap */ + BasicPort tap_from_port(const ClockTapId& tap_id) const; + /* Return the destination ports for a given tap */ + std::string tap_to_port(const ClockTapId& tap_id) const; + /* Find the type of tap point: + * all -> all coordinates in efpga are required to tap + * single -> only 1 coordinate is required to tap + * region -> coordinates in a region required to tap. Steps in region may be + * required + */ + e_tap_type tap_type(const ClockTapId& tap_id) const; + /* Require the type of single */ + size_t tap_x(const ClockTapId& tap_id) const; + size_t tap_y(const ClockTapId& tap_id) const; + /* Require the type of region */ + vtr::Rect tap_bounding_box(const ClockTapId& tap_id) const; + /* Steps are only available when type is region */ + size_t tap_step_x(const ClockTapId& tap_id) const; + size_t tap_step_y(const ClockTapId& tap_id) const; /* Return the list of flatten tap pins. For example: clb[0:1].clk[2:2] is * flatten to { clb[0].clk[2], clb[1].clk[2] } Useful to build clock routing * resource graph Note that the clk_pin_id limits only 1 clock to be accessed */ - std::vector tree_flatten_taps( - const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const; + std::vector tree_flatten_tap_to_ports( + const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, + const vtr::Point& tap_coord) const; /* Find a spine with a given name, if not found, return an valid id, otherwise * return an invalid one */ ClockSpineId find_spine(const std::string& name) const; @@ -145,12 +215,15 @@ class ClockNetwork { /* Reserve a number of trees to be memory efficent */ void reserve_trees(const size_t& num_trees); void set_default_segment(const RRSegmentId& seg_id); - void set_default_switch(const RRSwitchId& switch_id); + void set_default_tap_switch(const RRSwitchId& switch_id); + void set_default_driver_switch(const RRSwitchId& switch_id); void set_default_segment_name(const std::string& name); - void set_default_switch_name(const std::string& name); + void set_default_tap_switch_name(const std::string& name); + void set_default_driver_switch_name(const std::string& name); /* Create a new tree, by default the tree can accomodate only 1 clock signal; * use width to adjust the size */ - ClockTreeId create_tree(const std::string& name, size_t width = 1); + ClockTreeId create_tree(const std::string& name, + const BasicPort& global_port); /* Create a new spine, if the spine is already created, return an invalid id */ ClockSpineId create_spine(const std::string& name); @@ -168,10 +241,24 @@ class ClockNetwork { void set_spine_direction(const ClockSpineId& spine_id, const Direction& dir); void set_spine_track_type(const ClockSpineId& spine_id, const t_rr_type& type); - void add_spine_switch_point(const ClockSpineId& spine_id, - const ClockSpineId& drive_spine_id, - const vtr::Point& coord); - void add_tree_tap(const ClockTreeId& tree_id, const std::string& pin_name); + ClockSwitchPointId add_spine_switch_point(const ClockSpineId& spine_id, + const ClockSpineId& drive_spine_id, + const vtr::Point& coord); + ClockInternalDriverId add_spine_switch_point_internal_driver( + const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, + const std::string& internal_driver_from_port, + const std::string& internal_driver_to_port); + ClockInternalDriverId add_spine_intermediate_driver( + const ClockSpineId& spine_id, const vtr::Point& coord, + const std::string& internal_driver_from_port, + const std::string& internal_driver_to_port); + ClockTapId add_tree_tap(const ClockTreeId& tree_id, + const BasicPort& from_port, + const std::string& to_port); + bool set_tap_bounding_box(const ClockTapId& tap_id, + const vtr::Rect& bb); + bool set_tap_step_x(const ClockTapId& tap_id, const size_t& step); + bool set_tap_step_y(const ClockTapId& tap_id, const size_t& step); /* Build internal links between clock tree, spines etc. This is also an * validator to verify the correctness of the clock network. Must run before * using the data! */ @@ -208,7 +295,16 @@ class ClockNetwork { private: /* Public invalidators/validators */ /* Ensure tree data is clean. All the spines are valid, and switch points are * valid */ + bool validate_tree_taps() const; bool validate_tree() const; + /* Show if the internal driver id is a valid for data queries */ + bool valid_internal_driver_id( + const ClockInternalDriverId& int_driver_id) const; + /* Show if the tap id is a valid for data queries */ + bool valid_tap_id(const ClockTapId& tap_id) const; + /* Check if a given coordinate matches the requirements for a tap point */ + bool valid_tap_coord_in_bb(const ClockTapId& tap_id, + const vtr::Point& tap_coord) const; private: /* Private mutators */ /* Build internal links between spines under a given tree */ @@ -226,10 +322,10 @@ class ClockNetwork { /* Basic information of each tree */ vtr::vector tree_ids_; vtr::vector tree_names_; - vtr::vector tree_widths_; + vtr::vector tree_global_ports_; vtr::vector tree_depths_; vtr::vector> tree_top_spines_; - vtr::vector> tree_taps_; + vtr::vector> tree_taps_; /* Basic information of each spine */ vtr::vector spine_ids_; @@ -241,22 +337,47 @@ class ClockNetwork { vtr::vector spine_track_types_; vtr::vector> spine_switch_points_; vtr::vector>> spine_switch_coords_; + vtr::vector>> + spine_switch_internal_drivers_; + vtr::vector>> + spine_intermediate_drivers_; vtr::vector spine_parents_; vtr::vector> spine_children_; vtr::vector spine_parent_trees_; + /* Basic Information about internal drivers */ + vtr::vector + internal_driver_ids_; + vtr::vector internal_driver_from_pins_; + vtr::vector internal_driver_to_pins_; + /* Basic information about tap */ + vtr::vector tap_ids_; + vtr::vector tap_from_ports_; + vtr::vector tap_to_ports_; + vtr::vector> + tap_bbs_; /* Bounding box for tap points, (xlow, ylow) -> (xhigh, yhigh) */ + vtr::vector> + tap_bb_steps_; /* x() -> x-direction step, y() -> y-direction step */ + /* Default routing resource */ std::string default_segment_name_; /* The routing segment representing the clock wires */ RRSegmentId default_segment_id_; - std::string - default_switch_name_; /* The routing switch interconnecting clock wire */ - RRSwitchId default_switch_id_; + std::string default_tap_switch_name_; /* The routing switch interconnecting + clock wire */ + RRSwitchId default_tap_switch_id_; + std::string default_driver_switch_name_; /* The routing switch interconnecting + clock wire */ + RRSwitchId default_driver_switch_id_; /* Fast lookup */ std::map tree_name2id_map_; std::map spine_name2id_map_; + /* Constants */ + vtr::Rect empty_tap_bb_; + /* Flags */ mutable bool is_dirty_; }; diff --git a/libs/libclkarchopenfpga/src/base/clock_network_fwd.h b/libs/libclkarchopenfpga/src/base/clock_network_fwd.h index 1285f069c..dc329d04b 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network_fwd.h +++ b/libs/libclkarchopenfpga/src/base/clock_network_fwd.h @@ -19,12 +19,16 @@ struct clock_tree_id_tag; struct clock_tree_pin_id_tag; struct clock_spine_id_tag; struct clock_switch_point_id_tag; +struct clock_internal_driver_id_tag; +struct clock_tap_id_tag; typedef vtr::StrongId ClockLevelId; typedef vtr::StrongId ClockTreeId; typedef vtr::StrongId ClockTreePinId; typedef vtr::StrongId ClockSpineId; typedef vtr::StrongId ClockSwitchPointId; +typedef vtr::StrongId ClockInternalDriverId; +typedef vtr::StrongId ClockTapId; /* Short declaration of class */ class ClockNetwork; diff --git a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp index f47284281..320d1300e 100644 --- a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp +++ b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp @@ -10,7 +10,8 @@ RRClockSpatialLookup::RRClockSpatialLookup() {} RRNodeId RRClockSpatialLookup::find_node(int x, int y, const ClockTreeId& tree, const ClockLevelId& lvl, const ClockTreePinId& pin, - const Direction& direction) const { + const Direction& direction, + const bool& verbose) const { size_t dir = size_t(direction); /* Pre-check: the x, y, side and ptc should be non negative numbers! * Otherwise, return an invalid id */ @@ -25,33 +26,33 @@ RRNodeId RRClockSpatialLookup::find_node(int x, int y, const ClockTreeId& tree, * - Return an invalid id if any out-of-range is detected */ if (size_t(dir) >= rr_node_indices_.size()) { - VTR_LOG("Direction out of range"); + VTR_LOGV(verbose, "Direction out of range\n"); return RRNodeId::INVALID(); } if (size_t(x) >= rr_node_indices_[dir].dim_size(0)) { - VTR_LOG("X out of range"); + VTR_LOGV(verbose, "X out of range\n"); return RRNodeId::INVALID(); } if (size_t(y) >= rr_node_indices_[dir].dim_size(1)) { - VTR_LOG("Y out of range"); + VTR_LOG("Y out of range\n"); return RRNodeId::INVALID(); } if (size_t(tree) >= rr_node_indices_[dir][x][y].size()) { - VTR_LOG("Tree id out of range"); + VTR_LOGV(verbose, "Tree id out of range\n"); return RRNodeId::INVALID(); } if (size_t(lvl) == rr_node_indices_[dir][x][y][size_t(tree)].size()) { - VTR_LOG("Level id out of range"); + VTR_LOGV(verbose, "Level id out of range\n"); return RRNodeId::INVALID(); } if (size_t(pin) == rr_node_indices_[dir][x][y][size_t(tree)][size_t(lvl)].size()) { - VTR_LOG("Pin id out of range"); + VTR_LOGV(verbose, "Pin id out of range\n"); return RRNodeId::INVALID(); } diff --git a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h index 650c3e368..01df8ab9f 100644 --- a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h +++ b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h @@ -58,7 +58,7 @@ class RRClockSpatialLookup { */ RRNodeId find_node(int x, int y, const ClockTreeId& tree, const ClockLevelId& lvl, const ClockTreePinId& pin, - const Direction& direction) const; + const Direction& direction, const bool& verbose) const; /* -- Mutators -- */ public: diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index db7216f2d..2a1838c07 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -6,11 +6,13 @@ constexpr const char* XML_CLOCK_NETWORK_ROOT_NAME = "clock_networks"; constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SEGMENT = "default_segment"; -constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SWITCH = - "default_switch"; +constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_TAP_SWITCH = + "default_tap_switch"; +constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_DRIVER_SWITCH = + "default_driver_switch"; constexpr const char* XML_CLOCK_TREE_NODE_NAME = "clock_network"; constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_NAME = "name"; -constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_WIDTH = "width"; +constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT = "global_port"; constexpr const char* XML_CLOCK_SPINE_NODE_NAME = "spine"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_NAME = "name"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_START_X = "start_x"; @@ -19,12 +21,38 @@ constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_X = "end_x"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_Y = "end_y"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_TYPE = "type"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_DIRECTION = "direction"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME = + "intermediate_driver"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME = "tap"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X = "x"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y = "y"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN = + "from_pin"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN = + "to_pin"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point"; +constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = + "internal_driver"; +constexpr const char* + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_FROM_PIN = "from_pin"; +constexpr const char* + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN = "to_pin"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_TAP = "tap"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X = "x"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y = "y"; constexpr const char* XML_CLOCK_TREE_TAPS_NODE_NAME = "taps"; -constexpr const char* XML_CLOCK_TREE_TAP_NODE_NAME = "tap"; -constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN = "tile_pin"; +constexpr const char* XML_CLOCK_TREE_TAP_ALL_NODE_NAME = "all"; +constexpr const char* XML_CLOCK_TREE_TAP_REGION_NODE_NAME = "region"; +constexpr const char* XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME = "single"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN = "from_pin"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN = "to_pin"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_X = "x"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_Y = "y"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX = "start_x"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY = "start_y"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX = "end_x"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY = "end_y"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATX = "repeat_x"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATY = "repeat_y"; #endif diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index ed083f483..418e43611 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -25,21 +25,107 @@ namespace openfpga { // Begin namespace openfpga /******************************************************************** - * Parse XML codes of a to an object of ClockNetwork + * Parse XML codes of a to an object of ClockNetwork *******************************************************************/ -static void read_xml_clock_tree_tap(pugi::xml_node& xml_tap, - const pugiutil::loc_data& loc_data, - ClockNetwork& clk_ntwk, - const ClockTreeId& tree_id) { +static void read_xml_clock_tree_tap_type_all(pugi::xml_node& xml_tap, + const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, + const ClockTreeId& tree_id) { if (!clk_ntwk.valid_tree_id(tree_id)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap), "Invalid id of a clock tree!\n"); } - std::string tile_pin_name = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN, loc_data) + std::string from_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, loc_data) .as_string(); - clk_ntwk.add_tree_tap(tree_id, tile_pin_name); + std::string to_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) + .as_string(); + PortParser from_port_parser(from_pin_name); + clk_ntwk.add_tree_tap(tree_id, from_port_parser.port(), to_pin_name); +} + +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_tree_tap_type_single( + pugi::xml_node& xml_tap, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) { + if (!clk_ntwk.valid_tree_id(tree_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap), + "Invalid id of a clock tree!\n"); + } + + std::string from_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, loc_data) + .as_string(); + std::string to_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) + .as_string(); + PortParser from_port_parser(from_pin_name); + ClockTapId tap_id = + clk_ntwk.add_tree_tap(tree_id, from_port_parser.port(), to_pin_name); + + /* Single tap only require a coordinate */ + size_t tap_x = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, + loc_data, pugiutil::ReqOpt::REQUIRED) + .as_int(); + size_t tap_y = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, + loc_data, pugiutil::ReqOpt::REQUIRED) + .as_int(); + clk_ntwk.set_tap_bounding_box(tap_id, + vtr::Rect(tap_x, tap_y, tap_x, tap_y)); +} + +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_tree_tap_type_region( + pugi::xml_node& xml_tap, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) { + if (!clk_ntwk.valid_tree_id(tree_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap), + "Invalid id of a clock tree!\n"); + } + + std::string from_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, loc_data) + .as_string(); + std::string to_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) + .as_string(); + PortParser from_port_parser(from_pin_name); + ClockTapId tap_id = + clk_ntwk.add_tree_tap(tree_id, from_port_parser.port(), to_pin_name); + + /* Region require a bounding box */ + size_t tap_start_x = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data, + pugiutil::ReqOpt::REQUIRED) + .as_int(); + size_t tap_start_y = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data, + pugiutil::ReqOpt::REQUIRED) + .as_int(); + size_t tap_end_x = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, + loc_data, pugiutil::ReqOpt::REQUIRED) + .as_int(); + size_t tap_end_y = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, + loc_data, pugiutil::ReqOpt::REQUIRED) + .as_int(); + clk_ntwk.set_tap_bounding_box( + tap_id, vtr::Rect(tap_start_x, tap_start_y, tap_end_x, tap_end_y)); + + /* Default step is all 1 */ + size_t tap_step_x = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATX, loc_data) + .as_int(1); + size_t tap_step_y = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATY, loc_data) + .as_int(1); + clk_ntwk.set_tap_step_x(tap_id, tap_step_x); + clk_ntwk.set_tap_step_y(tap_id, tap_step_y); } static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps, @@ -48,14 +134,76 @@ static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps, const ClockTreeId& tree_id) { for (pugi::xml_node xml_tap : xml_taps.children()) { /* Error out if the XML child has an invalid name! */ - if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_NODE_NAME)) { - read_xml_clock_tree_tap(xml_tap, loc_data, clk_ntwk, tree_id); + if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_ALL_NODE_NAME)) { + read_xml_clock_tree_tap_type_all(xml_tap, loc_data, clk_ntwk, tree_id); + } else if (xml_tap.name() == + std::string(XML_CLOCK_TREE_TAP_REGION_NODE_NAME)) { + read_xml_clock_tree_tap_type_region(xml_tap, loc_data, clk_ntwk, tree_id); + } else if (xml_tap.name() == + std::string(XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME)) { + read_xml_clock_tree_tap_type_single(xml_tap, loc_data, clk_ntwk, tree_id); } else { - bad_tag(xml_taps, loc_data, xml_tap, {XML_CLOCK_TREE_TAP_NODE_NAME}); + bad_tag( + xml_taps, loc_data, xml_tap, + {XML_CLOCK_TREE_TAP_ALL_NODE_NAME, XML_CLOCK_TREE_TAP_REGION_NODE_NAME, + XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME}); } } } +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_spine_switch_point_internal_driver( + pugi::xml_node& xml_int_driver, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, + const ClockSwitchPointId& switch_point_id) { + if (!clk_ntwk.valid_spine_id(spine_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_int_driver), + "Invalid id of a clock spine!\n"); + } + + std::string int_driver_from_port_name = + get_attribute( + xml_int_driver, + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_FROM_PIN, loc_data) + .as_string(); + std::string int_driver_to_port_name = + get_attribute(xml_int_driver, + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN, + loc_data) + .as_string(); + clk_ntwk.add_spine_switch_point_internal_driver(spine_id, switch_point_id, + int_driver_from_port_name, + int_driver_to_port_name); +} + +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_spine_intermediate_driver_tap( + pugi::xml_node& xml_int_driver, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, + const vtr::Point& spine_coord) { + if (!clk_ntwk.valid_spine_id(spine_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_int_driver), + "Invalid id of a clock spine!\n"); + } + + std::string int_driver_from_port_name = + get_attribute(xml_int_driver, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN, + loc_data) + .as_string(); + std::string int_driver_to_port_name = + get_attribute(xml_int_driver, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN, + loc_data) + .as_string(); + clk_ntwk.add_spine_intermediate_driver( + spine_id, spine_coord, int_driver_from_port_name, int_driver_to_port_name); +} + /******************************************************************** * Parse XML codes of a to an object of ClockNetwork *******************************************************************/ @@ -90,8 +238,56 @@ static void read_xml_clock_spine_switch_point( XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y, loc_data) .as_int(); - clk_ntwk.add_spine_switch_point(spine_id, tap_spine_id, - vtr::Point(tap_x, tap_y)); + ClockSwitchPointId switch_point_id = clk_ntwk.add_spine_switch_point( + spine_id, tap_spine_id, vtr::Point(tap_x, tap_y)); + + /* Add internal drivers if possible */ + for (pugi::xml_node xml_int_driver : xml_switch_point.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_int_driver.name() == + std::string(XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME)) { + read_xml_clock_spine_switch_point_internal_driver( + xml_int_driver, loc_data, clk_ntwk, spine_id, switch_point_id); + } else { + bad_tag(xml_int_driver, loc_data, xml_switch_point, + {XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME}); + } + } +} + +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_spine_intermediate_driver( + pugi::xml_node& xml_driver, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockSpineId& spine_id) { + if (!clk_ntwk.valid_spine_id(spine_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_driver), + "Invalid id of a clock spine!\n"); + } + + int tap_x = + get_attribute(xml_driver, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, + loc_data) + .as_int(); + int tap_y = + get_attribute(xml_driver, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, + loc_data) + .as_int(); + + /* Add internal drivers if possible */ + for (pugi::xml_node xml_int_driver : xml_driver.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_int_driver.name() == + std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME)) { + read_xml_clock_spine_intermediate_driver_tap( + xml_int_driver, loc_data, clk_ntwk, spine_id, + vtr::Point(tap_x, tap_y)); + } else { + bad_tag(xml_int_driver, loc_data, xml_driver, + {XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME}); + } + } } /******************************************************************** @@ -198,9 +394,15 @@ static void read_xml_clock_spine(pugi::xml_node& xml_spine, std::string(XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME)) { read_xml_clock_spine_switch_point(xml_switch_point, loc_data, clk_ntwk, spine_id); + } else if (xml_switch_point.name() == + std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME)) { + read_xml_clock_spine_intermediate_driver(xml_switch_point, loc_data, + clk_ntwk, spine_id); + } else { bad_tag(xml_switch_point, loc_data, xml_spine, - {XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME}); + {XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME}); } } } @@ -212,14 +414,18 @@ static void read_xml_clock_tree(pugi::xml_node& xml_clk_tree, const pugiutil::loc_data& loc_data, ClockNetwork& clk_ntwk) { std::string clk_tree_name = - get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data) + get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data, + pugiutil::ReqOpt::REQUIRED) + .as_string(); + std::string clk_global_port_str = + get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, loc_data, + pugiutil::ReqOpt::REQUIRED) .as_string(); - int clk_tree_width = - get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_WIDTH, loc_data) - .as_int(); /* Create a new tree in the storage */ - ClockTreeId tree_id = clk_ntwk.create_tree(clk_tree_name, clk_tree_width); + PortParser gport_parser(clk_global_port_str); + ClockTreeId tree_id = + clk_ntwk.create_tree(clk_tree_name, gport_parser.port()); if (false == clk_ntwk.valid_tree_id(tree_id)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_clk_tree), @@ -263,11 +469,17 @@ ClockNetwork read_xml_clock_network(const char* fname) { .as_string(); clk_ntwk.set_default_segment_name(default_segment_name); - std::string default_switch_name = - get_attribute(xml_root, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SWITCH, + std::string default_tap_switch_name = + get_attribute(xml_root, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_TAP_SWITCH, loc_data) .as_string(); - clk_ntwk.set_default_switch_name(default_switch_name); + clk_ntwk.set_default_tap_switch_name(default_tap_switch_name); + + std::string default_driver_switch_name = + get_attribute(xml_root, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_DRIVER_SWITCH, + loc_data) + .as_string(); + clk_ntwk.set_default_driver_switch_name(default_driver_switch_name); size_t num_trees = std::distance(xml_root.children().begin(), xml_root.children().end()); diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 720335aa4..23f54addf 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -28,14 +28,66 @@ static int write_xml_clock_tree_taps(std::fstream& fp, const ClockTreeId& tree_id) { openfpga::write_tab_to_file(fp, 3); fp << "<" << XML_CLOCK_TREE_TAPS_NODE_NAME << ">\n"; - for (const std::string& tile_pin_name : clk_ntwk.tree_taps(tree_id)) { - openfpga::write_tab_to_file(fp, 4); - fp << "<" << XML_CLOCK_TREE_TAP_NODE_NAME << ""; - - write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN, - tile_pin_name.c_str()); - fp << "/>" - << "\n"; + /* Depends on the type */ + for (ClockTapId tap_id : clk_ntwk.tree_taps(tree_id)) { + switch (clk_ntwk.tap_type(tap_id)) { + case ClockNetwork::e_tap_type::ALL: { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_TREE_TAP_ALL_NODE_NAME << ""; + write_xml_attribute( + fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, + clk_ntwk.tap_to_port(tap_id).c_str()); + fp << "/>" + << "\n"; + break; + } + case ClockNetwork::e_tap_type::SINGLE: { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; + write_xml_attribute( + fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, + clk_ntwk.tap_to_port(tap_id).c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, + clk_ntwk.tap_x(tap_id)); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, + clk_ntwk.tap_y(tap_id)); + fp << "/>" + << "\n"; + break; + } + case ClockNetwork::e_tap_type::REGION: { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_TREE_TAP_REGION_NODE_NAME << ""; + write_xml_attribute( + fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, + clk_ntwk.tap_to_port(tap_id).c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, + clk_ntwk.tap_bounding_box(tap_id).xmin()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, + clk_ntwk.tap_bounding_box(tap_id).ymin()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, + clk_ntwk.tap_bounding_box(tap_id).xmax()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, + clk_ntwk.tap_bounding_box(tap_id).ymax()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATX, + clk_ntwk.tap_step_x(tap_id)); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATY, + clk_ntwk.tap_step_y(tap_id)); + fp << "/>" + << "\n"; + break; + } + default: { + VTR_LOG_ERROR("Invalid type of tap point!\n"); + return 1; + } + } } openfpga::write_tab_to_file(fp, 3); @@ -60,8 +112,67 @@ static int write_xml_clock_spine_switch_point( write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X, coord.x()); write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y, coord.y()); - fp << "/>" - << "\n"; + /* Optional: internal drivers */ + if (clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id) + .empty()) { + fp << "/>" + << "\n"; + } else { + fp << ">" + << "\n"; + for (ClockInternalDriverId int_driver_id : + clk_ntwk.spine_switch_point_internal_drivers(spine_id, + switch_point_id)) { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME; + write_xml_attribute( + fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_FROM_PIN, + clk_ntwk.internal_driver_from_pin(int_driver_id).c_str()); + write_xml_attribute( + fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN, + clk_ntwk.internal_driver_to_pin(int_driver_id) + .to_verilog_string() + .c_str()); + fp << "/>" + << "\n"; + } + fp << "\n"; + } + + return 0; +} + +static int write_xml_clock_spine_intermediate_drivers( + std::fstream& fp, const ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, + const vtr::Point& coord) { + std::vector int_drivers = + clk_ntwk.spine_intermediate_drivers(spine_id, coord); + if (int_drivers.empty()) { + return 0; + } + openfpga::write_tab_to_file(fp, 3); + fp << "<" << XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME << ""; + + write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, + coord.x()); + write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, + coord.y()); + + for (ClockInternalDriverId int_driver_id : int_drivers) { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME; + write_xml_attribute( + fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN, + clk_ntwk.internal_driver_from_pin(int_driver_id).c_str()); + write_xml_attribute(fp, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN, + clk_ntwk.internal_driver_to_pin(int_driver_id) + .to_verilog_string() + .c_str()); + fp << "/>" + << "\n"; + } + fp << "\n"; return 0; } @@ -90,6 +201,10 @@ static int write_xml_clock_spine(std::fstream& fp, const ClockNetwork& clk_ntwk, fp << ">" << "\n"; + for (const vtr::Point& coord : clk_ntwk.spine_coordinates(spine_id)) { + write_xml_clock_spine_intermediate_drivers(fp, clk_ntwk, spine_id, coord); + } + for (const ClockSwitchPointId& switch_point_id : clk_ntwk.spine_switch_points(spine_id)) { write_xml_clock_spine_switch_point(fp, clk_ntwk, spine_id, switch_point_id); @@ -126,8 +241,9 @@ static int write_xml_clock_tree(std::fstream& fp, const ClockNetwork& clk_ntwk, write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_NAME, clk_ntwk.tree_name(tree_id).c_str()); - write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_WIDTH, - clk_ntwk.tree_width(tree_id)); + write_xml_attribute( + fp, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, + clk_ntwk.tree_global_port(tree_id).to_verilog_string().c_str()); fp << ">" << "\n"; @@ -168,8 +284,10 @@ int write_xml_clock_network(const char* fname, const ClockNetwork& clk_ntwk) { fp << "<" << XML_CLOCK_NETWORK_ROOT_NAME; write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SEGMENT, clk_ntwk.default_segment_name().c_str()); - write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SWITCH, - clk_ntwk.default_switch_name().c_str()); + write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_TAP_SWITCH, + clk_ntwk.default_tap_switch_name().c_str()); + write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_DRIVER_SWITCH, + clk_ntwk.default_driver_switch_name().c_str()); fp << ">" << "\n"; diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp index 79737b46c..6f78b26fe 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp @@ -22,7 +22,10 @@ static int link_clock_network_rr_segments(ClockNetwork& clk_ntwk, return CMD_EXEC_SUCCESS; } } - + VTR_LOG_ERROR( + "Unable to find the default segement '%s' in VPR architecture " + "description!\n", + default_segment_name.c_str()); return CMD_EXEC_FATAL_ERROR; } @@ -30,19 +33,46 @@ static int link_clock_network_rr_segments(ClockNetwork& clk_ntwk, * Link all the switches that are defined in a routing resource graph to a given *clock network *******************************************************************/ -static int link_clock_network_rr_switches(ClockNetwork& clk_ntwk, - const RRGraphView& rr_graph) { - /* default switch id */ - std::string default_switch_name = clk_ntwk.default_switch_name(); +static int link_clock_network_tap_rr_switches(ClockNetwork& clk_ntwk, + const RRGraphView& rr_graph) { + /* default tap switch id */ + std::string default_tap_switch_name = clk_ntwk.default_tap_switch_name(); for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches(); ++rr_switch_id) { if (std::string(rr_graph.rr_switch_inf(RRSwitchId(rr_switch_id)).name) == - default_switch_name) { - clk_ntwk.set_default_switch(RRSwitchId(rr_switch_id)); + default_tap_switch_name) { + clk_ntwk.set_default_tap_switch(RRSwitchId(rr_switch_id)); return CMD_EXEC_SUCCESS; } } + VTR_LOG_ERROR( + "Unable to find the default tap switch '%s' in VPR architecture " + "description!\n", + default_tap_switch_name.c_str()); + return CMD_EXEC_FATAL_ERROR; +} +/******************************************************************** + * Link all the switches that are defined in a routing resource graph to a given + *clock network + *******************************************************************/ +static int link_clock_network_driver_rr_switches(ClockNetwork& clk_ntwk, + const RRGraphView& rr_graph) { + /* default driver switch id */ + std::string default_driver_switch_name = + clk_ntwk.default_driver_switch_name(); + for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches(); + ++rr_switch_id) { + if (std::string(rr_graph.rr_switch_inf(RRSwitchId(rr_switch_id)).name) == + default_driver_switch_name) { + clk_ntwk.set_default_driver_switch(RRSwitchId(rr_switch_id)); + return CMD_EXEC_SUCCESS; + } + } + VTR_LOG_ERROR( + "Unable to find the default driver switch '%s' in VPR architecture " + "description!\n", + default_driver_switch_name.c_str()); return CMD_EXEC_FATAL_ERROR; } @@ -54,7 +84,11 @@ int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, if (CMD_EXEC_FATAL_ERROR == status) { return status; } - status = link_clock_network_rr_switches(clk_ntwk, rr_graph); + status = link_clock_network_tap_rr_switches(clk_ntwk, rr_graph); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + status = link_clock_network_driver_rr_switches(clk_ntwk, rr_graph); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -62,4 +96,39 @@ int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, return status; } +/** Check for each global ports in tile annotation + * If a clock tree is required for a global port, the global port name define + * in the tile annotation should match the one in clock clock + */ +int check_clock_network_tile_annotation(const ClockNetwork& clk_ntwk, + const TileAnnotation& tile_annotation) { + for (const TileGlobalPortId& gport_id : tile_annotation.global_ports()) { + if (!tile_annotation.global_port_thru_dedicated_network(gport_id)) { + continue; + } + std::string gport_name = tile_annotation.global_port_name(gport_id); + std::string clk_tree_name = + tile_annotation.global_port_clock_arch_tree_name(gport_id); + ClockTreeId clk_tree_id = clk_ntwk.find_tree(clk_tree_name); + if (!clk_ntwk.valid_tree_id(clk_tree_id)) { + VTR_LOG_ERROR( + "Invalid clock tree name '%s' defined for global port '%s' in tile " + "annotation! Must be a valid name defined in the clock network " + "description!\n", + clk_tree_name.c_str(), gport_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + if (clk_ntwk.tree_global_port(clk_tree_id).get_name() != gport_name) { + VTR_LOG_ERROR( + "Global port '%s' of clock tree name '%s' must match the name of " + "assoicated global port '%s' in tile annotation! Must be a valid name " + "defined in the clock network description!\n", + clk_ntwk.tree_global_port(clk_tree_id).to_verilog_string().c_str(), + clk_tree_name.c_str(), gport_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + } + return CMD_EXEC_SUCCESS; +} + } // End of namespace openfpga diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.h b/libs/libclkarchopenfpga/src/utils/clock_network_utils.h index 0a266c188..f87c80a53 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.h +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.h @@ -6,6 +6,7 @@ *******************************************************************/ #include "clock_network.h" #include "rr_graph_view.h" +#include "tile_annotation.h" /******************************************************************** * Function declaration @@ -16,6 +17,9 @@ namespace openfpga { // Begin namespace openfpga int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, const RRGraphView& rr_graph); +int check_clock_network_tile_annotation(const ClockNetwork& clk_ntwk, + const TileAnnotation& tile_annotation); + } // End of namespace openfpga #endif diff --git a/libs/libclkarchopenfpga/test/xml_io_clock_network.cpp b/libs/libclkarchopenfpga/test/xml_io_clock_network.cpp index 7a3708c67..fbabf50c5 100644 --- a/libs/libclkarchopenfpga/test/xml_io_clock_network.cpp +++ b/libs/libclkarchopenfpga/test/xml_io_clock_network.cpp @@ -22,6 +22,10 @@ int main(int argc, const char** argv) { /* Validate before write out */ if (!clk_ntwk.link()) { + VTR_LOG_ERROR("Invalid clock network when linking.\n"); + exit(1); + } + if (!clk_ntwk.validate()) { VTR_LOG_ERROR("Invalid clock network.\n"); exit(1); } diff --git a/libs/libfabrickey/test/fabric_key_assistant.cpp b/libs/libfabrickey/test/fabric_key_assistant.cpp index c0befce57..ce99767fa 100644 --- a/libs/libfabrickey/test/fabric_key_assistant.cpp +++ b/libs/libfabrickey/test/fabric_key_assistant.cpp @@ -34,8 +34,7 @@ static int check_input_and_ref_key_alias_match( const openfpga::FabricKey& input_key, const openfpga::FabricKey& ref_key, const bool& verbose) { size_t num_errors = 0; - size_t num_keys_checked = 0; - float progress = 0.; + size_t num_ref_keys_checked = 0; VTR_LOG( "Checking key alias matching between reference key and input keys...\n"); for (openfpga::FabricKeyId key_id : ref_key.keys()) { @@ -43,8 +42,8 @@ static int check_input_and_ref_key_alias_match( std::string curr_alias = ref_key.key_alias(key_id); std::vector input_found_keys = input_key.find_key_by_alias(curr_alias); - progress = static_cast(num_keys_checked) / - static_cast(ref_key.num_keys()) * 100.0; + float progress = static_cast(num_ref_keys_checked) / + static_cast(ref_key.num_keys()) * 100.0; VTR_LOGV(verbose, "[%lu%] Checking key alias '%s'\r", size_t(progress), curr_alias.c_str()); if (input_found_keys.empty()) { @@ -61,11 +60,40 @@ static int check_input_and_ref_key_alias_match( curr_alias.c_str(), size_t(key_id), input_found_keys.size()); num_errors++; } - num_keys_checked++; + num_ref_keys_checked++; } VTR_LOG( "Checking key alias matching between reference key and input keys... %s\n", num_errors ? "[Fail]" : "[Pass]"); + /* If failed, provide a detailed diff on the key alias */ + if (num_errors) { + size_t num_input_keys_checked = 0; + for (openfpga::FabricKeyId key_id : input_key.keys()) { + /* Note that this is slow. May consider to build a map first */ + std::string curr_alias = input_key.key_alias(key_id); + std::vector ref_found_keys = + ref_key.find_key_by_alias(curr_alias); + float progress = static_cast(num_input_keys_checked) / + static_cast(input_key.num_keys()) * 100.0; + VTR_LOGV(verbose, "[%lu%] Checking key alias '%s'\r", size_t(progress), + curr_alias.c_str()); + if (ref_found_keys.empty()) { + VTR_LOG_ERROR( + "Invalid alias '%s' in the input key (id='%lu'), which does not " + "exist in the reference key!\n", + curr_alias.c_str(), size_t(key_id)); + num_errors++; + } + if (ref_found_keys.size() > 1) { + VTR_LOG_ERROR( + "Invalid alias '%s' in the reference key (id='%lu'), which have been " + "found %lu times!\n", + curr_alias.c_str(), size_t(key_id), ref_found_keys.size()); + num_errors++; + } + num_input_keys_checked++; + } + } return num_errors ? openfpga::CMD_EXEC_FATAL_ERROR : openfpga::CMD_EXEC_SUCCESS; } diff --git a/libs/libfpgabitstream/src/bitstream_manager.cpp b/libs/libfpgabitstream/src/bitstream_manager.cpp index cf18a6e86..291befb60 100644 --- a/libs/libfpgabitstream/src/bitstream_manager.cpp +++ b/libs/libfpgabitstream/src/bitstream_manager.cpp @@ -5,6 +5,10 @@ #include +#include "arch_error.h" +#include "bitstream_manager_utils.h" +#include "openfpga_port_parser.h" +#include "openfpga_tokenizer.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -296,6 +300,69 @@ void BitstreamManager::add_output_net_id_to_block( block_output_net_ids_[block] = output_net_id; } +void BitstreamManager::overwrite_bitstream(const std::string& path, + const bool& value) { + PortParser port_parser(path, PORT_PARSER_SUPPORT_SINGLE_INDEX_FORMAT); + if (!port_parser.valid()) { + archfpga_throw(__FILE__, __LINE__, + "overwrite_bitstream bit path '%s' does not match format " + "[bit index]", + path.c_str()); + } else { + BasicPort port = port_parser.port(); + size_t bit = port.get_lsb(); + StringToken tokenizer(port.get_name()); + std::vector blocks = tokenizer.split("."); + std::vector block_ids; + ConfigBlockId block_id = ConfigBlockId::INVALID(); + size_t found = 0; + for (size_t i = 0; i < blocks.size(); i++) { + if (i == 0) { + block_ids = find_bitstream_manager_top_blocks(*this); + } else { + block_ids = block_children(block_id); + } + // Reset + block_id = ConfigBlockId::INVALID(); + // Find the one from the list that match the name + for (auto id : block_ids) { + if (block_name(id) == blocks[i]) { + block_id = id; + break; + } + } + if (block_id != ConfigBlockId::INVALID()) { + // Found one that match the name + found++; + if (found == blocks.size()) { + // Last one, no more child must end here + if (block_children(block_id).size() == 0) { + std::vector ids = block_bits(block_id); + if (bit < ids.size()) { + VTR_ASSERT(valid_bit_id(ids[bit])); + bit_values_[ids[bit]] = value ? '1' : '0'; + } else { + // No configuration bits at all or out of range, invalidate + found = 0; + } + } else { + // There are more child, hence the path still no end, invalidate + found = 0; + } + } + } else { + // Cannot match the name, just stop + break; + } + } + if (found != blocks.size()) { + archfpga_throw(__FILE__, __LINE__, + "Failed to find path '%s' to overwrite bitstream", + path.c_str()); + } + } +} + /****************************************************************************** * Public Validators ******************************************************************************/ diff --git a/libs/libfpgabitstream/src/bitstream_manager.h b/libs/libfpgabitstream/src/bitstream_manager.h index 4af15084d..3cba54fc4 100644 --- a/libs/libfpgabitstream/src/bitstream_manager.h +++ b/libs/libfpgabitstream/src/bitstream_manager.h @@ -213,6 +213,9 @@ class BitstreamManager { void add_output_net_id_to_block(const ConfigBlockId& block, const std::string& output_net_id); + /* Set bit to the bitstream at the given path */ + void overwrite_bitstream(const std::string& path, const bool& value); + public: /* Public Validators */ bool valid_bit_id(const ConfigBitId& bit_id) const; diff --git a/libs/libnamemanager/src/base/io_name_map.h b/libs/libnamemanager/src/base/io_name_map.h index b1f107a10..5e4370b3b 100644 --- a/libs/libnamemanager/src/base/io_name_map.h +++ b/libs/libnamemanager/src/base/io_name_map.h @@ -4,7 +4,10 @@ /******************************************************************** * Include header files required by the data structure definition *******************************************************************/ +#include #include +#include +#include #include "openfpga_port.h" diff --git a/libs/libopenfpgacapnproto/CMakeLists.txt b/libs/libopenfpgacapnproto/CMakeLists.txt new file mode 100644 index 000000000..c81ab82f3 --- /dev/null +++ b/libs/libopenfpgacapnproto/CMakeLists.txt @@ -0,0 +1,67 @@ +include(GNUInstallDirs) + +if(NOT MSCV) + # These flags generate noisy but non-bug warnings when using lib kj, + # supress them. + set(WARN_FLAGS_TO_DISABLE + -Wno-undef + -Wno-non-virtual-dtor + ) + foreach(flag ${WARN_FLAGS_TO_DISABLE}) + CHECK_CXX_COMPILER_FLAG(${flag} CXX_COMPILER_SUPPORTS_${flag}) + if(CXX_COMPILER_SUPPORTS_${flag}) + #Flag supported, so enable it + add_compile_options(${flag}) + endif() + endforeach() +endif() + +# Create generated headers from capnp schema files +set(CAPNP_DEFS + gen/unique_blocks_uxsdcxx.capnp +) + +capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS + ${CAPNP_DEFS} +) + + + +add_library(libopenfpgacapnproto STATIC + ${CAPNP_SRCS} + ${IC_SRCS} + ) + + +add_dependencies(libopenfpgacapnproto + generate_unique_block_capnp + ) + + +target_include_directories(libopenfpgacapnproto PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_BINARY_DIR}/gen + ) +target_link_libraries(libopenfpgacapnproto + libopenfpgautil + libvtrcapnproto +) + + +add_custom_target( + generate_unique_block_capnp + COMMAND ${CMAKE_COMMAND} -E remove_directory unique_blocks_capnproto_generate + COMMAND ${CMAKE_COMMAND} -E make_directory unique_blocks_capnproto_generate + COMMAND ${CMAKE_COMMAND} -E chdir unique_blocks_capnproto_generate git clone https://github.com/duck2/uxsdcxx + COMMAND python3 -mpip install --user -r unique_blocks_capnproto_generate/uxsdcxx/requirements.txt + COMMAND ${CMAKE_COMMAND} -E chdir unique_blocks_capnproto_generate python3 uxsdcxx/uxsdcxx.py ${CMAKE_CURRENT_SOURCE_DIR}/gen/unique_blocks.xsd + COMMAND ${CMAKE_COMMAND} -E chdir unique_blocks_capnproto_generate python3 uxsdcxx/uxsdcap.py ${CMAKE_CURRENT_SOURCE_DIR}/gen/unique_blocks.xsd + unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.h + unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_capnp.h + unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_interface.h + ${CMAKE_CURRENT_SOURCE_DIR}/gen + COMMAND ${CMAKE_COMMAND} -E copy unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.capnp ${CMAKE_CURRENT_SOURCE_DIR}/gen + DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/gen/unique_blocks.xsd + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} +) \ No newline at end of file diff --git a/libs/libopenfpgacapnproto/README.md b/libs/libopenfpgacapnproto/README.md new file mode 100644 index 000000000..cba22314e --- /dev/null +++ b/libs/libopenfpgacapnproto/README.md @@ -0,0 +1,74 @@ +Capnproto usage in Openfpga +====================== + +Capnproto is a data serialization framework designed for portabliity and speed. +In Openfpga, capnproto is used to provide binary formats for internal data +structures that can be computed once, and used many times. Specific examples: + - preload unique blocks + +What is capnproto? +================== + +capnproto can be broken down into 3 parts: + - A schema language + - A code generator + - A library + +The schema language is used to define messages. Each message must have an +explcit capnproto schema, which are stored in files suffixed with ".capnp". +The capnproto documentation for how to write these schema files can be found +here: https://capnproto.org/language.html + +The schema by itself is not especially useful. In order to read and write +messages defined by the schema in a target language (e.g. C++), a code +generation step is required. Capnproto provides a cmake function for this +purpose, `capnp_generate_cpp`. This generates C++ source and header files. +These source and header files combined with the capnproto C++ library, enables +C++ code to read and write the messages matching a particular schema. The C++ +library API can be found here: https://capnproto.org/cxx.html + +Contents of libopenfpgacapnproto +=========================== + +libopenfpgacapnproto should contain two elements: + - Utilities for working capnproto messages in Openfpga + - Generate source and header files of all capnproto messages used in Openfpga + +I/O Utilities +------------- + +Capnproto does not provide IO support, instead it works from arrays (or file +descriptors). To avoid re-writing this code, libopenfpgacapnproto provides two +utilities that should be used whenever reading or writing capnproto message to +disk. These two files are copied : + - `serdes_utils.h` provides the writeMessageToFile function - Writes a + capnproto message to disk. + - `mmap_file.h` provides MmapFile object - Maps a capnproto message from the + disk as a flat array. + +Capnproto schemas +----------------- + +libopenfpgacapnproto should contain all capnproto schema definitions used within +Openfpga. To add a new schema: +1. Add the schema to git in `libs/libopenfpgacapnproto/` +2. Add the schema file name to `capnp_generate_cpp` invocation in + `libs/libopenfpgacapnproto/CMakeLists.txt`. + +The schema will be available in the header file `schema filename>.h`. The +actual header file will appear in the CMake build directory +`libs/libopenfpgacapnproto` after `libopenfpgacapnproto` has been rebuilt. + +Writing capnproto binary files to text +====================================== + +The `capnp` tool (found in the CMake build directiory +`/vtr-verilog-to-routing/libs/EXTERNAL/capnproto/c++/src/capnp`) can be used to convert from a binary +capnp message to a textual form. + +Example converting UniqueBlockCompactInfo from binary to text: + +``` +capnp convert binary:text unique_blocks_uxsdcxx.capnp UniqueBlockCompactInfo \ + < test.bin > test.txt +``` diff --git a/libs/libopenfpgacapnproto/gen/README.gen.md b/libs/libopenfpgacapnproto/gen/README.gen.md new file mode 100644 index 000000000..6e66ee7e5 --- /dev/null +++ b/libs/libopenfpgacapnproto/gen/README.gen.md @@ -0,0 +1,4 @@ +`unique_blocks_uxsdcxx.capnp` is generated via uxsdcxx and is checked in to +avoid requiring python3 and the uxsdcxx depedencies to build Openfpga. + + diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks.xsd b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd new file mode 100644 index 000000000..a68587320 --- /dev/null +++ b/libs/libopenfpgacapnproto/gen/unique_blocks.xsd @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp new file mode 100644 index 000000000..36d23bce7 --- /dev/null +++ b/libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp @@ -0,0 +1,34 @@ +# This file is generated by uxsdcap 0.1.0. +# https://github.com/duck2/uxsdcxx +# Modify only if your build process doesn't involve regenerating this file. +# +# Cmdline: uxsdcxx/uxsdcap.py /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd unique_blocks_capnproto_generate/unique_blocks_uxsdcxx.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_capnp.h unique_blocks_capnproto_generate/unique_blocks_uxsdcxx_interface.h /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen +# Input file: /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd +# md5sum of input file: 1db9d740309076fa51f61413bae1e072 + +@0xb1073886de13324f; +using Cxx = import "/capnp/c++.capnp"; +$Cxx.namespace("ucap"); + +enum Type { + uxsdInvalid @0; + cbx @1; + cby @2; + sb @3; +} + +struct Instance { + x @0 :UInt32; + y @1 :UInt32; +} + +struct Block { + type @0 :Type; + x @1 :UInt32; + y @2 :UInt32; + instances @3 :List(Instance); +} + +struct UniqueBlocks { + blocks @0 :List(Block); +} diff --git a/libs/libopenfpgautil/src/openfpga_port_parser.cpp b/libs/libopenfpgautil/src/openfpga_port_parser.cpp index 93b7e0899..da0a27368 100644 --- a/libs/libopenfpgautil/src/openfpga_port_parser.cpp +++ b/libs/libopenfpgautil/src/openfpga_port_parser.cpp @@ -5,6 +5,7 @@ #include +#include "arch_error.h" #include "openfpga_tokenizer.h" #include "vtr_assert.h" #include "vtr_geometry.h" @@ -19,9 +20,10 @@ namespace openfpga { /************************************************************************ * Constructors ***********************************************************************/ -PortParser::PortParser(const std::string& data) { +PortParser::PortParser(const std::string& data, const int support_format) { set_default_bracket(); set_default_delim(); + set_support_format(support_format); set_data(data); } @@ -33,9 +35,18 @@ std::string PortParser::data() const { return data_; } BasicPort PortParser::port() const { return port_; } +bool PortParser::valid() const { return valid_; } + /************************************************************************ * Public Mutators ***********************************************************************/ +void PortParser::set_support_format(const int support_format) { + VTR_ASSERT((support_format & PORT_PARSER_SUPPORT_ALL_FORMAT) != 0); + VTR_ASSERT((support_format & ~PORT_PARSER_SUPPORT_ALL_FORMAT) == 0); + support_format_ = support_format; + return; +} + void PortParser::set_data(const std::string& data) { data_ = data; parse(); @@ -47,6 +58,8 @@ void PortParser::set_data(const std::string& data) { ***********************************************************************/ /* Parse the data */ void PortParser::parse() { + valid_ = true; + /* Create a tokenizer */ StringToken tokenizer(data_); @@ -54,11 +67,14 @@ void PortParser::parse() { std::vector port_tokens = tokenizer.split(bracket_.x()); /* Make sure we have a port name! */ VTR_ASSERT_SAFE((1 == port_tokens.size()) || (2 == port_tokens.size())); + /* Store the port name! */ port_.set_name(port_tokens[0]); /* If we only have one token */ if (1 == port_tokens.size()) { + // there is no [ + valid_ = (support_format_ & PORT_PARSER_SUPPORT_NO_PORT_FORMAT) != 0; port_.set_width(1); return; /* We can finish here */ } @@ -72,19 +88,25 @@ void PortParser::parse() { /* Split the pin string now */ tokenizer.set_data(pin_tokens[0]); pin_tokens = tokenizer.split(delim_); + VTR_ASSERT_SAFE((1 == pin_tokens.size()) || (2 == pin_tokens.size())); /* Check if we have LSB and MSB or just one */ if (1 == pin_tokens.size()) { /* Single pin */ - port_.set_width(std::stoi(pin_tokens[0]), std::stoi(pin_tokens[0])); + valid_ = (support_format_ & PORT_PARSER_SUPPORT_SINGLE_INDEX_FORMAT) != 0; + size_t temp = string_to_number(pin_tokens[0]); + port_.set_width(temp, temp); } else if (2 == pin_tokens.size()) { /* A number of pins. * Note that we always use the LSB for token[0] and MSB for token[1] */ - if (std::stoi(pin_tokens[1]) < std::stoi(pin_tokens[0])) { - port_.set_width(std::stoi(pin_tokens[1]), std::stoi(pin_tokens[0])); + valid_ = (support_format_ & PORT_PARSER_SUPPORT_RANGE_FORMAT) != 0; + size_t temp0 = string_to_number(pin_tokens[0]); + size_t temp1 = string_to_number(pin_tokens[1]); + if (temp1 < temp0) { + port_.set_width(temp1, temp0); } else { - port_.set_width(std::stoi(pin_tokens[0]), std::stoi(pin_tokens[1])); + port_.set_width(temp0, temp1); } } @@ -102,6 +124,24 @@ void PortParser::set_default_delim() { return; } +/* + Make sure string is not empty and is all digit before stoi +*/ +size_t PortParser::string_to_number(const std::string& str) { + bool bad_format = str.empty(); + for (auto& chr : str) { + if (!std::isdigit(chr)) { + bad_format = true; + break; + } + } + if (bad_format) { + archfpga_throw(__FILE__, __LINE__, + "Invalid string '%s' to call std::stoi()", str.c_str()); + } + return (size_t)(std::stoi(str)); +} + /************************************************************************ * Member functions for MultiPortParser class ***********************************************************************/ diff --git a/libs/libopenfpgautil/src/openfpga_port_parser.h b/libs/libopenfpgautil/src/openfpga_port_parser.h index f596fd309..ab61603e0 100644 --- a/libs/libopenfpgautil/src/openfpga_port_parser.h +++ b/libs/libopenfpgautil/src/openfpga_port_parser.h @@ -21,37 +21,51 @@ /* namespace openfpga begins */ namespace openfpga { +constexpr int PORT_PARSER_SUPPORT_NO_PORT_FORMAT = (1 << 0); // (5) below +constexpr int PORT_PARSER_SUPPORT_SINGLE_INDEX_FORMAT = (1 << 1); // (3) below +constexpr int PORT_PARSER_SUPPORT_RANGE_FORMAT = (1 << 2); // (1) and (2) below +constexpr int PORT_PARSER_SUPPORT_ALL_FORMAT = ((1 << 3) - 1); + /************************************************************************ * Class PortParser: single port parser * Supported port definition: - * 1. [:] - * 2. [:] - * 3. [] - * 4. [] - * 5. + * (1) [:] + * (2) [:] + * (3) [] + * (4) [] -- this is not currently supported. Two problems: + * * tokenizer will error out and + * * stoi cannot support empty string, and give + * std::invalid_argument error + * (5) * In case 4 and 5, we will assign (-1,-1) for LSB and MSB ***********************************************************************/ class PortParser { public: /* Constructors*/ - PortParser(const std::string& data); + PortParser(const std::string& data, + const int support_format = PORT_PARSER_SUPPORT_ALL_FORMAT); public: /* Public Accessors */ std::string data() const; BasicPort port() const; + bool valid() const; public: /* Public Mutators */ + void set_support_format(const int support_format); void set_data(const std::string& data); private: /* Private Mutators */ void parse(); void set_default_bracket(); void set_default_delim(); + size_t string_to_number(const std::string& str); private: /* Internal data */ std::string data_; /* Lines to be splited */ + int support_format_; vtr::Point bracket_; char delim_; BasicPort port_; + bool valid_; }; /************************************************************************ diff --git a/libs/libopenfpgautil/src/openfpga_side_manager.cpp b/libs/libopenfpgautil/src/openfpga_side_manager.cpp index 4540984c8..0d9b04dd8 100644 --- a/libs/libopenfpgautil/src/openfpga_side_manager.cpp +++ b/libs/libopenfpgautil/src/openfpga_side_manager.cpp @@ -9,7 +9,7 @@ namespace openfpga { /* Constructors */ SideManager::SideManager(enum e_side side) { side_ = side; } -SideManager::SideManager() { side_ = NUM_SIDES; } +SideManager::SideManager() { side_ = NUM_2D_SIDES; } SideManager::SideManager(size_t side) { set_side(side); } @@ -27,7 +27,7 @@ enum e_side SideManager::get_opposite() const { case LEFT: return RIGHT; default: - return NUM_SIDES; + return NUM_2D_SIDES; } } @@ -42,7 +42,7 @@ enum e_side SideManager::get_rotate_clockwise() const { case LEFT: return TOP; default: - return NUM_SIDES; + return NUM_2D_SIDES; } } @@ -57,12 +57,12 @@ enum e_side SideManager::get_rotate_counterclockwise() const { case LEFT: return BOTTOM; default: - return NUM_SIDES; + return NUM_2D_SIDES; } } bool SideManager::validate() const { - if (NUM_SIDES == side_) { + if (NUM_2D_SIDES == side_) { return false; } return true; @@ -139,7 +139,7 @@ void SideManager::set_side(size_t side) { side_ = LEFT; return; default: - side_ = NUM_SIDES; + side_ = NUM_2D_SIDES; return; } } diff --git a/libs/libpcf/src/base/io_pin_table.cpp b/libs/libpcf/src/base/io_pin_table.cpp index 64f304acf..085ebd8c2 100644 --- a/libs/libpcf/src/base/io_pin_table.cpp +++ b/libs/libpcf/src/base/io_pin_table.cpp @@ -84,7 +84,7 @@ IoPinTableId IoPinTable::create_pin() { pin_ids_.push_back(pin_id); internal_pins_.emplace_back(); external_pins_.emplace_back(); - pin_sides_.emplace_back(NUM_SIDES); + pin_sides_.emplace_back(NUM_2D_SIDES); pin_directions_.emplace_back(NUM_IO_DIRECTIONS); return pin_id; diff --git a/libs/libpcf/src/base/pcf2place.cpp b/libs/libpcf/src/base/pcf2place.cpp index 7895667e7..539aa0a37 100644 --- a/libs/libpcf/src/base/pcf2place.cpp +++ b/libs/libpcf/src/base/pcf2place.cpp @@ -41,6 +41,8 @@ int pcf2place(const PcfData& pcf_data, VTR_LOG("PCF basic check passed\n"); } + /* Map from location to net */ + std::map, std::string> net_map; /* Build the I/O place */ for (const PcfIoConstraintId& io_id : pcf_data.io_constraints()) { /* Find the net name */ @@ -102,6 +104,20 @@ int pcf2place(const PcfData& pcf_data, continue; } + std::array loc = {x, y, z}; + auto itr = net_map.find(loc); + if (itr == net_map.end()) { + net_map.insert({loc, net}); + } else { + VTR_LOG_ERROR( + "Illegal pin constraint: Two nets '%s' and '%s' are mapped to the I/O " + "pin '%s[%lu]' which belongs to the same coordinate (%ld, %ld, %ld)!\n", + itr->second.c_str(), net.c_str(), int_pin.get_name().c_str(), + int_pin.get_lsb(), x, y, z); + num_err++; + continue; + } + /* Add a fixed prefix to net namei, this is hard coded by VPR */ if (IoPinTable::OUTPUT == pin_direction) { net = "out:" + net; diff --git a/libs/libpcf/src/io/write_csv_io_pin_table.cpp b/libs/libpcf/src/io/write_csv_io_pin_table.cpp index 48b74d324..218ff101a 100644 --- a/libs/libpcf/src/io/write_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/write_csv_io_pin_table.cpp @@ -52,7 +52,8 @@ int write_csv_io_pin_table(const char* fname, const IoPinTable& io_pin_table) { /* Print data */ for (const IoPinTableId& pin_id : io_pin_table.pins()) { std::vector data_row_str; - data_row_str.push_back(SIDE_STRING[io_pin_table.pin_side(pin_id)]); + data_row_str.push_back( + TOTAL_2D_SIDE_STRINGS[io_pin_table.pin_side(pin_id)]); data_row_str.push_back( generate_xml_port_name(io_pin_table.internal_pin(pin_id))); data_row_str.push_back( diff --git a/openfpga/CMakeLists.txt b/openfpga/CMakeLists.txt index 96c450876..f77e79139 100644 --- a/openfpga/CMakeLists.txt +++ b/openfpga/CMakeLists.txt @@ -44,7 +44,9 @@ target_link_libraries(libopenfpga libnamemanager libtileconfig libpugixml - libvpr) + libvpr + libopenfpgacapnproto + ) #Create the test executable add_executable(openfpga ${EXEC_SOURCE}) diff --git a/openfpga/src/annotation/annotate_placement.cpp b/openfpga/src/annotation/annotate_placement.cpp index bf7d0b895..6e6450095 100644 --- a/openfpga/src/annotation/annotate_placement.cpp +++ b/openfpga/src/annotation/annotate_placement.cpp @@ -25,10 +25,10 @@ void annotate_mapped_blocks(const DeviceContext& device_ctx, place_annotation.init_mapped_blocks(device_ctx.grid); for (const ClusterBlockId& blk_id : cluster_ctx.clb_nlist.blocks()) { - vtr::Point grid_coord(place_ctx.block_locs[blk_id].loc.x, - place_ctx.block_locs[blk_id].loc.y); + vtr::Point grid_coord(place_ctx.block_locs()[blk_id].loc.x, + place_ctx.block_locs()[blk_id].loc.y); place_annotation.add_mapped_block( - grid_coord, place_ctx.block_locs[blk_id].loc.sub_tile, blk_id); + grid_coord, place_ctx.block_locs()[blk_id].loc.sub_tile, blk_id); } VTR_LOG("Done\n"); } diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 3a904aefd..5f325d0a7 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -98,7 +98,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, const vtr::Point& gsb_range, const size_t& layer, const vtr::Point& gsb_coord, - const bool& include_clock) { + const bool& perimeter_cb, const bool& include_clock) { /* Create an object to return */ RRGSB rr_gsb; @@ -120,13 +120,12 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, rr_gsb.get_side_block_coordinate(side_manager.get_side()); RRChan rr_chan; std::vector> temp_opin_rr_nodes(2); - enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES}; + enum e_side opin_grid_side[2] = {NUM_2D_SIDES, NUM_2D_SIDES}; enum PORTS chan_dir_to_port_dir_mapping[2] = { OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ switch (side) { case TOP: /* TOP = 0 */ - /* For the border, we should take special care */ if (gsb_coord.y() == gsb_range.y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; @@ -157,7 +156,6 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, break; case RIGHT: /* RIGHT = 1 */ - /* For the border, we should take special care */ if (gsb_coord.x() == gsb_range.x()) { rr_gsb.clear_one_side(side_manager.get_side()); break; @@ -189,8 +187,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - /* For the border, we should take special care */ - if (gsb_coord.y() == 0) { + if (!perimeter_cb && gsb_coord.y() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -220,8 +217,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - /* For the border, we should take special care */ - if (gsb_coord.x() == 0) { + if (!perimeter_cb && gsb_coord.x() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -305,8 +301,8 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Clear the temp data */ temp_opin_rr_nodes[0].clear(); temp_opin_rr_nodes[1].clear(); - opin_grid_side[0] = NUM_SIDES; - opin_grid_side[1] = NUM_SIDES; + opin_grid_side[0] = NUM_2D_SIDES; + opin_grid_side[1] = NUM_2D_SIDES; } /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ @@ -333,11 +329,11 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, case RIGHT: /* RIGHT = 1 */ /* For the bording, we should take special care */ /* Check if TOP side chan width is 0 or not */ - chan_side = TOP; + chan_side = BOTTOM; /* Build the connection block: ipin and ipin_grid_side */ - /* LEFT side INPUT Pins of Grid[x+1][y+1] */ + /* LEFT side INPUT Pins of Grid[x+1][y] */ ix = rr_gsb.get_sb_x() + 1; - iy = rr_gsb.get_sb_y() + 1; + iy = rr_gsb.get_sb_y(); ipin_rr_node_grid_side = LEFT; break; case BOTTOM: /* BOTTOM = 2*/ @@ -353,11 +349,11 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, case LEFT: /* LEFT = 3 */ /* For the bording, we should take special care */ /* Check if left side chan width is 0 or not */ - chan_side = TOP; + chan_side = BOTTOM; /* Build the connection block: ipin and ipin_grid_side */ - /* RIGHT side INPUT Pins of Grid[x][y+1] */ + /* RIGHT side INPUT Pins of Grid[x][y] */ ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; + iy = rr_gsb.get_sb_y(); ipin_rr_node_grid_side = RIGHT; break; default: @@ -398,6 +394,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, temp_ipin_rr_nodes.clear(); } + /* Build OPIN node lists for connection blocks */ + rr_gsb.build_cb_opin_nodes(vpr_device_ctx.rr_graph); + return rr_gsb; } @@ -417,6 +416,9 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, */ vtr::Point gsb_range(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); + if (vpr_device_ctx.arch->perimeter_cb) { + gsb_range.set(vpr_device_ctx.grid.width(), vpr_device_ctx.grid.height()); + } device_rr_gsb.reserve(gsb_range); VTR_LOGV(verbose_output, "Start annotation GSB up to [%lu][%lu]\n", @@ -431,11 +433,11 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, * the GSBs at the borderside correctly sort drive_rr_nodes should be * called if required by users */ - const RRGSB& rr_gsb = - build_rr_gsb(vpr_device_ctx, - vtr::Point(vpr_device_ctx.grid.width() - 2, - vpr_device_ctx.grid.height() - 2), - layer, vtr::Point(ix, iy), include_clock); + vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 1, + vpr_device_ctx.grid.height() - 1); + const RRGSB& rr_gsb = build_rr_gsb( + vpr_device_ctx, sub_gsb_range, layer, vtr::Point(ix, iy), + vpr_device_ctx.arch->perimeter_cb, include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); device_rr_gsb.add_rr_gsb(gsb_coordinate, rr_gsb); @@ -701,14 +703,26 @@ static void annotate_direct_circuit_models( } /* Check the circuit model type */ - if (CIRCUIT_MODEL_WIRE != - openfpga_arch.circuit_lib.model_type(circuit_model)) { + if (openfpga_arch.arch_direct.type(direct_id) != + e_direct_type::PART_OF_CB && + CIRCUIT_MODEL_WIRE != + openfpga_arch.circuit_lib.model_type(circuit_model)) { VTR_LOG_ERROR( "Require circuit model type '%s' for a direct connection '%s'!\nPlease " "check your OpenFPGA architecture XML!\n", CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_WIRE], direct_name.c_str()); exit(1); } + if (openfpga_arch.arch_direct.type(direct_id) == + e_direct_type::PART_OF_CB && + CIRCUIT_MODEL_MUX != + openfpga_arch.circuit_lib.model_type(circuit_model)) { + VTR_LOG_ERROR( + "Require circuit model type '%s' for a direct connection '%s'!\nPlease " + "check your OpenFPGA architecture XML!\n", + CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_MUX], direct_name.c_str()); + exit(1); + } /* Now update the device annotation */ vpr_device_annotation.add_direct_annotation(idirect, direct_id); diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index a52a86ed2..87ee34b41 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -45,17 +45,25 @@ static size_t estimate_clock_rr_graph_num_chan_nodes( *******************************************************************/ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, const size_t& layer, + const bool& perimeter_cb, const bool& through_channel, const ClockNetwork& clk_ntwk) { size_t num_nodes = 0; + vtr::Rect chanx_bb(1, 0, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chanx_bb.set_xmin(0); + chanx_bb.set_xmax(grids.width()); + chanx_bb.set_ymin(0); + chanx_bb.set_ymax(grids.height() - 1); + } /* Check the number of CHANX nodes required */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { + for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, layer, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } /* Estimate the routing tracks required by clock routing only */ @@ -63,13 +71,21 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, } } - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chany_bb.set_xmin(0); + chany_bb.set_xmax(grids.width() - 1); + chany_bb.set_ymin(0); + chany_bb.set_ymax(grids.height()); + } + + for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { + for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, layer, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } /* Estimate the routing tracks required by clock routing only */ @@ -151,56 +167,59 @@ static void add_rr_graph_block_clock_nodes( static void add_rr_graph_clock_nodes( RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, const DeviceGrid& grids, - const size_t& layer, const bool& through_channel, + const size_t& layer, const bool& perimeter_cb, const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { /* Pre-allocate memory: Must do otherwise data will be messed up! */ clk_rr_lookup.reserve_nodes(grids.width(), grids.height(), clk_ntwk.num_trees(), clk_ntwk.max_tree_depth(), clk_ntwk.max_tree_width()); + vtr::Rect chanx_bb(1, 0, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chanx_bb.set_xmin(0); + chanx_bb.set_xmax(grids.width()); + chanx_bb.set_ymin(0); + chanx_bb.set_ymax(grids.height() - 1); + } /* Add X-direction clock nodes */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { + for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, layer, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_nodes( rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, chanx_coord, CHANX, CHANX_COST_INDEX_START, verbose); - VTR_ASSERT(rr_graph_view.valid_node( - clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), - ClockTreePinId(0), Direction::INC))); } } - VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node( - 1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); - /* Add Y-direction clock nodes */ - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chany_bb.set_xmin(0); + chany_bb.set_xmax(grids.width() - 1); + chany_bb.set_ymin(0); + chany_bb.set_ymax(grids.height()); + } + for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { + for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, layer, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_nodes( rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, chany_coord, CHANY, CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(), verbose); - VTR_ASSERT(rr_graph_view.valid_node( - clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), - ClockTreePinId(0), Direction::INC))); } } - VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node( - 1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); } /******************************************************************** @@ -243,7 +262,7 @@ static std::vector find_clock_track2track_node( const RRClockSpatialLookup& clk_rr_lookup, const t_rr_type& chan_type, const vtr::Point& chan_coord, const ClockTreeId& clk_tree, const ClockLevelId& clk_lvl, const ClockTreePinId& clk_pin, - const Direction& direction) { + const Direction& direction, const bool& verbose) { std::vector des_nodes; /* Straight connection */ @@ -266,7 +285,7 @@ static std::vector find_clock_track2track_node( } RRNodeId straight_des_node = clk_rr_lookup.find_node(straight_des_coord.x(), straight_des_coord.y(), - clk_tree, clk_lvl, clk_pin, direction); + clk_tree, clk_lvl, clk_pin, direction, verbose); if (rr_graph_view.valid_node(straight_des_node)) { VTR_ASSERT(chan_type == rr_graph_view.node_type(straight_des_node)); des_nodes.push_back(straight_des_node); @@ -325,7 +344,7 @@ static std::vector find_clock_track2track_node( } RRNodeId left_des_node = clk_rr_lookup.find_node(left_des_coord.x(), left_des_coord.y(), clk_tree, - next_clk_lvl, clk_pin, left_direction); + next_clk_lvl, clk_pin, left_direction, verbose); if (rr_graph_view.valid_node(left_des_node)) { VTR_ASSERT(left_des_chan_type == rr_graph_view.node_type(left_des_node)); des_nodes.push_back(left_des_node); @@ -377,7 +396,7 @@ static std::vector find_clock_track2track_node( } RRNodeId right_des_node = clk_rr_lookup.find_node(right_des_coord.x(), right_des_coord.y(), clk_tree, - next_clk_lvl, clk_pin, right_direction); + next_clk_lvl, clk_pin, right_direction, verbose); if (rr_graph_view.valid_node(right_des_node)) { VTR_ASSERT(right_des_chan_type == rr_graph_view.node_type(right_des_node)); des_nodes.push_back(right_des_node); @@ -396,19 +415,25 @@ static void try_find_and_add_clock_track2ipin_node( const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& grid_coord, const e_side& pin_side, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, - const ClockTreePinId& clk_pin) { + const ClockTreePinId& clk_pin, const bool& verbose) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); + VTR_LOGV(verbose, "Getting type of grid at (x=%d, y=%d)\n", grid_coord.x(), + grid_coord.y()); for (std::string tap_pin_name : - clk_ntwk.tree_flatten_taps(clk_tree, clk_pin)) { + clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) { + VTR_LOGV(verbose, "Checking tap pin name: %s\n", tap_pin_name.c_str()); /* tap pin name could be 'io[5:5].a2f[0]' */ int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name); if (grid_pin_idx == grid_type->num_pins) { continue; } + VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n", + grid_pin_idx); RRNodeId des_node = rr_graph_view.node_lookup().find_node( layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side); if (rr_graph_view.valid_node(des_node)) { + VTR_LOGV(verbose, "Found a valid pin in rr graph\n"); des_nodes.push_back(des_node); } } @@ -444,34 +469,35 @@ static std::vector find_clock_track2ipin_node( const DeviceGrid& grids, const RRGraphView& rr_graph_view, const t_rr_type& chan_type, const size_t& layer, const vtr::Point& chan_coord, const ClockNetwork& clk_ntwk, - const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) { + const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin, + const bool& verbose) { std::vector des_nodes; if (chan_type == CHANX) { /* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */ vtr::Point bot_grid_coord(chan_coord.x(), chan_coord.y() + 1); - try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, bot_grid_coord, BOTTOM, - clk_ntwk, clk_tree, clk_pin); + try_find_and_add_clock_track2ipin_node( + des_nodes, grids, rr_graph_view, layer, bot_grid_coord, BOTTOM, clk_ntwk, + clk_tree, clk_pin, verbose); /* Get the clock IPINs at the TOP side of adjacent grids [x][y] */ vtr::Point top_grid_coord(chan_coord.x(), chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, layer, top_grid_coord, TOP, clk_ntwk, - clk_tree, clk_pin); + clk_tree, clk_pin, verbose); } else { VTR_ASSERT(chan_type == CHANY); /* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */ vtr::Point left_grid_coord(chan_coord.x() + 1, chan_coord.y()); - try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, left_grid_coord, LEFT, - clk_ntwk, clk_tree, clk_pin); + try_find_and_add_clock_track2ipin_node( + des_nodes, grids, rr_graph_view, layer, left_grid_coord, LEFT, clk_ntwk, + clk_tree, clk_pin, verbose); /* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */ vtr::Point right_grid_coord(chan_coord.x(), chan_coord.y()); - try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, right_grid_coord, RIGHT, - clk_ntwk, clk_tree, clk_pin); + try_find_and_add_clock_track2ipin_node( + des_nodes, grids, rr_graph_view, layer, right_grid_coord, RIGHT, clk_ntwk, + clk_tree, clk_pin, verbose); } return des_nodes; @@ -509,7 +535,7 @@ static void add_rr_graph_block_clock_edges( /* find the driver clock node through lookup */ RRNodeId src_node = clk_rr_lookup.find_node(chan_coord.x(), chan_coord.y(), itree, ilvl, - ClockTreePinId(ipin), node_dir); + ClockTreePinId(ipin), node_dir, verbose); VTR_LOGV(verbose, "Try to find node '%lu' from clock node lookup (x='%lu' " "y='%lu' tree='%lu' level='%lu' pin='%lu' direction='%s')\n", @@ -522,11 +548,12 @@ static void add_rr_graph_block_clock_edges( size_t curr_edge_count = edge_count; for (RRNodeId des_node : find_clock_track2track_node( rr_graph_view, clk_ntwk, clk_rr_lookup, chan_type, - chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir)) { + chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir, + verbose)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_switch(), false); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_driver_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n", @@ -538,14 +565,14 @@ static void add_rr_graph_block_clock_edges( size_t curr_edge_count = edge_count; for (RRNodeId des_node : find_clock_track2ipin_node( grids, rr_graph_view, chan_type, layer, chan_coord, clk_ntwk, - itree, ClockTreePinId(ipin))) { + itree, ClockTreePinId(ipin), verbose)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_switch(), false); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_tap_switch(), false); edge_count++; } - VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n", + VTR_LOGV(verbose, "\tWill add %lu edges to IPINs\n", edge_count - curr_edge_count); } } @@ -557,6 +584,219 @@ static void add_rr_graph_block_clock_edges( num_edges_to_create += edge_count; } +/******************************************************************** + * Try to find an OPIN of a grid which satisfy the requirement of clock pins + * that has been defined in clock network. If the OPIN does exist in a + * routing resource graph, add it to the node list + *******************************************************************/ +static void try_find_and_add_clock_opin2track_node( + std::vector& opin_nodes, const DeviceGrid& grids, + const RRGraphView& rr_graph_view, const size_t& layer, + const vtr::Point& grid_coord, const e_side& pin_side, + const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin, + const ClockInternalDriverId& int_driver_id, const bool& verbose) { + t_physical_tile_type_ptr grid_type = grids.get_physical_type( + t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); + for (std::string tap_pin_name : + clk_ntwk.flatten_internal_driver_from_pin(int_driver_id, clk_pin)) { + /* tap pin name could be 'io[5:5].a2f[0]' */ + int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name); + if (grid_pin_idx == grid_type->num_pins) { + continue; + } + RRNodeId opin_node = rr_graph_view.node_lookup().find_node( + layer, grid_coord.x(), grid_coord.y(), OPIN, grid_pin_idx, pin_side); + if (rr_graph_view.valid_node(opin_node)) { + VTR_LOGV(verbose, "Connected OPIN '%s' to clock network\n", + tap_pin_name.c_str()); + opin_nodes.push_back(opin_node); + } + } +} + +/******************************************************************** + * Find the source OPIN nodes as internal drivers for a clock node + * For example + * clk0_lvl1_chany[1][1] + * ^ + * | + * internal_driver OPIN[0] -->-------+ + * ^ + * | + * internal_driver OPIN[1] + * + * Coordinate system: + * + * +----------+----------+------------+ + * | Grid | CBy | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * +----------+----------+------------+ + * | CBx | SB | CBx | + * | [x][y] | [x][y] | [x+1][y] | + * +----------+----------+------------+ + * | Grid | CBy | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * +----------+----------+------------+ + *******************************************************************/ +static std::vector find_clock_opin2track_node( + const DeviceGrid& grids, const RRGraphView& rr_graph_view, + const size_t& layer, const vtr::Point& sb_coord, + const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin, + const std::vector& int_driver_ids, + const bool& verbose) { + std::vector opin_nodes; + /* Find opins from + * - Grid[x][y+1] on right and bottom sides + * - Grid[x+1][y+1] on left and bottom sides + * - Grid[x][y] on right and top sides + * - Grid[x+1][y] on left and top sides + */ + std::array, 4> grid_coords; + std::array, 4> grid_sides; + grid_coords[0] = vtr::Point(sb_coord.x(), sb_coord.y() + 1); + grid_sides[0] = {RIGHT, BOTTOM}; + grid_coords[1] = vtr::Point(sb_coord.x() + 1, sb_coord.y() + 1); + grid_sides[1] = {LEFT, BOTTOM}; + grid_coords[2] = vtr::Point(sb_coord.x(), sb_coord.y()); + grid_sides[2] = {RIGHT, TOP}; + grid_coords[3] = vtr::Point(sb_coord.x() + 1, sb_coord.y()); + grid_sides[3] = {LEFT, TOP}; + for (size_t igrid = 0; igrid < 4; igrid++) { + vtr::Point grid_coord = grid_coords[igrid]; + for (e_side grid_side : grid_sides[igrid]) { + for (ClockInternalDriverId int_driver_id : int_driver_ids) { + try_find_and_add_clock_opin2track_node( + opin_nodes, grids, rr_graph_view, layer, grid_coord, grid_side, + clk_ntwk, clk_pin, int_driver_id, verbose); + } + } + } + return opin_nodes; +} + +/******************************************************************** + * Add edges between OPIN of programmable blocks and clock routing tracks + * Note that such edges only occur at the switching points of spines + * Different from add_rr_graph_block_clock_edges(), we follow the clock spines + *here By expanding on switching points, internal drivers will be added + *******************************************************************/ +static int add_rr_graph_opin2clk_edges( + RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, + const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, + const DeviceGrid& grids, const size_t& layer, const ClockNetwork& clk_ntwk, + const bool& verbose) { + size_t edge_count = 0; + for (ClockTreeId clk_tree : clk_ntwk.trees()) { + for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) { + VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); + for (auto ipin : clk_ntwk.pins(clk_tree)) { + for (ClockSwitchPointId switch_point_id : + clk_ntwk.spine_switch_points(ispine)) { + if (clk_ntwk + .spine_switch_point_internal_drivers(ispine, switch_point_id) + .empty()) { + continue; /* We only focus on switching points containing internal + drivers */ + } + size_t curr_edge_count = edge_count; + /* Get the rr node of destination spine */ + ClockSpineId des_spine = + clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); + vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); + Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); + RRNodeId des_node = clk_rr_lookup.find_node( + des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin, + des_spine_direction, verbose); + /* Walk through each qualified OPIN, build edges */ + vtr::Point src_coord = + clk_ntwk.spine_switch_point(ispine, switch_point_id); + std::vector int_driver_ids = + clk_ntwk.spine_switch_point_internal_drivers(ispine, + switch_point_id); + for (RRNodeId src_node : find_clock_opin2track_node( + grids, rr_graph_view, layer, src_coord, clk_ntwk, ipin, + int_driver_ids, verbose)) { + /* Create edges */ + VTR_ASSERT(rr_graph_view.valid_node(des_node)); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_driver_switch(), false); + edge_count++; + } + VTR_LOGV(verbose, "\tWill add %lu edges to OPINs at (x=%lu, y=%lu)\n", + edge_count - curr_edge_count, des_coord.x(), des_coord.y()); + } + } + } + } + /* Allocate edges */ + rr_graph_builder.build_edges(true); + num_edges_to_create += edge_count; + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Add edges between OPIN of programmable blocks and clock routing tracks + * Note that such edges only occur at the intermeidate points of spines + * Different from add_rr_graph_opin2clk_edges(), we follow the clock spines + *here By expanding on intermediate points, internal drivers will be added + *******************************************************************/ +static int add_rr_graph_opin2clk_intermediate_edges( + RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, + const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, + const DeviceGrid& grids, const size_t& layer, const ClockNetwork& clk_ntwk, + const bool& verbose) { + size_t edge_count = 0; + for (ClockTreeId clk_tree : clk_ntwk.trees()) { + for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) { + VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); + for (auto ipin : clk_ntwk.pins(clk_tree)) { + for (const vtr::Point& coord : + clk_ntwk.spine_coordinates(ispine)) { + if (clk_ntwk.spine_intermediate_drivers(ispine, coord).empty()) { + continue; + } + size_t curr_edge_count = edge_count; + /* Get the rr node of destination spine */ + Direction des_spine_direction = clk_ntwk.spine_direction(ispine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); + vtr::Point des_coord = + clk_ntwk.spine_intermediate_driver_routing_track_coord(ispine, + coord); + RRNodeId des_node = clk_rr_lookup.find_node( + des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin, + des_spine_direction, verbose); + if (!rr_graph_view.valid_node(des_node)) { + continue; + } + /* Walk through each qualified OPIN, build edges */ + std::vector int_driver_ids = + clk_ntwk.spine_intermediate_drivers(ispine, coord); + for (RRNodeId src_node : find_clock_opin2track_node( + grids, rr_graph_view, layer, coord, clk_ntwk, ipin, + int_driver_ids, verbose)) { + /* Create edges */ + VTR_ASSERT(rr_graph_view.valid_node(des_node)); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_driver_switch(), false); + edge_count++; + } + VTR_LOGV(verbose, + "\tWill add %lu edges from OPINs as intermediate drivers at " + "(x=%lu, y=%lu)\n", + edge_count - curr_edge_count, des_coord.x(), des_coord.y()); + } + } + } + } + /* Allocate edges */ + rr_graph_builder.build_edges(true); + num_edges_to_create += edge_count; + return CMD_EXEC_SUCCESS; +} + /******************************************************************** * Add edges to interconnect clock nodes * Walk through the routing tracks in each connection block (driver nodes) @@ -581,16 +821,24 @@ static void add_rr_graph_block_clock_edges( static void add_rr_graph_clock_edges( RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, - const DeviceGrid& grids, const size_t& layer, const bool& through_channel, - const ClockNetwork& clk_ntwk, const bool& verbose) { + const DeviceGrid& grids, const size_t& layer, const bool& perimeter_cb, + const bool& through_channel, const ClockNetwork& clk_ntwk, + const bool& verbose) { + vtr::Rect chanx_bb(1, 0, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chanx_bb.set_xmin(0); + chanx_bb.set_xmax(grids.width()); + chanx_bb.set_ymin(0); + chanx_bb.set_ymax(grids.height() - 1); + } /* Add edges which is driven by X-direction clock routing tracks */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { + for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, layer, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, @@ -600,13 +848,20 @@ static void add_rr_graph_clock_edges( } /* Add edges which is driven by Y-direction clock routing tracks */ - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chany_bb.set_xmin(0); + chany_bb.set_xmax(grids.width() - 1); + chany_bb.set_ymin(0); + chany_bb.set_ymax(grids.height()); + } + for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { + for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, layer, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, @@ -614,6 +869,13 @@ static void add_rr_graph_clock_edges( clk_ntwk, chany_coord, CHANY, verbose); } } + /* Add edges between OPIN (internal driver) and clock routing tracks */ + add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, + clk_rr_lookup, rr_graph_view, grids, layer, + clk_ntwk, verbose); + add_rr_graph_opin2clk_intermediate_edges( + rr_graph_builder, num_edges_to_create, clk_rr_lookup, rr_graph_view, grids, + layer, clk_ntwk, verbose); } /******************************************************************** @@ -638,18 +900,11 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, return CMD_EXEC_SUCCESS; } - /* Report any clock structure we do not support yet! */ - if (clk_ntwk.num_trees() > 1) { - VTR_LOG( - "Currently only support 1 clock tree in programmable clock " - "architecture\nPlease update your clock architecture definition\n"); - return CMD_EXEC_FATAL_ERROR; - } - /* Estimate the number of nodes and pre-allocate */ size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes(); size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes( - vpr_device_ctx.grid, 0, vpr_device_ctx.arch->through_channel, clk_ntwk); + vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, + vpr_device_ctx.arch->through_channel, clk_ntwk); vpr_device_ctx.rr_graph_builder.unlock_storage(); vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes + orig_num_nodes); @@ -659,10 +914,10 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, num_clock_nodes, (float)(num_clock_nodes / orig_num_nodes)); /* Add clock nodes */ - add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup, - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, - vpr_device_ctx.arch->through_channel, clk_ntwk, - verbose); + add_rr_graph_clock_nodes( + vpr_device_ctx.rr_graph_builder, clk_rr_lookup, vpr_device_ctx.rr_graph, + vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, + vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); VTR_LOGV(verbose, "Added %lu clock nodes to routing " "resource graph.\n", @@ -676,7 +931,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, vpr_device_ctx.rr_graph_builder, num_clock_edges, static_cast(clk_rr_lookup), vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, - vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); + vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, + clk_ntwk, verbose); VTR_LOGV(verbose, "Added %lu clock edges to routing " "resource graph.\n", diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 963d53bc1..86d6cfdc4 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -45,19 +45,8 @@ const RRGSB& DeviceRRGSB::get_gsb(const size_t& x, const size_t& y) const { /* Get a rr switch block in the array with a coordinate */ const RRGSB& DeviceRRGSB::get_gsb_by_cb_coordinate( - const t_rr_type& cb_type, const vtr::Point& coordinate) const { + const vtr::Point& coordinate) const { vtr::Point gsb_coord = coordinate; - /* TODO move the coordinate conversion to RRGSB */ - switch (cb_type) { - case CHANX: - break; - case CHANY: - gsb_coord.set_y(gsb_coord.y() - 1); - break; - default: - VTR_LOG("Invalid type of connection block!\n"); - exit(1); - } VTR_ASSERT(validate_coordinate(gsb_coord)); return rr_gsb_[gsb_coord.x()][gsb_coord.y()]; @@ -76,6 +65,8 @@ size_t DeviceRRGSB::get_num_cb_unique_module(const t_rr_type& cb_type) const { exit(1); } } +/* Identify if unique blocks are preloaded or built */ +bool DeviceRRGSB::is_compressed() const { return is_compressed_; } /* Identify if a GSB actually exists at a location */ bool DeviceRRGSB::is_gsb_exist(const RRGraphView& rr_graph, @@ -106,6 +97,94 @@ size_t DeviceRRGSB::get_num_sb_unique_module() const { return sb_unique_module_.size(); } +/* get the coordinate of unique mirrors of switch blocks */ +vtr::Point DeviceRRGSB::get_sb_unique_block_coord(size_t id) const { + return sb_unique_module_[id]; +} + +/* get the coordinates of the instances of a unique switch block */ +std::vector> DeviceRRGSB::get_sb_unique_block_instance_coord( + const vtr::Point& unique_block_coord) const { + auto unique_module_id = + sb_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; + std::vector> instance_map; + for (size_t location_x = 0; location_x < sb_unique_module_id_.size(); + ++location_x) { + for (size_t location_y = 0; location_y < sb_unique_module_id_[0].size(); + ++location_y) { + auto unique_module_id_instance = + sb_unique_module_id_[location_x][location_y]; + if (unique_module_id_instance == unique_module_id) { + vtr::Point instance_coord(location_x, location_y); + if (instance_coord != unique_block_coord) { + instance_map.push_back(instance_coord); + } + } + } + } + return instance_map; +} + +/* get the coordinate of unique mirrors of connection blocks of CHANX type */ +vtr::Point DeviceRRGSB::get_cbx_unique_block_coord(size_t id) const { + return cbx_unique_module_[id]; +} + +/* get the coordinates of the instances of a unique connection block of CHANX + * type */ +std::vector> +DeviceRRGSB::get_cbx_unique_block_instance_coord( + const vtr::Point& unique_block_coord) const { + auto unique_module_id = + cbx_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; + std::vector> instance_map; + for (size_t location_x = 0; location_x < cbx_unique_module_id_.size(); + ++location_x) { + for (size_t location_y = 0; location_y < cbx_unique_module_id_[0].size(); + ++location_y) { + auto unique_module_id_instance = + cbx_unique_module_id_[location_x][location_y]; + if (unique_module_id_instance == unique_module_id) { + vtr::Point instance_coord(location_x, location_y); + if (instance_coord != unique_block_coord) { + instance_map.push_back(instance_coord); + } + } + } + } + return instance_map; +} + +/* get the coordinate of unique mirrors of connection blocks of CHANY type */ +vtr::Point DeviceRRGSB::get_cby_unique_block_coord(size_t id) const { + return cby_unique_module_[id]; +} + +/* get the coordinates of the instances of a unique connection block of CHANY + * type */ +std::vector> +DeviceRRGSB::get_cby_unique_block_instance_coord( + const vtr::Point& unique_block_coord) const { + auto unique_module_id = + cby_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; + std::vector> instance_map; + for (size_t location_x = 0; location_x < cby_unique_module_id_.size(); + ++location_x) { + for (size_t location_y = 0; location_y < cby_unique_module_id_[0].size(); + ++location_y) { + auto unique_module_id_instance = + cby_unique_module_id_[location_x][location_y]; + if (unique_module_id_instance == unique_module_id) { + vtr::Point instance_coord(location_x, location_y); + if (instance_coord != unique_block_coord) { + instance_map.push_back(instance_coord); + } + } + } + } + return instance_map; +} + /* get the number of unique mirrors of switch blocks */ size_t DeviceRRGSB::get_num_gsb_unique_module() const { return gsb_unique_module_.size(); @@ -183,6 +262,20 @@ void DeviceRRGSB::reserve(const vtr::Point& coordinate) { } } +void DeviceRRGSB::reserve_unique_modules() { + /* As rr_gsb_ has been built, it has valid size. Will reserve space for + * unique blocks according to rr_gsb_'s size*/ + sb_unique_module_id_.resize(rr_gsb_.size()); + cbx_unique_module_id_.resize(rr_gsb_.size()); + cby_unique_module_id_.resize(rr_gsb_.size()); + + for (std::size_t i = 0; i < rr_gsb_.size(); ++i) { + sb_unique_module_id_[i].resize(rr_gsb_[i].size()); + cbx_unique_module_id_[i].resize(rr_gsb_[i].size()); + cby_unique_module_id_[i].resize(rr_gsb_[i].size()); + } +} + /* Resize rr_switch_block array is needed*/ void DeviceRRGSB::resize_upon_need(const vtr::Point& coordinate) { if (coordinate.x() + 1 > rr_gsb_.size()) { @@ -203,8 +296,8 @@ void DeviceRRGSB::resize_upon_need(const vtr::Point& coordinate) { } } -/* Add a switch block to the array, which will automatically identify and update - * the lists of unique mirrors and rotatable mirrors */ +/* Add a switch block to the array, which will automatically identify and + * update the lists of unique mirrors and rotatable mirrors */ void DeviceRRGSB::add_rr_gsb(const vtr::Point& coordinate, const RRGSB& rr_gsb) { /* Resize upon needs*/ @@ -226,8 +319,8 @@ RRGSB& DeviceRRGSB::get_mutable_gsb(const size_t& x, const size_t& y) { return get_mutable_gsb(coordinate); } -/* Add a switch block to the array, which will automatically identify and update - * the lists of unique mirrors and rotatable mirrors */ +/* Add a switch block to the array, which will automatically identify and + * update the lists of unique mirrors and rotatable mirrors */ void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph, const t_rr_type& cb_type) { /* Make sure a clean start */ @@ -243,7 +336,8 @@ void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph, continue; } - /* Traverse the unique_mirror list and check it is an mirror of another */ + /* Traverse the unique_mirror list and check it is an mirror of another + */ for (size_t id = 0; id < get_num_cb_unique_module(cb_type); ++id) { const RRGSB& unique_module = get_cb_unique_module(cb_type, id); if (true == is_cb_mirror(rr_graph, device_annotation_, rr_gsb_[ix][iy], @@ -266,8 +360,8 @@ void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph, } } -/* Add a switch block to the array, which will automatically identify and update - * the lists of unique mirrors and rotatable mirrors */ +/* Add a switch block to the array, which will automatically identify and + * update the lists of unique mirrors and rotatable mirrors */ void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) { /* Make sure a clean start */ clear_sb_unique_module(); @@ -278,7 +372,8 @@ void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) { bool is_unique_module = true; vtr::Point sb_coordinate(ix, iy); - /* Traverse the unique_mirror list and check it is an mirror of another */ + /* Traverse the unique_mirror list and check it is an mirror of another + */ for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { /* Check if the two modules have the same submodules, * if so, these two modules are the same, indicating the sb is not @@ -305,8 +400,8 @@ void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) { } } -/* Add a switch block to the array, which will automatically identify and update - * the lists of unique mirrors and rotatable mirrors */ +/* Add a switch block to the array, which will automatically identify and + * update the lists of unique mirrors and rotatable mirrors */ /* Find repeatable GSB block in the array */ void DeviceRRGSB::build_gsb_unique_module() { @@ -318,11 +413,12 @@ void DeviceRRGSB::build_gsb_unique_module() { bool is_unique_module = true; vtr::Point gsb_coordinate(ix, iy); - /* Traverse the unique_mirror list and check it is an mirror of another */ + /* Traverse the unique_mirror list and check it is an mirror of another + */ for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) { /* We have alreay built sb and cb unique module list - * We just need to check if the unique module id of SBs, CBX and CBY are - * the same or not + * We just need to check if the unique module id of SBs, CBX and CBY + * are the same or not */ const vtr::Point& gsb_unique_module_coordinate = gsb_unique_module_[id]; @@ -350,6 +446,7 @@ void DeviceRRGSB::build_gsb_unique_module() { } } } + is_compressed_ = true; } void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { @@ -358,7 +455,8 @@ void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { build_cb_unique_module(rr_graph, CHANX); build_cb_unique_module(rr_graph, CHANY); - build_gsb_unique_module(); + build_gsb_unique_module(); /*is_compressed_ flip inside + build_gsb_unique_module*/ } void DeviceRRGSB::add_gsb_unique_module(const vtr::Point& coordinate) { @@ -419,6 +517,20 @@ void DeviceRRGSB::clear() { clear_sb_unique_module(); clear_sb_unique_module_id(); + is_compressed_ = false; +} + +void DeviceRRGSB::clear_unique_modules() { + /* clean unique module lists */ + clear_cb_unique_module(CHANX); + clear_cb_unique_module_id(CHANX); + + clear_cb_unique_module(CHANY); + clear_cb_unique_module_id(CHANY); + + clear_sb_unique_module(); + clear_sb_unique_module_id(); + is_compressed_ = false; } void DeviceRRGSB::clear_gsb() { @@ -562,4 +674,82 @@ size_t DeviceRRGSB::get_cb_unique_module_index( return cb_unique_module_id; } +/************************************************************************ + * Preload unique blocks + ***********************************************************************/ +/* preload unique cbx blocks and their corresponding instance information. This + * function will be called when read_unique_blocks command invoked */ +void DeviceRRGSB::preload_unique_cbx_module( + const vtr::Point& block_coordinate, + const std::vector>& instance_coords) { + /*check whether the preloaded value exceeds the limit */ + size_t limit_x = cbx_unique_module_id_.size(); + size_t limit_y = cbx_unique_module_id_[0].size(); + VTR_ASSERT(block_coordinate.x() < limit_x); + VTR_ASSERT(block_coordinate.y() < limit_y); + add_cb_unique_module(CHANX, block_coordinate); + /* preload the unique block */ + set_cb_unique_module_id(CHANX, block_coordinate, + get_num_cb_unique_module(CHANX) - 1); + + /* preload the instances of the unique block. Instance will have the same id + * as the unique block */ + for (auto instance_location : instance_coords) { + VTR_ASSERT(instance_location.x() < limit_x); + VTR_ASSERT(instance_location.y() < limit_y); + set_cb_unique_module_id( + CHANX, instance_location, + cbx_unique_module_id_[block_coordinate.x()][block_coordinate.y()]); + } +} + +/* preload unique cby blocks and their corresponding instance information. This + * function will be called when read_unique_blocks command invoked */ +void DeviceRRGSB::preload_unique_cby_module( + const vtr::Point& block_coordinate, + const std::vector>& instance_coords) { + /*check whether the preloaded value exceeds the limit */ + size_t limit_x = cby_unique_module_id_.size(); + size_t limit_y = cby_unique_module_id_[0].size(); + + VTR_ASSERT(block_coordinate.x() < limit_x); + VTR_ASSERT(block_coordinate.y() < limit_y); + add_cb_unique_module(CHANY, block_coordinate); + /* preload the unique block */ + set_cb_unique_module_id(CHANY, block_coordinate, + get_num_cb_unique_module(CHANY) - 1); + + /* preload the instances of the unique block. Instance will have the same id + * as the unique block */ + for (auto instance_location : instance_coords) { + VTR_ASSERT(instance_location.x() < limit_x); + VTR_ASSERT(instance_location.y() < limit_y); + set_cb_unique_module_id( + CHANY, instance_location, + cby_unique_module_id_[block_coordinate.x()][block_coordinate.y()]); + } +} + +/* preload unique sb blocks and their corresponding instance information. This + * function will be called when read_unique_blocks command invoked */ +void DeviceRRGSB::preload_unique_sb_module( + const vtr::Point& block_coordinate, + const std::vector>& instance_coords) { + /*check whether the preloaded value exceeds the limit */ + VTR_ASSERT(block_coordinate.x() < sb_unique_module_id_.size()); + VTR_ASSERT(block_coordinate.y() < sb_unique_module_id_[0].size()); + sb_unique_module_.push_back(block_coordinate); + /* Record the id of unique module */ + sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()] = + sb_unique_module_.size() - 1; + + /* each mirror instance of the unique module will have the same module id as + * the unique module */ + for (auto instance_location : instance_coords) { + VTR_ASSERT(instance_location.x() < sb_unique_module_id_.size()); + VTR_ASSERT(instance_location.y() < sb_unique_module_id_[0].size()); + sb_unique_module_id_[instance_location.x()][instance_location.y()] = + sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()]; + } +} } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 245b1646b..1325b557b 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -40,11 +40,31 @@ class DeviceRRGSB { const; /* Get a rr switch block in the array with a coordinate */ /* Get a gsb using its connection block coordinate */ const RRGSB& get_gsb_by_cb_coordinate( - const t_rr_type& cb_type, const vtr::Point& coordinate) const; + const vtr::Point& coordinate) const; size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */ + size_t get_num_sb_unique_module() - const; /* get the number of unique mirrors of switch blocks */ + const; /* get the number of unique mirrors of SB */ + vtr::Point get_sb_unique_block_coord( + size_t id) const; /* get the coordinate of a unique switch block */ + std::vector> get_sb_unique_block_instance_coord( + const vtr::Point& unique_block_coord) + const; /* get the coordinates of the instances of a unique switch block */ + + vtr::Point get_cbx_unique_block_coord(size_t id) + const; /* get the coordinate of a unique connection block of CHANX type */ + std::vector> get_cbx_unique_block_instance_coord( + const vtr::Point& unique_block_coord) + const; /* get the coordinates of the instances of a unique connection block + of CHANX type*/ + vtr::Point get_cby_unique_block_coord(size_t id) + const; /* get the coordinate of a unique connection block of CHANY type */ + std::vector> get_cby_unique_block_instance_coord( + const vtr::Point& unique_block_coord) + const; /* get the coordinates of the instances of a unique connection block + of CHANY type */ + const RRGSB& get_gsb_unique_module( const size_t& index) const; /* Get a rr-gsb which is a unique mirror */ const RRGSB& get_sb_unique_module(const size_t& index) @@ -69,13 +89,15 @@ class DeviceRRGSB { const vtr::Point& coordinate) const; public: /* Mutators */ + bool is_compressed() const; + void build_gsb_unique_module(); /* Add a switch block to the array, which will + automatically identify and update the lists + of unique mirrors and rotatable mirrors */ void reserve( const vtr::Point& coordinate); /* Pre-allocate the rr_switch_block array that the device requires */ - void reserve_sb_unique_submodule_id( - const vtr::Point& - coordinate); /* Pre-allocate the rr_sb_unique_module_id matrix that the - device requires */ + void reserve_unique_modules(); /* Pre-allocate the rr_sb_unique_module_id + matrix that the device requires */ void resize_upon_need( const vtr::Point& coordinate); /* Resize the rr_switch_block array if needed */ @@ -95,8 +117,27 @@ class DeviceRRGSB { automatically identify and update the lists of unique mirrors and rotatable mirrors */ void clear(); /* clean the content */ - private: /* Internal cleaners */ - void clear_gsb(); /* clean the content */ + void preload_unique_cbx_module( + const vtr::Point& block_coordinate, + const std::vector>& + instance_coords); /* preload unique CBX blocks and their corresponding + instance information. This function will be called + when read_unique_blocks command invoked */ + void preload_unique_cby_module( + const vtr::Point& block_coordinate, + const std::vector>& + instance_coords); /* preload unique CBY blocks and their corresponding +instance information. This function will be called +when read_unique_blocks command invoked */ + void preload_unique_sb_module(const vtr::Point& block_coordinate, + const std::vector>& + instance_coords); /* preload unique SB blocks + and their corresponding instance information. This function + will be called when read_unique_blocks command invoked */ + void clear_unique_modules(); /* clean the content of unique blocks*/ + + private: /* Internal cleaners */ + void clear_gsb(); /* clean the content */ void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */ void clear_cb_unique_module_id( const t_rr_type& cb_type); /* clean the content */ @@ -133,11 +174,11 @@ class DeviceRRGSB { const t_rr_type& cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */ - void build_gsb_unique_module(); /* Add a switch block to the array, which will - automatically identify and update the lists - of unique mirrors and rotatable mirrors */ - private: /* Internal Data */ + + private: /* Internal Data */ std::vector> rr_gsb_; + bool is_compressed_ = + false; /* True if the unique blocks have been preloaded or built */ std::vector> gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 780b1d99d..48c8d732f 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -8,10 +8,102 @@ #include "old_traceback.h" #include "vtr_assert.h" #include "vtr_log.h" +#include "vtr_time.h" /* begin namespace openfpga */ namespace openfpga { +/******************************************************************** + * Create a mapping between each rr_node and its mapped nets + * - Only applicable to global nets for dedicated clock routing purpose + * - Note that this function is different than annotate_vpr_rr_nodes() + * Please do not annotate global nets in vpr_routing_annotation! + *******************************************************************/ +vtr::vector annotate_rr_node_global_net( + const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, + const VprClusteringAnnotation& clustering_annotation, const bool& verbose) { + vtr::vector rr_node_nets; + + size_t counter = 0; + vtr::ScopedStartFinishTimer timer("Annotating rr_node with global nets"); + + const auto& rr_graph = device_ctx.rr_graph; + + rr_node_nets.resize(rr_graph.num_nodes(), ClusterNetId::INVALID()); + + size_t layer = 0; + + for (ClusterNetId net_id : cluster_nlist.nets()) { + if (!cluster_nlist.net_is_ignored(net_id)) { + continue; + } + /* Walk through all the sinks */ + for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) { + ClusterBlockId block_id = cluster_nlist.pin_block(pin_id); + t_block_loc blk_loc = get_block_loc(block_id, false); + int phy_pin = placement_ctx.physical_pins()[pin_id]; + t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type( + t_physical_tile_loc(blk_loc.loc.x, blk_loc.loc.y, 0)); + int node_pin_num = phy_tile->num_pins; + /* Note that the phy_pin may not reflect the actual pin index at the + * top-level physical tile type. It could be one of the random pin to the + * same pin class. So here, we have to find an exact match of the pin + * index from the clustering results! */ + int subtile_idx = blk_loc.loc.sub_tile; + auto logical_block = cluster_nlist.block_type(block_id); + for (int j = 0; j < logical_block->pb_type->num_pins; j++) { + /* Find the net mapped to this pin in clustering results*/ + ClusterNetId cluster_net_id = cluster_nlist.block_net(block_id, j); + /* Get the actual net id because it may be renamed during routing */ + if (true == clustering_annotation.is_net_renamed(block_id, j)) { + cluster_net_id = clustering_annotation.net(block_id, j); + } + /* Bypass unmatched pins */ + if (cluster_net_id != net_id) { + continue; + } + int curr_pin_num = get_physical_pin_at_sub_tile_location( + phy_tile, logical_block, subtile_idx, j); + if (phy_tile->pin_class[curr_pin_num] != phy_tile->pin_class[phy_pin]) { + continue; + } + node_pin_num = curr_pin_num; + break; + } + VTR_ASSERT(node_pin_num < phy_tile->num_pins); + t_rr_type rr_pin_type = IPIN; + if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == + RECEIVER) { + rr_pin_type = IPIN; + } else if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == + DRIVER) { + rr_pin_type = OPIN; + } else { + VTR_LOG_ERROR( + "When annotating global net '%s', invalid rr node pin type for '%s' " + "pin '%d'\n", + cluster_nlist.net_name(net_id).c_str(), phy_tile->name, node_pin_num); + exit(1); + } + std::vector curr_rr_nodes = + rr_graph.node_lookup().find_nodes_at_all_sides( + layer, blk_loc.loc.x, blk_loc.loc.y, rr_pin_type, node_pin_num); + for (RRNodeId curr_rr_node : curr_rr_nodes) { + VTR_LOGV(verbose, "Annotate global net '%s' on '%s' pin '%d'\n", + cluster_nlist.net_name(net_id).c_str(), phy_tile->name, + node_pin_num); + rr_node_nets[curr_rr_node] = net_id; + counter++; + } + } + } + + VTR_LOGV(verbose, "Done with %d nodes mapping\n", counter); + + return rr_node_nets; +} + /******************************************************************** * Create a mapping between each rr_node and its mapped nets * based on VPR routing results @@ -19,17 +111,14 @@ namespace openfpga { *******************************************************************/ void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, - const RoutingContext& routing_ctx, VprRoutingAnnotation& vpr_routing_annotation, const bool& verbose) { - vtr::vector node2net = - annotate_rr_node_nets((const Netlist<>&)clustering_ctx.clb_nlist, - device_ctx, routing_ctx, verbose, false); + vtr::vector node2net = + annotate_rr_node_nets(clustering_ctx, device_ctx, verbose); for (size_t node_id = 0; node_id < device_ctx.rr_graph.num_nodes(); ++node_id) { - vpr_routing_annotation.set_rr_node_net( - RRNodeId(node_id), - convert_to_cluster_net_id(node2net[RRNodeId(node_id)])); + vpr_routing_annotation.set_rr_node_net(RRNodeId(node_id), + node2net[RRNodeId(node_id)]); } VTR_LOG("Loaded node-to-net mapping\n"); } diff --git a/openfpga/src/annotation/openfpga_annotate_routing.h b/openfpga/src/annotation/openfpga_annotate_routing.h index aa79e69d5..b8f5a83e7 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.h +++ b/openfpga/src/annotation/openfpga_annotate_routing.h @@ -5,6 +5,7 @@ * Include header files that are required by function declaration *******************************************************************/ #include "openfpga_context.h" +#include "vpr_clustering_annotation.h" #include "vpr_context.h" #include "vpr_routing_annotation.h" @@ -15,9 +16,13 @@ /* begin namespace openfpga */ namespace openfpga { +vtr::vector annotate_rr_node_global_net( + const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, + const VprClusteringAnnotation& clustering_annotation, const bool& verbose); + void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, - const RoutingContext& routing_ctx, VprRoutingAnnotation& vpr_routing_annotation, const bool& verbose); diff --git a/openfpga/src/annotation/read_unique_blocks_bin.cpp b/openfpga/src/annotation/read_unique_blocks_bin.cpp new file mode 100644 index 000000000..1d739403e --- /dev/null +++ b/openfpga/src/annotation/read_unique_blocks_bin.cpp @@ -0,0 +1,103 @@ +#include +#include +#include + +#include +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "command_exit_codes.h" +#include "device_rr_gsb_utils.h" +#include "mmap_file.h" +#include "openfpga_digest.h" +#include "read_unique_blocks_bin.h" +#include "read_unique_blocks_xml.h" +#include "read_xml_util.h" +#include "rr_gsb.h" +#include "unique_blocks_uxsdcxx.capnp.h" +#include "write_xml_utils.h" + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads a bin file of unique blocks to the associated + * data structures: device_rr_gsb + *******************************************************************/ +namespace openfpga { + +/*read the instances' coordinate of a unique block from a bin file*/ +std::vector> read_bin_unique_instance_coords( + const ucap::Block::Reader& unique_block) { + std::vector> instance_coords; + if (unique_block.hasInstances()) { + auto instance_list = unique_block.getInstances(); + for (auto instance : instance_list) { + int instance_x = instance.getX(); + int instance_y = instance.getY(); + vtr::Point instance_coordinate(instance_x, instance_y); + instance_coords.push_back(instance_coordinate); + } + } + return instance_coords; +} + +/*read the unique block coordinate from a bin file */ +vtr::Point read_bin_unique_block_coord( + const ucap::Block::Reader& unique_block, ucap::Type& type) { + int block_x = unique_block.getX(); + int block_y = unique_block.getY(); + type = unique_block.getType(); + vtr::Point block_coordinate(block_x, block_y); + return block_coordinate; +} + +/*top-level function to read unique blocks from bin file*/ +int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output) { + /* clear unique modules & reserve memory to relavant vectors */ + device_rr_gsb.clear_unique_modules(); + device_rr_gsb.reserve_unique_modules(); + MmapFile f(file_name); + ::capnp::FlatArrayMessageReader reader(f.getData()); + auto root = reader.getRoot(); + if (root.hasBlocks()) { + auto block_list = root.getBlocks(); + for (auto unique_block : block_list) { + ucap::Type type; + vtr::Point block_coordinate = read_bin_unique_block_coord( + unique_block, type); /*get block coordinate and type*/ + std::vector> instance_coords = + read_bin_unique_instance_coords( + unique_block); /* get a list of instance coordinates*/ + /* get block coordinate and instance coordinate, try to setup + * device_rr_gsb */ + if (type == ucap::Type::SB) { + device_rr_gsb.preload_unique_sb_module(block_coordinate, + instance_coords); + } else if (type == ucap::Type::CBY) { + device_rr_gsb.preload_unique_cby_module(block_coordinate, + instance_coords); + } else if (type == ucap::Type::CBX) { + device_rr_gsb.preload_unique_cbx_module(block_coordinate, + instance_coords); + } else if (type == ucap::Type::UXSD_INVALID) { + VTR_LOG_ERROR("Invalid block type!"); + return CMD_EXEC_FATAL_ERROR; + } + } + } + device_rr_gsb.build_gsb_unique_module(); + if (verbose_output) { + report_unique_module_status_read(device_rr_gsb, true); + } + return CMD_EXEC_SUCCESS; +} +} // namespace openfpga diff --git a/openfpga/src/annotation/read_unique_blocks_bin.h b/openfpga/src/annotation/read_unique_blocks_bin.h new file mode 100644 index 000000000..54da11a3a --- /dev/null +++ b/openfpga/src/annotation/read_unique_blocks_bin.h @@ -0,0 +1,36 @@ +#ifndef READ_XML_UNIQUE_BLOCKS_BIN_H +#define READ_XML_UNIQUE_BLOCKS_BIN_H + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "device_rr_gsb_utils.h" +#include "unique_blocks_uxsdcxx.capnp.h" +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads a bin file of unique blocks to the associated + * data structures: device_rr_gsb + *******************************************************************/ +namespace openfpga { +std::vector> read_bin_unique_instance_coords( + const ucap::Block::Reader& unique_block); + +vtr::Point read_bin_unique_block_coord( + const ucap::Block::Reader& unique_block, ucap::Type& type); + +int read_bin_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output); +} // namespace openfpga + +#endif diff --git a/openfpga/src/annotation/read_unique_blocks_xml.cpp b/openfpga/src/annotation/read_unique_blocks_xml.cpp new file mode 100644 index 000000000..201c253c2 --- /dev/null +++ b/openfpga/src/annotation/read_unique_blocks_xml.cpp @@ -0,0 +1,159 @@ + +#include +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "command_exit_codes.h" +#include "device_rr_gsb_utils.h" +#include "mmap_file.h" +#include "openfpga_digest.h" +#include "read_unique_blocks_xml.h" +#include "read_xml_util.h" +#include "rr_gsb.h" +#include "unique_blocks_uxsdcxx.capnp.h" +#include "write_xml_utils.h" + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads an XML file of unique blocks to the associated + * data structures: device_rr_gsb + *******************************************************************/ +namespace openfpga { +/*read the instances' coordinate of a unique block from a xml file*/ +std::vector> read_xml_unique_instance_coords( + const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data) { + std::vector> instance_coords; + for (pugi::xml_node xml_instance_info : xml_block_info.children()) { + if (xml_instance_info.name() == std::string("instance")) { + int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); + int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); + vtr::Point instance_coordinate(instance_x, instance_y); + instance_coords.push_back(instance_coordinate); + } + } + return instance_coords; +} + +/*read the unique block coordinate from a xml file */ +vtr::Point read_xml_unique_block_coord( + const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data) { + int block_x = get_attribute(xml_block_info, "x", loc_data).as_int(); + int block_y = get_attribute(xml_block_info, "y", loc_data).as_int(); + vtr::Point block_coordinate(block_x, block_y); + return block_coordinate; +} + +/*report information of read unique blocks*/ +void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, + bool verbose_output) { + /* Report the stats */ + VTR_LOGV( + verbose_output, + "Read %lu unique X-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + device_rr_gsb.get_num_cb_unique_module(CHANX), + find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX), + 100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX) / + (float)device_rr_gsb.get_num_cb_unique_module(CHANX) - + 1.)); + VTR_LOGV( + verbose_output, + "Read %lu unique Y-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + device_rr_gsb.get_num_cb_unique_module(CHANY), + find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY), + 100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY) / + (float)device_rr_gsb.get_num_cb_unique_module(CHANY) - + 1.)); + + VTR_LOGV(verbose_output, + "Read %lu unique switch blocks from a total of %d (compression " + "rate=%.2f%)\n", + device_rr_gsb.get_num_sb_unique_module(), + find_device_rr_gsb_num_sb_modules(device_rr_gsb, + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_sb_modules( + device_rr_gsb, g_vpr_ctx.device().rr_graph) / + (float)device_rr_gsb.get_num_sb_unique_module() - + 1.)); + + VTR_LOG( + "Read %lu unique general switch blocks from a total of %d " + "(compression " + "rate=%.2f%)\n", + device_rr_gsb.get_num_gsb_unique_module(), + find_device_rr_gsb_num_gsb_modules(device_rr_gsb, + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_gsb_modules( + device_rr_gsb, g_vpr_ctx.device().rr_graph) / + (float)device_rr_gsb.get_num_gsb_unique_module() - + 1.)); +} + +/*Parse XML codes about to an object of device_rr_gsb*/ +int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output) { + vtr::ScopedStartFinishTimer timer("Read unique blocks xml file"); + /* Parse the file */ + pugi::xml_document doc; + pugiutil::loc_data loc_data; + try { + loc_data = pugiutil::load_xml(doc, file_name); + + pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data); + /* clear unique modules & reserve memory to relavant vectors */ + device_rr_gsb.clear_unique_modules(); + device_rr_gsb.reserve_unique_modules(); + + /* load unique blocks xml file and set up device_rr_gdb */ + for (pugi::xml_node xml_block_info : xml_root.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_block_info.name() == std::string("block")) { + std::string type = + get_attribute(xml_block_info, "type", loc_data).as_string(); + vtr::Point block_coordinate = + read_xml_unique_block_coord(xml_block_info, loc_data); + std::vector> instance_coords = + read_xml_unique_instance_coords(xml_block_info, loc_data); + + /* get block coordinate and instance coordinate, try to setup + * device_rr_gsb */ + if (type == "sb") { + device_rr_gsb.preload_unique_sb_module(block_coordinate, + instance_coords); + } else if (type == "cby") { + device_rr_gsb.preload_unique_cby_module(block_coordinate, + instance_coords); + } else if (type == "cbx") { + device_rr_gsb.preload_unique_cbx_module(block_coordinate, + instance_coords); + } else { + archfpga_throw(loc_data.filename_c_str(), + loc_data.line(xml_block_info), + "Invalid block type '%s'\n", type.c_str()); + } + } else { + bad_tag(xml_block_info, loc_data, xml_root, {"block"}); + } + } + /* As preloading gsb hasn't been developed, we should build gsb using the + * preloaded cbs and sbs*/ + device_rr_gsb.build_gsb_unique_module(); + if (verbose_output) { + report_unique_module_status_read(device_rr_gsb, true); + } + return CMD_EXEC_SUCCESS; + } catch (pugiutil::XmlError& e) { + archfpga_throw(file_name, e.line(), "%s", e.what()); + } +} +} // namespace openfpga diff --git a/openfpga/src/annotation/read_unique_blocks_xml.h b/openfpga/src/annotation/read_unique_blocks_xml.h new file mode 100644 index 000000000..241bc07e2 --- /dev/null +++ b/openfpga/src/annotation/read_unique_blocks_xml.h @@ -0,0 +1,40 @@ +#ifndef READ_XML_UNIQUE_BLOCKS_XML_H +#define READ_XML_UNIQUE_BLOCKS_XML_H + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "device_rr_gsb_utils.h" +#include "unique_blocks_uxsdcxx.capnp.h" +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads an XML file of unique blocks to the associated + * data structures: device_rr_gsb + *******************************************************************/ +namespace openfpga { + +std::vector> read_xml_unique_instance_coords( + const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data); + +vtr::Point read_xml_unique_block_coord( + const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data); + +void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, + bool verbose_output); + +int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output); +} // namespace openfpga + +#endif diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index bafc8215f..55e096566 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -1,7 +1,8 @@ #include "route_clock_rr_graph.h" #include "command_exit_codes.h" -#include "openfpga_atom_netlist_utils.h" +#include "openfpga_annotate_routing.h" +#include "openfpga_clustered_netlist_utils.h" #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_log.h" @@ -21,27 +22,30 @@ namespace openfpga { static int build_clock_tree_net_map( std::map& tree2clk_pin_map, const ClusteredNetlist& cluster_nlist, const PinConstraints& pin_constraints, - const std::vector& clk_names, const ClockNetwork& clk_ntwk, + const std::vector& gnets, const ClockNetwork& clk_ntwk, const ClockTreeId clk_tree, const bool& verbose) { + BasicPort tree_gport = clk_ntwk.tree_global_port(clk_tree); /* Find the pin id for each clock name, error out if there is any mismatch */ - if (clk_names.size() == 1 && clk_ntwk.tree_width(clk_tree) == 1) { + if (clk_ntwk.num_trees() == 1 && gnets.size() == 1 && + clk_ntwk.tree_width(clk_tree) == 1) { /* Find cluster net id */ - ClusterNetId clk_net = cluster_nlist.find_net(clk_names[0]); - if (!cluster_nlist.valid_net_id(clk_net)) { - VTR_LOG_ERROR("Invalid clock name '%s'! Cannot found from netlists!\n", - clk_names[0].c_str()); + if (!cluster_nlist.valid_net_id(gnets[0])) { + VTR_LOG_ERROR("Invalid clock name '%s'! Cannot be found from netlists!\n", + cluster_nlist.net_name(gnets[0]).c_str()); return CMD_EXEC_FATAL_ERROR; } - tree2clk_pin_map[ClockTreePinId(0)] = clk_net; + tree2clk_pin_map[ClockTreePinId(0)] = gnets[0]; } else { - for (std::string clk_name : clk_names) { + for (ClusterNetId gnet : gnets) { /* Find the pin information that the net should be mapped to */ - BasicPort tree_pin = pin_constraints.net_pin(clk_name); + std::string gnet_name = cluster_nlist.net_name(gnet); + /* The pin should match be global port name of the tree */ + BasicPort tree_pin = pin_constraints.net_pin(gnet_name); if (!tree_pin.is_valid()) { VTR_LOG_ERROR( - "Invalid tree pin for clock '%s'! Clock name may not be valid " - "(mismatched with netlists)!\n", - clk_name.c_str()); + "Global net '%s' is not mapped to a valid pin '%s' in pin " + "constraints!\n", + gnet_name.c_str(), tree_pin.to_verilog_string().c_str()); return CMD_EXEC_FATAL_ERROR; } if (tree_pin.get_width() != 1) { @@ -49,25 +53,28 @@ static int build_clock_tree_net_map( "Invalid tree pin %s[%lu:%lu] for clock '%s'! Clock pin must have " "only a width of 1!\n", tree_pin.get_name().c_str(), tree_pin.get_lsb(), tree_pin.get_msb(), - clk_name.c_str()); + gnet_name.c_str()); return CMD_EXEC_FATAL_ERROR; } - if (tree_pin.get_lsb() >= clk_ntwk.tree_width(clk_tree)) { + if (tree_gport.get_name() != tree_pin.get_name()) { + continue; + } + if (!tree_gport.contained(tree_pin)) { VTR_LOG_ERROR( - "Invalid tree pin %s[%lu] is out of range of clock tree size '%lu'\n", - tree_pin.get_name().c_str(), tree_pin.get_lsb(), - clk_ntwk.tree_width(clk_tree)); - return CMD_EXEC_FATAL_ERROR; - } - /* Find cluster net id */ - ClusterNetId clk_net = cluster_nlist.find_net(clk_name); - if (!cluster_nlist.valid_net_id(clk_net)) { - VTR_LOG_ERROR("Invalid clock name '%s'! Cannot found from netlists!\n", - clk_name.c_str()); + "Invalid pin constraint port '%s' which is out of range of the " + "global port '%s' of clock tree '%s'\n", + tree_pin.to_verilog_string().c_str(), + tree_gport.to_verilog_string().c_str(), + clk_ntwk.tree_name(clk_tree).c_str()); return CMD_EXEC_FATAL_ERROR; } + /* TODO: Check the tree_pin.get_name(), see if matches the tree from ports + */ /* Register the pin mapping */ - tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = clk_net; + tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = gnet; + VTR_LOGV(verbose, "Mapped net '%s' to pin '%s' of clock tree '%s'.\n", + gnet_name.c_str(), tree_pin.to_verilog_string().c_str(), + clk_ntwk.tree_name(clk_tree).c_str()); } } @@ -77,6 +84,484 @@ static int build_clock_tree_net_map( return CMD_EXEC_SUCCESS; } +/******************************************************************** + * Route a switching points between spines + * - connect between two routing tracks (left or right turns) + * - connect internal driver to routing track + *******************************************************************/ +static int route_clock_spine_switch_point( + VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, + const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, + const std::map& tree2clk_pin_map, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockSpineId& ispine, const ClockTreePinId& ipin, + const ClockSwitchPointId& switch_point_id, const bool& verbose) { + vtr::Point src_coord = + clk_ntwk.spine_switch_point(ispine, switch_point_id); + ClockSpineId des_spine = + clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); + vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); + VTR_LOGV(verbose, "Routing switch points from spine '%s' to spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str(), + clk_ntwk.spine_name(des_spine).c_str()); + Direction src_spine_direction = clk_ntwk.spine_direction(ispine); + Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); + ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); + /* Special for DEC_DIR CHANX and CHANY, there should be a offset on the source + * coordinate Note that in the following condition, the switching point occurs + * in switch block (x, y) INC CHANY (x, y + 1) + * ^ + * | + * INC CHANX (x, y) --->+<---- DEC CHANX (x + 1, y) + * | + * v + * DEC CHANY (x, y) + * + * Note that in the following condition, the switching point occurs in switch + * block (x, y) DEC CHANY (x, y + 1) + * | + * v + * DEC CHANX (x, y) <---+----> INC CHANX (x + 1, y) + * ^ + * | + * INC CHANY (x, y) + * From the user point of view, the switching point should only occur in a + * switch block So the coordinate of a switch block should be provided as the + * coordinate of switching point However, the src node and des node may not + * follow the switch block coordinate! In short, the src coordinate requires + * an adjustment only when + * - The src is an CHANX in DEC + * - The src is an CHANY in DEC + * No adjustment is required for des node as it always comes from the starting + * point of the des spine + */ + if (clk_ntwk.spine_track_type(ispine) == CHANX && + src_spine_direction == Direction::DEC) { + src_coord.set_x(des_coord.x() + 1); + } + if (clk_ntwk.spine_track_type(ispine) == CHANY && + src_spine_direction == Direction::DEC) { + src_coord.set_y(des_coord.y() + 1); + } + RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), + clk_tree, src_spine_level, ipin, + src_spine_direction, verbose); + RRNodeId des_node = clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), + clk_tree, des_spine_level, ipin, + des_spine_direction, verbose); + VTR_ASSERT(rr_graph.valid_node(src_node)); + VTR_ASSERT(rr_graph.valid_node(des_node)); + /* Internal drivers may appear at the switch point. Check if there are + * any defined and related rr_node found as incoming edges. If the + * global net is mapped to the internal driver, use it as the previous + * node */ + size_t use_int_driver = 0; + if (!clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id) + .empty() && + tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { + RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); + if (OPIN != rr_graph.node_type(opin_node)) { + continue; + } + if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(ipin)) { + continue; + } + /* This is the opin node we need, use it as the internal driver */ + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + opin_node); + vpr_routing_annotation.set_rr_node_net(opin_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); + use_int_driver++; + VTR_LOGV(verbose, + "Routed switch points of spine '%s' at the switching point " + "(%lu, %lu) using internal driver\n", + clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), + src_coord.y()); + } + } + if (use_int_driver > 1) { + VTR_LOG_ERROR( + "Found %lu internal drivers for the switching point (%lu, %lu) for " + "spine '%s'!\n Expect only 1!\n", + use_int_driver, src_coord.x(), src_coord.y(), + clk_ntwk.spine_name(ispine).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + if (use_int_driver == 1) { + return CMD_EXEC_SUCCESS; /* Used internal driver, early pass */ + } + VTR_LOGV(verbose, + "Routed switch points of spine '%s' (node '%lu') from (x=%lu, " + "y=%lu) to spine " + "'%s' (node '%lu') at (x=%lu, y=%lu)\n", + clk_ntwk.spine_name(ispine).c_str(), size_t(src_node), src_coord.x(), + src_coord.y(), clk_ntwk.spine_name(des_spine).c_str(), + size_t(des_node), des_coord.x(), des_coord.y()); + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); + /* It could happen that there is no net mapped some clock pin, skip the + * net mapping */ + if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net(src_node, tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, tree2clk_pin_map.at(ipin)); + } + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Route a spine to its tap points + * - Only connect to tap points which are mapped by a global net + *******************************************************************/ +static int route_spine_taps( + VprRoutingAnnotation& vpr_routing_annotation, bool& spine_usage, + const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, + const std::map& tree2clk_pin_map, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockSpineId& ispine, const ClockTreePinId& ipin, const bool& verbose) { + size_t spine_tap_cnt = 0; + /* Route the spine-to-IPIN connections (only for the last level) */ + if (clk_ntwk.is_last_level(ispine)) { + VTR_LOGV(verbose, + "Routing clock taps of spine '%s' for pin '%d' of tree '%s'...\n", + clk_ntwk.spine_name(ispine).c_str(), size_t(ipin), + clk_ntwk.tree_name(clk_tree).c_str()); + std::vector> spine_coords = + clk_ntwk.spine_coordinates(ispine); + /* Connect to any fan-out node which is IPIN */ + for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { + vtr::Point src_coord = spine_coords[icoord]; + Direction src_spine_direction = clk_ntwk.spine_direction(ispine); + ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); + RRNodeId src_node = clk_rr_lookup.find_node( + src_coord.x(), src_coord.y(), clk_tree, src_spine_level, ipin, + src_spine_direction, verbose); + for (RREdgeId edge : rr_graph.edge_range(src_node)) { + RRNodeId des_node = rr_graph.edge_sink_node(edge); + if (rr_graph.node_type(des_node) == IPIN) { + VTR_LOGV(verbose, "Trying to route to IPIN '%s'\n", + rr_graph.node_coordinate_to_string(des_node).c_str()); + /* Check if the IPIN is mapped, if not, do not connect */ + /* if the IPIN is mapped, only connect when net mapping is + * expected */ + if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the tree is " + "not used\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } + if (!rr_node_gnets[des_node]) { + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the IPIN is " + "not mapped\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } + if (rr_node_gnets[des_node] != tree2clk_pin_map.at(ipin)) { + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the net " + "mapping does not match clock net\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } + VTR_ASSERT(rr_graph.valid_node(src_node)); + VTR_ASSERT(rr_graph.valid_node(des_node)); + VTR_LOGV(verbose, "Routed clock tap of spine '%s'\n", + clk_ntwk.spine_name(ispine).c_str()); + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + src_node); + vpr_routing_annotation.set_rr_node_net(src_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); + /* Increment upon any required tap */ + spine_tap_cnt++; + } + } + } + } + if (spine_tap_cnt) { + spine_usage = true; + } + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Recursively route a clock spine on an existing routing resource graph + *******************************************************************/ +static int route_spine_intermediate_drivers( + VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, + const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, + const std::map& tree2clk_pin_map, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockSpineId& curr_spine, const ClockTreePinId& curr_pin, + const vtr::Point& des_coord, const bool& verbose) { + Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(curr_spine); + RRNodeId des_node = clk_rr_lookup.find_node( + des_coord.x(), des_coord.y(), clk_tree, des_spine_level, curr_pin, + des_spine_direction, verbose); + VTR_ASSERT(rr_graph.valid_node(des_node)); + + /* Internal drivers may appear at the intermediate. Check if there are + * any defined and related rr_node found as incoming edges. If the + * global net is mapped to the internal driver, use it as the previous + * node */ + size_t use_int_driver = 0; + if (!clk_ntwk + .spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) + .empty() && + tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + VTR_LOGV( + verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n", + des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str()); + for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { + RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); + if (OPIN != rr_graph.node_type(opin_node)) { + continue; + } + if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(curr_pin)) { + continue; + } + /* This is the opin node we need, use it as the internal driver */ + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + opin_node); + vpr_routing_annotation.set_rr_node_net(opin_node, + tree2clk_pin_map.at(curr_pin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(curr_pin)); + use_int_driver++; + VTR_LOGV(verbose, + "Routed intermediate point of spine '%s' at " + "(%lu, %lu) using internal driver\n", + clk_ntwk.spine_name(curr_spine).c_str(), des_coord.x(), + des_coord.y()); + } + } + if (use_int_driver > 1) { + VTR_LOG_ERROR( + "Found %lu internal drivers for the intermediate point (%lu, %lu) " + "for " + "spine '%s'!\n Expect only 1!\n", + use_int_driver, des_coord.x(), des_coord.y(), + clk_ntwk.spine_name(curr_spine).c_str()); + } + return use_int_driver; +} + +/******************************************************************** + * Recursively route a clock spine on an existing routing resource graph + * The strategy is to route spine one by one + * - route the spine from the ending point to starting point (straight line) + * - for each stops on the staight line, route the spine-to-spine switching + points + * - for each switching point (des_spine_top|bottom), go recursively + * - If the downstream spine at any switching point is not used, disconnect + * - If any stop on the spine (straght line) is not used, disconnect + * - route the spine-to-IPIN connections (only for the last level) + * + * des_spine_top[0...N] + * ^ ^ ^ ^ + * | | | | + * spine_start ---->+---->+---->+---->+->spine_end + * | | | | + * v v v v + * des_spine_bottom[0...N] + * + * <-------------------------------------------- direction to walk through + * + * + * On each stop, we expand the spine to switch points and tap points + * - If the previous stop is used (connection to des_spines are required), then + the current stop should be connected to the previous stop + * - If previous stop is not used, while the des_spines are required to + connect, then the current stop should be connected to the previous stop + * - Only when previous stops and des_spines are not used, the current stop + will be NOT connected to the previous stop + * + * des_spine_top[i] + * ^ + * | + * spine_curr_stop ---->+->spine_prev_stop + * | + * v + * des_spine_bottom[i] + + * + *******************************************************************/ +static int rec_expand_and_route_clock_spine( + VprRoutingAnnotation& vpr_routing_annotation, bool& spine_usage, + const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, + const std::map& tree2clk_pin_map, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockSpineId& curr_spine, const ClockTreePinId& curr_pin, + const bool& disable_unused_spines, const bool& verbose) { + int status = CMD_EXEC_SUCCESS; + bool curr_spine_usage = false; + bool curr_tap_usage = false; + /* For last level, we just connect tap points */ + status = route_spine_taps(vpr_routing_annotation, curr_tap_usage, rr_graph, + clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, + clk_ntwk, clk_tree, curr_spine, curr_pin, verbose); + if (CMD_EXEC_SUCCESS != status) { + return CMD_EXEC_FATAL_ERROR; + } + /* If no taps are routed, this spine is not used. Early exit */ + if (disable_unused_spines && !curr_tap_usage && + clk_ntwk.is_last_level(curr_spine)) { + spine_usage = false; + VTR_LOGV(verbose, + "Disable last-level spine '%s' as " + "none of the taps are not used\n", + clk_ntwk.spine_name(curr_spine).c_str()); + return CMD_EXEC_SUCCESS; + } + + std::vector> spine_coords = + clk_ntwk.spine_coordinates(curr_spine); + /* We expand from the the ending point to starting point on the straight line. + * As such, it is easy to turn off spines by any stop. + * The spine should go in a straight line, connect all the stops on the line + */ + bool prev_stop_usage = false; + if (clk_ntwk.is_last_level(curr_spine)) { + curr_spine_usage = curr_tap_usage; + prev_stop_usage = curr_tap_usage; + } + std::reverse(spine_coords.begin(), spine_coords.end()); + for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { + vtr::Point switch_point_coord = spine_coords[icoord]; + bool curr_stop_usage = false; + /* Expand on the switching point here */ + for (ClockSwitchPointId switch_point_id : + clk_ntwk.find_spine_switch_points_with_coord(curr_spine, + switch_point_coord)) { + ClockSpineId des_spine = + clk_ntwk.spine_switch_point_tap(curr_spine, switch_point_id); + /* Go recursively for the destination spine */ + bool curr_branch_usage = false; + status = rec_expand_and_route_clock_spine( + vpr_routing_annotation, curr_branch_usage, rr_graph, clk_rr_lookup, + rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, des_spine, + curr_pin, disable_unused_spines, verbose); + if (CMD_EXEC_SUCCESS != status) { + return CMD_EXEC_FATAL_ERROR; + } + /* Connect only when the destination spine is used */ + if (disable_unused_spines && !curr_branch_usage) { + VTR_LOGV(verbose, + "Disconnect switching from spine '%s' to spine '%s' as " + "downstream is not used\n", + clk_ntwk.spine_name(curr_spine).c_str(), + clk_ntwk.spine_name(des_spine).c_str()); + continue; + } + curr_stop_usage = true; + /* Now connect to next spine, internal drivers may join */ + status = route_clock_spine_switch_point( + vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, + tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, + switch_point_id, verbose); + if (CMD_EXEC_SUCCESS != status) { + return CMD_EXEC_FATAL_ERROR; + } + } + if (curr_stop_usage) { + curr_spine_usage = true; + } + if (disable_unused_spines && !curr_stop_usage && !prev_stop_usage) { + VTR_LOGV(verbose, + "Disconnect backbone of spine '%s' at (x=%lu, y=%lu) as " + "downstream is not used\n", + clk_ntwk.spine_name(curr_spine).c_str(), switch_point_coord.x(), + switch_point_coord.y()); + continue; + } + /* If there are any stop is used, mark this spine is used. This is to avoid + * that a spine is marked unused when only its 1st stop is actually used. + * The skip condition may cause this. */ + /* Skip the first stop */ + if (icoord == spine_coords.size() - 1) { + vtr::Point des_coord = spine_coords[icoord]; + + int use_int_driver = route_spine_intermediate_drivers( + vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, + tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, des_coord, + verbose); + if (use_int_driver > 1) { + return CMD_EXEC_FATAL_ERROR; + } + continue; + } + /* Connect only when next stop is used */ + vtr::Point src_coord = spine_coords[icoord + 1]; + vtr::Point des_coord = spine_coords[icoord]; + VTR_LOGV(verbose, + "(icoord=%lu) Expanding on backbone of spine '%s' from (x=%lu, " + "y=%lu) to (x=%lu, y=%lu)...\n", + icoord, clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), + src_coord.y(), des_coord.x(), des_coord.y()); + Direction src_spine_direction = clk_ntwk.spine_direction(curr_spine); + Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine); + ClockLevelId src_spine_level = clk_ntwk.spine_level(curr_spine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(curr_spine); + RRNodeId src_node = clk_rr_lookup.find_node( + src_coord.x(), src_coord.y(), clk_tree, src_spine_level, curr_pin, + src_spine_direction, verbose); + RRNodeId des_node = clk_rr_lookup.find_node( + des_coord.x(), des_coord.y(), clk_tree, des_spine_level, curr_pin, + des_spine_direction, verbose); + VTR_ASSERT(rr_graph.valid_node(src_node)); + VTR_ASSERT(rr_graph.valid_node(des_node)); + + /* Internal drivers may appear at the intermediate. Check if there are + * any defined and related rr_node found as incoming edges. If the + * global net is mapped to the internal driver, use it as the previous + * node */ + int use_int_driver = route_spine_intermediate_drivers( + vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, + tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, des_coord, + verbose); + if (use_int_driver > 1) { + return CMD_EXEC_FATAL_ERROR; + } + if (use_int_driver == 1) { + continue; /* Used internal driver, early pass. */ + } + + VTR_LOGV(verbose, + "Routed backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, " + "y=%lu)...\n", + clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), + src_coord.y(), des_coord.x(), des_coord.y()); + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); + /* It could happen that there is no net mapped some clock pin, skip the + * net mapping */ + if (tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net(src_node, + tree2clk_pin_map.at(curr_pin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(curr_pin)); + } + + prev_stop_usage = true; + curr_spine_usage = true; + } + /* Update status */ + spine_usage = curr_spine_usage; + + return CMD_EXEC_SUCCESS; +} + /******************************************************************** * Route a clock tree on an existing routing resource graph * The strategy is to route spine one by one @@ -87,99 +572,35 @@ static int build_clock_tree_net_map( static int route_clock_tree_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const bool& disable_unused_trees, const bool& disable_unused_spines, const bool& verbose) { - for (auto ispine : clk_ntwk.spines(clk_tree)) { - VTR_LOGV(verbose, "Routing spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - for (auto ipin : clk_ntwk.pins(clk_tree)) { - /* Route the spine from starting point to ending point */ - std::vector> spine_coords = - clk_ntwk.spine_coordinates(ispine); - VTR_LOGV(verbose, "Routing backbone of spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - for (size_t icoord = 0; icoord < spine_coords.size() - 1; ++icoord) { - vtr::Point src_coord = spine_coords[icoord]; - vtr::Point des_coord = spine_coords[icoord + 1]; - Direction src_spine_direction = clk_ntwk.spine_direction(ispine); - Direction des_spine_direction = clk_ntwk.spine_direction(ispine); - ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); - RRNodeId src_node = - clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); - RRNodeId des_node = - clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); - VTR_ASSERT(rr_graph.valid_node(src_node)); - VTR_ASSERT(rr_graph.valid_node(des_node)); - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); - } - /* Route the spine-to-spine switching points */ - VTR_LOGV(verbose, "Routing switch points of spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - for (ClockSwitchPointId switch_point_id : - clk_ntwk.spine_switch_points(ispine)) { - vtr::Point src_coord = - clk_ntwk.spine_switch_point(ispine, switch_point_id); - ClockSpineId des_spine = - clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); - vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); - Direction src_spine_direction = clk_ntwk.spine_direction(ispine); - Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); - ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); - RRNodeId src_node = - clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); - RRNodeId des_node = - clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); - VTR_ASSERT(rr_graph.valid_node(src_node)); - VTR_ASSERT(rr_graph.valid_node(des_node)); - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); - /* It could happen that there is no net mapped some clock pin, skip the - * net mapping */ - if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { - vpr_routing_annotation.set_rr_node_net(src_node, - tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net(des_node, - tree2clk_pin_map.at(ipin)); - } - } - /* Route the spine-to-IPIN connections (only for the last level) */ - if (clk_ntwk.is_last_level(ispine)) { - VTR_LOGV(verbose, "Routing clock taps of spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - /* Connect to any fan-out node which is IPIN */ - for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { - vtr::Point src_coord = spine_coords[icoord]; - Direction src_spine_direction = clk_ntwk.spine_direction(ispine); - ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); - RRNodeId src_node = - clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); - for (RREdgeId edge : rr_graph.edge_range(src_node)) { - RRNodeId des_node = rr_graph.edge_sink_node(edge); - if (rr_graph.node_type(des_node) == IPIN) { - VTR_ASSERT(rr_graph.valid_node(src_node)); - VTR_ASSERT(rr_graph.valid_node(des_node)); - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); - if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { - vpr_routing_annotation.set_rr_node_net( - src_node, tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net( - des_node, tree2clk_pin_map.at(ipin)); - } - } - } - } + for (auto ipin : clk_ntwk.pins(clk_tree)) { + /* Do not route unused clock spines */ + if (disable_unused_trees && + tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + VTR_LOGV(verbose, "Skip routing unused tree '%s' pin '%lu'...\n", + clk_ntwk.tree_name(clk_tree).c_str(), size_t(ipin)); + continue; + } + /* Start with the top-level spines. Recursively walk through coordinates and + * expand on switch points */ + bool tree_usage = false; + for (auto top_spine : clk_ntwk.tree_top_spines(clk_tree)) { + int status = rec_expand_and_route_clock_spine( + vpr_routing_annotation, tree_usage, rr_graph, clk_rr_lookup, + rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, top_spine, ipin, + disable_unused_spines, verbose); + if (CMD_EXEC_SUCCESS != status) { + return CMD_EXEC_FATAL_ERROR; } } + if (!tree_usage) { + VTR_LOGV(verbose, "Detect unused tree '%s' pin '%lu'...\n", + clk_ntwk.tree_name(clk_tree).c_str(), size_t(ipin)); + } } return CMD_EXEC_SUCCESS; } @@ -190,15 +611,14 @@ static int route_clock_tree_rr_graph( * - configure the routing annotation w.r.t. the clock node connections * - quick check to ensure routing is valid *******************************************************************/ -int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const AtomContext& atom_ctx, - const ClusteredNetlist& cluster_nlist, - const VprNetlistAnnotation& netlist_annotation, - const RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& verbose) { +int route_clock_rr_graph( + VprRoutingAnnotation& vpr_routing_annotation, + const VprClusteringAnnotation& vpr_clustering_annotation, + const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, + const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, + const PinConstraints& pin_constraints, const bool& disable_unused_trees, + const bool& disable_unused_spines, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Route programmable clock network based on routing resource graph"); @@ -210,41 +630,40 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, return CMD_EXEC_SUCCESS; } - /* Report any clock structure we do not support yet! */ - if (clk_ntwk.num_trees() > 1) { - VTR_LOG( - "Currently only support 1 clock tree in programmable clock " - "architecture\nPlease update your clock architecture definition\n"); - return CMD_EXEC_FATAL_ERROR; - } - - /* If there are multiple clock signals from the netlist, require pin + /* If there are multiple global signals from the netlist, require pin * constraints */ - std::vector clock_net_names = - find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); - if (clock_net_names.empty()) { + std::vector gnets = + find_clustered_netlist_global_nets(cluster_nlist); + if (gnets.empty()) { VTR_LOG( - "Skip due to 0 clocks found from netlist\nDouble check your HDL design " + "Skip due to 0 global nets found from netlist\nDouble check your HDL " + "design " "if this is unexpected\n"); return CMD_EXEC_SUCCESS; } - if (clock_net_names.size() > 1 && pin_constraints.empty()) { + if (gnets.size() > 1 && pin_constraints.empty()) { VTR_LOG( - "There is %lu clock nets (more than 1). Require pin constraints to be " + "There is %lu global nets (more than 1). Require pin constraints to be " "specified\n", - clock_net_names.size()); + gnets.size()); return CMD_EXEC_FATAL_ERROR; } + /* Build rr_node-to-net mapping for global nets */ + vtr::vector rr_node_gnets = + annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, + vpr_clustering_annotation, verbose); + /* Route spines one by one */ for (auto itree : clk_ntwk.trees()) { - VTR_LOGV(verbose, "Build clock name to clock tree '%s' pin mapping...\n", + VTR_LOGV(verbose, + "Build global net name to clock tree '%s' pin mapping...\n", clk_ntwk.tree_name(itree).c_str()); std::map tree2clk_pin_map; int status = CMD_EXEC_SUCCESS; status = build_clock_tree_net_map(tree2clk_pin_map, cluster_nlist, pin_constraints, - clock_net_names, clk_ntwk, itree, verbose); + gnets, clk_ntwk, itree, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; } @@ -253,7 +672,8 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, clk_ntwk.tree_name(itree).c_str()); status = route_clock_tree_rr_graph( vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, - tree2clk_pin_map, clk_ntwk, itree, verbose); + rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, disable_unused_trees, + disable_unused_spines, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; } diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index 6a1b2cad4..1c37bc8b6 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -7,8 +7,8 @@ #include "clock_network.h" #include "pin_constraints.h" #include "rr_clock_spatial_lookup.h" +#include "vpr_clustering_annotation.h" #include "vpr_context.h" -#include "vpr_netlist_annotation.h" #include "vpr_routing_annotation.h" /******************************************************************** @@ -18,15 +18,14 @@ /* begin namespace openfpga */ namespace openfpga { -int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const AtomContext& atom_ctx, - const ClusteredNetlist& cluster_nlist, - const VprNetlistAnnotation& netlist_annotation, - const RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& verbose); +int route_clock_rr_graph( + VprRoutingAnnotation& vpr_routing_annotation, + const VprClusteringAnnotation& vpr_clustering_annotation, + const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, + const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, + const PinConstraints& pin_constraints, const bool& disable_unused_trees, + const bool& disable_unused_spines, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/annotation/write_unique_blocks_bin.cpp b/openfpga/src/annotation/write_unique_blocks_bin.cpp new file mode 100644 index 000000000..13dc53cec --- /dev/null +++ b/openfpga/src/annotation/write_unique_blocks_bin.cpp @@ -0,0 +1,119 @@ + +#include + +#include +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" +#include "serdes_utils.h" +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "command_exit_codes.h" +#include "device_rr_gsb_utils.h" +#include "openfpga_digest.h" +#include "read_xml_util.h" +#include "rr_gsb.h" +#include "unique_blocks_uxsdcxx.capnp.h" +#include "write_unique_blocks_bin.h" +#include "write_unique_blocks_xml.h" +#include "write_xml_utils.h" + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- write the unique blocks' information in the associated data structures: + *device_rr_gsb to a bin file + *******************************************************************/ +namespace openfpga { +/* write each unique block (including a single unique block info and its mirror + * instances' info)into capnp builder */ +int write_bin_atom_block(const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + const ucap::Type type, ucap::Block::Builder& root) { + root.setX(unique_block_coord.x()); + root.setY(unique_block_coord.y()); + root.setType(type); + if (instance_map.size() > 0) { + auto instance_list = root.initInstances(instance_map.size()); + for (size_t instance_id = 0; instance_id < instance_map.size(); + instance_id++) { + auto instance = instance_list[instance_id]; + instance.setX(instance_map[instance_id].x()); + instance.setY(instance_map[instance_id].y()); + } + } + return openfpga::CMD_EXEC_SUCCESS; +} + +/* Top-level function to write bin file of unique blocks */ +int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, + bool verbose_output) { + ::capnp::MallocMessageBuilder builder; + auto unique_blocks = builder.initRoot(); + int num_unique_blocks = device_rr_gsb.get_num_sb_unique_module() + + device_rr_gsb.get_num_cb_unique_module(CHANX) + + device_rr_gsb.get_num_cb_unique_module(CHANY); + auto block_list = unique_blocks.initBlocks(num_unique_blocks); + + /*write switch blocks into bin file */ + for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { + const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); + auto unique_block = block_list[id]; + int status_code = write_bin_atom_block(instance_map, unique_block_coord, + ucap::Type::SB, unique_block); + if (status_code != 0) { + VTR_LOG_ERROR("write sb unique blocks into bin file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } + + /*write cbx blocks into bin file */ + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANX); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cbx_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); + int block_id = id + device_rr_gsb.get_num_sb_unique_module(); + auto unique_block = block_list[block_id]; + int status_code = write_bin_atom_block(instance_map, unique_block_coord, + ucap::Type::CBX, unique_block); + if (status_code != 0) { + VTR_LOG_ERROR("write cbx unique blocks into bin file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } + + /*write cby blocks into bin file */ + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANY); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cby_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord); + int block_id = id + device_rr_gsb.get_num_sb_unique_module() + + device_rr_gsb.get_num_cb_unique_module(CHANX); + auto unique_block = block_list[block_id]; + int status_code = write_bin_atom_block(instance_map, unique_block_coord, + ucap::Type::CBY, unique_block); + if (status_code != 0) { + VTR_LOG_ERROR("write cby unique blocks into bin file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } + + writeMessageToFile(fname, &builder); + if (verbose_output) { + report_unique_module_status_write(device_rr_gsb, true); + } + return openfpga::CMD_EXEC_SUCCESS; +} + +} // namespace openfpga diff --git a/openfpga/src/annotation/write_unique_blocks_bin.h b/openfpga/src/annotation/write_unique_blocks_bin.h new file mode 100644 index 000000000..e49fc095e --- /dev/null +++ b/openfpga/src/annotation/write_unique_blocks_bin.h @@ -0,0 +1,33 @@ +#ifndef WRITE_XML_UNIQUE_BLOCKS_BIN_H +#define WRITE_XML_UNIQUE_BLOCKS_BIN_H + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "device_rr_gsb_utils.h" + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- write the unique blocks' information in the associated data structures: + *device_rr_gsb to a bin file + *******************************************************************/ + +namespace openfpga { +int write_bin_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, + bool verbose_output); +int write_bin_atom_block(const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + const ucap::Type type, ucap::Block::Builder& root); +} // namespace openfpga +#endif diff --git a/openfpga/src/annotation/write_unique_blocks_xml.cpp b/openfpga/src/annotation/write_unique_blocks_xml.cpp new file mode 100644 index 000000000..e9950f015 --- /dev/null +++ b/openfpga/src/annotation/write_unique_blocks_xml.cpp @@ -0,0 +1,187 @@ + +#include + +#include +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" +#include "serdes_utils.h" +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "command_exit_codes.h" +#include "device_rr_gsb_utils.h" +#include "openfpga_digest.h" +#include "read_xml_util.h" +#include "rr_gsb.h" +#include "unique_blocks_uxsdcxx.capnp.h" +#include "write_unique_blocks_xml.h" +#include "write_xml_utils.h" + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- write the unique blocks' information in the associated data structures: + *device_rr_gsb to a XML file + *******************************************************************/ +namespace openfpga { + +/*Write unique blocks and their corresponding instances' information from + *device_rr_gsb to a XML file*/ +int write_xml_atom_block(std::fstream& fp, + const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + std::string type) { + if (false == openfpga::valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; + + for (const auto& instance_info : instance_map) { + openfpga::write_tab_to_file(fp, 2); + fp << "" + << "\n"; + } + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; + return openfpga::CMD_EXEC_SUCCESS; +} + +/* Report information about written unique blocks */ +void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, + bool verbose_output) { + /* Report the stats */ + VTR_LOGV( + verbose_output, + "Write %lu unique X-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + device_rr_gsb.get_num_cb_unique_module(CHANX), + find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX), + 100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX) / + (float)device_rr_gsb.get_num_cb_unique_module(CHANX) - + 1.)); + + VTR_LOGV( + verbose_output, + "Write %lu unique Y-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + device_rr_gsb.get_num_cb_unique_module(CHANY), + find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY), + 100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY) / + (float)device_rr_gsb.get_num_cb_unique_module(CHANY) - + 1.)); + + VTR_LOGV(verbose_output, + "Write %lu unique switch blocks from a total of %d (compression " + "rate=%.2f%)\n", + device_rr_gsb.get_num_sb_unique_module(), + find_device_rr_gsb_num_sb_modules(device_rr_gsb, + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_sb_modules( + device_rr_gsb, g_vpr_ctx.device().rr_graph) / + (float)device_rr_gsb.get_num_sb_unique_module() - + 1.)); + + VTR_LOG( + "Write %lu unique general switch blocks from a total of %d " + "(compression " + "rate=%.2f%)\n", + device_rr_gsb.get_num_gsb_unique_module(), + find_device_rr_gsb_num_gsb_modules(device_rr_gsb, + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_gsb_modules( + device_rr_gsb, g_vpr_ctx.device().rr_graph) / + (float)device_rr_gsb.get_num_gsb_unique_module() - + 1.)); +} + +/*Top level function to write the xml file of unique blocks*/ +int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, + bool verbose_output) { + vtr::ScopedStartFinishTimer timer("Write unique blocks..."); + if (device_rr_gsb.is_compressed() == false) { + VTR_LOG_ERROR("unique_blocks are empty!"); + return CMD_EXEC_FATAL_ERROR; + } + /* Create a file handler */ + std::fstream fp; + /* Open the file stream */ + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + /* Write the root node */ + fp << "" + << "\n"; + + for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { + const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); + int status_code = + write_xml_atom_block(fp, instance_map, unique_block_coord, "sb"); + if (status_code != 0) { + VTR_LOG_ERROR("write sb unique blocks into xml file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } + + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANX); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cbx_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); + int status_code = + write_xml_atom_block(fp, instance_map, unique_block_coord, "cbx"); + if (status_code != 0) { + VTR_LOG_ERROR("write cbx unique blocks into xml file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } + + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANY); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cby_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord); + int status_code = + write_xml_atom_block(fp, instance_map, unique_block_coord, "cby"); + if (status_code != 0) { + VTR_LOG_ERROR("write cby unique blocks into xml file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } + + /* Finish writing the root node */ + fp << "" + << "\n"; + + /* Close the file stream */ + fp.close(); + if (verbose_output) { + report_unique_module_status_write(device_rr_gsb, true); + } + + return CMD_EXEC_SUCCESS; +} +} // namespace openfpga diff --git a/openfpga/src/annotation/write_unique_blocks_xml.h b/openfpga/src/annotation/write_unique_blocks_xml.h new file mode 100644 index 000000000..0dafa5f47 --- /dev/null +++ b/openfpga/src/annotation/write_unique_blocks_xml.h @@ -0,0 +1,37 @@ +#ifndef WRITE_XML_UNIQUE_BLOCKS_XML_H +#define WRITE_XML_UNIQUE_BLOCKS_XML_H + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "device_rr_gsb_utils.h" + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- write the unique blocks' information in the associated data structures: + *device_rr_gsb to a XML file + *******************************************************************/ + +namespace openfpga { +int write_xml_atom_block(std::fstream& fp, + const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + std::string type); +void report_unique_module_status_write( + const DeviceRRGSB& device_rr_gsb, + bool verbose_output); /*report status of written info*/ +int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, + bool verbose_output); +} // namespace openfpga +#endif diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp index 89b31d9c6..552ee361a 100644 --- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp +++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp @@ -149,7 +149,7 @@ static void write_rr_gsb_chan_connection_to_xml( } else { for (const RREdgeId& driver_rr_edge : driver_rr_edges) { const RRNodeId& driver_rr_node = rr_graph.edge_src_node(driver_rr_edge); - e_side driver_node_side = NUM_SIDES; + e_side driver_node_side = NUM_2D_SIDES; int driver_node_index = -1; rr_gsb.get_node_side_and_index(rr_graph, driver_rr_node, IN_PORT, driver_node_side, driver_node_index); @@ -166,7 +166,7 @@ static void write_rr_gsb_chan_connection_to_xml( fp << "\" node_id=\"" << size_t(driver_rr_node) << "\" grid_side=\"" << grid_side.to_string() << "\" sb_module_pin_name=\"" << generate_sb_module_grid_port_name( - gsb_side, driver_node_side, vpr_device_grid, + gsb_side, grid_side.get_side(), vpr_device_grid, vpr_device_annotation, rr_graph, driver_rr_node); } fp << "\"/>" << std::endl; diff --git a/openfpga/src/base/openfpga_basic.cpp b/openfpga/src/base/openfpga_basic.cpp index 240caaa6f..6546ff909 100644 --- a/openfpga/src/base/openfpga_basic.cpp +++ b/openfpga/src/base/openfpga_basic.cpp @@ -69,7 +69,19 @@ int call_external_command(const Command& cmd, return CMD_EXEC_FATAL_ERROR; } - return system(cmd_ss.c_str()); + // Refer https://pubs.opengroup.org/onlinepubs/009695399/functions/system.html + // Refer + // https://pubs.opengroup.org/onlinepubs/009695399/functions/waitpid.html + int status = system(cmd_ss.c_str()); + if (WIFEXITED(status)) { + // This is normal program exit, WEXITSTATUS() will help you shift the status + // accordingly (status >> 8) + // Becareful if the final status is 2 or beyond, program will not error + // as it is treated as CMD_EXEC_MINOR_ERROR + return WEXITSTATUS(status); + } + // Program maybe terminated because of various killed or stopped signal + return CMD_EXEC_FATAL_ERROR; } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_bitstream_template.h b/openfpga/src/base/openfpga_bitstream_template.h index 8821c8392..af5bf1ae7 100644 --- a/openfpga/src/base/openfpga_bitstream_template.h +++ b/openfpga/src/base/openfpga_bitstream_template.h @@ -11,10 +11,12 @@ #include "command.h" #include "command_context.h" #include "command_exit_codes.h" +#include "extract_device_non_fabric_bitstream.h" #include "globals.h" #include "openfpga_digest.h" #include "openfpga_naming.h" #include "openfpga_reserved_words.h" +#include "overwrite_bitstream.h" #include "read_xml_arch_bitstream.h" #include "report_bitstream_distribution.h" #include "vtr_log.h" @@ -46,6 +48,10 @@ int fpga_bitstream_template(T& openfpga_ctx, const Command& cmd, g_vpr_ctx, openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); } + overwrite_bitstream(openfpga_ctx.mutable_bitstream_manager(), + openfpga_ctx.bitstream_setting(), + cmd_context.option_enable(cmd, opt_verbose)); + if (true == cmd_context.option_enable(cmd, opt_write_file)) { std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_write_file)); @@ -59,6 +65,9 @@ int fpga_bitstream_template(T& openfpga_ctx, const Command& cmd, !cmd_context.option_enable(cmd, opt_no_time_stamp)); } + extract_device_non_fabric_bitstream( + g_vpr_ctx, openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); + /* TODO: should identify the error code from internal function execution */ return CMD_EXEC_SUCCESS; } diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 63e623398..1c1d23172 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -16,13 +16,19 @@ #include "fabric_key_writer.h" #include "globals.h" #include "openfpga_naming.h" +#include "read_unique_blocks_bin.h" +#include "read_unique_blocks_xml.h" #include "read_xml_fabric_key.h" #include "read_xml_io_name_map.h" #include "read_xml_module_name_map.h" #include "read_xml_tile_config.h" #include "rename_modules.h" +#include "report_reference.h" #include "vtr_log.h" #include "vtr_time.h" +#include "write_unique_blocks_bin.h" +#include "write_unique_blocks_xml.h" +#include "write_xml_fabric_pin_physical_location.h" #include "write_xml_module_name_map.h" /* begin namespace openfpga */ @@ -122,13 +128,6 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, cmd.option_name(opt_duplicate_grid_pin).c_str()); return CMD_EXEC_FATAL_ERROR; } - if (!cmd_context.option_enable(cmd, opt_compress_routing)) { - VTR_LOG_ERROR( - "Option '%s' requires options '%s' to be enabled due to a conflict!\n", - cmd.option_name(opt_group_tile).c_str(), - cmd.option_name(opt_compress_routing).c_str()); - return CMD_EXEC_FATAL_ERROR; - } } /* Conflicts: duplicate_grid_pin does not support any port merge */ if (cmd_context.option_enable(cmd, opt_duplicate_grid_pin)) { @@ -141,13 +140,24 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, } } - if (true == cmd_context.option_enable(cmd, opt_compress_routing)) { + if (true == cmd_context.option_enable(cmd, opt_compress_routing) && + false == openfpga_ctx.device_rr_gsb().is_compressed()) { compress_routing_hierarchy_template( openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); /* Update flow manager to enable compress routing */ openfpga_ctx.mutable_flow_manager().set_compress_routing(true); + } else if (true == openfpga_ctx.device_rr_gsb().is_compressed()) { + openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } + if (cmd_context.option_enable(cmd, opt_group_tile)) { + if (!openfpga_ctx.device_rr_gsb().is_compressed()) { + VTR_LOG_ERROR( + "Option '%s' requires unique blocks to be valid due to a conflict!\n", + cmd.option_name(opt_group_tile).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + } VTR_LOG("\n"); /* Record the execution status in curr_status for each command @@ -173,7 +183,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, */ TileConfig tile_config; if (cmd_context.option_enable(cmd, opt_group_tile)) { - if (!cmd_context.option_enable(cmd, opt_compress_routing)) { + if (!openfpga_ctx.device_rr_gsb().is_compressed()) { VTR_LOG_ERROR( "Group tile is applicable only when compress routing is enabled!\n"); return CMD_EXEC_FATAL_ERROR; @@ -191,7 +201,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, openfpga_ctx.mutable_fabric_tile(), openfpga_ctx.mutable_module_name_map(), const_cast(openfpga_ctx), g_vpr_ctx.device(), cmd_context.option_enable(cmd, opt_frame_view), - cmd_context.option_enable(cmd, opt_compress_routing), + openfpga_ctx.device_rr_gsb().is_compressed(), cmd_context.option_enable(cmd, opt_duplicate_grid_pin), predefined_fabric_key, tile_config, cmd_context.option_enable(cmd, opt_group_config_block), @@ -269,6 +279,8 @@ template int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_exclude_empty_modules = + cmd.option("exclude_empty_modules"); /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check @@ -278,6 +290,19 @@ int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd, VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + CommandOptionId opt_module = cmd.option("module"); + std::string root_module = + openfpga_ctx.module_name_map().name(generate_fpga_top_module_name()); + if (true == cmd_context.option_enable(cmd, opt_module)) { + root_module = cmd_context.option_value(cmd, opt_module); + } + + CommandOptionId opt_filter = cmd.option("filter"); + std::string filter("*"); + if (true == cmd_context.option_enable(cmd, opt_filter)) { + filter = cmd_context.option_value(cmd, opt_filter); + } + /* Default depth requirement, will not stop until the leaf */ int depth = -1; CommandOptionId opt_depth = cmd.option("depth"); @@ -296,7 +321,9 @@ int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd, /* Write hierarchy to a file */ return write_fabric_hierarchy_to_text_file( openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), hie_file_name, - size_t(depth), cmd_context.option_enable(cmd, opt_verbose)); + root_module, filter, size_t(depth), + cmd_context.option_enable(cmd, opt_exclude_empty_modules), + cmd_context.option_enable(cmd, opt_verbose)); } /******************************************************************** @@ -419,6 +446,131 @@ int write_module_naming_rules_template(const T& openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); } +/******************************************************************** + * Write fabric pin physical location to a file + *******************************************************************/ +template +int write_fabric_pin_physical_location_template( + const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); + CommandOptionId opt_show_invalid_side = cmd.option("show_invalid_side"); + + /* Check the option '--file' is enabled or not + * Actually, it must be enabled as the shell interface will check + * before reaching this fuction + */ + CommandOptionId opt_file = cmd.option("file"); + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + + std::string file_name = cmd_context.option_value(cmd, opt_file); + + std::string module_name("*"); /* Use a wildcard for everything */ + CommandOptionId opt_module = cmd.option("module"); + if (true == cmd_context.option_enable(cmd, opt_module)) { + module_name = cmd_context.option_value(cmd, opt_module); + } + + /* Write hierarchy to a file */ + return write_xml_fabric_pin_physical_location( + file_name.c_str(), module_name, openfpga_ctx.module_graph(), + cmd_context.option_enable(cmd, opt_show_invalid_side), + !cmd_context.option_enable(cmd, opt_no_time_stamp), + cmd_context.option_enable(cmd, opt_verbose)); +} + +template +int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_file = cmd.option("file"); + CommandOptionId opt_type = cmd.option("type"); + + /* Check the option '--file' is enabled or not + * Actually, it must be enabled as the shell interface will check + * before reaching this fuction + */ + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + + std::string file_name = cmd_context.option_value(cmd, opt_file); + std::string file_type = cmd_context.option_value(cmd, opt_type); + /* read unique blocks from a file */ + if (file_type == "xml") { + return read_xml_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(), + file_name.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); + } else if (file_type == "bin") { + return read_bin_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(), + file_name.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); + } else { + VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); + return CMD_EXEC_FATAL_ERROR; + } +} + +template +int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_file = cmd.option("file"); + CommandOptionId opt_type = cmd.option("type"); + + /* Check the option '--file' is enabled or not + * Actually, it must be enabled as the shell interface will check + * before reaching this fuction + */ + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + + std::string file_name = cmd_context.option_value(cmd, opt_file); + std::string file_type = cmd_context.option_value(cmd, opt_type); + /* Write unique blocks to a file */ + /* add check flag */ + if (file_type == "xml") { + return write_xml_unique_blocks(openfpga_ctx.device_rr_gsb(), + file_name.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); + } else if (file_type == "bin") { + return write_bin_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(), + file_name.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); + } else { + VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); + return CMD_EXEC_FATAL_ERROR; + } +} + +/******************************************************************** + * Report reference to a file + *******************************************************************/ +template +int report_reference_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); + + CommandOptionId opt_file = cmd.option("file"); + + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + std::string file_name = cmd_context.option_value(cmd, opt_file); + + std::string module_name("*"); /* Use a wildcard for everything */ + CommandOptionId opt_module = cmd.option("module"); + if (true == cmd_context.option_enable(cmd, opt_module)) { + module_name = cmd_context.option_value(cmd, opt_module); + } + /* Write hierarchy to a file */ + return report_reference(file_name.c_str(), module_name, + openfpga_ctx.module_graph(), + !cmd_context.option_enable(cmd, opt_no_time_stamp), + cmd_context.option_enable(cmd, opt_verbose)); +} + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index dc2e04ac4..eb289c471 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -86,8 +86,10 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd, openfpga_ctx.mutable_vpr_routing_annotation().init( g_vpr_ctx.device().rr_graph); + // Incase the incoming edges are not built. This may happen when loading + // rr_graph from an external file + g_vpr_ctx.mutable_device().rr_graph_builder.build_in_edges(); annotate_vpr_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), - g_vpr_ctx.routing(), openfpga_ctx.mutable_vpr_routing_annotation(), cmd_context.option_enable(cmd, opt_verbose)); @@ -105,7 +107,6 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd, } /* Build incoming edges as VPR only builds fan-out edges for each node */ - g_vpr_ctx.mutable_device().rr_graph_builder.build_in_edges(); VTR_LOG("Built %ld incoming edges for routing resource graph\n", g_vpr_ctx.device().rr_graph.in_edges_count()); VTR_ASSERT(g_vpr_ctx.device().rr_graph.validate_in_edges()); @@ -217,6 +218,9 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, /* add an option '--pin_constraints_file in short '-pcf' */ CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); + CommandOptionId opt_disable_unused_trees = cmd.option("disable_unused_trees"); + CommandOptionId opt_disable_unused_spines = + cmd.option("disable_unused_spines"); CommandOptionId opt_verbose = cmd.option("verbose"); /* If pin constraints are enabled by command options, read the file */ @@ -227,10 +231,12 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, } return route_clock_rr_graph( - openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), - g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, - openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.clock_rr_lookup(), - openfpga_ctx.clock_arch(), pin_constraints, + openfpga_ctx.mutable_vpr_routing_annotation(), + openfpga_ctx.vpr_clustering_annotation(), g_vpr_ctx.device(), + g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), + openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, + cmd_context.option_enable(cmd, opt_disable_unused_trees), + cmd_context.option_enable(cmd, opt_disable_unused_spines), cmd_context.option_enable(cmd, opt_verbose)); } diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index b80c3ba36..9fb186674 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -413,6 +413,35 @@ std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, return port_name; } +/********************************************************************* + * Get the physical side for a routing track in a Connection Block module + * Upper_location: specify if an upper/lower prefix to be added. + * The location indicates where the bus port should be + * placed on the perimeter of the connection block + * - For X-directional CB: + * - upper is the left side + * - lower is the right side + * - For Y-directional CB: + * - upper is the bottom side + * - lower is the top side + *********************************************************************/ +e_side get_cb_module_track_port_side(const t_rr_type& chan_type, + const bool& upper_location) { + /* Channel must be either CHANX or CHANY */ + VTR_ASSERT((CHANX == chan_type) || (CHANY == chan_type)); + + /* Create a map between chan_type and module_prefix */ + std::map> port_side_map; + /* TODO: use a constexpr string to replace the fixed name? */ + /* IMPORTANT: This part must be consistent with the mapping in the + * generate_cb_module_track_port_name() !!! */ + port_side_map[CHANX][true] = LEFT; + port_side_map[CHANX][false] = RIGHT; + port_side_map[CHANY][true] = BOTTOM; + port_side_map[CHANY][false] = TOP; + return port_side_map[chan_type][upper_location]; +} + /********************************************************************* * Generate the port name for a routing track in a Connection Block module * This function is created to ease the PnR for each unique routing module @@ -1062,7 +1091,7 @@ std::string generate_grid_block_prefix(const std::string& prefix, const e_side& io_side) { std::string block_prefix(prefix); - if (NUM_SIDES != io_side) { + if (NUM_2D_SIDES != io_side) { SideManager side_manager(io_side); block_prefix += std::string(side_manager.to_string()); block_prefix += std::string("_"); @@ -1081,7 +1110,7 @@ std::string generate_grid_block_netlist_name(const std::string& block_name, /* Add the name of physical block */ std::string module_name(block_name); - if ((true == is_block_io) && (NUM_SIDES != io_side)) { + if ((true == is_block_io) && (NUM_2D_SIDES != io_side)) { SideManager side_manager(io_side); module_name += std::string("_"); module_name += std::string(side_manager.to_string()); @@ -1356,7 +1385,7 @@ std::string generate_physical_block_instance_name(t_pb_type* pb_type, * This function try to infer if a grid locates at the border of a * FPGA fabric, i.e., TOP/RIGHT/BOTTOM/LEFT sides * 1. if this grid is on the border, it will return the side it locates, - * 2. if this grid is in the center, it will return an valid value NUM_SIDES + * 2. if this grid is in the center, it will return an valid value NUM_2D_SIDES * * In this function, we assume that the corner grids are actually empty! * @@ -1383,7 +1412,7 @@ std::string generate_physical_block_instance_name(t_pb_type* pb_type, *******************************************************************/ e_side find_grid_border_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate) { - e_side grid_side = NUM_SIDES; + e_side grid_side = NUM_2D_SIDES; if (device_size.y() - 1 == grid_coordinate.y()) { return TOP; diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h index 378a2836a..bbad6e510 100644 --- a/openfpga/src/base/openfpga_naming.h +++ b/openfpga/src/base/openfpga_naming.h @@ -97,6 +97,9 @@ std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, const e_side& module_side, const PORTS& port_direction); +e_side get_cb_module_track_port_side(const t_rr_type& chan_type, + const bool& upper_location); + std::string generate_cb_module_track_port_name(const t_rr_type& chan_type, const PORTS& port_direction, const bool& upper_location); diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index e17a22183..53fb390cc 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -23,6 +23,106 @@ /* begin namespace openfpga */ namespace openfpga { +/******************************************************************** + * For global net which was remapped during routing, no tracking can be found. + *Packer only keeps an out-of-date record on its pin mapping. Router does not + *assign it to a new pin. So we have to restore the pin mapping. The strategy is + *to find the first unused pin in the same port as it was mapped by the packer. + *******************************************************************/ +static int update_cluster_pin_global_net_with_post_routing_results( + const ClusteringContext& clustering_ctx, + VprClusteringAnnotation& clustering_annotation, const ClusterBlockId& blk_id, + t_logical_block_type_ptr logical_block, const bool& map_gnet2msb, + size_t& num_fixup, const bool& verbose) { + /* Reassign global nets to unused pins in the same port where they were mapped + * NO optimization is done here!!! First find first fit + */ + for (int pb_type_pin = 0; pb_type_pin < logical_block->pb_type->num_pins; + ++pb_type_pin) { + const t_pb_graph_pin* pb_graph_pin = + get_pb_graph_node_pin_from_block_pin(blk_id, pb_type_pin); + + /* Limitation: bypass output pins now + * TODO: This is due to the 'instance' equivalence port + * where outputs may be swapped. This definitely requires re-run of packing + * It can not be solved by swapping routing traces now + */ + if (OUT_PORT == pb_graph_pin->port->type) { + continue; + } + + /* Sanity check to ensure the pb_graph_pin is the top-level */ + VTR_ASSERT(pb_graph_pin->parent_node->is_root()); + + /* Focus on global net only */ + ClusterNetId global_net_id = + clustering_ctx.clb_nlist.block_net(blk_id, pb_type_pin); + if (!clustering_ctx.clb_nlist.valid_net_id(global_net_id)) { + continue; + } + if ((clustering_ctx.clb_nlist.valid_net_id(global_net_id)) && + (!clustering_ctx.clb_nlist.net_is_ignored(global_net_id))) { + continue; + } + /* Skip this pin: it is consistent in pre- and post- routing results */ + if (!clustering_annotation.is_net_renamed(blk_id, pb_type_pin)) { + continue; + } + /* This net has been remapped, find the first unused pin in the same port + * Get the offset of the pin index in the port, based on which we can infer + * the pin index in the context of logical block + */ + VTR_LOG( + "Searching for a candidate pin to accomodate global net '%s' was lost " + "during routing optimization\n", + clustering_ctx.clb_nlist.net_name(global_net_id).c_str()); + size_t cand_pin_start = pb_type_pin - pb_graph_pin->pin_number; + std::vector cand_pins(pb_graph_pin->port->num_pins); + std::iota(cand_pins.begin(), cand_pins.end(), cand_pin_start); + if (map_gnet2msb) { + std::reverse(cand_pins.begin(), cand_pins.end()); + } + bool found_cand = false; + for (size_t cand_pin : cand_pins) { + ClusterNetId cand_pin_net_id = + clustering_ctx.clb_nlist.block_net(blk_id, cand_pin); + const t_pb_graph_pin* cand_pb_graph_pin = + get_pb_graph_node_pin_from_block_pin(blk_id, cand_pin); + if (clustering_annotation.is_net_renamed(blk_id, cand_pin)) { + cand_pin_net_id = clustering_annotation.net(blk_id, cand_pin); + } + if (clustering_ctx.clb_nlist.valid_net_id(cand_pin_net_id)) { + VTR_LOG("Candidate pin '%s' is already mapped to net '%s'\n", + cand_pb_graph_pin->to_string().c_str(), + clustering_ctx.clb_nlist.net_name(cand_pin_net_id).c_str()); + continue; + } + /* Add to net modification */ + clustering_annotation.rename_net(blk_id, cand_pin, global_net_id); + VTR_LOGV(verbose, + "Remap clustered block '%s' global net '%s' to pin '%s'\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, + clustering_ctx.clb_nlist.net_name(global_net_id).c_str(), + cand_pb_graph_pin->to_string().c_str()); + found_cand = true; + break; + } + /* Error out if no candidates are found */ + if (!found_cand) { + VTR_LOG_ERROR( + "Failed to find any unused pin in the same port to remap clustered " + "block '%s' global net '%s' (was mapped to pin '%s').\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, + clustering_ctx.clb_nlist.net_name(global_net_id).c_str(), + pb_graph_pin->to_string().c_str()); + return CMD_EXEC_FATAL_ERROR; + } + /* Update fixup counter */ + num_fixup++; + } + return CMD_EXEC_SUCCESS; +} + /******************************************************************** * Fix up the pb pin mapping results for a given clustered block * 1. For each input/output pin of a clustered pb, @@ -30,13 +130,20 @@ namespace openfpga { * - find the net id for the node in routing context * - find the net id for the node in clustering context * - if the net id does not match, we update the clustering context + * TODO: For global net which was remapped during routing, no tracking can be + *found. Packer only keeps an out-of-date record on its pin mapping. Router does + *not assign it to a new pin. So we have to restore the pin mapping. The + *strategy is to find the first unused pin in the same port as it was mapped by + *the packer. *******************************************************************/ -static void update_cluster_pin_with_post_routing_results( +static int update_cluster_pin_with_post_routing_results( const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const VprRoutingAnnotation& vpr_routing_annotation, VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer, const vtr::Point& grid_coord, const ClusterBlockId& blk_id, - const e_side& border_side, const size_t& z, const bool& verbose) { + const e_side& border_side, const size_t& z, const bool& perimeter_cb, + const bool& map_gnet2msb, size_t& num_fixup, const bool& verbose) { + int status = CMD_EXEC_SUCCESS; /* Handle each pin */ auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id); auto physical_tile = device_ctx.grid.get_physical_type( @@ -47,8 +154,8 @@ static void update_cluster_pin_with_post_routing_results( * here z offset is the location in the multiple-logic-tile tile Get * physical pin does not consider THIS!!!! */ - int physical_pin = z * logical_block->pb_type->num_pins + - get_physical_pin(physical_tile, logical_block, j); + int physical_pin = + get_physical_pin_at_sub_tile_location(physical_tile, logical_block, z, j); auto pin_class = physical_tile->pin_class[physical_pin]; auto class_inf = physical_tile->class_inf[pin_class]; @@ -59,8 +166,8 @@ static void update_cluster_pin_with_post_routing_results( VTR_ASSERT(class_inf.type == RECEIVER); rr_node_type = IPIN; } - std::vector pin_sides = - find_physical_tile_pin_side(physical_tile, physical_pin, border_side); + std::vector pin_sides = find_physical_tile_pin_side( + physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb); /* As some grid has height/width offset, we may not have the pin on any side */ if (0 == pin_sides.size()) { @@ -72,15 +179,70 @@ static void update_cluster_pin_with_post_routing_results( * but the expected side (only used side) will be opposite side of the * border side! */ - e_side pin_side = NUM_SIDES; - if (NUM_SIDES == border_side) { - VTR_ASSERT(1 == pin_sides.size()); + e_side pin_side = NUM_2D_SIDES; + if (NUM_2D_SIDES == border_side) { + if (1 != pin_sides.size()) { + VTR_LOG_ERROR( + "For tile '%s', found pin '%s' on %lu sides. Expect only 1. " + "Following info is for debugging:\n", + physical_tile->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin) + ->to_string() + .c_str(), + pin_sides.size()); + for (e_side curr_side : pin_sides) { + VTR_LOG_ERROR("\t%s\n", SideManager(curr_side).c_str()); + } + return CMD_EXEC_FATAL_ERROR; + } + pin_side = pin_sides[0]; + } else if (perimeter_cb) { + /* When perimeter connection blcoks are allowed, I/O pins may occur on any + * side but the border side */ + if (pin_sides.end() != + std::find(pin_sides.begin(), pin_sides.end(), border_side)) { + VTR_LOG_ERROR( + "For tile '%s', found pin '%s' on the boundary side '%s', which is " + "not physically possible.\n", + physical_tile->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin) + ->to_string() + .c_str(), + SideManager(border_side).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + if (1 != pin_sides.size()) { + VTR_LOG_ERROR( + "For tile '%s', found pin '%s' on %lu sides. Expect only 1. " + "Following info is for debugging:\n", + physical_tile->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin) + ->to_string() + .c_str(), + pin_sides.size()); + for (e_side curr_side : pin_sides) { + VTR_LOG_ERROR("\t%s\n", SideManager(curr_side).c_str()); + } + return CMD_EXEC_FATAL_ERROR; + } pin_side = pin_sides[0]; } else { SideManager side_manager(border_side); - VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(), - pin_sides.end(), - side_manager.get_opposite())); + if (pin_sides.end() == std::find(pin_sides.begin(), pin_sides.end(), + side_manager.get_opposite())) { + VTR_LOG_ERROR( + "For boundary tile '%s', expect pin '%s' only on the side '%s' but " + "found on the following sides:\n", + physical_tile->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin) + ->to_string() + .c_str(), + SideManager(side_manager.get_opposite()).c_str()); + for (e_side curr_side : pin_sides) { + VTR_LOG_ERROR("\t%s\n", SideManager(curr_side).c_str()); + } + return CMD_EXEC_FATAL_ERROR; + } pin_side = side_manager.get_opposite(); } @@ -113,44 +275,41 @@ static void update_cluster_pin_with_post_routing_results( if ((ClusterNetId::INVALID() != cluster_net_id) && (ClusterNetId::INVALID() == routing_net_id) && (true == clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id))) { - VTR_LOGV( - verbose, - "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as " - "it is not routed\n", - clustering_ctx.clb_nlist.block_pb(blk_id)->name, grid_coord.x(), - grid_coord.y(), - clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, - get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, - get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number); + VTR_LOGV(verbose, + "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s' as " + "it is not routed\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, grid_coord.x(), + grid_coord.y(), + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin) + ->to_string() + .c_str()); continue; } /* Ignore used in local cluster only, reserved one CLB pin */ if ((ClusterNetId::INVALID() != cluster_net_id) && (0 == clustering_ctx.clb_nlist.net_sinks(cluster_net_id).size())) { - VTR_LOGV( - verbose, - "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as " - "it is a local net inside the cluster\n", - clustering_ctx.clb_nlist.block_pb(blk_id)->name, grid_coord.x(), - grid_coord.y(), - clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, - get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, - get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number); + VTR_LOGV(verbose, + "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s' as " + "it is a local net inside the cluster\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, grid_coord.x(), + grid_coord.y(), + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin) + ->to_string() + .c_str()); continue; } /* If matched, we finish here */ if (routing_net_id == cluster_net_id) { - VTR_LOGV( - verbose, - "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as " - "it matches cluster routing\n", - clustering_ctx.clb_nlist.block_pb(blk_id)->name, grid_coord.x(), - grid_coord.y(), - clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, - get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, - get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number); + VTR_LOGV(verbose, + "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s' as " + "it matches cluster routing\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, grid_coord.x(), + grid_coord.y(), + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin) + ->to_string() + .c_str()); continue; } @@ -167,28 +326,40 @@ static void update_cluster_pin_with_post_routing_results( cluster_net_name = clustering_ctx.clb_nlist.net_name(cluster_net_id); } - VTR_LOGV( - verbose, - "Fixed up net '%s' mapping mismatch at clustered block '%s' pin " - "'grid[%ld][%ld].%s.%s[%d]' (was net '%s')\n", - routing_net_name.c_str(), clustering_ctx.clb_nlist.block_pb(blk_id)->name, - grid_coord.x(), grid_coord.y(), - clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, - get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, - get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number, - cluster_net_name.c_str()); + VTR_LOGV(verbose, + "Fixed up net '%s' mapping mismatch at clustered block '%s' pin " + "'grid[%ld][%ld].%s' (was net '%s')\n", + routing_net_name.c_str(), + clustering_ctx.clb_nlist.block_pb(blk_id)->name, grid_coord.x(), + grid_coord.y(), + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin) + ->to_string() + .c_str(), + cluster_net_name.c_str()); + num_fixup++; } + /* 2nd round of fixup: focus on global nets */ + status = update_cluster_pin_global_net_with_post_routing_results( + clustering_ctx, vpr_clustering_annotation, blk_id, logical_block, + map_gnet2msb, num_fixup, verbose); + return status; } /******************************************************************** * Main function to fix up the pb pin mapping results * This function will walk through each grid *******************************************************************/ -void update_pb_pin_with_post_routing_results( +int update_pb_pin_with_post_routing_results( const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const PlacementContext& placement_ctx, const VprRoutingAnnotation& vpr_routing_annotation, - VprClusteringAnnotation& vpr_clustering_annotation, const bool& verbose) { + VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb, + const bool& map_gnet2msb, const bool& verbose) { + int status = CMD_EXEC_SUCCESS; + size_t num_fixup = 0; + /* Confirm options */ + VTR_LOGV(verbose && map_gnet2msb, + "User choose to map global net to the best fit MSB of input port\n"); /* Ensure a clean start: remove all the remapping results from VTR's * post-routing clustering result sync-up */ vpr_clustering_annotation.clear_net_remapping(); @@ -206,7 +377,7 @@ void update_pb_pin_with_post_routing_results( /* Get the mapped blocks to this grid */ for (int isubtile = 0; isubtile < phy_tile->capacity; ++isubtile) { ClusterBlockId cluster_blk_id = - placement_ctx.grid_blocks.block_at_location( + placement_ctx.grid_blocks().block_at_location( {(int)x, (int)y, (int)isubtile, (int)layer}); /* Skip invalid ids */ if (ClusterBlockId::INVALID() == cluster_blk_id) { @@ -215,11 +386,14 @@ void update_pb_pin_with_post_routing_results( /* We know the entrance to grid info and mapping results, do the fix-up * for this block */ vtr::Point grid_coord(x, y); - update_cluster_pin_with_post_routing_results( + status = update_cluster_pin_with_post_routing_results( device_ctx, clustering_ctx, vpr_routing_annotation, vpr_clustering_annotation, layer, grid_coord, cluster_blk_id, - NUM_SIDES, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, - verbose); + NUM_2D_SIDES, placement_ctx.block_locs()[cluster_blk_id].loc.sub_tile, + perimeter_cb, map_gnet2msb, num_fixup, verbose); + if (status != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } } } } @@ -240,20 +414,26 @@ void update_pb_pin_with_post_routing_results( /* Get the mapped blocks to this grid */ for (int isubtile = 0; isubtile < phy_tile_type->capacity; ++isubtile) { ClusterBlockId cluster_blk_id = - placement_ctx.grid_blocks.block_at_location( + placement_ctx.grid_blocks().block_at_location( {(int)io_coord.x(), (int)io_coord.y(), (int)isubtile, (int)layer}); /* Skip invalid ids */ if (ClusterBlockId::INVALID() == cluster_blk_id) { continue; } /* Update on I/O grid */ - update_cluster_pin_with_post_routing_results( + status = update_cluster_pin_with_post_routing_results( device_ctx, clustering_ctx, vpr_routing_annotation, vpr_clustering_annotation, layer, io_coord, cluster_blk_id, io_side, - placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, verbose); + placement_ctx.block_locs()[cluster_blk_id].loc.sub_tile, perimeter_cb, + map_gnet2msb, num_fixup, verbose); + if (status != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } } } } + VTR_LOG("In total %lu fixup have been applied\n", num_fixup); + return status; } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.h b/openfpga/src/base/openfpga_pb_pin_fixup.h index 6afaa43d1..1d7faa83b 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.h +++ b/openfpga/src/base/openfpga_pb_pin_fixup.h @@ -14,11 +14,12 @@ /* begin namespace openfpga */ namespace openfpga { -void update_pb_pin_with_post_routing_results( +int update_pb_pin_with_post_routing_results( const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const PlacementContext& placement_ctx, const VprRoutingAnnotation& vpr_routing_annotation, - VprClusteringAnnotation& vpr_clustering_annotation, const bool& verbose); + VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb, + const bool& map_gnet2msb, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_pb_pin_fixup_template.h b/openfpga/src/base/openfpga_pb_pin_fixup_template.h index e28c99467..beb402572 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup_template.h +++ b/openfpga/src/base/openfpga_pb_pin_fixup_template.h @@ -35,17 +35,17 @@ int pb_pin_fixup_template(T& openfpga_context, const Command& cmd, vtr::ScopedStartFinishTimer timer( "Fix up pb pin mapping results after routing optimization"); + CommandOptionId opt_map_gnet2msb = cmd.option("map_global_net_to_msb"); CommandOptionId opt_verbose = cmd.option("verbose"); /* Apply fix-up to each grid */ - update_pb_pin_with_post_routing_results( + return update_pb_pin_with_post_routing_results( g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.placement(), openfpga_context.vpr_routing_annotation(), openfpga_context.mutable_vpr_clustering_annotation(), + g_vpr_ctx.device().arch->perimeter_cb, + cmd_context.option_enable(cmd, opt_map_gnet2msb), cmd_context.option_enable(cmd, opt_verbose)); - - /* TODO: should identify the error code from internal function execution */ - return CMD_EXEC_SUCCESS; } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_read_arch_template.h b/openfpga/src/base/openfpga_read_arch_template.h index 829499c45..346deae5f 100644 --- a/openfpga/src/base/openfpga_read_arch_template.h +++ b/openfpga/src/base/openfpga_read_arch_template.h @@ -236,9 +236,23 @@ int read_openfpga_clock_arch_template(T& openfpga_context, const Command& cmd, openfpga_context.mutable_clock_arch() = read_xml_clock_network(arch_file_name.c_str()); /* Build internal links */ - openfpga_context.mutable_clock_arch().link(); - link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(), - g_vpr_ctx.device().rr_graph); + if (!openfpga_context.mutable_clock_arch().link()) { + VTR_LOG_ERROR("Link clock network failed!"); + return CMD_EXEC_FATAL_ERROR; + } + if (CMD_EXEC_SUCCESS != + link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(), + g_vpr_ctx.device().rr_graph)) { + VTR_LOG_ERROR("Link clock network to routing architecture failed!"); + return CMD_EXEC_FATAL_ERROR; + } + if (CMD_EXEC_SUCCESS != check_clock_network_tile_annotation( + openfpga_context.clock_arch(), + openfpga_context.arch().tile_annotations)) { + VTR_LOG_ERROR( + "Check clock network consistency with tile annotation failed!"); + return CMD_EXEC_FATAL_ERROR; + } /* Ensure clean data */ openfpga_context.clock_arch().validate(); if (!openfpga_context.clock_arch().is_valid()) { diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 96d8e3e3b..3c8c41f77 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -324,6 +324,13 @@ ShellCommandId add_pb_pin_fixup_command_template( const std::vector& dependent_cmds, const bool& hidden) { Command shell_cmd("pb_pin_fixup"); + /* Add an option '--map_global_net_to_msb' */ + shell_cmd.add_option( + "map_global_net_to_msb", false, + "If specified, any global net including clock, reset etc, will be mapped " + "to a best-fit Most Significant Bit (MSB) of input ports of programmable " + "blocks. If not specified, a best-fit Least Significant Bit (LSB) will be " + "the default choice"); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); @@ -461,12 +468,29 @@ ShellCommandId add_write_fabric_hierarchy_command_template( shell_cmd.set_option_short_name(opt_file, "f"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + /* Add an option '--module' */ + CommandOptionId opt_module = shell_cmd.add_option( + "module", false, + "Specify the root module name(s) which should be considered. By default, " + "it is fpga_top. Regular expression is supported"); + shell_cmd.set_option_require_value(opt_module, openfpga::OPT_STRING); + CommandOptionId opt_filter = + shell_cmd.add_option("filter", false, + "Specify the filter which allows user to select " + "modules to appear under each root module tree. By " + "default, it is *. Regular expression is supported"); + shell_cmd.set_option_require_value(opt_filter, openfpga::OPT_STRING); + /* Add an option '--depth' */ CommandOptionId opt_depth = shell_cmd.add_option( "depth", false, "Specify the depth of hierarchy to which the writer should stop"); shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_INT); + shell_cmd.add_option("exclude_empty_modules", false, + "Exclude modules with no qualified children (match the " + "names defined through filter) from the output file"); + /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); @@ -693,6 +717,12 @@ ShellCommandId add_route_clock_rr_graph_command_template( shell_cmd.set_option_short_name(opt_file, "pcf"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + shell_cmd.add_option("disable_unused_trees", false, + "Disable entire clock trees when they are not used by " + "any clock nets. Useful to reduce clock power"); + shell_cmd.add_option("disable_unused_spines", false, + "Disable part of the clock tree which are used by clock " + "nets. Useful to reduce clock power"); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); @@ -858,6 +888,177 @@ ShellCommandId add_write_module_naming_rules_command_template( return shell_cmd_id; } +/******************************************************************** + * - Add a command to Shell environment: write_pin_physical_location + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_fabric_pin_physical_location_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_fabric_pin_physical_location"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, + "file path to the XML file that contains pin physical location"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--module'*/ + CommandOptionId opt_module = shell_cmd.add_option( + "module", false, + "specify the module whose pin physical location should be outputted"); + shell_cmd.set_option_require_value(opt_module, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + shell_cmd.add_option( + "show_invalid_side", false, + "Include pins with invalid sides in output files. Recommended for " + "debugging as the output file may include a lot of useless information"); + + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, + "Output the pin physical location of an FPGA fabric to a given file", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function( + shell_cmd_id, write_fabric_pin_physical_location_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: read_unique_blocks + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_read_unique_blocks_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("read_unique_blocks"); + + /* Add an option '--file' */ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "specify the file which contains unique block information"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--type' */ + CommandOptionId opt_type = + shell_cmd.add_option("type", true, + "Specify the type of the unique blocks file " + "[xml|bin]. If not specified, by default it is XML."); + shell_cmd.set_option_require_value(opt_type, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'compact_routing_hierarchy' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, "Preload unique blocks from xml file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + read_unique_blocks_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_unique_blocks + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_unique_blocks_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_unique_blocks"); + + /* Add an option '--file' */ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, + "specify the file which we will write unique block information to"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--type' */ + CommandOptionId opt_type = + shell_cmd.add_option("type", true, + "Specify the type of the unique blocks file " + "[xml|bin]. If not specified, by default it is XML."); + shell_cmd.set_option_require_value(opt_type, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'compact_routing_hierarchy' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, "Write unique blocks to a xml file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_unique_blocks_template); + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/****************************************************************** + * - Add a command to Shell environment: report_reference + * - Add associated options + * - Add command dependency + ******************************************************************/ +template +ShellCommandId add_report_reference_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("report_reference"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = + shell_cmd.add_option("file", true, "specify the file to output results"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--module'*/ + CommandOptionId opt_module = + shell_cmd.add_option("module", false, + "specify the module under which the references of " + "child modules will be reported"); + shell_cmd.set_option_require_value(opt_module, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "do not print time stamp in output files"); + + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, + "report all instances of each unique module, " + "under a given module", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function(shell_cmd_id, + report_reference_template); + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + template void add_setup_command_templates(openfpga::Shell& shell, const bool& hidden = false) { @@ -1098,8 +1299,44 @@ void add_setup_command_templates(openfpga::Shell& shell, add_write_module_naming_rules_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_write_module_naming_rules, hidden); -} + /******************************** + * Command 'write_fabric_pin_physical_location' + */ + /* The command should NOT be executed before 'build_fabric' */ + std::vector cmd_dependency_write_fabric_pin_physical_location; + cmd_dependency_write_fabric_pin_physical_location.push_back( + build_fabric_cmd_id); + add_write_fabric_pin_physical_location_command_template( + shell, openfpga_setup_cmd_class, + cmd_dependency_write_fabric_pin_physical_location, hidden); + + /******************************** + * Command 'report_reference' + */ + /* The command should NOT be executed before 'build_fabric' */ + std::vector cmd_dependency_report_reference; + cmd_dependency_report_reference.push_back(build_fabric_cmd_id); + add_report_reference_command_template( + shell, openfpga_setup_cmd_class, cmd_dependency_report_reference, hidden); + + /******************************** + * Command 'read_unique_blocks' + */ + /* The command should NOT be executed before + * 'link_openfpga_arch' */ + std::vector cmd_dependency_read_unique_blocks_command; + cmd_dependency_read_unique_blocks_command.push_back(link_arch_cmd_id); + add_read_unique_blocks_command_template( + shell, openfpga_setup_cmd_class, cmd_dependency_read_unique_blocks_command, + hidden); + + /******************************** + * Command 'write_unique_blocks' + */ + add_write_unique_blocks_command_template( + shell, openfpga_setup_cmd_class, std::vector(), hidden); +} } /* end namespace openfpga */ #endif diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h index 6b27dd5e1..99376f5fe 100644 --- a/openfpga/src/base/openfpga_verilog_command_template.h +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -30,6 +30,15 @@ ShellCommandId add_write_fabric_verilog_command_template( shell_cmd.set_option_short_name(output_opt, "f"); shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + /* Add an option '--constant_undriven_inputs' */ + CommandOptionId const_undriven_inputs_opt = shell_cmd.add_option( + "constant_undriven_inputs", false, + "Can be [none|bus0|bus1|bit0|bit1]. Use constant vdd/gnd for undriven " + "wires in Verilog netlists. Recommand to " + "enable when there are boundary routing tracks in FPGA fabric"); + shell_cmd.set_option_require_value(const_undriven_inputs_opt, + openfpga::OPT_STRING); + /* Add an option '--explicit_port_mapping' */ shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists"); @@ -104,6 +113,11 @@ ShellCommandId add_write_full_testbench_command_template( "bitstream", true, "specify the bitstream to be loaded in the testbench"); shell_cmd.set_option_require_value(bitstream_opt, openfpga::OPT_STRING); + /* add an option '--simulator'*/ + CommandOptionId sim_opt = shell_cmd.add_option( + "simulator", false, "specify the simulator to be used for the testbench"); + shell_cmd.set_option_require_value(sim_opt, openfpga::OPT_STRING); + /* add an option '--fabric_netlist_file_path'*/ CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, @@ -245,6 +259,10 @@ ShellCommandId add_write_preconfigured_fabric_wrapper_command_template( shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches"); + /* add an option '--dump_waveform' */ + shell_cmd.add_option("dump_waveform", false, + "add waveform output commands to the output file"); + /* Add an option '--no_time_stamp' */ shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files"); diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index 66070a777..dd024c72c 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -28,6 +28,8 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); + CommandOptionId opt_constant_undriven_inputs = + cmd.option("constant_undriven_inputs"); CommandOptionId opt_include_timing = cmd.option("include_timing"); CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template"); @@ -56,6 +58,22 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, } options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing()); + /* For perimeter cb, enable the constant-zero undriven inputs, unless it is + * defined by user. Throw error if the constant inputs are not selected! */ + if (cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) { + options.set_constant_undriven_inputs( + cmd_context.option_value(cmd, opt_constant_undriven_inputs)); + } + if (g_vpr_ctx.device().arch->perimeter_cb) { + if (FabricVerilogOption::e_undriven_input_type::NONE == + options.constant_undriven_inputs()) { + options.set_constant_undriven_inputs( + FabricVerilogOption::e_undriven_input_type::BUS0); + VTR_LOG( + "Automatically enable the constant_undriven_input option as perimeter " + "connection blocks are seen in FPGA fabric\n"); + } + } return fpga_fabric_verilog( openfpga_ctx.mutable_module_graph(), @@ -74,6 +92,7 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_bitstream = cmd.option("bitstream"); + CommandOptionId opt_sim = cmd.option("simulator"); CommandOptionId opt_dut_module = cmd.option("dut_module"); CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); @@ -132,6 +151,11 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd, read_xml_bus_group(cmd_context.option_value(cmd, opt_bgf).c_str()); } + /* Configure the simulator */ + if (true == cmd_context.option_enable(cmd, opt_sim)) { + options.set_simulator_type(cmd_context.option_value(cmd, opt_sim)); + } + return fpga_verilog_full_testbench( openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(), openfpga_ctx.fabric_bitstream(), openfpga_ctx.blwl_shift_register_banks(), @@ -163,6 +187,7 @@ int write_preconfigured_fabric_wrapper_template( CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); + CommandOptionId opt_dump_waveform = cmd.option("dump_waveform"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the @@ -178,6 +203,7 @@ int write_preconfigured_fabric_wrapper_template( options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_include_signal_init( cmd_context.option_enable(cmd, opt_include_signal_init)); + options.set_dump_waveform(cmd_context.option_enable(cmd, opt_dump_waveform)); options.set_print_formal_verification_top_netlist(true); if (true == cmd_context.option_enable(cmd, opt_dut_module)) { diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 012e3a529..d517002a7 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -88,8 +88,9 @@ int build_device_module_graph( module_manager, decoder_lib, vpr_device_ctx, openfpga_ctx.vpr_device_annotation(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), openfpga_ctx.arch().tile_annotations, - openfpga_ctx.arch().config_protocol.type(), sram_model, duplicate_grid_pin, - group_config_block, verbose); + openfpga_ctx.arch().config_protocol.type(), sram_model, + openfpga_ctx.arch().config_protocol.ql_memory_bank_config_setting(), + duplicate_grid_pin, group_config_block, verbose); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -127,7 +128,8 @@ int build_device_module_graph( openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph, openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib, sram_model, openfpga_ctx.arch().config_protocol.type(), - name_module_using_index, frame_view, verbose); + name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view, + verbose); } /* Build FPGA fabric top-level module */ @@ -140,7 +142,8 @@ int build_device_module_graph( openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol, sram_model, fabric_tile, name_module_using_index, frame_view, compress_routing, duplicate_grid_pin, fabric_key, - generate_random_fabric_key, group_config_block, verbose); + generate_random_fabric_key, group_config_block, + vpr_device_ctx.arch->perimeter_cb, verbose); if (CMD_EXEC_FATAL_ERROR == status) { return status; diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index a1e5f9460..e9747e920 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -22,10 +22,175 @@ namespace openfpga { /******************************************************************** - * Build tiles by following the top-level style. + * With a given coordinate of a grid, find an existing fabric tile + * or create a new fabric tile + * - A grid may never exist in any fabric tile (no coordinate matches) + * Create a new one + * - A grid already in another fabric tile (occur in heterogeneous blocks) + * Find the existing one + *******************************************************************/ +static int find_or_create_one_fabric_tile_from_grid( + FabricTile& fabric_tile, FabricTileId& curr_tile_id, const DeviceGrid& grids, + const t_physical_tile_loc& tile_loc, const bool& verbose) { + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); + vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); + vtr::Point curr_gsb_coord(tile_loc.x, tile_loc.y); + + bool skip_add_pb = false; + /* For EMPTY grid, routing blocks may still be required if there is a gsb + */ + if (true == is_empty_type(phy_tile_type)) { + return CMD_EXEC_SUCCESS; + } else if ((0 < grids.get_width_offset(tile_loc)) || + (0 < grids.get_height_offset(tile_loc))) { + /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ + /* Find the root of this grid, the instance id should be valid. + * We just copy it here + */ + vtr::Point root_tile_coord( + curr_tile_coord.x() - grids.get_width_offset(tile_loc), + curr_tile_coord.y() - grids.get_height_offset(tile_loc)); + skip_add_pb = true; + VTR_LOGV(verbose, + "Tile[%lu][%lu] contains a heterogeneous block which is " + "rooted from tile[%lu][%lu]\n", + curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(), + root_tile_coord.y()); + curr_tile_id = fabric_tile.find_tile(root_tile_coord); + /* Update the coordinates of the pb in tiles */ + size_t root_pb_idx_in_curr_tile = + fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord); + int status_code = fabric_tile.set_pb_max_coordinate( + curr_tile_id, root_pb_idx_in_curr_tile, curr_tile_coord); + if (status_code != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } + } else { + /* Need to create a new tile here */ + VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", curr_tile_coord.x(), + curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); + } + + /* Ensure that we have a valid id */ + if (!fabric_tile.valid_tile_id(curr_tile_id)) { + VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n", + curr_tile_coord.x(), curr_tile_coord.y()); + return CMD_EXEC_FATAL_ERROR; + } + + /* Add components: pb, cbx, cby, and sb if exists */ + if (!skip_add_pb) { + fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord, + curr_gsb_coord); + } + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Build tiles by following the bottom style. + * - The programmble block, e.g., clb, is placed on the bottom-left corner + * - The connection blocks and switch block are placed on the top and bottom + *sides + * This is exactly how GSB is organized. Just need to transfer data from one GSB + * The gsb coordinate is the same as the grid coordinate when the + * bottom-left style is considered + * + * ------------------------------ + * +----------+ +----------+ ^ + * | CBx | | SB | | + * | [x][y] | | [x][y] | GSB[x][y] + * +----------+ +----------+ | + * +----------+ +----------+ | + * | Grid | | CBy | | + * | [x][y] | | [x][y] | | + * +----------+ +----------+ v + * ------------------------------ + * + *******************************************************************/ +static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, + const DeviceGrid& grids, + const size_t& layer, + const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, + const bool& verbose) { + int status_code = CMD_EXEC_SUCCESS; + + /* Walk through all the device rr_gsb and create tile one by one */ + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + t_physical_tile_loc tile_loc(ix, iy, layer); + FabricTileId curr_tile_id = FabricTileId::INVALID(); + status_code = find_or_create_one_fabric_tile_from_grid( + fabric_tile, curr_tile_id, grids, tile_loc, verbose); + if (status_code != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } + /* If no tile is created for the pb, check if routing exists */ + vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); + vtr::Point curr_gsb_coord(ix, iy); + if (!fabric_tile.valid_tile_id(curr_tile_id)) { + if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", + curr_tile_coord.x(), curr_tile_coord.y()); + continue; + } + /* Need to create a new tile here */ + VTR_LOGV(verbose, + "Create tile[%lu][%lu] which only has routing but not a " + "programmable block\n", + curr_tile_coord.x(), curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); + } + if (fabric_tile.valid_tile_id(curr_tile_id) && + !device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV( + verbose, + "Skip to add routing to tile[%lu][%lu] as it is not required\n", + curr_tile_coord.x(), curr_tile_coord.y()); + continue; + } + const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); + for (t_rr_type cb_type : {CHANX, CHANY}) { + if (curr_rr_gsb.is_cb_exist(cb_type)) { + fabric_tile.add_cb_coordinate(curr_tile_id, cb_type, + curr_rr_gsb.get_sb_coordinate()); + VTR_LOGV( + verbose, "Added %s connection block [%lu][%lu] to tile[%lu][%lu]\n", + cb_type == CHANX ? "x-" : "y-", curr_rr_gsb.get_cb_x(cb_type), + curr_rr_gsb.get_cb_y(cb_type), ix, iy); + } + } + if (curr_rr_gsb.is_sb_exist(rr_graph)) { + fabric_tile.add_sb_coordinate(curr_tile_id, + curr_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", + curr_rr_gsb.get_sb_x(), curr_rr_gsb.get_sb_y(), ix, iy); + } + } + } + + return status_code; +} + +/******************************************************************** + * Build tiles by following the top-left style. * - The programmble block, e.g., clb, is placed on the top-left corner * - The connection blocks and switch block are placed on the right and bottom *sides + * Tile[x][y] + * ------------------------------ + * +----------+ +----------+ ^ + * | Grid | | CBy | GSB[x][y] + * | [x][y] | | [x][y] | | + * +----------+ +----------+ v + * ------------------------------ + * +----------+ +----------+ ^ + * | CBx | | SB | | + * | [x][y-1] | | [x][y-1] | GSB[x][y-1] + * +----------+ +----------+ | + * ------------------------------ + *******************************************************************/ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, const DeviceGrid& grids, @@ -39,17 +204,34 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); - t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(tile_loc); - bool skip_add_pb = false; - vtr::Point curr_tile_coord(ix, iy); - vtr::Point curr_gsb_coord(ix, iy - 1); FabricTileId curr_tile_id = FabricTileId::INVALID(); - /* For EMPTY grid, routing blocks may still be required if there is a gsb - */ - if (true == is_empty_type(phy_tile_type)) { - skip_add_pb = true; - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + status_code = find_or_create_one_fabric_tile_from_grid( + fabric_tile, curr_tile_id, grids, tile_loc, verbose); + if (status_code != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } + /* If no valid tile is created/found by the pb, check if there is any + * routing inside */ + vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); + vtr::Point curr_gsb_coord(ix, iy); + vtr::Point neighbor_gsb_coord(ix, iy - 1); + if (!fabric_tile.valid_tile_id(curr_tile_id)) { + bool routing_exist = false; + if (device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + const RRGSB& routing_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); + if (routing_rr_gsb.is_cb_exist(CHANY)) { + routing_exist = true; + } + } + if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { + const RRGSB& routing_rr_gsb = + device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (routing_rr_gsb.is_cb_exist(CHANX) || + routing_rr_gsb.is_sb_exist(rr_graph)) { + routing_exist = true; + } + } + if (!routing_exist) { VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", curr_tile_coord.x(), curr_tile_coord.y()); continue; @@ -60,74 +242,38 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, "programmable block\n", curr_tile_coord.x(), curr_tile_coord.y()); curr_tile_id = fabric_tile.create_tile(curr_tile_coord); - } else if ((0 < grids.get_width_offset(tile_loc)) || - (0 < grids.get_height_offset(tile_loc))) { - /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ - /* Find the root of this grid, the instance id should be valid. - * We just copy it here - */ - vtr::Point root_tile_coord( - ix - grids.get_width_offset(tile_loc), - iy - grids.get_height_offset(tile_loc)); - skip_add_pb = true; - VTR_LOGV(verbose, - "Tile[%lu][%lu] contains a heterogeneous block which is " - "rooted from tile[%lu][%lu]\n", - curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(), - root_tile_coord.y()); - curr_tile_id = fabric_tile.find_tile(root_tile_coord); - /* Update the coordinates of the pb in tiles */ - size_t root_pb_idx_in_curr_tile = - fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord); - status_code = fabric_tile.set_pb_max_coordinate( - curr_tile_id, root_pb_idx_in_curr_tile, vtr::Point(ix, iy)); - if (status_code != CMD_EXEC_SUCCESS) { - return CMD_EXEC_FATAL_ERROR; - } - } else { - /* Need to create a new tile here */ - VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", - curr_tile_coord.x(), curr_tile_coord.y()); - curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } - - /* Ensure that we have a valid id */ - if (!fabric_tile.valid_tile_id(curr_tile_id)) { - VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n", ix, iy); - return CMD_EXEC_FATAL_ERROR; - } - - /* Add components: pb, cbx, cby, and sb if exists */ - if (!skip_add_pb) { - fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord, - curr_gsb_coord); - } - /* The gsb coordinate is different than the grid coordinate when the - * top-left style is considered - * - * +----------+ +----------+ - * | Grid | | CBx | - * | [x][y] | | [x][y] | - * +----------+ +----------+ - * +----------+ +----------+ - * | CBy | | SB | - * | [x][y-1] | | [x][y-1] | - * +----------+ +----------+ - * - */ - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - continue; - } - const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); - for (t_rr_type cb_type : {CHANX, CHANY}) { - if (curr_rr_gsb.is_cb_exist(cb_type)) { - fabric_tile.add_cb_coordinate(curr_tile_id, cb_type, + /* For the cby in the same gsb */ + if (device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); + if (curr_rr_gsb.is_cb_exist(CHANY)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANY, curr_rr_gsb.get_sb_coordinate()); + VTR_LOGV( + verbose, "Added y- connection block [%lu][%lu] to tile[%lu][%lu]\n", + curr_rr_gsb.get_cb_x(CHANY), curr_rr_gsb.get_cb_y(CHANY), ix, iy); } } - if (curr_rr_gsb.is_sb_exist(rr_graph)) { - fabric_tile.add_sb_coordinate(curr_tile_id, - curr_rr_gsb.get_sb_coordinate()); + /* For the cbx and sb in the neighbour gsb */ + if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { + const RRGSB& neighbor_rr_gsb = + device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (neighbor_rr_gsb.is_cb_exist(CHANX)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANX, + neighbor_rr_gsb.get_sb_coordinate()); + + VTR_LOGV(verbose, + "Added x- connection block [%lu][%lu] to tile[%lu][%lu]\n", + neighbor_rr_gsb.get_cb_x(CHANX), + neighbor_rr_gsb.get_cb_y(CHANX), ix, iy); + } + if (neighbor_rr_gsb.is_sb_exist(rr_graph)) { + fabric_tile.add_sb_coordinate(curr_tile_id, + neighbor_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", + neighbor_rr_gsb.get_sb_x(), neighbor_rr_gsb.get_sb_y(), ix, + iy); + } } } } @@ -152,6 +298,10 @@ int build_fabric_tile(FabricTile& fabric_tile, const TileConfig& tile_config, if (tile_config.style() == TileConfig::e_style::TOP_LEFT) { status_code = build_fabric_tile_style_top_left( fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose); + } else if (tile_config.style() == TileConfig::e_style::BOTTOM_LEFT) { + status_code = build_fabric_tile_style_bottom_left( + fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose); + } else { /* Error out for styles that are not supported yet! */ VTR_LOG_ERROR("Tile style '%s' is not supported yet!\n", diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index cae215259..6118e673d 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -55,7 +55,8 @@ void add_grid_module_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(false == is_empty_type(grid_type_descriptor)); @@ -65,8 +66,8 @@ void add_grid_module_duplicated_pb_type_ports( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -123,8 +124,10 @@ void add_grid_module_duplicated_pb_type_ports( } BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ - module_manager.add_port(grid_module, grid_port, - pin_type2type_map[pin_class_type]); + ModulePortId grid_port_id = module_manager.add_port( + grid_module, grid_port, pin_type2type_map[pin_class_type]); + /* Set port side */ + module_manager.set_port_side(grid_module, grid_port_id, side); } else { /* For each DRIVER pin, we create two copies. * One with a postfix of upper, indicating it is located on the @@ -136,15 +139,19 @@ void add_grid_module_duplicated_pb_type_ports( iwidth, iheight, subtile_index, side, pin_info, true); BasicPort grid_upper_port(upper_port_name, 0, 0); /* Add the port to the module */ - module_manager.add_port(grid_module, grid_upper_port, - pin_type2type_map[pin_class_type]); + ModulePortId grid_upper_port_id = module_manager.add_port( + grid_module, grid_upper_port, pin_type2type_map[pin_class_type]); + /* Set port side */ + module_manager.set_port_side(grid_module, grid_upper_port_id, side); std::string lower_port_name = generate_grid_duplicated_port_name( iwidth, iheight, subtile_index, side, pin_info, false); BasicPort grid_lower_port(lower_port_name, 0, 0); /* Add the port to the module */ - module_manager.add_port(grid_module, grid_lower_port, - pin_type2type_map[pin_class_type]); + ModulePortId grid_lower_port_id = module_manager.add_port( + grid_module, grid_lower_port, pin_type2type_map[pin_class_type]); + /* Set port side */ + module_manager.set_port_side(grid_module, grid_lower_port_id, side); } } } @@ -166,7 +173,8 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( const size_t& child_inst_subtile_index, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) { + const e_side& border_side, const bool& perimeter_cb, + const e_pin2pin_interc_type& pin2pin_interc_type) { /* Make sure this is ONLY applied to output pins */ VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type); @@ -176,8 +184,8 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -310,7 +318,8 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(false == is_empty_type(grid_type_descriptor)); @@ -328,7 +337,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } @@ -339,7 +348,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->output_pins[iport][ipin]), border_side, - OUTPUT2OUTPUT_INTERC); + perimeter_cb, OUTPUT2OUTPUT_INTERC); } } @@ -350,7 +359,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } } diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.h b/openfpga/src/fabric/build_grid_module_duplicated_pins.h index 4f2eafee2..9f95b7dd7 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.h +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.h @@ -21,14 +21,16 @@ void add_grid_module_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side); + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb); void add_grid_module_nets_connect_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side); + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 3b3f14203..f1b18bdba 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -24,16 +24,29 @@ namespace openfpga { * 5. I/O grids in the center part of FPGA can have ports on any side *******************************************************************/ std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, + const bool& perimeter_cb) { /* We must have an regular (non-I/O) type here */ VTR_ASSERT(true == is_io_type(grid_type_descriptor)); SideManager side_manager(border_side); - if (NUM_SIDES == border_side) { + if (NUM_2D_SIDES == border_side) { return {TOP, RIGHT, BOTTOM, LEFT}; } - return std::vector(1, side_manager.get_opposite()); + if (!perimeter_cb) { + return std::vector(1, side_manager.get_opposite()); + } + /* For cbs on perimeter, exclude the border side. All the other 3 sides are ok + */ + std::vector pin_sides; + pin_sides.reserve(3); + for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) { + if (pin_side != border_side) { + pin_sides.push_back(pin_side); + } + } + return pin_sides; } /******************************************************************** @@ -47,15 +60,16 @@ void add_grid_module_net_connect_pb_graph_pin( const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) { + const e_side& border_side, const bool& perimeter_cb, + const e_pin2pin_interc_type& pin2pin_interc_type) { /* Find the pin side for I/O grids*/ std::vector grid_pin_sides; /* For I/O grids, we care only one side * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } diff --git a/openfpga/src/fabric/build_grid_module_utils.h b/openfpga/src/fabric/build_grid_module_utils.h index a8d5f9d12..d83d9ab9f 100644 --- a/openfpga/src/fabric/build_grid_module_utils.h +++ b/openfpga/src/fabric/build_grid_module_utils.h @@ -19,7 +19,8 @@ namespace openfpga { std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side); + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, + const bool& perimeter_cb); void add_grid_module_net_connect_pb_graph_pin( ModuleManager& module_manager, const ModuleId& grid_module, @@ -28,7 +29,7 @@ void add_grid_module_net_connect_pb_graph_pin( const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, + const e_side& border_side, const bool& perimeter_cb, const enum e_pin2pin_interc_type& pin2pin_interc_type); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index 94b9d884c..a2bb0abf4 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -42,7 +42,8 @@ static void add_grid_module_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -52,8 +53,8 @@ static void add_grid_module_pb_type_ports( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -103,8 +104,10 @@ static void add_grid_module_pb_type_ports( } BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ - module_manager.add_port(grid_module, grid_port, - pin_type2type_map[pin_class_type]); + ModulePortId grid_port_id = module_manager.add_port( + grid_module, grid_port, pin_type2type_map[pin_class_type]); + /* Set port side */ + module_manager.set_port_side(grid_module, grid_port_id, side); } } } @@ -123,7 +126,8 @@ static void add_grid_module_nets_connect_pb_type_ports( const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -142,7 +146,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } @@ -153,7 +157,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->output_pins[iport][ipin]), - border_side, OUTPUT2OUTPUT_INTERC); + border_side, perimeter_cb, OUTPUT2OUTPUT_INTERC); } } @@ -164,7 +168,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } } @@ -1164,8 +1168,9 @@ static int build_physical_tile_module( const e_config_protocol_type& sram_orgz_type, const CircuitModelId& sram_model, t_physical_tile_type_ptr phy_block_type, const TileAnnotation& tile_annotation, const e_side& border_side, + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, const bool& duplicate_grid_pin, const bool& group_config_block, - const bool& verbose) { + const bool& perimeter_cb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; /* Create a Module for the top-level physical block, and add to module manager */ @@ -1244,7 +1249,7 @@ static int build_physical_tile_module( /* Default way to add these ports by following the definition in pb_types */ add_grid_module_pb_type_ports(module_manager, grid_module, vpr_device_annotation, phy_block_type, - tile_annotation, border_side); + tile_annotation, border_side, perimeter_cb); /* Add module nets to connect the pb_type ports to sub modules */ for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) { VTR_ASSERT(sub_tile.equivalent_sites.size() == 1); @@ -1261,7 +1266,8 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, + perimeter_cb); } } } else { @@ -1269,7 +1275,7 @@ static int build_physical_tile_module( /* Add these ports with duplication */ add_grid_module_duplicated_pb_type_ports( module_manager, grid_module, vpr_device_annotation, phy_block_type, - tile_annotation, border_side); + tile_annotation, border_side, perimeter_cb); /* Add module nets to connect the duplicated pb_type ports to sub modules */ for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) { @@ -1287,7 +1293,8 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, + perimeter_cb); } } } @@ -1332,9 +1339,10 @@ static int build_physical_tile_module( module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, config_child_type); if (0 < module_num_config_bits) { - add_pb_sram_ports_to_module_manager(module_manager, grid_module, - circuit_lib, sram_model, sram_orgz_type, - module_num_config_bits); + add_pb_sram_ports_to_module_manager( + module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, + module_num_config_bits, + ql_memory_bank_config_setting->pb_setting(phy_block_type->name).num_wl); } /* Add module nets to connect memory cells inside @@ -1372,8 +1380,10 @@ int build_grid_modules( const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const TileAnnotation& tile_annotation, const e_config_protocol_type& sram_orgz_type, - const CircuitModelId& sram_model, const bool& duplicate_grid_pin, - const bool& group_config_block, const bool& verbose) { + const CircuitModelId& sram_model, + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, + const bool& duplicate_grid_pin, const bool& group_config_block, + const bool& verbose) { /* Start time count */ vtr::ScopedStartFinishTimer timer("Build grid modules"); @@ -1420,8 +1430,8 @@ int build_grid_modules( * i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT}, * we will generate one module for each border side * - If a I/O block locates in the center of FPGA fabric: - * we will generate one module with NUM_SIDES (same treatment as regular - * grids) + * we will generate one module with NUM_2D_SIDES (same treatment as + * regular grids) */ std::set io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile); @@ -1429,7 +1439,8 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, - io_type_side, duplicate_grid_pin, group_config_block, verbose); + io_type_side, ql_memory_bank_config_setting, duplicate_grid_pin, + group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1438,8 +1449,9 @@ int build_grid_modules( /* For CLB and heterogenenous blocks */ status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, - sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES, - duplicate_grid_pin, group_config_block, verbose); + sram_orgz_type, sram_model, &physical_tile, tile_annotation, + NUM_2D_SIDES, ql_memory_bank_config_setting, duplicate_grid_pin, + group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_grid_modules.h b/openfpga/src/fabric/build_grid_modules.h index 996b9bda2..523b545ea 100644 --- a/openfpga/src/fabric/build_grid_modules.h +++ b/openfpga/src/fabric/build_grid_modules.h @@ -7,6 +7,7 @@ #include "decoder_library.h" #include "module_manager.h" #include "mux_library.h" +#include "ql_memory_bank_config_setting.h" #include "tile_annotation.h" #include "vpr_context.h" #include "vpr_device_annotation.h" @@ -24,8 +25,10 @@ int build_grid_modules( const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const TileAnnotation& tile_annotation, const e_config_protocol_type& sram_orgz_type, - const CircuitModelId& sram_model, const bool& duplicate_grid_pin, - const bool& group_config_block, const bool& verbose); + const CircuitModelId& sram_model, + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, + const bool& duplicate_grid_pin, const bool& group_config_block, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_mux_modules.cpp b/openfpga/src/fabric/build_mux_modules.cpp index 3233db768..5d9fb93d7 100644 --- a/openfpga/src/fabric/build_mux_modules.cpp +++ b/openfpga/src/fabric/build_mux_modules.cpp @@ -496,6 +496,71 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( module_manager.module_port(std_cell_module_id, std_cell_module_output); VTR_ASSERT(1 == std_cell_module_output_port.get_width()); + /* Find module information of the standard cell MUX2 */ + CircuitModelId last_stage_std_cell_model = + circuit_lib.last_stage_pass_gate_logic_model(mux_model); + std::string last_stage_std_cell_module_name = + circuit_lib.model_name(last_stage_std_cell_model); + /* Get the moduleId for the submodule */ + ModuleId last_stage_std_cell_module_id = + module_manager.find_module(last_stage_std_cell_module_name); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != last_stage_std_cell_module_id); + + /* Find the input ports and output ports of the standard cell */ + std::vector last_stage_std_cell_input_ports = + circuit_lib.model_ports_by_type(last_stage_std_cell_model, + CIRCUIT_MODEL_PORT_INPUT, true); + std::vector last_stage_std_cell_output_ports = + circuit_lib.model_ports_by_type(last_stage_std_cell_model, + CIRCUIT_MODEL_PORT_OUTPUT, true); + /* Quick check the requirements on port map */ + VTR_ASSERT(3 == last_stage_std_cell_input_ports.size()); + VTR_ASSERT(1 == last_stage_std_cell_output_ports.size()); + + /* Find the module ports of the standard cell MUX2 module */ + std::vector last_stage_std_cell_module_inputs; + std::vector last_stage_std_cell_module_input_ports; + /* Input 0 port is the first data path input of the tgate, whose size must be + * 1 ! */ + for (size_t port_id = 0; port_id < 2; ++port_id) { + last_stage_std_cell_module_inputs.push_back(module_manager.find_module_port( + last_stage_std_cell_module_id, + circuit_lib.port_prefix(last_stage_std_cell_input_ports[port_id]))); + VTR_ASSERT(true == module_manager.valid_module_port_id( + last_stage_std_cell_module_id, + last_stage_std_cell_module_inputs[port_id])); + last_stage_std_cell_module_input_ports.push_back( + module_manager.module_port(last_stage_std_cell_module_id, + last_stage_std_cell_module_inputs[port_id])); + VTR_ASSERT(1 == + last_stage_std_cell_module_input_ports[port_id].get_width()); + } + + /* Mem port is the memory of the standard cell MUX2, whose size must be 1 ! */ + ModulePortId last_stage_std_cell_module_mem = module_manager.find_module_port( + last_stage_std_cell_module_id, + circuit_lib.port_prefix(last_stage_std_cell_input_ports[2])); + VTR_ASSERT(true == + module_manager.valid_module_port_id( + last_stage_std_cell_module_id, last_stage_std_cell_module_mem)); + BasicPort last_stage_std_cell_module_mem_port = module_manager.module_port( + last_stage_std_cell_module_id, last_stage_std_cell_module_mem); + VTR_ASSERT(1 == last_stage_std_cell_module_mem_port.get_width()); + + /* Output port is the data path output of the standard cell MUX2, whose size + * must be 1 ! */ + ModulePortId last_stage_std_cell_module_output = + module_manager.find_module_port( + last_stage_std_cell_module_id, + circuit_lib.port_prefix(last_stage_std_cell_output_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id( + last_stage_std_cell_module_id, + last_stage_std_cell_module_output)); + BasicPort last_stage_std_cell_module_output_port = module_manager.module_port( + last_stage_std_cell_module_id, last_stage_std_cell_module_output); + VTR_ASSERT(1 == last_stage_std_cell_module_output_port.get_width()); + /* Cache Net ids for each level of the multiplexer */ std::vector> module_nets_by_level; module_nets_by_level.resize(mux_graph.num_node_levels()); @@ -518,11 +583,16 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( /* To match the standard cell MUX2: We should have only 2 input_nodes */ VTR_ASSERT(2 == branch_size); + /* Last stage MUX model may have a different name */ + ModuleId curr_stage_std_cell_module_id = std_cell_module_id; + if (true == mux_graph.is_node_output(node)) { + curr_stage_std_cell_module_id = last_stage_std_cell_module_id; + } /* Find the instance id */ size_t std_cell_instance_id = - module_manager.num_instance(mux_module, std_cell_module_id); + module_manager.num_instance(mux_module, curr_stage_std_cell_module_id); /* Add the module to mux_module */ - module_manager.add_child_module(mux_module, std_cell_module_id); + module_manager.add_child_module(mux_module, curr_stage_std_cell_module_id); /* Get the node level and index in the current level */ size_t output_node_level = mux_graph.node_level(node); @@ -530,9 +600,9 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( /* Set a name for the instance */ std::string std_cell_instance_name = generate_mux_branch_instance_name( output_node_level, output_node_index_at_level, false); - module_manager.set_child_instance_name(mux_module, std_cell_module_id, - std_cell_instance_id, - std_cell_instance_name); + module_manager.set_child_instance_name( + mux_module, curr_stage_std_cell_module_id, std_cell_instance_id, + std_cell_instance_name); /* Add module nets to wire to next stage modules */ ModuleNetId branch_net; @@ -540,13 +610,18 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( /* This is an output node, we should use existing output nets */ MuxOutputId output_id = mux_graph.output_id(node); branch_net = mux_module_output_nets[output_id]; + module_manager.add_module_net_source( + mux_module, branch_net, curr_stage_std_cell_module_id, + std_cell_instance_id, last_stage_std_cell_module_output, + last_stage_std_cell_module_output_port.get_lsb()); } else { VTR_ASSERT(false == mux_graph.is_node_output(node)); branch_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source( + mux_module, branch_net, curr_stage_std_cell_module_id, + std_cell_instance_id, std_cell_module_output, + std_cell_module_output_port.get_lsb()); } - module_manager.add_module_net_source( - mux_module, branch_net, std_cell_module_id, std_cell_instance_id, - std_cell_module_output, std_cell_module_output_port.get_lsb()); /* Record the module net id in the cache */ module_nets_by_level[output_node_level][output_node_index_at_level] = @@ -567,10 +642,17 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( * Note that standard cell MUX2 only needs mem but NOT mem_inv */ for (const MuxMemId& mem : mems) { - module_manager.add_module_net_sink( - mux_module, mux_module_mem_nets[mem], std_cell_module_id, - std_cell_instance_id, std_cell_module_mem, - std_cell_module_mem_port.get_lsb()); + if (true == mux_graph.is_node_output(node)) { + module_manager.add_module_net_sink( + mux_module, mux_module_mem_nets[mem], last_stage_std_cell_module_id, + std_cell_instance_id, last_stage_std_cell_module_mem, + last_stage_std_cell_module_mem_port.get_lsb()); + } else { + module_manager.add_module_net_sink( + mux_module, mux_module_mem_nets[mem], std_cell_module_id, + std_cell_instance_id, std_cell_module_mem, + std_cell_module_mem_port.get_lsb()); + } } /* Wire the branch module inputs to the nets in previous stage */ @@ -602,8 +684,15 @@ static void build_cmos_mux_module_mux2_multiplexing_structure( mux_module, mux_module_input_nets[input_id], std_cell_module_id, std_cell_instance_id, std_cell_module_inputs[node_id], std_cell_module_input_ports[node_id].get_lsb()); + } else if (true == mux_graph.is_node_output(node)) { + /* Find the input port of standard cell */ + module_manager.add_module_net_sink( + mux_module, + module_nets_by_level[input_node_level][input_node_index_at_level], + last_stage_std_cell_module_id, std_cell_instance_id, + last_stage_std_cell_module_inputs[node_id], + last_stage_std_cell_module_input_ports[node_id].get_lsb()); } else { - VTR_ASSERT(false == mux_graph.is_node_input(input_nodes[node_id])); /* Find the input port of standard cell */ module_manager.add_module_net_sink( mux_module, diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp index e1f3db9ad..f340d0f5b 100644 --- a/openfpga/src/fabric/build_routing_module_utils.cpp +++ b/openfpga/src/fabric/build_routing_module_utils.cpp @@ -143,7 +143,7 @@ ModulePinInfo find_switch_block_module_chan_port( int index = rr_gsb.get_node_index(rr_graph, cur_rr_node, chan_side, cur_rr_node_direction); /* Make sure this node is included in this sb_info */ - VTR_ASSERT((-1 != index) && (NUM_SIDES != chan_side)); + VTR_ASSERT((-1 != index) && (NUM_2D_SIDES != chan_side)); std::string chan_port_name = generate_sb_module_track_port_name( rr_graph.node_type(rr_gsb.get_chan_node(chan_side, index)), chan_side, @@ -194,7 +194,7 @@ ModulePinInfo find_switch_block_module_input_port( /* Find the side where the grid pin locates in the grid */ enum e_side grid_pin_side = get_rr_graph_single_node_side(rr_graph, input_rr_node); - VTR_ASSERT(NUM_SIDES != grid_pin_side); + VTR_ASSERT(NUM_2D_SIDES != grid_pin_side); std::string input_port_name = generate_sb_module_grid_port_name( input_side, grid_pin_side, grids, vpr_device_annotation, rr_graph, @@ -235,12 +235,12 @@ std::vector find_switch_block_module_input_ports( for (const RRNodeId& input_rr_node : input_rr_nodes) { /* Find the side where the input locates in the Switch Block */ - enum e_side input_pin_side = NUM_SIDES; + enum e_side input_pin_side = NUM_2D_SIDES; /* The input could be at any side of the switch block, find it */ int index = -1; rr_gsb.get_node_side_and_index(rr_graph, input_rr_node, IN_PORT, input_pin_side, index); - VTR_ASSERT(NUM_SIDES != input_pin_side); + VTR_ASSERT(NUM_2D_SIDES != input_pin_side); VTR_ASSERT(-1 != index); input_ports.push_back(find_switch_block_module_input_port( @@ -302,12 +302,12 @@ ModulePortId find_connection_block_module_ipin_port( rr_graph.node_ylow(src_rr_node)); /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ - enum e_side cb_ipin_side = NUM_SIDES; + enum e_side cb_ipin_side = NUM_2D_SIDES; int cb_ipin_index = -1; rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, OUT_PORT, cb_ipin_side, cb_ipin_index); /* We need to be sure that drive_rr_node is part of the CB */ - VTR_ASSERT((-1 != cb_ipin_index) && (NUM_SIDES != cb_ipin_side)); + VTR_ASSERT((-1 != cb_ipin_index) && (NUM_2D_SIDES != cb_ipin_side)); std::string port_name = generate_cb_module_grid_port_name( cb_ipin_side, grids, vpr_device_annotation, rr_graph, rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)); @@ -320,19 +320,58 @@ ModulePortId find_connection_block_module_ipin_port( return ipin_port_id; } +/********************************************************************* + * Generate a port for a connection block + ********************************************************************/ +ModulePortId find_connection_block_module_opin_port( + const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const RRGraphView& rr_graph, const RRGSB& rr_gsb, + const RRNodeId& src_rr_node) { + /* Ensure the src_rr_node is an input pin of a CLB */ + VTR_ASSERT(OPIN == rr_graph.node_type(src_rr_node)); + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB + */ + enum e_side cb_opin_side = NUM_2D_SIDES; + int cb_opin_index = -1; + rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, IN_PORT, cb_opin_side, + cb_opin_index); + /* We need to be sure that drive_rr_node is part of the CB */ + VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); + std::string port_name = generate_cb_module_grid_port_name( + cb_opin_side, grids, vpr_device_annotation, rr_graph, + rr_gsb.get_opin_node(cb_opin_side, cb_opin_index)); + + /* Must find a valid port id in the Switch Block module */ + ModulePortId opin_port_id = + module_manager.find_module_port(cb_module, port_name); + VTR_ASSERT(true == + module_manager.valid_module_port_id(cb_module, opin_port_id)); + return opin_port_id; +} + /********************************************************************* * Generate a list of routing track middle output ports * for routing multiplexer inside the connection block ********************************************************************/ std::vector find_connection_block_module_input_ports( const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, const std::vector& input_rr_nodes) { std::vector input_ports; for (auto input_rr_node : input_rr_nodes) { - input_ports.push_back(find_connection_block_module_chan_port( - module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node)); + if (OPIN == rr_graph.node_type(input_rr_node)) { + input_ports.push_back(ModulePinInfo( + find_connection_block_module_opin_port(module_manager, cb_module, grids, + vpr_device_annotation, rr_graph, + rr_gsb, input_rr_node), + 0)); + } else { + input_ports.push_back(find_connection_block_module_chan_port( + module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node)); + } } return input_ports; diff --git a/openfpga/src/fabric/build_routing_module_utils.h b/openfpga/src/fabric/build_routing_module_utils.h index 8c3907dfa..f2995f27e 100644 --- a/openfpga/src/fabric/build_routing_module_utils.h +++ b/openfpga/src/fabric/build_routing_module_utils.h @@ -62,8 +62,15 @@ ModulePortId find_connection_block_module_ipin_port( const RRGraphView& rr_graph, const RRGSB& rr_gsb, const RRNodeId& src_rr_node); +ModulePortId find_connection_block_module_opin_port( + const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const RRGraphView& rr_graph, const RRGSB& rr_gsb, + const RRNodeId& src_rr_node); + std::vector find_connection_block_module_input_ports( const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, const std::vector& input_rr_nodes); diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp index d552a611c..6b7cf92a1 100644 --- a/openfpga/src/fabric/build_routing_modules.cpp +++ b/openfpga/src/fabric/build_routing_modules.cpp @@ -435,6 +435,9 @@ static void build_switch_block_module( BasicPort chan_input_port(chan_input_port_name, chan_input_port_size); ModulePortId chan_input_port_id = module_manager.add_port( sb_module, chan_input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(sb_module, chan_input_port_id, + side_manager.get_side()); /* Cache the input net */ for (const size_t& pin : chan_input_port.pins()) { @@ -446,8 +449,11 @@ static void build_switch_block_module( std::string chan_output_port_name = generate_sb_module_track_port_name( chan_type, side_manager.get_side(), OUT_PORT); BasicPort chan_output_port(chan_output_port_name, chan_output_port_size); - module_manager.add_port(sb_module, chan_output_port, - ModuleManager::MODULE_OUTPUT_PORT); + ModulePortId chan_output_port_id = module_manager.add_port( + sb_module, chan_output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(sb_module, chan_output_port_id, + side_manager.get_side()); } /* Dump OPINs of adjacent CLBs */ @@ -468,6 +474,9 @@ static void build_switch_block_module( /* Grid outputs are inputs of switch blocks */ ModulePortId input_port_id = module_manager.add_port( sb_module, module_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(sb_module, input_port_id, + side_manager.get_side()); /* Cache the input net */ ModuleNetId net = create_module_source_pin_net( @@ -682,8 +691,9 @@ static void build_connection_block_mux_module( /* TODO: Generate input ports that are wired to the input bus of the routing * multiplexer */ std::vector cb_input_port_ids = - find_connection_block_module_input_ports( - module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_nodes); + find_connection_block_module_input_ports(module_manager, cb_module, grids, + device_annotation, rr_graph, + rr_gsb, cb_type, driver_rr_nodes); /* Link input bus port to Switch Block inputs */ std::vector mux_model_input_ports = @@ -925,6 +935,9 @@ static void build_connection_block_module( rr_gsb.get_cb_chan_width(cb_type) / 2); ModulePortId chan_upper_input_port_id = module_manager.add_port( cb_module, chan_upper_input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, chan_upper_input_port_id, + get_cb_module_track_port_side(cb_type, true)); /* Lower input port: W/2 == 1 tracks */ std::string chan_lower_input_port_name = @@ -933,6 +946,9 @@ static void build_connection_block_module( rr_gsb.get_cb_chan_width(cb_type) / 2); ModulePortId chan_lower_input_port_id = module_manager.add_port( cb_module, chan_lower_input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, chan_lower_input_port_id, + get_cb_module_track_port_side(cb_type, false)); /* Upper output port: W/2 == 0 tracks */ std::string chan_upper_output_port_name = @@ -941,6 +957,9 @@ static void build_connection_block_module( rr_gsb.get_cb_chan_width(cb_type) / 2); ModulePortId chan_upper_output_port_id = module_manager.add_port( cb_module, chan_upper_output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, chan_upper_output_port_id, + get_cb_module_track_port_side(cb_type, true)); /* Lower output port: W/2 == 1 tracks */ std::string chan_lower_output_port_name = @@ -949,6 +968,9 @@ static void build_connection_block_module( rr_gsb.get_cb_chan_width(cb_type) / 2); ModulePortId chan_lower_output_port_id = module_manager.add_port( cb_module, chan_lower_output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, chan_lower_output_port_id, + get_cb_module_track_port_side(cb_type, false)); /* Add the input pins of grids, which are output ports of the connection block */ @@ -957,16 +979,39 @@ static void build_connection_block_module( enum e_side cb_ipin_side = cb_ipin_sides[iside]; for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - const RRNodeId& ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - vtr::Point port_coord(rr_graph.node_xlow(ipin_node), - rr_graph.node_ylow(ipin_node)); + RRNodeId ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); std::string port_name = generate_cb_module_grid_port_name( cb_ipin_side, grids, device_annotation, rr_graph, ipin_node); BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ /* Grid outputs are inputs of switch blocks */ - module_manager.add_port(cb_module, module_port, - ModuleManager::MODULE_OUTPUT_PORT); + ModulePortId module_port_id = module_manager.add_port( + cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, module_port_id, cb_ipin_side); + } + } + + /* Add the output pins of grids which are input ports of the connection block, + * if there is any */ + std::vector opin_module_port_ids; + std::vector cb_opin_sides = rr_gsb.get_cb_opin_sides(cb_type); + for (size_t iside = 0; iside < cb_opin_sides.size(); ++iside) { + enum e_side cb_opin_side = cb_opin_sides[iside]; + for (size_t inode = 0; + inode < rr_gsb.get_num_cb_opin_nodes(cb_type, cb_opin_side); ++inode) { + RRNodeId opin_node = + rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode); + std::string port_name = generate_cb_module_grid_port_name( + cb_opin_side, grids, device_annotation, rr_graph, opin_node); + BasicPort module_port(port_name, + 1); /* Every grid output has a port size of 1 */ + /* Grid outputs are inputs of switch blocks */ + ModulePortId module_port_id = module_manager.add_port( + cb_module, module_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, module_port_id, cb_opin_side); + opin_module_port_ids.push_back(module_port_id); } } @@ -1011,6 +1056,13 @@ static void build_connection_block_module( chan_lower_input_port_id, chan_lower_input_port.pins()[pin_id])] = net; } + for (ModulePortId opin_module_port_id : opin_module_port_ids) { + ModuleNetId net = create_module_source_pin_net( + module_manager, cb_module, cb_module, 0, opin_module_port_id, 0); + /* Cache the module net */ + input_port_to_module_nets[ModulePinInfo(opin_module_port_id, 0)] = net; + } + /* Add sub modules of routing multiplexers or direct interconnect*/ for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { enum e_side cb_ipin_side = cb_ipin_sides[iside]; diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index caf82f075..f10d913bb 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -211,6 +211,10 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( ModulePortId src_tile_port_id = module_manager.add_port( tile_module, src_grid_port, ModuleManager::e_module_port_type::MODULE_INPUT_PORT); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, src_tile_port_id, + module_manager.port_side(sink_sb_module, sink_sb_port_id)); VTR_LOGV( verbose, "Adding ports '%s' to tile as required by the switch block '%s'...\n", @@ -442,6 +446,10 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( ModulePortId sink_tile_port_id = module_manager.add_port( tile_module, src_cb_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, sink_tile_port_id, + module_manager.port_side(src_cb_module, src_cb_port_id)); VTR_LOGV(verbose, "Adding ports '%s' to tile as required by the connection " "block '%s'...\n", @@ -463,6 +471,158 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( } } } + /* Iterate over the output pins of the Connection Block */ + std::vector cb_opin_sides = module_cb.get_cb_opin_sides(cb_type); + for (size_t iside = 0; iside < cb_opin_sides.size(); ++iside) { + enum e_side cb_opin_side = cb_opin_sides[iside]; + for (size_t inode = 0; + inode < module_cb.get_num_cb_opin_nodes(cb_type, cb_opin_side); + ++inode) { + /* Collect source-related information */ + RRNodeId module_opin_node = + module_cb.get_cb_opin_node(cb_type, cb_opin_side, inode); + vtr::Point cb_src_port_coord( + rr_graph.node_xlow(module_opin_node), + rr_graph.node_ylow(module_opin_node)); + std::string src_cb_port_name = generate_cb_module_grid_port_name( + cb_opin_side, grids, vpr_device_annotation, rr_graph, module_opin_node); + ModulePortId src_cb_port_id = + module_manager.find_module_port(src_cb_module, src_cb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, + src_cb_port_id)); + BasicPort src_cb_port = + module_manager.module_port(src_cb_module, src_cb_port_id); + + /* Collect sink-related information */ + /* Note that we use the instance cb pin here!!! + * because it has the correct coordinator for the grid!!! + */ + RRNodeId instance_opin_node = + rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode); + vtr::Point grid_coordinate( + rr_graph.node_xlow(instance_opin_node), + rr_graph.node_ylow(instance_opin_node)); + std::string sink_grid_module_name = + generate_grid_block_module_name_in_top_module( + std::string(GRID_MODULE_NAME_PREFIX), grids, grid_coordinate); + ModuleId sink_grid_module = + module_manager.find_module(sink_grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); + size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_opin_node); + + t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + size_t sink_grid_pin_width = + grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; + size_t sink_grid_pin_height = + grid_type_descriptor->pin_height_offset[sink_grid_pin_index]; + BasicPort sink_grid_pin_info = + vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, + sink_grid_pin_index); + VTR_ASSERT(true == sink_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index( + grid_type_descriptor, sink_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && + subtile_index < grid_type_descriptor->capacity); + std::string sink_grid_port_name = generate_grid_port_name( + sink_grid_pin_width, sink_grid_pin_height, subtile_index, + get_rr_graph_single_node_side( + rr_graph, rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode)), + sink_grid_pin_info); + ModulePortId sink_grid_port_id = + module_manager.find_module_port(sink_grid_module, sink_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id( + sink_grid_module, sink_grid_port_id)); + BasicPort sink_grid_port = + module_manager.module_port(sink_grid_module, sink_grid_port_id); + + /* Check if the grid is inside the tile, if not, create ports */ + if (fabric_tile.pb_in_tile(fabric_tile_id, grid_coordinate)) { + if (!frame_view) { + size_t sink_grid_instance = + pb_instances[fabric_tile.find_pb_index_in_tile(fabric_tile_id, + grid_coordinate)]; + + /* Source and sink port should match in size */ + VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width()); + + /* Create a net for each pin. Note that the sink and source tags are + * reverted in the following code!!! */ + for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); + ++pin_id) { + ModuleNetId net = create_module_source_pin_net( + module_manager, tile_module, sink_grid_module, sink_grid_instance, + sink_grid_port_id, sink_grid_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(tile_module, net, src_cb_module, + src_cb_instance, src_cb_port_id, + src_cb_port.pins()[pin_id]); + } + } + } else { + /* Special: No need to create a new port! Since we only support OPINs + * from Switch blocks. Walk through all the switch blocks and find the + * new port that it is created when connecting pb and sb */ + if (!frame_view) { + /* This is the source sb that is added to the top module */ + const RRGSB& module_sb = device_rr_gsb.get_gsb(module_gsb_coordinate); + vtr::Point module_sb_coordinate(module_sb.get_sb_x(), + module_sb.get_sb_y()); + + /* Collect sink-related information */ + std::string sink_sb_module_name = + generate_switch_block_module_name(module_sb_coordinate); + ModuleId sink_sb_module = + module_manager.find_module(sink_sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module)); + size_t isb = fabric_tile.find_sb_index_in_tile(fabric_tile_id, + module_sb_coordinate); + std::string temp_sb_module_name = generate_switch_block_module_name( + fabric_tile.sb_coordinates(fabric_tile_id)[isb]); + if (name_module_using_index) { + temp_sb_module_name = + generate_switch_block_module_name_using_index(isb); + } + /* FIXME: may find a way to determine the side. Currently using + * cb_opin_side is fine */ + vtr::Point sink_sb_port_coord( + rr_graph.node_xlow(module_sb.get_opin_node(cb_opin_side, inode)), + rr_graph.node_ylow(module_sb.get_opin_node(cb_opin_side, inode))); + std::string sink_sb_port_name = generate_sb_module_grid_port_name( + cb_opin_side, + get_rr_graph_single_node_side( + rr_graph, module_sb.get_opin_node(cb_opin_side, inode)), + grids, vpr_device_annotation, rr_graph, + module_sb.get_opin_node(cb_opin_side, inode)); + ModulePortId sink_sb_port_id = + module_manager.find_module_port(sink_sb_module, sink_sb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id( + sink_sb_module, sink_sb_port_id)); + BasicPort sink_sb_port = + module_manager.module_port(sink_sb_module, sink_sb_port_id); + + sink_sb_port.set_name(generate_tile_module_port_name( + temp_sb_module_name, sink_sb_port.get_name())); + ModulePortId src_tile_port_id = module_manager.find_module_port( + tile_module, sink_sb_port.get_name()); + + /* Create a net for each pin */ + VTR_ASSERT(src_cb_port.pins().size() == sink_sb_port.pins().size()); + for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); + ++pin_id) { + ModuleNetId net = create_module_source_pin_net( + module_manager, tile_module, tile_module, 0, src_tile_port_id, + sink_sb_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(tile_module, net, src_cb_module, + src_cb_instance, src_cb_port_id, + src_cb_port.pins()[pin_id]); + } + } + } + } + } + return CMD_EXEC_SUCCESS; } @@ -572,13 +732,13 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( * is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then * use is_cb_exist() */ - if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) { + if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) { if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } } - if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate); if (false == adjacent_gsb.is_cb_exist(cb_type)) { @@ -739,6 +899,10 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( ModulePortId tile_chan_output_port_id = module_manager.add_port( tile_module, chan_output_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, tile_chan_output_port_id, + module_manager.port_side(sb_module_id, sb_chan_output_port_id)); VTR_LOGV( verbose, "Adding ports '%s' to tile as required by the switch block '%s'...\n", @@ -816,6 +980,10 @@ static int build_tile_module_one_port_from_cb( * avoid naming conflicts */ ModulePortId tile_module_port_id = module_manager.add_port(tile_module, tile_chan_port, chan_port_type); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, tile_module_port_id, + module_manager.port_side(cb_module, chan_port_id)); if (!frame_view) { for (size_t pin_id = 0; pin_id < chan_port.pins().size(); ++pin_id) { @@ -1007,7 +1175,7 @@ static int build_tile_port_and_nets_from_pb( const TileAnnotation& tile_annotation, const vtr::Point& pb_coord, const std::vector& pb_instances, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const size_t& ipb, - const bool& frame_view, const bool& verbose) { + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { size_t pb_instance = pb_instances[ipb]; t_physical_tile_type_ptr phy_tile = grids.get_physical_type( t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer)); @@ -1033,7 +1201,8 @@ static int build_tile_port_and_nets_from_pb( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(phy_tile)) { - grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side); + grid_pin_sides = + find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -1161,6 +1330,10 @@ static int build_tile_port_and_nets_from_pb( ModulePortId tile_module_port_id = module_manager.add_port( tile_module, pb_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, tile_module_port_id, + module_manager.port_side(pb_module, pb_module_port_id)); if (!frame_view) { ModuleNetId net = create_module_source_pin_net( module_manager, tile_module, pb_module, pb_instance, @@ -1206,7 +1379,7 @@ static int build_tile_module_ports_and_nets( const FabricTileId& fabric_tile_id, const std::vector& pb_instances, const std::map>& cb_instances, const std::vector& sb_instances, const bool& name_module_using_index, - const bool& frame_view, const bool& verbose) { + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; /* Get the submodule of Switch blocks one by one, build connections between sb @@ -1269,7 +1442,7 @@ static int build_tile_module_ports_and_nets( status_code = build_tile_port_and_nets_from_pb( module_manager, tile_module, grids, layer, vpr_device_annotation, rr_graph_view, tile_annotation, pb_coord, pb_instances, fabric_tile, - fabric_tile_id, ipb, frame_view, verbose); + fabric_tile_id, ipb, perimeter_cb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1315,8 +1488,8 @@ static int build_tile_module( const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, const bool& frame_view, - const bool& verbose) { + const bool& name_module_using_index, const bool& perimeter_cb, + const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; /* Create the module */ @@ -1463,7 +1636,7 @@ static int build_tile_module( module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, fabric_tile, fabric_tile_id, pb_instances, cb_instances, sb_instances, name_module_using_index, - frame_view, verbose); + perimeter_cb, frame_view, verbose); /* Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), @@ -1526,18 +1699,16 @@ static int build_tile_module( /******************************************************************** * Build all the tile modules *******************************************************************/ -int build_tile_modules(ModuleManager& module_manager, - DecoderLibrary& decoder_lib, - const FabricTile& fabric_tile, const DeviceGrid& grids, - const VprDeviceAnnotation& vpr_device_annotation, - const DeviceRRGSB& device_rr_gsb, - const RRGraphView& rr_graph_view, - const TileAnnotation& tile_annotation, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, - const bool& frame_view, const bool& verbose) { +int build_tile_modules( + ModuleManager& module_manager, DecoderLibrary& decoder_lib, + const FabricTile& fabric_tile, const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, + const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view, + const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& sram_orgz_type, + const bool& name_module_using_index, const bool& perimeter_cb, + const bool& frame_view, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric"); int status_code = CMD_EXEC_SUCCESS; @@ -1550,7 +1721,7 @@ int build_tile_modules(ModuleManager& module_manager, module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, circuit_lib, sram_model, sram_orgz_type, name_module_using_index, - frame_view, verbose); + perimeter_cb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_tile_modules.h b/openfpga/src/fabric/build_tile_modules.h index 83f219610..b1507e62c 100644 --- a/openfpga/src/fabric/build_tile_modules.h +++ b/openfpga/src/fabric/build_tile_modules.h @@ -25,18 +25,16 @@ /* begin namespace openfpga */ namespace openfpga { -int build_tile_modules(ModuleManager& module_manager, - DecoderLibrary& decoder_lib, - const FabricTile& fabric_tile, const DeviceGrid& grids, - const VprDeviceAnnotation& vpr_device_annotation, - const DeviceRRGSB& device_rr_gsb, - const RRGraphView& rr_graph_view, - const TileAnnotation& tile_annotation, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, - const bool& frame_view, const bool& verbose); +int build_tile_modules( + ModuleManager& module_manager, DecoderLibrary& decoder_lib, + const FabricTile& fabric_tile, const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, + const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view, + const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& sram_orgz_type, + const bool& name_module_using_index, const bool& perimeter_cb, + const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 238004e4d..fc2831d95 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -58,7 +58,8 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, const bool& verbose) { + const bool& group_config_block, const bool& perimeter_cb, + const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build FPGA fabric module"); int status = CMD_EXEC_SUCCESS; @@ -79,7 +80,7 @@ int build_top_module( rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol, sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin, - fabric_key, group_config_block); + fabric_key, group_config_block, perimeter_cb, verbose); } else { /* Build the tile instances under the top module */ status = build_top_module_tile_child_instances( @@ -87,7 +88,7 @@ int build_top_module( rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile, config_protocol, sram_model, fabric_key, group_config_block, - name_module_using_index, frame_view, verbose); + name_module_using_index, perimeter_cb, frame_view, verbose); } if (status != CMD_EXEC_SUCCESS) { diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index ee9d346d2..4e560d4f3 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -45,7 +45,8 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, const bool& verbose); + const bool& group_config_block, const bool& perimeter_cb, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 7640a969c..990472856 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -173,7 +173,7 @@ static vtr::Matrix add_top_module_grid_instances( /* Add a grid module to top_module*/ vtr::Point grid_coord(ix, iy); grid_instance_ids[ix][iy] = add_top_module_grid_instance( - module_manager, top_module, phy_tile_type, NUM_SIDES, grid_coord); + module_manager, top_module, phy_tile_type, NUM_2D_SIDES, grid_coord); } } @@ -244,7 +244,7 @@ static vtr::Matrix add_top_module_switch_block_instances( static vtr::Matrix add_top_module_connection_block_instances( ModuleManager& module_manager, const ModuleId& top_module, const DeviceRRGSB& device_rr_gsb, const t_rr_type& cb_type, - const bool& compact_routing_hierarchy) { + const bool& compact_routing_hierarchy, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Add connection block instances to top module"); @@ -261,9 +261,15 @@ static vtr::Matrix add_top_module_connection_block_instances( * We will skip those modules */ const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); + VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n", + cb_type == CHANX ? "X-" : "Y-", ix, iy); vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); if (false == rr_gsb.is_cb_exist(cb_type)) { + VTR_LOGV( + verbose, + "Skip %s connnection block at (%lu, %lu) as it does not exist\n", + cb_type == CHANX ? "X-" : "Y-", cb_coordinate.x(), cb_coordinate.y()); continue; } /* If we use compact routing hierarchy, we should instanciate the unique @@ -295,6 +301,9 @@ static vtr::Matrix add_top_module_connection_block_instances( top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], cb_instance_name); + VTR_LOGV(verbose, "Added %s connnection block '%s' (module '%s')\n", + cb_type == CHANX ? "X-" : "Y-", cb_instance_name.c_str(), + cb_module_name.c_str()); } } @@ -418,7 +427,7 @@ static void add_top_module_io_children( std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); std::string grid_module_name = generate_grid_block_module_name( grid_module_name_prefix, std::string(grid_type->name), - is_io_type(grid_type), NUM_SIDES); + is_io_type(grid_type), NUM_2D_SIDES); ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); /* Add a I/O children to top_module*/ @@ -445,7 +454,8 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block) { + const bool& group_config_block, const bool& perimeter_cb, + const bool& verbose) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; @@ -459,11 +469,11 @@ int build_top_module_fine_grained_child_instances( compact_routing_hierarchy); /* Add all the CBX and CBYs across the fabric */ cb_instance_ids[CHANX] = add_top_module_connection_block_instances( - module_manager, top_module, device_rr_gsb, CHANX, - compact_routing_hierarchy); + module_manager, top_module, device_rr_gsb, CHANX, compact_routing_hierarchy, + verbose); cb_instance_ids[CHANY] = add_top_module_connection_block_instances( - module_manager, top_module, device_rr_gsb, CHANY, - compact_routing_hierarchy); + module_manager, top_module, device_rr_gsb, CHANY, compact_routing_hierarchy, + verbose); /* Update I/O children list */ add_top_module_io_children(module_manager, top_module, grids, layer, @@ -492,7 +502,7 @@ int build_top_module_fine_grained_child_instances( status = add_top_module_global_ports_from_grid_modules( module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer, rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids, - clk_ntwk, rr_clock_lookup); + clk_ntwk, rr_clock_lookup, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index f54e07c24..b4d1677d8 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -44,7 +44,8 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block); + const bool& group_config_block, const bool& perimeter_cb, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 3c1c86c1c..b3d3224d7 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -802,13 +802,13 @@ static int build_top_module_tile_nets_between_sb_and_cb( * is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then * use is_cb_exist() */ - if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) { + if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) { if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } } - if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate); if (false == adjacent_gsb.is_cb_exist(cb_type)) { @@ -1157,8 +1157,9 @@ static void organize_top_module_tile_based_memory_modules( ********************************************************************/ static ModulePinInfo find_tile_module_chan_port( const ModuleManager& module_manager, const ModuleId& tile_module, - const vtr::Point& cb_coord_in_tile, const RRGraphView& rr_graph, - const RRGSB& rr_gsb, const t_rr_type& cb_type, const RRNodeId& chan_rr_node) { + const vtr::Point& cb_coord_in_tile, const size_t& cb_idx_in_tile, + const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, + const RRNodeId& chan_rr_node, const bool& name_module_using_index) { ModulePinInfo input_port_info; /* Generate the input port object */ switch (rr_graph.node_type(chan_rr_node)) { @@ -1170,9 +1171,15 @@ static ModulePinInfo find_tile_module_chan_port( /* Create a port description for the middle output */ std::string input_port_name = generate_cb_module_track_port_name( cb_type, IN_PORT, 0 == chan_node_track_id % 2); + std::string cb_instance_name_in_tile = + generate_connection_block_module_name(cb_type, cb_coord_in_tile); + if (name_module_using_index) { + cb_instance_name_in_tile = + generate_connection_block_module_name_using_index(cb_type, + cb_idx_in_tile); + } std::string tile_input_port_name = generate_tile_module_port_name( - generate_connection_block_module_name(cb_type, cb_coord_in_tile), - input_port_name); + cb_instance_name_in_tile, input_port_name); /* Must find a valid port id in the Switch Block module */ input_port_info.first = module_manager.find_module_port(tile_module, tile_input_port_name); @@ -1199,7 +1206,8 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, const ClockNetwork& clk_ntwk, const std::string& clk_tree_name, - const RRClockSpatialLookup& rr_clock_lookup) { + const RRClockSpatialLookup& rr_clock_lookup, + const bool& name_module_using_index) { int status = CMD_EXEC_SUCCESS; /* Ensure the clock arch tree name is valid */ @@ -1216,11 +1224,11 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( if (clk_ntwk.tree_width(clk_tree) != module_manager.module_port(top_module, top_module_port).get_width()) { VTR_LOG( - "Clock tree '%s' does not have the same width '%lu' as the port '%'s of " + "Clock tree '%s' does not have the same width '%lu' as the port '%s' of " "FPGA top module", clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree), module_manager.module_port(top_module, top_module_port) - .get_name() + .to_verilog_string() .c_str()); return CMD_EXEC_FATAL_ERROR; } @@ -1239,13 +1247,13 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( Direction entry_dir = clk_ntwk.spine_direction(spine); t_rr_type entry_track_type = clk_ntwk.spine_track_type(spine); /* Find the routing resource node of the entry point */ - RRNodeId entry_rr_node = - rr_clock_lookup.find_node(entry_point.x(), entry_point.y(), clk_tree, - clk_ntwk.spine_level(spine), pin, entry_dir); + RRNodeId entry_rr_node = rr_clock_lookup.find_node( + entry_point.x(), entry_point.y(), clk_tree, clk_ntwk.spine_level(spine), + pin, entry_dir, false); /* Get the tile module and instance at the entry point */ const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate( - entry_track_type, vtr::Point(entry_point.x(), entry_point.y())); + vtr::Point(entry_point.x(), entry_point.y())); vtr::Point cb_coord_in_tile = rr_gsb.get_sb_coordinate(); FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_cb_coordinate( entry_track_type, cb_coord_in_tile); @@ -1268,8 +1276,9 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( fabric_tile.cb_coordinates( unique_fabric_tile_id, entry_track_type)[cb_idx_in_curr_fabric_tile]; ModulePinInfo des_pin_info = find_tile_module_chan_port( - module_manager, tile_module, cb_coord_in_unique_fabric_tile, rr_graph, - rr_gsb, entry_track_type, entry_rr_node); + module_manager, tile_module, cb_coord_in_unique_fabric_tile, + cb_idx_in_curr_fabric_tile, rr_graph, rr_gsb, entry_track_type, + entry_rr_node, name_module_using_index); /* Configure the net sink */ BasicPort sink_port = @@ -1295,7 +1304,7 @@ static int build_top_module_global_net_for_given_tile_module( const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const size_t& layer, const vtr::Point& grid_coordinate, const e_side& border_side, const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile) { + const FabricTile& fabric_tile, const bool& perimeter_cb) { /* Get the tile module and instance */ FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); @@ -1392,7 +1401,7 @@ static int build_top_module_global_net_for_given_tile_module( size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index]; std::vector pin_sides = find_physical_tile_pin_side( - physical_tile, grid_pin_index, border_side); + physical_tile, grid_pin_index, border_side, perimeter_cb); BasicPort grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, @@ -1452,7 +1461,7 @@ static int build_top_module_global_net_from_tile_modules( const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const size_t& layer, const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile) { + const FabricTile& fabric_tile, const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; std::map>> io_coordinates = @@ -1530,8 +1539,8 @@ static int build_top_module_global_net_from_tile_modules( status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, - fabric_tile); + vtr::Point(ix, iy), NUM_2D_SIDES, tile_instance_ids, + fabric_tile, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1578,7 +1587,7 @@ static int build_top_module_global_net_from_tile_modules( status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - io_coordinate, io_side, tile_instance_ids, fabric_tile); + io_coordinate, io_side, tile_instance_ids, fabric_tile, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1600,7 +1609,8 @@ static int add_top_module_global_ports_from_tile_modules( const size_t& layer, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, - const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) { + const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, + const bool& perimeter_cb, const bool& name_module_using_index) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1617,12 +1627,20 @@ static int add_top_module_global_ports_from_tile_modules( BasicPort global_port_to_add; global_port_to_add.set_name( tile_annotation.global_port_name(tile_global_port)); - size_t max_port_size = 0; - for (const BasicPort& tile_port : - tile_annotation.global_port_tile_ports(tile_global_port)) { - max_port_size = std::max(tile_port.get_width(), max_port_size); + if (tile_annotation.global_port_thru_dedicated_network( + tile_global_port)) { + std::string clk_tree_name = + tile_annotation.global_port_clock_arch_tree_name(tile_global_port); + ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name); + global_port_to_add.set_width(clk_ntwk.tree_width(clk_tree)); + } else { + size_t max_port_size = 0; + for (const BasicPort& tile_port : + tile_annotation.global_port_tile_ports(tile_global_port)) { + max_port_size = std::max(tile_port.get_width(), max_port_size); + } + global_port_to_add.set_width(max_port_size); } - global_port_to_add.set_width(max_port_size); global_ports_to_add.push_back(global_port_to_add); } } @@ -1652,12 +1670,12 @@ static int add_top_module_global_ports_from_tile_modules( module_manager, top_module, top_module_port, rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk, tile_annotation.global_port_clock_arch_tree_name(tile_global_port), - rr_clock_lookup); + rr_clock_lookup, name_module_using_index); } else { status = build_top_module_global_net_from_tile_modules( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, vpr_device_annotation, grids, layer, - tile_instance_ids, fabric_tile); + tile_instance_ids, fabric_tile, perimeter_cb); } if (status == CMD_EXEC_FATAL_ERROR) { return status; @@ -1905,7 +1923,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, - const bool& frame_view, const bool& verbose) { + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status = CMD_EXEC_SUCCESS; vtr::Matrix tile_instance_ids; status = add_top_module_tile_instances(module_manager, top_module, @@ -1942,7 +1960,7 @@ int build_top_module_tile_child_instances( status = add_top_module_global_ports_from_tile_modules( module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer, rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk, - rr_clock_lookup); + rr_clock_lookup, perimeter_cb, name_module_using_index); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.h b/openfpga/src/fabric/build_top_module_child_tile_instance.h index bec2a9fa1..05b44d017 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.h +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.h @@ -44,7 +44,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, - const bool& frame_view, const bool& verbose); + const bool& perimeter_cb, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 98b256fe0..91ae8f363 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -563,6 +563,90 @@ static void add_top_module_nets_connect_grids_and_cb( } } } + + /* Iterate over the input pins of the Connection Block */ + std::vector cb_opin_sides = module_cb.get_cb_opin_sides(cb_type); + for (size_t iside = 0; iside < cb_opin_sides.size(); ++iside) { + enum e_side cb_opin_side = cb_opin_sides[iside]; + for (size_t inode = 0; + inode < module_cb.get_num_cb_opin_nodes(cb_type, cb_opin_side); + ++inode) { + /* Collect source-related information */ + RRNodeId module_opin_node = + module_cb.get_cb_opin_node(cb_type, cb_opin_side, inode); + vtr::Point cb_src_port_coord( + rr_graph.node_xlow(module_opin_node), + rr_graph.node_ylow(module_opin_node)); + std::string src_cb_port_name = generate_cb_module_grid_port_name( + cb_opin_side, grids, vpr_device_annotation, rr_graph, module_opin_node); + ModulePortId src_cb_port_id = + module_manager.find_module_port(src_cb_module, src_cb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, + src_cb_port_id)); + BasicPort src_cb_port = + module_manager.module_port(src_cb_module, src_cb_port_id); + + /* Collect sink-related information */ + /* Note that we use the instance cb pin here!!! + * because it has the correct coordinator for the grid!!! + */ + RRNodeId instance_opin_node = + rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode); + vtr::Point grid_coordinate( + rr_graph.node_xlow(instance_opin_node), + rr_graph.node_ylow(instance_opin_node)); + std::string sink_grid_module_name = + generate_grid_block_module_name_in_top_module( + std::string(GRID_MODULE_NAME_PREFIX), grids, grid_coordinate); + ModuleId sink_grid_module = + module_manager.find_module(sink_grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); + size_t sink_grid_instance = + grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; + size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_opin_node); + + t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + size_t sink_grid_pin_width = + grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; + size_t sink_grid_pin_height = + grid_type_descriptor->pin_height_offset[sink_grid_pin_index]; + BasicPort sink_grid_pin_info = + vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, + sink_grid_pin_index); + VTR_ASSERT(true == sink_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index( + grid_type_descriptor, sink_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && + subtile_index < grid_type_descriptor->capacity); + std::string sink_grid_port_name = generate_grid_port_name( + sink_grid_pin_width, sink_grid_pin_height, subtile_index, + get_rr_graph_single_node_side( + rr_graph, rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode)), + sink_grid_pin_info); + ModulePortId sink_grid_port_id = + module_manager.find_module_port(sink_grid_module, sink_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id( + sink_grid_module, sink_grid_port_id)); + BasicPort sink_grid_port = + module_manager.module_port(sink_grid_module, sink_grid_port_id); + + /* Source and sink port should match in size */ + VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width()); + + /* Create a net for each pin. Note that the src/sink tag is reverted in + * the following code. */ + for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) { + ModuleNetId net = create_module_source_pin_net( + module_manager, top_module, sink_grid_module, sink_grid_instance, + sink_grid_port_id, sink_grid_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(top_module, net, src_cb_module, + src_cb_instance, src_cb_port_id, + src_cb_port.pins()[pin_id]); + } + } + } } /******************************************************************** @@ -669,13 +753,24 @@ static void add_top_module_nets_connect_sb_and_cb( * is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then * use is_cb_exist() */ - if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) { + if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) { if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } } - if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { + /* Only for the condition where cbs are on perimeter, the neighbour cb + * will be invalid Bypass in such case on finding neighbour cbs + */ + if (TOP == side_manager.get_side() && + instance_sb_coordinate.y() == device_rr_gsb.get_gsb_range().y()) { + continue; + } + if (RIGHT == side_manager.get_side() && + instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) { + continue; + } const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate); if (false == adjacent_gsb.is_cb_exist(cb_type)) { @@ -861,7 +956,8 @@ static int build_top_module_global_net_for_given_grid_module( const BasicPort& tile_port_to_connect, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const size_t& layer, const vtr::Point& grid_coordinate, - const e_side& border_side, const vtr::Matrix& grid_instance_ids) { + const e_side& border_side, const vtr::Matrix& grid_instance_ids, + const bool& perimeter_cb) { t_physical_tile_type_ptr physical_tile = grids.get_physical_type( t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); /* Find the module name for this type of grid */ @@ -879,6 +975,7 @@ static int build_top_module_global_net_for_given_grid_module( /* Walk through each instance considering the unique sub tile and capacity * range, each instance may have an independent pin to be driven by a global * net! */ + int curr_sub_tile_start_pin_index = 0; for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) { VTR_ASSERT(1 == sub_tile.equivalent_sites.size()); int grid_pin_start_index = physical_tile->num_pins; @@ -899,16 +996,15 @@ static int build_top_module_global_net_for_given_grid_module( /* Port size must match!!! */ if (false == ref_tile_port.contained(tile_port_to_connect)) { VTR_LOG_ERROR( - "Tile annotation '%s' port '%s[%lu:%lu]' is out of the range of " - "physical tile port '%s[%lu:%lu]'!", + "Tile annotation '%s' port '%s' is out of the range of " + "physical tile port '%s'!\n", tile_annotation.global_port_name(tile_global_port).c_str(), - tile_port_to_connect.get_name().c_str(), - tile_port_to_connect.get_lsb(), tile_port_to_connect.get_msb(), - ref_tile_port.get_name().c_str(), ref_tile_port.get_lsb(), - ref_tile_port.get_msb()); + tile_port_to_connect.to_verilog_string().c_str(), + ref_tile_port.to_verilog_string().c_str()); return CMD_EXEC_FATAL_ERROR; } grid_pin_start_index = + curr_sub_tile_start_pin_index + (subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + tile_port.absolute_first_pin_index; physical_tile_port = tile_port; @@ -938,7 +1034,7 @@ static int build_top_module_global_net_for_given_grid_module( size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index]; std::vector pin_sides = find_physical_tile_pin_side( - physical_tile, grid_pin_index, border_side); + physical_tile, grid_pin_index, border_side, perimeter_cb); BasicPort grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, @@ -983,6 +1079,9 @@ static int build_top_module_global_net_for_given_grid_module( } } } + /* Note that the start pin index for a new type of tile should be calculated + * by the accumulated number of pins of previous sub tiles */ + curr_sub_tile_start_pin_index += sub_tile.num_phy_pins; } return CMD_EXEC_SUCCESS; @@ -996,7 +1095,8 @@ static int build_top_module_global_net_from_grid_modules( const ModulePortId& top_module_port, const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, const vtr::Matrix& grid_instance_ids) { + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; std::map>> io_coordinates = @@ -1043,7 +1143,7 @@ static int build_top_module_global_net_from_grid_modules( if (true == out_of_range) { VTR_LOG_ERROR( "Coordinate (%lu, %lu) in tile annotation for tile '%s' is out of " - "range (%lu:%lu, %lu:%lu)!", + "range (%lu:%lu, %lu:%lu)!\n", range.x(), range.y(), tile_name.c_str(), start_coord.x(), end_coord.x(), start_coord.y(), end_coord.y()); return CMD_EXEC_FATAL_ERROR; @@ -1074,7 +1174,8 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids); + vtr::Point(ix, iy), NUM_2D_SIDES, grid_instance_ids, + perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1121,7 +1222,7 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - io_coordinate, io_side, grid_instance_ids); + io_coordinate, io_side, grid_instance_ids, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1158,11 +1259,11 @@ static int build_top_module_global_net_from_clock_arch_tree( if (clk_ntwk.tree_width(clk_tree) != module_manager.module_port(top_module, top_module_port).get_width()) { VTR_LOG( - "Clock tree '%s' does not have the same width '%lu' as the port '%'s of " + "Clock tree '%s' does not have the same width '%lu' as the port '%s' of " "FPGA top module", clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree), module_manager.module_port(top_module, top_module_port) - .get_name() + .to_verilog_string() .c_str()); return CMD_EXEC_FATAL_ERROR; } @@ -1181,17 +1282,20 @@ static int build_top_module_global_net_from_clock_arch_tree( Direction entry_dir = clk_ntwk.spine_direction(spine); t_rr_type entry_track_type = clk_ntwk.spine_track_type(spine); /* Find the routing resource node of the entry point */ - RRNodeId entry_rr_node = - rr_clock_lookup.find_node(entry_point.x(), entry_point.y(), clk_tree, - clk_ntwk.spine_level(spine), pin, entry_dir); + RRNodeId entry_rr_node = rr_clock_lookup.find_node( + entry_point.x(), entry_point.y(), clk_tree, clk_ntwk.spine_level(spine), + pin, entry_dir, false); /* Get the connection block module and instance at the entry point */ - const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate( - entry_track_type, vtr::Point(entry_point.x(), entry_point.y())); - ModuleId cb_module = - module_manager.find_module(generate_connection_block_module_name( - entry_track_type, - vtr::Point(entry_point.x(), entry_point.y()))); + vtr::Point entry_cb_coord(entry_point.x(), entry_point.y()); + const RRGSB& rr_gsb = + device_rr_gsb.get_gsb_by_cb_coordinate(entry_cb_coord); + vtr::Point entry_unique_cb_coord = + device_rr_gsb.get_cb_unique_module(entry_track_type, entry_cb_coord) + .get_cb_coordinate(entry_track_type); + std::string cb_module_name = generate_connection_block_module_name( + entry_track_type, entry_unique_cb_coord); + ModuleId cb_module = module_manager.find_module(cb_module_name); size_t cb_instance = cb_instance_ids.at(entry_track_type)[entry_point.x()][entry_point.y()]; ModulePinInfo des_pin_info = find_connection_block_module_chan_port( @@ -1222,7 +1326,7 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup) { + const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1239,12 +1343,21 @@ int add_top_module_global_ports_from_grid_modules( BasicPort global_port_to_add; global_port_to_add.set_name( tile_annotation.global_port_name(tile_global_port)); - size_t max_port_size = 0; - for (const BasicPort& tile_port : - tile_annotation.global_port_tile_ports(tile_global_port)) { - max_port_size = std::max(tile_port.get_width(), max_port_size); + /* Dedicated network has their own sizes of port */ + if (tile_annotation.global_port_thru_dedicated_network( + tile_global_port)) { + std::string clk_tree_name = + tile_annotation.global_port_clock_arch_tree_name(tile_global_port); + ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name); + global_port_to_add.set_width(clk_ntwk.tree_width(clk_tree)); + } else { + size_t max_port_size = 0; + for (const BasicPort& tile_port : + tile_annotation.global_port_tile_ports(tile_global_port)) { + max_port_size = std::max(tile_port.get_width(), max_port_size); + } + global_port_to_add.set_width(max_port_size); } - global_port_to_add.set_width(max_port_size); global_ports_to_add.push_back(global_port_to_add); } } @@ -1268,8 +1381,7 @@ int add_top_module_global_ports_from_grid_modules( * - If the net will be directly wired to tiles, the net will drive an input * of a tile */ - if (!tile_annotation.global_port_clock_arch_tree_name(tile_global_port) - .empty()) { + if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) { status = build_top_module_global_net_from_clock_arch_tree( module_manager, top_module, top_module_port, rr_graph, device_rr_gsb, cb_instance_ids, clk_ntwk, @@ -1279,7 +1391,7 @@ int add_top_module_global_ports_from_grid_modules( status = build_top_module_global_net_from_grid_modules( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, vpr_device_annotation, grids, layer, - grid_instance_ids); + grid_instance_ids, perimeter_cb); } if (status == CMD_EXEC_FATAL_ERROR) { return status; diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index d4c18e7a7..1c04d0e25 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -42,7 +42,7 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup); + const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb); void add_top_module_nets_prog_clock(ModuleManager& module_manager, const ModuleId& top_module, diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index a7d137a5e..756985d29 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -141,7 +141,7 @@ static void organize_top_module_tile_memory_modules( const vtr::Point& tile_coord, const e_side& tile_border_side) { vtr::Point gsb_coord_range = device_rr_gsb.get_gsb_range(); - vtr::Point gsb_coord(tile_coord.x(), tile_coord.y() - 1); + vtr::Point gsb_coord(tile_coord.x(), tile_coord.y()); /* We do NOT consider SB and CBs if the gsb is not in the range! */ if ((gsb_coord.x() < gsb_coord_range.x()) && @@ -370,12 +370,13 @@ void build_top_module_configurable_regions( * Note: the organization of inter-tile aims to reduce the wire length * to connect between tiles. Therefore, it is organized as a snake * where we can avoid long wires between rows and columns + * Note: Corner I/Os only occur when perimeter cb is allowed * * +--------------------------------------------------------+ - * | +------+------+-----+------+ | - * | | I/O | I/O | ... | I/O | | - * | | TOP | TOP | | TOP | | - * | +------+------+-----+------+ | + * | +------+ +------+------+-----+------+ +------+ | + * | | I/O | | I/O | I/O | ... | I/O | | I/O | | + * | | LEFT | | TOP | TOP | | TOP | | TOP | | + * | +------+ +------+------+-----+------+ +------+ | * | +---------------------------------->tail | * | +------+ | +------+------+-----+------+ +------+ | * | | | | | | | | | | | | @@ -397,10 +398,10 @@ void build_top_module_configurable_regions( * | | LEFT | | [0] | [1] | | [i] | | |RIGHT | | * | +------+ +------+------+-----+------+ | +------+ | * +-------------------------------------------+ | - * +------+------+-----+------+ | - * | I/O | I/O | ... | I/O | | - * |BOTTOM|BOTTOM| |BOTTOM| | - * +------+------+-----+------+ | + * +------+ +------+------+-----+------+ +------+ | + * | I/O | | I/O | I/O | ... | I/O | | I/O | | + * |BOTTOM| |BOTTOM|BOTTOM| |BOTTOM| |RIGHT | | + * +------+ +------+------+-----+------+ +------+ | * head >-----------------------------------------------+ * * Inner tile connection: @@ -458,12 +459,12 @@ void organize_top_module_memory_modules( std::map>> io_coords; /* BOTTOM side I/Os */ - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { io_coords[BOTTOM].push_back(vtr::Point(ix, 0)); } /* RIGHT side I/Os */ - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { io_coords[RIGHT].push_back(vtr::Point(grids.width() - 1, iy)); } @@ -483,13 +484,12 @@ void organize_top_module_memory_modules( * +--------+ +--------+ * */ - for (size_t ix = grids.width() - 2; ix >= 1; --ix) { + for (size_t ix = grids.width() - 1; ix >= 1; --ix) { io_coords[TOP].push_back(vtr::Point(ix, grids.height() - 1)); } - io_coords[TOP].push_back(vtr::Point(0, grids.height() - 1)); /* LEFT side I/Os */ - for (size_t iy = grids.height() - 2; iy >= 1; --iy) { + for (size_t iy = grids.height() - 1; iy >= 1; --iy) { io_coords[LEFT].push_back(vtr::Point(0, iy)); } @@ -529,7 +529,7 @@ void organize_top_module_memory_modules( module_manager, top_module, circuit_lib, config_protocol.type(), sram_model, grids, grid_instance_ids, device_rr_gsb, rr_graph, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, layer, - core_coord, NUM_SIDES); + core_coord, NUM_2D_SIDES); } /* Split memory modules into different regions */ @@ -1110,14 +1110,14 @@ static void add_top_module_nets_cmos_memory_bank_config_bus( /* Each memory bank has a unified number of BL/WLs */ size_t num_bls = 0; for (const auto& curr_config_bits : num_config_bits) { - num_bls = - std::max(num_bls, find_memory_decoder_data_size(curr_config_bits.first)); + num_bls = std::max( + num_bls, find_memory_decoder_data_size(curr_config_bits.first, 0, true)); } size_t num_wls = 0; for (const auto& curr_config_bits : num_config_bits) { - num_wls = - std::max(num_wls, find_memory_decoder_data_size(curr_config_bits.first)); + num_wls = std::max( + num_wls, find_memory_decoder_data_size(curr_config_bits.first, 0, false)); } /* Create separated memory bank circuitry, i.e., BL/WL decoders for each diff --git a/openfpga/src/fabric/build_top_module_utils.cpp b/openfpga/src/fabric/build_top_module_utils.cpp index ebf52eb77..586163bfa 100644 --- a/openfpga/src/fabric/build_top_module_utils.cpp +++ b/openfpga/src/fabric/build_top_module_utils.cpp @@ -79,7 +79,7 @@ std::string generate_grid_module_port_name_in_top_module( * RIGHT/LEFT side: CHANX *******************************************************************/ t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side) { - VTR_ASSERT(NUM_SIDES != sb_side); + VTR_ASSERT(NUM_2D_SIDES != sb_side); if ((TOP == sb_side) || (BOTTOM == sb_side)) { return CHANY; @@ -96,17 +96,17 @@ t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side) { *******************************************************************/ vtr::Point find_top_module_gsb_coordinate_by_sb_side( const RRGSB& rr_gsb, const e_side& sb_side) { - VTR_ASSERT(NUM_SIDES != sb_side); + VTR_ASSERT(NUM_2D_SIDES != sb_side); vtr::Point gsb_coordinate; - if ((TOP == sb_side) || (LEFT == sb_side)) { + if ((BOTTOM == sb_side) || (LEFT == sb_side)) { gsb_coordinate.set_x(rr_gsb.get_x()); gsb_coordinate.set_y(rr_gsb.get_y()); return gsb_coordinate; } - VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side)); + VTR_ASSERT((RIGHT == sb_side) || (TOP == sb_side)); /* RIGHT side: x + 1 */ if (RIGHT == sb_side) { @@ -115,9 +115,9 @@ vtr::Point find_top_module_gsb_coordinate_by_sb_side( } /* BOTTOM side: y - 1 */ - if (BOTTOM == sb_side) { + if (TOP == sb_side) { gsb_coordinate.set_x(rr_gsb.get_x()); - gsb_coordinate.set_y(rr_gsb.get_y() - 1); + gsb_coordinate.set_y(rr_gsb.get_y() + 1); } return gsb_coordinate; diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.cpp b/openfpga/src/fabric/fabric_hierarchy_writer.cpp index 46daae954..6b24a4484 100644 --- a/openfpga/src/fabric/fabric_hierarchy_writer.cpp +++ b/openfpga/src/fabric/fabric_hierarchy_writer.cpp @@ -1,12 +1,14 @@ /*************************************************************************************** * Output internal structure of Module Graph hierarchy to file formats ***************************************************************************************/ +#include /* Headers from vtrutil library */ #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_time.h" /* Headers from openfpgautil library */ +#include "command_exit_codes.h" #include "fabric_hierarchy_writer.h" #include "openfpga_digest.h" #include "openfpga_naming.h" @@ -14,6 +16,32 @@ /* begin namespace openfpga */ namespace openfpga { +/** Identify if the module has no child whose name matches the filter */ +static bool module_filter_all_children(const ModuleManager& module_manager, + const ModuleId& curr_module, + const ModuleNameMap& module_name_map, + const std::string& module_name_filter) { + for (const ModuleId& child_module : + module_manager.child_modules(curr_module)) { + /* Filter out the names which do not match the pattern */ + std::string child_module_name = module_manager.module_name(child_module); + if (module_name_map.name_exist(child_module_name)) { + child_module_name = module_name_map.name(child_module_name); + } + std::string pattern = module_name_filter; + std::regex star_replace("\\*"); + std::regex questionmark_replace("\\?"); + std::string wildcard_pattern = + std::regex_replace(std::regex_replace(pattern, star_replace, ".*"), + questionmark_replace, "."); + std::regex wildcard_regex(wildcard_pattern); + if (std::regex_match(child_module_name, wildcard_regex)) { + return false; + } + } + return true; +} + /*************************************************************************************** * Recursively output child module of the parent_module to a text file * We use Depth-First Search (DFS) here so that we can output a tree down to @@ -23,52 +51,88 @@ namespace openfpga { static int rec_output_module_hierarchy_to_text_file( std::fstream& fp, const size_t& hie_depth_to_stop, const size_t& current_hie_depth, const ModuleManager& module_manager, - const ModuleId& parent_module, const bool& verbose) { + const ModuleId& parent_module, const ModuleNameMap& module_name_map, + const std::string& module_name_filter, const bool& verbose) { /* Stop if hierarchy depth is beyond the stop line */ if (hie_depth_to_stop < current_hie_depth) { - return 0; + return CMD_EXEC_SUCCESS; } if (false == valid_file_stream(fp)) { - return 2; + return CMD_EXEC_FATAL_ERROR; } + /* Check if all the child module has not qualified grand-child, use leaf for + * this level */ + bool use_list = true; + for (const ModuleId& child_module : + module_manager.child_modules(parent_module)) { + if (!module_filter_all_children(module_manager, child_module, + module_name_map, module_name_filter)) { + use_list = false; + break; + } + } + /* For debug use only + VTR_LOGV(verbose, "Current depth: %lu, Target depth: %lu\n", + current_hie_depth, hie_depth_to_stop); + */ + std::string parent_module_name = module_manager.module_name(parent_module); + if (module_name_map.name_exist(parent_module_name)) { + parent_module_name = module_name_map.name(parent_module_name); + } + VTR_LOGV( + use_list && verbose, "Use list as module '%s' contains only leaf nodes\n", + module_name_map.name(module_manager.module_name(parent_module)).c_str()); + /* Iterate over all the child module */ for (const ModuleId& child_module : module_manager.child_modules(parent_module)) { - if (false == write_space_to_file(fp, current_hie_depth * 2)) { - return 2; - } - if (true != module_manager.valid_module_id(child_module)) { - VTR_LOGV_ERROR(verbose, "Unable to find the child module '%u'!\n", - size_t(child_module)); - return 1; + VTR_LOGV_ERROR( + verbose, + "Unable to find the child module '%s' under its parent '%s'!\n", + module_manager.module_name(child_module).c_str(), + module_manager.module_name(parent_module).c_str()); + return CMD_EXEC_FATAL_ERROR; } - fp << "- "; - fp << module_manager.module_name(child_module); - - /* If this is the leaf node, we leave a new line - * Otherwise, we will leave a ':' to be compatible to YAML file format - */ - if ((0 != module_manager.child_modules(child_module).size()) && - (hie_depth_to_stop >= current_hie_depth + 1)) { - fp << ":"; + /* Filter out the names which do not match the pattern */ + std::string child_module_name = module_manager.module_name(child_module); + if (module_name_map.name_exist(child_module_name)) { + child_module_name = module_name_map.name(child_module_name); + } + std::string pattern = module_name_filter; + std::regex star_replace("\\*"); + std::regex questionmark_replace("\\?"); + std::string wildcard_pattern = + std::regex_replace(std::regex_replace(pattern, star_replace, ".*"), + questionmark_replace, "."); + std::regex wildcard_regex(wildcard_pattern); + if (!std::regex_match(child_module_name, wildcard_regex)) { + continue; } - fp << "\n"; + if (false == write_space_to_file(fp, current_hie_depth * 2)) { + return CMD_EXEC_FATAL_ERROR; + } + if (hie_depth_to_stop == current_hie_depth || use_list) { + fp << "- " << child_module_name.c_str() << "\n"; + } else { + fp << child_module_name.c_str() << ":\n"; + } /* Go to next level */ int status = rec_output_module_hierarchy_to_text_file( fp, hie_depth_to_stop, current_hie_depth + 1, /* Increment the depth for the next level */ - module_manager, child_module, verbose); - if (0 != status) { + module_manager, child_module, module_name_map, module_name_filter, + verbose); + if (status != CMD_EXEC_SUCCESS) { return status; } } - return 0; + return CMD_EXEC_SUCCESS; } /*************************************************************************************** @@ -83,11 +147,11 @@ static int rec_output_module_hierarchy_to_text_file( * Return 1 if there are more serious bugs in the architecture * Return 2 if fail when creating files ***************************************************************************************/ -int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const std::string& fname, - const size_t& hie_depth_to_stop, - const bool& verbose) { +int write_fabric_hierarchy_to_text_file( + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const std::string& fname, const std::string& root_module_names, + const std::string& module_name_filter, const size_t& hie_depth_to_stop, + const bool& exclude_empty_modules, const bool& verbose) { std::string timer_message = std::string("Write fabric hierarchy to plain-text file '") + fname + std::string("'"); @@ -111,35 +175,61 @@ int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager, /* Validate the file stream */ check_file_stream(fname.c_str(), fp); - /* Find top-level module */ - std::string top_module_name = - module_name_map.name(generate_fpga_top_module_name()); - ModuleId top_module = module_manager.find_module(top_module_name); - if (true != module_manager.valid_module_id(top_module)) { - VTR_LOGV_ERROR(verbose, "Unable to find the top-level module '%s'!\n", - top_module_name.c_str()); - return 1; + size_t cnt = 0; + /* Use regular expression to capture the module whose name matches the pattern + */ + for (ModuleId curr_module : module_manager.modules()) { + std::string curr_module_name = module_manager.module_name(curr_module); + if (module_name_map.name_exist(curr_module_name)) { + curr_module_name = module_name_map.name(curr_module_name); + } + std::string pattern = root_module_names; + std::regex star_replace("\\*"); + std::regex questionmark_replace("\\?"); + std::string wildcard_pattern = + std::regex_replace(std::regex_replace(pattern, star_replace, ".*"), + questionmark_replace, "."); + std::regex wildcard_regex(wildcard_pattern); + if (!std::regex_match(curr_module_name, wildcard_regex)) { + continue; + } + /* Filter out module without children if required */ + if (exclude_empty_modules && + module_filter_all_children(module_manager, curr_module, module_name_map, + module_name_filter)) { + continue; + } + VTR_LOGV(verbose, "Select module '%s' as root\n", curr_module_name.c_str()); + /* Record current depth of module: top module is the root with 0 depth */ + size_t hie_depth = 0; + + fp << curr_module_name << ":" + << "\n"; + + /* Visit child module recursively and output the hierarchy */ + int err_code = rec_output_module_hierarchy_to_text_file( + fp, hie_depth_to_stop, hie_depth + 1, /* Start with level 1 */ + module_manager, curr_module, module_name_map, module_name_filter, + verbose); + /* Catch error code and exit if required */ + if (err_code == CMD_EXEC_FATAL_ERROR) { + return err_code; + } + cnt++; } - /* Record current depth of module: top module is the root with 0 depth */ - size_t hie_depth = 0; - - if (hie_depth_to_stop < hie_depth) { - return 0; + if (cnt == 0) { + VTR_LOG_ERROR( + "Unable to find any module matching the root module name pattern '%s'!\n", + root_module_names.c_str()); + return CMD_EXEC_FATAL_ERROR; } - - fp << top_module_name << ":" - << "\n"; - - /* Visit child module recursively and output the hierarchy */ - int err_code = rec_output_module_hierarchy_to_text_file( - fp, hie_depth_to_stop, hie_depth + 1, /* Start with level 1 */ - module_manager, top_module, verbose); + VTR_LOG("Outputted %lu modules as root\n", cnt); /* close a file */ fp.close(); - return err_code; + return CMD_EXEC_SUCCESS; } } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.h b/openfpga/src/fabric/fabric_hierarchy_writer.h index 71fbea25b..c12d6af2f 100644 --- a/openfpga/src/fabric/fabric_hierarchy_writer.h +++ b/openfpga/src/fabric/fabric_hierarchy_writer.h @@ -14,11 +14,11 @@ /* begin namespace openfpga */ namespace openfpga { -int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const std::string& fname, - const size_t& hie_depth_to_stop, - const bool& verbose); +int write_fabric_hierarchy_to_text_file( + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const std::string& fname, const std::string& root_module_names, + const std::string& module_name_filter, const size_t& hie_depth_to_stop, + const bool& exclude_empty_modules, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/fabric_pin_physical_location_xml_constants.h b/openfpga/src/fabric/fabric_pin_physical_location_xml_constants.h new file mode 100644 index 000000000..70ff67a6d --- /dev/null +++ b/openfpga/src/fabric/fabric_pin_physical_location_xml_constants.h @@ -0,0 +1,13 @@ +#ifndef FABRIC_PIN_PHYSICAL_LOCATION_XML_CONSTANTS_H +#define FABRIC_PIN_PHYSICAL_LOCATION_XML_CONSTANTS_H + +/* Constants required by XML parser */ + +constexpr const char* XML_PINLOC_ROOT_NAME = "pin_location"; +constexpr const char* XML_MODULE_NODE_NAME = "module"; +constexpr const char* XML_MODULE_ATTRIBUTE_NAME = "name"; +constexpr const char* XML_MODULE_PINLOC_NODE_NAME = "loc"; +constexpr const char* XML_MODULE_PINLOC_ATTRIBUTE_PIN = "pin"; +constexpr const char* XML_MODULE_PINLOC_ATTRIBUTE_SIDE = "side"; + +#endif diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp index 48d03095d..82aa1732a 100644 --- a/openfpga/src/fabric/module_manager.cpp +++ b/openfpga/src/fabric/module_manager.cpp @@ -304,6 +304,12 @@ std::vector ModuleManager::module_ports_by_type( return ports; } +e_side ModuleManager::port_side(const ModuleId& module_id, + const ModulePortId& port_id) const { + VTR_ASSERT(valid_module_port_id(module_id, port_id)); + return port_sides_[module_id][port_id]; +} + /* Find a list of port ids of a module by a given types */ std::vector ModuleManager::module_port_ids_by_type( const ModuleId& module_id, const enum e_module_port_type& port_type) const { @@ -746,6 +752,7 @@ ModuleId ModuleManager::add_module(const std::string& name) { port_is_wire_.emplace_back(); port_is_mappable_io_.emplace_back(); port_is_register_.emplace_back(); + port_sides_.emplace_back(); port_preproc_flags_.emplace_back(); num_nets_.emplace_back(0); @@ -789,6 +796,8 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, port_ids_[module].push_back(port); ports_[module].push_back(port_info); port_types_[module].push_back(port_type); + /* Deposit invalid value for each side */ + port_sides_[module].push_back(NUM_2D_SIDES); port_is_wire_[module].push_back(false); port_is_mappable_io_[module].push_back(false); port_is_register_[module].push_back(false); @@ -893,6 +902,15 @@ void ModuleManager::set_port_preproc_flag(const ModuleId& module, port_preproc_flags_[module][port] = preproc_flag; } +/* Set the side for a pin of a port port */ +void ModuleManager::set_port_side(const ModuleId& module, + const ModulePortId& port, + const e_side& pin_side) { + /* Must find something, otherwise drop an error */ + VTR_ASSERT(valid_module_port_id(module, port)); + port_sides_[module][port] = pin_side; +} + /* Add a child module to a parent module */ void ModuleManager::add_child_module(const ModuleId& parent_module, const ModuleId& child_module, diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h index 235719cbc..6f9f2e267 100644 --- a/openfpga/src/fabric/module_manager.h +++ b/openfpga/src/fabric/module_manager.h @@ -9,6 +9,7 @@ #include "module_manager_fwd.h" #include "openfpga_port.h" +#include "physical_types.h" #include "vtr_geometry.h" #include "vtr_vector.h" @@ -273,6 +274,10 @@ class ModuleManager { /* Find the type of a port */ ModuleManager::e_module_port_type port_type(const ModuleId& module, const ModulePortId& port) const; + /* Get the physical side of a port. Note that not every pin has a valid side. + * An invalid value NUM_SIDES will be returned when the pin does not has a + * specific physical location */ + e_side port_side(const ModuleId& module, const ModulePortId& port) const; /* Find if a port is a wire connection */ bool port_is_wire(const ModuleId& module, const ModulePortId& port) const; /* Find if a port is mappable to an I/O from users' implementations */ @@ -369,6 +374,11 @@ class ModuleManager { /* Set the preprocessing flag for a port */ void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag); + /* Set side to a given pin of a module port. Note that the pin id must be a + * valid one. Otherwise, abort and error out. The valid pin range can be get + * from module_port().pins() */ + void set_port_side(const ModuleId& module, const ModulePortId& port, + const e_side& pin_side); /** @brief Add a child module to a parent module. * By default, it considers the child module as an I/O child, and update the * children list of I/O modules inside It not needed, just turn it off. Then @@ -626,6 +636,8 @@ class ModuleManager { ports_; /* List of ports for each Module */ vtr::vector> port_types_; /* Type of ports */ + vtr::vector> + port_sides_; /* Type of ports */ vtr::vector> port_is_mappable_io_; /* If the port is mappable to an I/O for user's implementations */ diff --git a/openfpga/src/fabric/write_xml_fabric_pin_physical_location.cpp b/openfpga/src/fabric/write_xml_fabric_pin_physical_location.cpp new file mode 100644 index 000000000..959d7c252 --- /dev/null +++ b/openfpga/src/fabric/write_xml_fabric_pin_physical_location.cpp @@ -0,0 +1,192 @@ +/*************************************************************************************** + * Output internal structure of module graph to XML format + ***************************************************************************************/ +/* Headers from system goes first */ +#include +#include +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from openfpgautil library */ +#include "command_exit_codes.h" +#include "openfpga_digest.h" +#include "openfpga_side_manager.h" + +/* Headers from arch openfpga library */ +#include "fabric_pin_physical_location_xml_constants.h" +#include "write_xml_fabric_pin_physical_location.h" +#include "write_xml_utils.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * This function write header information to a pin location file + *******************************************************************/ +static void write_xml_fabric_pin_physical_location_file_head( + std::fstream& fp, const bool& include_time_stamp) { + valid_file_stream(fp); + + fp << "" << std::endl; + fp << std::endl; +} + +/******************************************************************** + * This function write header information to a pin location file + *******************************************************************/ +static int write_xml_fabric_module_pin_phy_loc( + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& curr_module, const bool& show_invalid_side, + const bool& verbose) { + valid_file_stream(fp); + + /* If show invalid side is off, we should check if there is any valid side. If + * there are not any, skip this module */ + bool skip_curr_module = true; + for (ModulePortId curr_port_id : module_manager.module_ports(curr_module)) { + SideManager side_mgr(module_manager.port_side(curr_module, curr_port_id)); + if (side_mgr.validate()) { + skip_curr_module = false; + break; + } + } + + if (!show_invalid_side && skip_curr_module) { + VTR_LOGV(verbose, "Skip module '%s' as it contains no valid sides\n", + module_manager.module_name(curr_module).c_str()); + return CMD_EXEC_SUCCESS; + } + /* Print a head */ + write_tab_to_file(fp, 1); + fp << "<" << XML_MODULE_NODE_NAME; + write_xml_attribute(fp, XML_MODULE_ATTRIBUTE_NAME, + module_manager.module_name(curr_module).c_str()); + fp << ">" + << "\n"; + + size_t cnt = 0; + for (ModulePortId curr_port_id : module_manager.module_ports(curr_module)) { + BasicPort curr_port = module_manager.module_port(curr_module, curr_port_id); + SideManager side_mgr(module_manager.port_side(curr_module, curr_port_id)); + if (!side_mgr.validate() && !show_invalid_side) { + continue; + } + for (int curr_pin_id : curr_port.pins()) { + BasicPort curr_pin(curr_port.get_name(), curr_pin_id, curr_pin_id); + std::string curr_port_str = generate_xml_port_name(curr_pin); + write_tab_to_file(fp, 2); + fp << "<" << XML_MODULE_PINLOC_NODE_NAME; + write_xml_attribute(fp, XML_MODULE_PINLOC_ATTRIBUTE_PIN, + curr_port_str.c_str()); + write_xml_attribute(fp, XML_MODULE_PINLOC_ATTRIBUTE_SIDE, + side_mgr.c_str()); + fp << "/>"; + fp << std::endl; + } + cnt++; + } + VTR_LOGV(verbose, "Output %lu ports with physical sides for module '%s'\n", + cnt, module_manager.module_name(curr_module).c_str()); + + /* Print a tail */ + write_tab_to_file(fp, 1); + fp << "" + << "\n"; + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Top-level function + *******************************************************************/ +int write_xml_fabric_pin_physical_location(const char* fname, + const std::string& module_name, + const ModuleManager& module_manager, + const bool& show_invalid_side, + const bool& include_time_stamp, + const bool& verbose) { + vtr::ScopedStartFinishTimer timer("Write fabric pin physical location"); + + /* Create a file handler */ + std::fstream fp; + /* Open the file stream */ + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + write_xml_fabric_pin_physical_location_file_head(fp, include_time_stamp); + + /* Write the root node */ + fp << "<" << XML_PINLOC_ROOT_NAME; + fp << ">" + << "\n"; + + /* If module name is not specified, walk through all the modules and write + * physical pin location when any is specified */ + short cnt = 0; + /* Use regular expression to capture the module whose name matches the pattern + */ + for (ModuleId curr_module : module_manager.modules()) { + std::string curr_module_name = module_manager.module_name(curr_module); + std::string pattern = module_name; + std::regex star_replace("\\*"); + std::regex questionmark_replace("\\?"); + std::string wildcard_pattern = + std::regex_replace(std::regex_replace(pattern, star_replace, ".*"), + questionmark_replace, "."); + std::regex wildcard_regex(wildcard_pattern); + if (!std::regex_match(curr_module_name, wildcard_regex)) { + continue; + } + VTR_LOGV(verbose, "Outputted pin physical location of module '%s'.\n", + curr_module_name.c_str()); + /* Write the pin physical location for this module */ + int err_code = write_xml_fabric_module_pin_phy_loc( + fp, module_manager, curr_module, show_invalid_side, verbose); + if (err_code != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } + cnt++; + } + + /* Finish writing the root node */ + fp << "" + << "\n"; + + /* Close the file stream */ + fp.close(); + + /* If there is no match, error out! */ + if (cnt == 0) { + VTR_LOG_ERROR( + "Invalid regular expression for module name '%s' which does not match " + "any in current fabric!\n", + module_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + + VTR_LOGV(verbose, "Outputted %lu modules with pin physical location.\n", cnt); + + return CMD_EXEC_SUCCESS; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fabric/write_xml_fabric_pin_physical_location.h b/openfpga/src/fabric/write_xml_fabric_pin_physical_location.h new file mode 100644 index 000000000..6dd0ef214 --- /dev/null +++ b/openfpga/src/fabric/write_xml_fabric_pin_physical_location.h @@ -0,0 +1,27 @@ +#ifndef WRITE_XML_FABRIC_PIN_PHYSICAL_LOCATION_H +#define WRITE_XML_FABRIC_PIN_PHYSICAL_LOCATION_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "module_manager.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +int write_xml_fabric_pin_physical_location(const char* fname, + const std::string& module_name, + const ModuleManager& module_manager, + const bool& show_invalid_side, + const bool& include_time_stamp, + const bool& verbose); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index 9d7b89789..a3fb26432 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -230,6 +230,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_routing_annotation(), vpr_ctx.device().rr_graph, openfpga_ctx.device_rr_gsb(), openfpga_ctx.flow_manager().compress_routing(), verbose); + VTR_LOGV(verbose, "Done\n"); VTR_LOGV(verbose, "Decoded %lu configuration bits into %lu blocks\n", diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index d8e4f17fb..cbc5e99b1 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -1007,7 +1007,7 @@ void build_grid_bitstream( bitstream_manager, parent_block, module_manager, module_name_map, fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, place_annotation, - bitstream_annotation, grids, layer, grid_coord, NUM_SIDES, verbose); + bitstream_annotation, grids, layer, grid_coord, NUM_2D_SIDES, verbose); } } VTR_LOGV(verbose, "Done\n"); diff --git a/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp b/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp index 77c7b3e8a..9a26e8a1f 100644 --- a/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp +++ b/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp @@ -90,9 +90,9 @@ IoMap build_fpga_io_mapping_info( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index d299c635e..dd2cc7329 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -60,11 +60,17 @@ static void build_switch_block_mux_bitstream( * - There is a net mapped to cur_rr_node: we find the path id */ int path_id = DEFAULT_PATH_ID; - if (ClusterNetId::INVALID() != output_net) { + VTR_LOGV(verbose, "Prev node '%lu' for src_node '%lu'\n", + size_t(routing_annotation.rr_node_prev_node(cur_rr_node)), + size_t(cur_rr_node)); + AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net); + if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) { /* We must have a valid previous node that is supposed to drive the source * node! */ VTR_ASSERT(routing_annotation.rr_node_prev_node(cur_rr_node)); for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { + VTR_LOGV(verbose, "Path: %lu -> Driver node '%lu' for src_node '%lu'\n", + inode, size_t(drive_rr_nodes[inode]), size_t(cur_rr_node)); if ((input_nets[inode] == output_net) && (drive_rr_nodes[inode] == routing_annotation.rr_node_prev_node(cur_rr_node))) { @@ -135,7 +141,6 @@ static void build_switch_block_mux_bitstream( /* Add output nets */ std::string output_net_ids; - AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net); if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) { output_net_ids += atom_ctx.nlist.net_name(output_atom_net); } else { @@ -380,7 +385,8 @@ static void build_connection_block_interc_bitstream( const bool& verbose) { RRNodeId src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index); - VTR_LOGV(verbose, "\tGenerating bitstream for IPIN '%lu'\n", ipin_index); + VTR_LOGV(verbose, "\tGenerating bitstream for IPIN '%lu'. Details: %s\n", + ipin_index, rr_graph.node_coordinate_to_string(src_rr_node).c_str()); /* Consider configurable edges only */ std::vector driver_rr_edges = diff --git a/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.cpp new file mode 100644 index 000000000..b4fcd7851 --- /dev/null +++ b/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.cpp @@ -0,0 +1,283 @@ +/******************************************************************** + * This file includes functions to build bitstream from a mapped + * FPGA fabric. + * We decode the bitstream from configuration of routing multiplexers + * and Look-Up Tables (LUTs) which locate in CLBs and global routing + *architecture + *******************************************************************/ +#include +#include + +/* Headers from vtrutil library */ +#include "extract_device_non_fabric_bitstream.h" +#include "openfpga_pb_parser.h" +#include "pb_type_utils.h" +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* begin namespace openfpga */ +namespace openfpga { + +#define PRINT_LAYOUT_NAME "__layout__" + +/******************************************************************** + * Extract data from the targetted PB + * 1. If it is primitive + * a. If it match the targetted PB, try to get data from + * param of attr depends on what being defined in XML + * b. If it is does not match, do nothing + * 2. If it is not primitive, then we loop for the child + *******************************************************************/ +static bool extract_pb_data(std::fstream& fp, const AtomContext& atom_ctx, + const t_pb* op_pb, const t_pb_type* target_pb_type, + const NonFabricBitstreamPBSetting& setting) { + t_pb_graph_node* pb_graph_node = op_pb->pb_graph_node; + t_pb_type* pb_type = pb_graph_node->pb_type; + bool found_pb = false; + if (true == is_primitive_pb_type(pb_type)) { + if (target_pb_type == pb_type) { + AtomBlockId atom_blk = atom_ctx.nlist.find_block(op_pb->name); + VTR_ASSERT(atom_blk); + if (setting.type == "param") { + for (const auto& param_search : atom_ctx.nlist.block_params(atom_blk)) { + std::string param = param_search.first; + std::string content = param_search.second; + if (setting.content == param) { + fp << ",\n \"data\" : \"" << content.c_str() << "\""; + break; + } + } + } else { + VTR_ASSERT(setting.type == "attr"); + for (const auto& attr_search : atom_ctx.nlist.block_attrs(atom_blk)) { + std::string attr = attr_search.first; + std::string content = attr_search.second; + if (setting.content == attr) { + fp << ",\n \"data\" : \"" << content.c_str() << "\""; + break; + } + } + } + found_pb = true; + } + } else { + t_mode* mapped_mode = &(pb_graph_node->pb_type->modes[op_pb->mode]); + for (int ipb = 0; ipb < mapped_mode->num_pb_type_children && !found_pb; + ++ipb) { + /* Each child may exist multiple times in the hierarchy*/ + for (int jpb = 0; + jpb < mapped_mode->pb_type_children[ipb].num_pb && !found_pb; + ++jpb) { + if ((nullptr != op_pb->child_pbs[ipb]) && + (nullptr != op_pb->child_pbs[ipb][jpb].name)) { + found_pb = + extract_pb_data(fp, atom_ctx, &(op_pb->child_pbs[ipb][jpb]), + target_pb_type, setting); + } + } + } + } + return found_pb; +} + +/******************************************************************** + * Extract data from the targetted PB (from that particular grid) + *******************************************************************/ +static void extract_grid_non_fabric_bitstream( + std::fstream& fp, const VprContext& vpr_ctx, + const ClusterBlockId& cluster_block_id, const t_pb_type* target_pb_type, + const NonFabricBitstreamPBSetting setting) { + const ClusteringContext& clustering_ctx = vpr_ctx.clustering(); + const AtomContext& atom_ctx = vpr_ctx.atom(); + + if (ClusterBlockId::INVALID() != cluster_block_id) { + const t_pb* op_pb = clustering_ctx.clb_nlist.block_pb(cluster_block_id); + extract_pb_data(fp, atom_ctx, op_pb, target_pb_type, setting); + } else { + // Grid is valid, but this resource is not being used + } +} + +/******************************************************************** + * Extract data from the targetted PB (from the device) + *******************************************************************/ +static void extract_device_non_fabric_pb_bitstream( + std::fstream& fp, const NonFabricBitstreamPBSetting setting, + const std::string& target_parent_pb_name, const t_pb_type* target_pb_type, + const VprContext& vpr_ctx) { + const DeviceContext& device_ctx = vpr_ctx.device(); + const PlacementContext& placement_ctx = vpr_ctx.placement(); + const DeviceGrid& grids = device_ctx.grid; + const size_t& layer = 0; + + // Loop logic block one by one + if (target_parent_pb_name != PRINT_LAYOUT_NAME) { + fp << ",\n \"grid\" : ["; + } + size_t grid_count = 0; + for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + t_physical_tile_loc phy_tile_loc(ix, iy, layer); + t_physical_tile_type_ptr grid_type = + grids.get_physical_type(phy_tile_loc); + // Bypass EMPTY grid + if (true == is_empty_type(grid_type)) { + continue; + } + + // Skip width > 1 or height > 1 tiles (mostly heterogeneous blocks) + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { + continue; + } + + // Skip if this grid is not what we are looking for + if (target_parent_pb_name == PRINT_LAYOUT_NAME) { + if (grid_count) { + fp << ",\n"; + } + fp << " {\n"; + fp << " \"x\" : " << (uint32_t)(ix) << ",\n"; + fp << " \"y\" : " << (uint32_t)(iy) << ",\n"; + fp << " \"name\" : \"" << grid_type->name << "\"\n"; + fp << " }"; + grid_count++; + continue; + } + + // Skip if this grid is not what we are looking for + if (target_parent_pb_name != std::string(grid_type->name)) { + continue; + } + + // Get the mapped blocks to this grid + for (int isubtile = 0; isubtile < grid_type->capacity; ++isubtile) { + ClusterBlockId cluster_blk_id = + placement_ctx.grid_blocks().block_at_location( + {(int)ix, (int)iy, (int)isubtile, (int)layer}); + if (grid_count) { + fp << ","; + } + fp << "\n"; + fp << " {\n"; + fp << " \"x\" : " << (uint32_t)(ix) << ",\n"; + fp << " \"y\" : " << (uint32_t)(iy); + extract_grid_non_fabric_bitstream(fp, vpr_ctx, cluster_blk_id, + target_pb_type, setting); + fp << "\n }"; + grid_count++; + } + } + } + if (target_parent_pb_name == PRINT_LAYOUT_NAME) { + fp << "\n"; + } else { + fp << "\n ]"; + } +} + +/******************************************************************** + * Search the PB type based on the given name defined in XML + *******************************************************************/ +static t_pb_type* find_pb_type(const DeviceContext& device_ctx, + const std::string& parent_pb, + const std::string& pb) { + t_pb_type* pb_type = nullptr; + openfpga::PbParser pb_parser(pb); + std::vector names = pb_parser.parents(); + names.push_back(pb_parser.leaf()); + for (const t_logical_block_type& lb_type : device_ctx.logical_block_types) { + /* Bypass nullptr for pb_type head */ + if (nullptr == lb_type.pb_type) { + continue; + } + + /* Check the name of the top-level pb_type, if it does not match, we can + * bypass */ + if (parent_pb != std::string(lb_type.pb_type->name)) { + continue; + } + + /* Match the name in the top-level, we go further to search the pb_type in + * the graph */ + pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, names, + pb_parser.modes()); + if (nullptr == pb_type) { + continue; + } + break; + } + return pb_type; +} + +/******************************************************************** + * A top-level function to extract data based on non-fabric bitstream setting + *******************************************************************/ +void extract_device_non_fabric_bitstream(const VprContext& vpr_ctx, + const OpenfpgaContext& openfpga_ctx, + const bool& verbose) { + std::string timer_message = + std::string("\nBuild non-fabric bitstream for implementation '") + + vpr_ctx.atom().nlist.netlist_name() + std::string("'\n"); + vtr::ScopedStartFinishTimer timer(timer_message); + const openfpga::BitstreamSetting& bitstream_setting = + openfpga_ctx.bitstream_setting(); + std::vector non_fabric_setting = + bitstream_setting.non_fabric(); + + // Only proceed if it is defined in bitstream_setting.xml + if (non_fabric_setting.size()) { + // Go through each non_fabric settting + for (auto setting : non_fabric_setting) { + std::fstream fp; + fp.open(setting.file.c_str(), std::fstream::out); + fp << "{\n"; + fp << " \"" << setting.name.c_str() << "\" : [\n"; + if (setting.name == PRINT_LAYOUT_NAME) { + extract_device_non_fabric_pb_bitstream( + fp, NonFabricBitstreamPBSetting{}, setting.name, nullptr, vpr_ctx); + } else { + int pb_count = 0; + // Extract each needed PB data + for (auto pb_setting : setting.pbs) { + std::string pb_type = setting.name + pb_setting.pb; + t_pb_type* target_pb_type = + find_pb_type(vpr_ctx.device(), setting.name, pb_type); + if (pb_count) { + fp << ",\n"; + } + fp << " {\n"; + fp << " \"pb\" : \"" << pb_type.c_str() << "\",\n"; + if (target_pb_type == nullptr) { + fp << " \"is_primitive_pb_type\" : \"invalid\",\n"; + } else { + if (is_primitive_pb_type(target_pb_type)) { + fp << " \"is_primitive_pb_type\" : \"true\",\n"; + } else { + fp << " \"is_primitive_pb_type\" : \"false\",\n"; + } + } + fp << " \"type\" : \"" << pb_setting.type.c_str() << "\",\n"; + fp << " \"content\" : \"" << pb_setting.content.c_str() << "\""; + if (target_pb_type != nullptr && + is_primitive_pb_type(target_pb_type)) { + extract_device_non_fabric_pb_bitstream(fp, pb_setting, setting.name, + target_pb_type, vpr_ctx); + } + fp << "\n }"; + pb_count++; + } + if (pb_count) { + fp << "\n"; + } + } + fp << " ]\n"; + fp << "}\n"; + fp.close(); + } + } + VTR_LOGV(verbose, "Done\n"); +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.h b/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.h new file mode 100644 index 000000000..658c40b96 --- /dev/null +++ b/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.h @@ -0,0 +1,25 @@ +#ifndef EXTRACT_DEVICE_NON_FABRIC_BITSTREAM_H +#define EXTRACT_DEVICE_NON_FABRIC_BITSTREAM_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "openfpga_context.h" +#include "vpr_context.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +void extract_device_non_fabric_bitstream(const VprContext& vpr_ctx, + const OpenfpgaContext& openfpga_ctx, + const bool& verbose); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.h b/openfpga/src/fpga_bitstream/fabric_bitstream.h index 67e92f9f8..85a5054b8 100644 --- a/openfpga/src/fpga_bitstream/fabric_bitstream.h +++ b/openfpga/src/fpga_bitstream/fabric_bitstream.h @@ -30,6 +30,7 @@ #ifndef FABRIC_BITSTREAM_H #define FABRIC_BITSTREAM_H +#include #include #include #include diff --git a/openfpga/src/fpga_bitstream/overwrite_bitstream.cpp b/openfpga/src/fpga_bitstream/overwrite_bitstream.cpp new file mode 100644 index 000000000..e25d63e94 --- /dev/null +++ b/openfpga/src/fpga_bitstream/overwrite_bitstream.cpp @@ -0,0 +1,38 @@ +/******************************************************************** + * This file includes functions to build bitstream from a mapped + * FPGA fabric. + * We decode the bitstream from configuration of routing multiplexers + * and Look-Up Tables (LUTs) which locate in CLBs and global routing + *architecture + *******************************************************************/ + +/* Headers from vtrutil library */ +#include "overwrite_bitstream.h" + +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Overwrite bitstream retrieve from bitstream annotation XML which stored in + *BitstreamSetting + *******************************************************************/ +void overwrite_bitstream(openfpga::BitstreamManager& bitstream_manager, + const openfpga::BitstreamSetting& bitstream_setting, + const bool& verbose) { + vtr::ScopedStartFinishTimer timer("\nOverwrite Bitstream\n"); + + /* Apply overwrite_bitstream bit's path and value */ + for (auto& id : bitstream_setting.overwrite_bitstreams()) { + std::string path = bitstream_setting.overwrite_bitstream_path(id); + bool value = bitstream_setting.overwrite_bitstream_value(id); + VTR_LOGV(verbose, "Overwrite bitstream path='%s' to value='%d'\n", + path.c_str(), value); + bitstream_manager.overwrite_bitstream(path, value); + } +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/overwrite_bitstream.h b/openfpga/src/fpga_bitstream/overwrite_bitstream.h new file mode 100644 index 000000000..de142232b --- /dev/null +++ b/openfpga/src/fpga_bitstream/overwrite_bitstream.h @@ -0,0 +1,23 @@ +#ifndef OVERWRITE_BITSTREAM_H +#define OVERWRITE_BITSTREAM_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ + +#include "openfpga_context.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +void overwrite_bitstream(openfpga::BitstreamManager& bitstream_manager, + const openfpga::BitstreamSetting& bitstream_setting, + const bool& verbose); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp index 2de04a881..d2e673c2b 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp @@ -693,7 +693,7 @@ void print_analysis_sdc_disable_unused_grids( for (size_t iy = 1; iy < grids.height() - 1; ++iy) { print_analysis_sdc_disable_unused_grid( fp, vtr::Point(ix, iy), grids, device_annotation, - cluster_annotation, place_annotation, module_manager, NUM_SIDES); + cluster_annotation, place_annotation, module_manager, NUM_2D_SIDES); } } diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp index 65a0d3efa..11e5e5908 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp @@ -120,9 +120,9 @@ static void print_analysis_sdc_io_delays( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, module_io_port.get_name()); if (size_t(-1) == io_index) { diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp index ae8b42781..56a63a595 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp @@ -593,7 +593,7 @@ void print_pnr_sdc_constrain_grid_timing( /* For CLB and heterogenenous blocks */ std::string grid_module_name = generate_grid_block_module_name( std::string(GRID_MODULE_NAME_PREFIX), std::string(physical_tile.name), - is_io_type(&physical_tile), NUM_SIDES); + is_io_type(&physical_tile), NUM_2D_SIDES); /* Find the module Id */ ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp index 1f56da15e..1002da4b0 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp @@ -317,8 +317,9 @@ static void print_pnr_sdc_constrain_cb_mux_timing( /* Find the module port corresponding to the fan-in rr_nodes of the output * rr_node */ std::vector module_input_ports = - find_connection_block_module_input_ports( - module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_nodes); + find_connection_block_module_input_ports(module_manager, cb_module, grids, + device_annotation, rr_graph, + rr_gsb, cb_type, input_rr_nodes); /* Find timing constraints for each path (edge) */ std::map switch_delays; diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp index f2ae08864..42d434617 100644 --- a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp +++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp @@ -323,7 +323,7 @@ void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir, * i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT}, * we will generate one module for each border side * - If a I/O block locates in the center of FPGA fabric: - * we will generate one module with NUM_SIDES (same treatment as + * we will generate one module with NUM_2D_SIDES (same treatment as * regular grids) */ std::set io_type_sides = @@ -361,7 +361,7 @@ void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir, /* For CLB and heterogenenous blocks */ std::string grid_module_name = generate_grid_block_module_name( std::string(GRID_MODULE_NAME_PREFIX), std::string(physical_tile.name), - is_io_type(&physical_tile), NUM_SIDES); + is_io_type(&physical_tile), NUM_2D_SIDES); /* Find the module Id */ ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); diff --git a/openfpga/src/fpga_spice/spice_grid.cpp b/openfpga/src/fpga_spice/spice_grid.cpp index fee98b43f..ec8a58bc1 100644 --- a/openfpga/src/fpga_spice/spice_grid.cpp +++ b/openfpga/src/fpga_spice/spice_grid.cpp @@ -274,7 +274,7 @@ static void print_spice_physical_tile_netlist( const e_side& border_side) { /* Check code: if this is an IO block, the border side MUST be valid */ if (true == is_io_type(phy_block_type)) { - VTR_ASSERT(NUM_SIDES != border_side); + VTR_ASSERT(NUM_2D_SIDES != border_side); } /* Give a name to the Verilog netlist */ @@ -393,8 +393,8 @@ void print_spice_grids(NetlistManager& netlist_manager, * i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT}, * we will generate one module for each border side * - If a I/O block locates in the center of FPGA fabric: - * we will generate one module with NUM_SIDES (same treatment as regular - * grids) + * we will generate one module with NUM_2D_SIDES (same treatment as + * regular grids) */ std::set io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile); @@ -407,7 +407,8 @@ void print_spice_grids(NetlistManager& netlist_manager, } else { /* For CLB and heterogenenous blocks */ print_spice_physical_tile_netlist(netlist_manager, module_manager, - subckt_dir, &physical_tile, NUM_SIDES); + subckt_dir, &physical_tile, + NUM_2D_SIDES); } } VTR_LOG("Building physical tiles..."); diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp index 17fdad397..0dafb4414 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp @@ -21,6 +21,9 @@ FabricVerilogOption::FabricVerilogOption() { default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE; time_stamp_ = true; use_relative_path_ = false; + constant_undriven_inputs_ = FabricVerilogOption::e_undriven_input_type::NONE; + CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_ = {"none", "bus0", "bus1", "bit0", + "bit1"}; verbose_output_ = false; } @@ -53,6 +56,41 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const { return default_net_type_; } +FabricVerilogOption::e_undriven_input_type +FabricVerilogOption::constant_undriven_inputs() const { + return constant_undriven_inputs_; +} + +bool FabricVerilogOption::constant_undriven_inputs_use_bus() const { + return constant_undriven_inputs_ == + FabricVerilogOption::e_undriven_input_type::BUS0 || + constant_undriven_inputs_ == + FabricVerilogOption::e_undriven_input_type::BUS1; +} + +size_t FabricVerilogOption::constant_undriven_inputs_value() const { + if (constant_undriven_inputs_ == + FabricVerilogOption::e_undriven_input_type::BUS1 || + constant_undriven_inputs_ == + FabricVerilogOption::e_undriven_input_type::BIT1) { + return 1; + } + return 0; +} + +std::string FabricVerilogOption::full_constant_undriven_input_type_str() const { + std::string full_type_str("["); + for (size_t itype = 0; + itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES); + ++itype) { + full_type_str += std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) + + std::string("|"); + } + full_type_str.pop_back(); + full_type_str += std::string("]"); + return full_type_str; +} + bool FabricVerilogOption::verbose_output() const { return verbose_output_; } /****************************************************************************** @@ -106,6 +144,33 @@ void FabricVerilogOption::set_default_net_type( } } +bool FabricVerilogOption::set_constant_undriven_inputs( + const std::string& type_str) { + bool valid_type = false; + for (size_t itype = 0; + itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES); + ++itype) { + if (std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) == type_str) { + constant_undriven_inputs_ = + static_cast(itype); + valid_type = true; + break; + } + } + if (!valid_type) { + VTR_LOG_ERROR("Invalid types for undriven inputs: %s. Expect %s\n", + type_str.c_str(), + full_constant_undriven_input_type_str().c_str()); + } + return valid_type; +} + +bool FabricVerilogOption::set_constant_undriven_inputs( + const FabricVerilogOption::e_undriven_input_type& type) { + constant_undriven_inputs_ = type; + return type != FabricVerilogOption::e_undriven_input_type::NUM_TYPES; +} + void FabricVerilogOption::set_verbose_output(const bool& enabled) { verbose_output_ = enabled; } diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h index dfa7844e9..83483112a 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.h +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h @@ -15,6 +15,16 @@ namespace openfpga { * Options for Fabric Verilog generator *******************************************************************/ class FabricVerilogOption { + public: /* Types */ + enum class e_undriven_input_type { + NONE = 0, /* Leave undriven input to be dangling */ + BUS0, /* Wire to a bus format of constant 0 */ + BUS1, /* Wire to a bus format of constant 1 */ + BIT0, /* Wire to a blast-bit format of constant 0 */ + BIT1, /* Wire to a blast-bit format of constant 1 */ + NUM_TYPES + }; + public: /* Public constructor */ /* Set default options */ FabricVerilogOption(); @@ -28,6 +38,14 @@ class FabricVerilogOption { bool compress_routing() const; e_verilog_default_net_type default_net_type() const; bool print_user_defined_template() const; + e_undriven_input_type constant_undriven_inputs() const; + /* Identify if a bus format should be applied when wiring undriven inputs to + * constants */ + bool constant_undriven_inputs_use_bus() const; + /* Identify the logic value should be applied when wiring undriven inputs to + * constants */ + size_t constant_undriven_inputs_value() const; + std::string full_constant_undriven_input_type_str() const; bool verbose_output() const; public: /* Public mutators */ @@ -39,6 +57,13 @@ class FabricVerilogOption { void set_compress_routing(const bool& enabled); void set_print_user_defined_template(const bool& enabled); void set_default_net_type(const std::string& default_net_type); + /** Decode the type from string to enumeration + * "none" -> NONE, "bus0" -> BUS0, "bus1" -> BUS1, "bit0" -> BIT0, "bit1" -> + * BIT1 For invalid types, error out + */ + bool set_constant_undriven_inputs(const std::string& type_str); + /** For invalid types, error out */ + bool set_constant_undriven_inputs(const e_undriven_input_type& type); void set_verbose_output(const bool& enabled); private: /* Internal Data */ @@ -50,6 +75,11 @@ class FabricVerilogOption { e_verilog_default_net_type default_net_type_; bool time_stamp_; bool use_relative_path_; + e_undriven_input_type constant_undriven_inputs_; + std::array + CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_; // String versions of constant + // undriven input types bool verbose_output_; }; diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index da5370fd9..7b77f53bd 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -61,6 +61,11 @@ constexpr const char* FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME = constexpr const char* FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX = "_top_formal_verification_random_tb"; +constexpr const char* VERILOG_FSDB_PREPROC_FLAG = + "DUMP_FSDB"; // the flag to enable fsdb waveform output during compilation +constexpr const char* VERILOG_VCD_PREPROC_FLAG = + "DUMP_VCD"; // the flag to enable vcd waveform output during compilation + #define VERILOG_DEFAULT_SIGNAL_INIT_VALUE 0 #endif diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index 7d79f3a4d..8d6fbf513 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -113,8 +113,10 @@ static void print_verilog_primitive_block( module_manager.module_name(primitive_module).c_str()); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, primitive_module, true, - options.default_net_type()); + FabricVerilogOption curr_options = options; + curr_options.set_explicit_port_mapping(true); + write_verilog_module_to_file(fp, module_manager, primitive_module, + curr_options); /* Close file handler */ fp.close(); @@ -232,9 +234,7 @@ static void rec_print_verilog_logical_tile( std::string(physical_pb_type->name) + " -----")); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, pb_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, pb_module, options); print_verilog_comment( fp, @@ -346,9 +346,7 @@ static void print_verilog_physical_tile_netlist( print_verilog_comment( fp, std::string("----- BEGIN Grid Verilog module: " + module_manager.module_name(grid_module) + " -----")); - write_verilog_module_to_file(fp, module_manager, grid_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, grid_module, options); print_verilog_comment( fp, std::string("----- END Grid Verilog module: " + @@ -447,7 +445,7 @@ void print_verilog_grids( /* For CLB and heterogenenous blocks */ print_verilog_physical_tile_netlist( netlist_manager, module_manager, module_name_map, subckt_dir, - subckt_dir_name, &physical_tile, NUM_SIDES, options); + subckt_dir_name, &physical_tile, NUM_2D_SIDES, options); } } VTR_LOG("Building physical tiles..."); diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index fab9205e4..267ff8f15 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -59,11 +59,11 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager, ModuleId lut_module = module_manager.find_module( module_name_map.name(circuit_lib.model_name(lut_model))); VTR_ASSERT(true == module_manager.valid_module_id(lut_module)); - write_verilog_module_to_file( - fp, module_manager, lut_module, + FabricVerilogOption curr_options = options; + curr_options.set_explicit_port_mapping( options.explicit_port_mapping() || - circuit_lib.dump_explicit_port_map(lut_model), - options.default_net_type()); + circuit_lib.dump_explicit_port_map(lut_model)); + write_verilog_module_to_file(fp, module_manager, lut_module, curr_options); } /* Close the file handler */ diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 8c56e5e8e..d3799264a 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -57,11 +57,12 @@ static void print_verilog_mux_memory_module( ModuleId mem_module = module_manager.find_module(module_name); VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); /* Write the module content in Verilog format */ - write_verilog_module_to_file( - fp, module_manager, mem_module, + FabricVerilogOption curr_options = options; + curr_options.set_explicit_port_mapping( options.explicit_port_mapping() || - circuit_lib.dump_explicit_port_map(mux_model), - options.default_net_type()); + circuit_lib.dump_explicit_port_map(mux_model)); + write_verilog_module_to_file(fp, module_manager, mem_module, + curr_options); /* Add an empty line as a splitter */ fp << std::endl; @@ -80,11 +81,8 @@ static void print_verilog_mux_memory_module( if (module_manager.valid_module_id(feedthru_mem_module)) { VTR_ASSERT(true == module_manager.valid_module_id(feedthru_mem_module)); /* Write the module content in Verilog format */ - write_verilog_module_to_file( - fp, module_manager, feedthru_mem_module, - options.explicit_port_mapping() || - circuit_lib.dump_explicit_port_map(mux_model), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, feedthru_mem_module, + curr_options); /* Add an empty line as a splitter */ fp << std::endl; @@ -205,10 +203,11 @@ void print_verilog_submodule_memories( ModuleId mem_module = module_manager.find_module(module_name); VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, mem_module, - options.explicit_port_mapping() || - circuit_lib.dump_explicit_port_map(model), - options.default_net_type()); + FabricVerilogOption curr_options = options; + curr_options.set_explicit_port_mapping( + options.explicit_port_mapping() || + circuit_lib.dump_explicit_port_map(model)); + write_verilog_module_to_file(fp, module_manager, mem_module, curr_options); /* Add an empty line as a splitter */ fp << std::endl; @@ -226,9 +225,7 @@ void print_verilog_submodule_memories( if (module_manager.valid_module_id(feedthru_mem_module)) { /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, feedthru_mem_module, - options.explicit_port_mapping() || - circuit_lib.dump_explicit_port_map(model), - options.default_net_type()); + curr_options); /* Add an empty line as a splitter */ fp << std::endl; @@ -239,9 +236,7 @@ void print_verilog_submodule_memories( for (ModuleId mem_group_module : module_manager.modules_by_usage( ModuleManager::e_module_usage_type::MODULE_CONFIG_GROUP)) { /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, mem_group_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, mem_group_module, options); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp index ad238dbf2..6f38c9cef 100644 --- a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp +++ b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp @@ -115,9 +115,9 @@ static void print_verilog_mock_fpga_wrapper_connect_ios( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index af901e592..72599e4bc 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -139,6 +139,66 @@ static BasicPort generate_verilog_port_for_module_net( return port_to_return; } +/******************************************************************** + * Find all the undriven nets that are going to be local wires + * And organize it in a vector of ports + * Verilog wire writter function will use the output of this function + * to write up local wire declaration in Verilog format + *******************************************************************/ +static void find_verilog_module_local_undriven_wires( + std::map>& local_wires, + const ModuleManager& module_manager, const ModuleId& module_id, + const std::vector& port_type_blacklist) { + /* Local wires could also happen for undriven ports of child module */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + for (size_t instance : + module_manager.child_module_instances(module_id, child)) { + for (const ModulePortId& child_port_id : + module_manager.module_ports(child)) { + BasicPort child_port = module_manager.module_port(child, child_port_id); + ModuleManager::e_module_port_type child_port_type = + module_manager.port_type(child, child_port_id); + bool filter_out = false; + for (ModuleManager::e_module_port_type curr_port_type : + port_type_blacklist) { + if (child_port_type == curr_port_type) { + filter_out = true; + break; + } + } + if (filter_out) { + continue; + } + std::vector undriven_pins; + for (size_t child_pin : child_port.pins()) { + /* Find the net linked to the pin */ + ModuleNetId net = module_manager.module_instance_port_net( + module_id, child, instance, child_port_id, child_pin); + /* We only care undriven ports */ + if (ModuleNetId::INVALID() == net) { + undriven_pins.push_back(child_pin); + } + } + if (true == undriven_pins.empty()) { + continue; + } + /* Reach here, we need a local wire, we will create a port only for the + * undriven pins of the port! */ + BasicPort instance_port; + instance_port.set_name(generate_verilog_undriven_local_wire_name( + module_manager, module_id, child, instance, child_port_id)); + /* We give the same port name as child module, this case happens to + * global ports */ + instance_port.set_width( + *std::min_element(undriven_pins.begin(), undriven_pins.end()), + *std::max_element(undriven_pins.begin(), undriven_pins.end())); + + local_wires[instance_port.get_name()].push_back(instance_port); + } + } + } +} + /******************************************************************** * Find all the nets that are going to be local wires * And organize it in a vector of ports @@ -206,41 +266,9 @@ find_verilog_module_local_wires(const ModuleManager& module_manager, } } - /* Local wires could also happen for undriven ports of child module */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - for (size_t instance : - module_manager.child_module_instances(module_id, child)) { - for (const ModulePortId& child_port_id : - module_manager.module_ports(child)) { - BasicPort child_port = module_manager.module_port(child, child_port_id); - std::vector undriven_pins; - for (size_t child_pin : child_port.pins()) { - /* Find the net linked to the pin */ - ModuleNetId net = module_manager.module_instance_port_net( - module_id, child, instance, child_port_id, child_pin); - /* We only care undriven ports */ - if (ModuleNetId::INVALID() == net) { - undriven_pins.push_back(child_pin); - } - } - if (true == undriven_pins.empty()) { - continue; - } - /* Reach here, we need a local wire, we will create a port only for the - * undriven pins of the port! */ - BasicPort instance_port; - instance_port.set_name(generate_verilog_undriven_local_wire_name( - module_manager, module_id, child, instance, child_port_id)); - /* We give the same port name as child module, this case happens to - * global ports */ - instance_port.set_width( - *std::min_element(undriven_pins.begin(), undriven_pins.end()), - *std::max_element(undriven_pins.begin(), undriven_pins.end())); - - local_wires[instance_port.get_name()].push_back(instance_port); - } - } - } + find_verilog_module_local_undriven_wires( + local_wires, module_manager, module_id, + std::vector()); return local_wires; } @@ -542,10 +570,10 @@ static void write_verilog_instance_to_file(std::fstream& fp, * This is a key function, maybe most frequently called in our Verilog writer * Note that file stream must be valid *******************************************************************/ -void write_verilog_module_to_file( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& module_id, const bool& use_explicit_port_map, - const e_verilog_default_net_type& default_net_type) { +void write_verilog_module_to_file(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const FabricVerilogOption& options) { VTR_ASSERT(true == valid_file_stream(fp)); /* Ensure we have a valid module_id */ @@ -553,7 +581,7 @@ void write_verilog_module_to_file( /* Print module declaration */ print_verilog_module_declaration(fp, module_manager, module_id, - default_net_type); + options.default_net_type()); /* Print an empty line as splitter */ fp << std::endl; @@ -566,7 +594,7 @@ void write_verilog_module_to_file( for (const BasicPort& local_wire : port_group.second) { /* When default net type is wire, we can skip single-bit wires whose LSB * is 0 */ - if ((VERILOG_DEFAULT_NET_TYPE_WIRE == default_net_type) && + if ((VERILOG_DEFAULT_NET_TYPE_WIRE == options.default_net_type()) && (1 == local_wire.get_width()) && (0 == local_wire.get_lsb())) { continue; } @@ -575,6 +603,38 @@ void write_verilog_module_to_file( } } + /* Use constant to drive undriven local wires */ + if (options.constant_undriven_inputs() != + FabricVerilogOption::e_undriven_input_type::NONE) { + std::vector blacklist = { + ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT, + ModuleManager::e_module_port_type::MODULE_GPIN_PORT, + ModuleManager::e_module_port_type::MODULE_GPOUT_PORT, + ModuleManager::e_module_port_type::MODULE_GPIO_PORT, + ModuleManager::e_module_port_type::MODULE_INOUT_PORT, + ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT, + ModuleManager::e_module_port_type::MODULE_CLOCK_PORT}; + std::map> local_undriven_wires; + find_verilog_module_local_undriven_wires( + local_undriven_wires, module_manager, module_id, blacklist); + for (std::pair> port_group : + local_undriven_wires) { + for (const BasicPort& local_undriven_wire : port_group.second) { + if (options.constant_undriven_inputs_use_bus()) { + print_verilog_wire_constant_values( + fp, local_undriven_wire, + std::vector(local_undriven_wire.get_width(), + options.constant_undriven_inputs_value())); + } else { + print_verilog_wire_constant_values_bit_blast( + fp, local_undriven_wire, + std::vector(local_undriven_wire.get_width(), + options.constant_undriven_inputs_value())); + } + } + } + } + /* Print an empty line as splitter */ fp << std::endl; @@ -601,7 +661,7 @@ void write_verilog_module_to_file( /* Print an instance */ write_verilog_instance_to_file(fp, module_manager, module_id, child_module, instance, - use_explicit_port_map); + options.explicit_port_mapping()); /* Print an empty line as splitter */ fp << std::endl; } @@ -609,7 +669,7 @@ void write_verilog_module_to_file( /* Print an end for the module */ print_verilog_module_end(fp, module_manager.module_name(module_id), - default_net_type); + options.default_net_type()); /* Print an empty line as splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.h b/openfpga/src/fpga_verilog/verilog_module_writer.h index 8e11637a7..3c4c024e5 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.h +++ b/openfpga/src/fpga_verilog/verilog_module_writer.h @@ -6,6 +6,7 @@ *******************************************************************/ #include +#include "fabric_verilog_options.h" #include "module_manager.h" #include "verilog_port_types.h" @@ -16,10 +17,10 @@ /* begin namespace openfpga */ namespace openfpga { -void write_verilog_module_to_file( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& module_id, const bool& use_explicit_port_map, - const e_verilog_default_net_type& default_net_type); +void write_verilog_module_to_file(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const FabricVerilogOption& options); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index 6fd2b2df4..d4844b080 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -643,8 +643,7 @@ static void generate_verilog_rram_mux_branch_module( static void generate_verilog_mux_branch_module( ModuleManager& module_manager, const CircuitLibrary& circuit_lib, std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph, - const ModuleNameMap& module_name_map, const bool& use_explicit_port_map, - const e_verilog_default_net_type& default_net_type, + const ModuleNameMap& module_name_map, const FabricVerilogOption& options, std::map& branch_mux_module_is_outputted) { std::string module_name = generate_mux_branch_subckt_name( circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(), @@ -675,24 +674,28 @@ static void generate_verilog_mux_branch_module( /* Structural verilog can be easily generated by module writer */ ModuleId mux_module = module_manager.find_module(module_name); VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - write_verilog_module_to_file( - fp, module_manager, mux_module, - use_explicit_port_map || - circuit_lib.dump_explicit_port_map(mux_model), - default_net_type); + FabricVerilogOption curr_options = options; + curr_options.set_explicit_port_mapping( + curr_options.explicit_port_mapping() || + circuit_lib.dump_explicit_port_map(mux_model)); + curr_options.set_constant_undriven_inputs( + FabricVerilogOption::e_undriven_input_type::NONE); + write_verilog_module_to_file(fp, module_manager, mux_module, + curr_options); /* Add an empty line as a splitter */ fp << std::endl; } else { /* Behavioral verilog requires customized generation */ print_verilog_cmos_mux_branch_module_behavioral( module_manager, circuit_lib, fp, mux_model, module_name, mux_graph, - default_net_type); + options.default_net_type()); } break; case CIRCUIT_MODEL_DESIGN_RRAM: generate_verilog_rram_mux_branch_module( module_manager, circuit_lib, fp, mux_model, module_name, mux_graph, - default_net_type, circuit_lib.dump_structural_verilog(mux_model)); + options.default_net_type(), + circuit_lib.dump_structural_verilog(mux_model)); break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -1401,8 +1404,7 @@ static void generate_verilog_rram_mux_module( static void generate_verilog_mux_module( ModuleManager& module_manager, const CircuitLibrary& circuit_lib, std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph, - const ModuleNameMap& module_name_map, const bool& use_explicit_port_map, - const e_verilog_default_net_type& default_net_type) { + const ModuleNameMap& module_name_map, const FabricVerilogOption& options) { std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, find_mux_num_datapath_inputs( @@ -1417,13 +1419,16 @@ static void generate_verilog_mux_module( /* Use Verilog writer to print the module to file */ ModuleId mux_module = module_manager.find_module(module_name); VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - write_verilog_module_to_file( - fp, module_manager, mux_module, - (use_explicit_port_map || + FabricVerilogOption curr_options = options; + curr_options.set_explicit_port_mapping( + (curr_options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model) || circuit_lib.dump_explicit_port_map( - circuit_lib.pass_gate_logic_model(mux_model))), - default_net_type); + circuit_lib.pass_gate_logic_model(mux_model)))); + curr_options.set_constant_undriven_inputs( + FabricVerilogOption::e_undriven_input_type::NONE); + write_verilog_module_to_file(fp, module_manager, mux_module, + curr_options); /* Add an empty line as a splitter */ fp << std::endl; break; @@ -1432,7 +1437,7 @@ static void generate_verilog_mux_module( /* TODO: RRAM-based Multiplexer Verilog module generation */ generate_verilog_rram_mux_module(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph, - default_net_type); + options.default_net_type()); break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -1486,8 +1491,7 @@ static void print_verilog_submodule_mux_primitives( for (auto branch_mux_graph : branch_mux_graphs) { generate_verilog_mux_branch_module( module_manager, circuit_lib, fp, mux_circuit_model, branch_mux_graph, - module_name_map, options.explicit_port_mapping(), - options.default_net_type(), branch_mux_module_is_outputted); + module_name_map, options, branch_mux_module_is_outputted); } } @@ -1540,8 +1544,7 @@ static void print_verilog_submodule_mux_top_modules( /* Create MUX circuits */ generate_verilog_mux_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph, module_name_map, - options.explicit_port_mapping(), - options.default_net_type()); + options); } /* Close the file stream */ diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index e278ff9fa..3e47c6a16 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -65,6 +65,10 @@ static void print_verilog_preconfig_top_module_ports( /* The block may be renamed as it contains special characters which violate * Verilog syntax */ if (true == netlist_annotation.is_block_renamed(atom_blk)) { + VTR_LOG( + "Replace pin name '%s' with '%s' as it is renamed to comply verilog " + "syntax\n", + block_name.c_str(), netlist_annotation.block_name(atom_blk).c_str()); block_name = netlist_annotation.block_name(atom_blk); } /* For output block, remove the prefix which is added by VPR */ @@ -445,8 +449,8 @@ int print_verilog_preconfig_top_module( /* Connect FPGA top module global ports to constant or benchmark global * signals! */ status = print_verilog_preconfig_top_module_connect_global_ports( - fp, module_manager, core_module, pin_constraints, global_ports, - benchmark_clock_port_names, + fp, module_manager, core_module, pin_constraints, atom_ctx, + netlist_annotation, global_ports, benchmark_clock_port_names, std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX)); if (CMD_EXEC_FATAL_ERROR == status) { return status; @@ -490,6 +494,12 @@ int print_verilog_preconfig_top_module( module_manager, top_module, false); } + /* Add waveform output command, support both fsdb and vcd */ + if (true == options.dump_waveform()) { + print_verilog_testbench_dump_waveform( + fp, circuit_name, std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME)); + } + /* Testbench ends*/ print_verilog_module_end( fp, diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp index 944506c89..0073ab46d 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp @@ -57,6 +57,7 @@ void print_verilog_preconfig_top_module_internal_wires( int print_verilog_preconfig_top_module_connect_global_ports( std::fstream &fp, const ModuleManager &module_manager, const ModuleId &top_module, const PinConstraints &pin_constraints, + const AtomContext &atom_ctx, const VprNetlistAnnotation &netlist_annotation, const FabricGlobalPortInfo &fabric_global_ports, const std::vector &benchmark_clock_port_names, const std::string &port_postfix) { @@ -121,7 +122,27 @@ int print_verilog_preconfig_top_module_connect_global_ports( } clock_name_to_connect = benchmark_clock_port_names[pin_id]; } - + /* The clock name must be a valid primary input. Otherwise, it could be + * a signal generated by internal logics, e.g., clb */ + AtomBlockId atom_blk = atom_ctx.nlist.find_block(clock_name_to_connect); + if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))) { + VTR_LOG( + "Global net '%s' is not a primary input of the netlist (which " + "could a signal generated by internal logic). Will not wire it to " + "any FPGA primary input pin\n", + clock_name_to_connect.c_str()); + continue; + } + /* The block may be renamed as it contains special characters which + * violate Verilog syntax */ + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + VTR_LOG( + "Replace pin name '%s' with '%s' as it is renamed to comply " + "verilog syntax\n", + clock_name_to_connect.c_str(), + netlist_annotation.block_name(atom_blk).c_str()); + clock_name_to_connect = netlist_annotation.block_name(atom_blk); + } BasicPort benchmark_clock_pin(clock_name_to_connect, 1); print_verilog_wire_connection(fp, module_clock_pin, benchmark_clock_pin, false); @@ -151,6 +172,27 @@ int print_verilog_preconfig_top_module_connect_global_ports( */ if ((false == pin_constraints.unconstrained_net(constrained_net_name)) && (false == pin_constraints.unmapped_net(constrained_net_name))) { + /* The clock name must be a valid primary input. Otherwise, it could be + * a signal generated by internal logics, e.g., clb */ + AtomBlockId atom_blk = atom_ctx.nlist.find_block(constrained_net_name); + if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))) { + VTR_LOG( + "Global net '%s' is not a primary input of the netlist (which " + "could a signal generated by internal logic). Will not wire it to " + "any FPGA primary input pin\n", + constrained_net_name.c_str()); + continue; + } + /* The block may be renamed as it contains special characters which + * violate Verilog syntax */ + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + VTR_LOG( + "Replace pin name '%s' with '%s' as it is renamed to comply " + "verilog syntax\n", + constrained_net_name.c_str(), + netlist_annotation.block_name(atom_blk).c_str()); + constrained_net_name = netlist_annotation.block_name(atom_blk); + } BasicPort benchmark_pin(constrained_net_name, 1); print_verilog_wire_connection(fp, module_global_pin, benchmark_pin, false); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h index 55c85eadd..20ae797e2 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h @@ -35,6 +35,7 @@ void print_verilog_preconfig_top_module_internal_wires( int print_verilog_preconfig_top_module_connect_global_ports( std::fstream &fp, const ModuleManager &module_manager, const ModuleId &top_module, const PinConstraints &pin_constraints, + const AtomContext &atom_ctx, const VprNetlistAnnotation &netlist_annotation, const FabricGlobalPortInfo &fabric_global_ports, const std::vector &benchmark_clock_port_names, const std::string &port_postfix); diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp index dbe59e935..f346b7087 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.cpp +++ b/openfpga/src/fpga_verilog/verilog_routing.cpp @@ -115,9 +115,7 @@ static void print_verilog_routing_connection_box_unique_module( VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, cb_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, cb_module, options); /* Add an empty line as a splitter */ fp << std::endl; @@ -236,9 +234,7 @@ static void print_verilog_routing_switch_box_unique_module( VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, sb_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, sb_module, options); /* Close file handler */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp index f2c0e02e6..67ccdb4af 100644 --- a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp +++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp @@ -56,9 +56,7 @@ void print_verilog_submodule_shift_register_banks( for (const ModuleId& sr_module : blwl_sr_banks.bl_bank_unique_modules()) { VTR_ASSERT(true == module_manager.valid_module_id(sr_module)); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, sr_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, sr_module, options); /* Add an empty line as a splitter */ fp << std::endl; @@ -67,9 +65,7 @@ void print_verilog_submodule_shift_register_banks( for (const ModuleId& sr_module : blwl_sr_banks.wl_bank_unique_modules()) { VTR_ASSERT(true == module_manager.valid_module_id(sr_module)); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, sr_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, sr_module, options); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp index 3eb2a209e..b7ed5e628 100644 --- a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp @@ -137,9 +137,10 @@ void print_verilog_simulation_info( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)] + .loc.sub_tile, module_io_port.get_name()); if (size_t(-1) == io_index) { diff --git a/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp b/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp index 30018e400..0f4978c60 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp @@ -90,8 +90,9 @@ int print_verilog_testbench_io_connection( /* Connect FPGA top module global ports to constant or benchmark global * signals! */ status = print_verilog_preconfig_top_module_connect_global_ports( - fp, module_manager, core_module, pin_constraints, global_ports, - benchmark_clock_port_names, std::string()); + fp, module_manager, core_module, pin_constraints, atom_ctx, + netlist_annotation, global_ports, benchmark_clock_port_names, + std::string()); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp index a6db0353b..55e758e34 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp @@ -30,7 +30,11 @@ VerilogTestbenchOption::VerilogTestbenchOption() { time_unit_ = 1E-3; time_stamp_ = true; use_relative_path_ = false; + simulator_type_ = e_simulator_type::IVERILOG; + dump_waveform_ = false; verbose_output_ = false; + + SIMULATOR_TYPE_STRING_ = {{"iverilog", "vcs"}}; } /************************************************** @@ -84,6 +88,8 @@ bool VerilogTestbenchOption::include_signal_init() const { return include_signal_init_; } +bool VerilogTestbenchOption::dump_waveform() const { return dump_waveform_; } + bool VerilogTestbenchOption::no_self_checking() const { return reference_benchmark_file_path_.empty(); } @@ -107,6 +113,11 @@ bool VerilogTestbenchOption::use_relative_path() const { bool VerilogTestbenchOption::verbose_output() const { return verbose_output_; } +VerilogTestbenchOption::e_simulator_type +VerilogTestbenchOption::simulator_type() const { + return simulator_type_; +} + /****************************************************************************** * Private Mutators ******************************************************************************/ @@ -198,6 +209,10 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) { include_signal_init_ = enabled; } +void VerilogTestbenchOption::set_dump_waveform(const bool& enabled) { + dump_waveform_ = enabled; +} + void VerilogTestbenchOption::set_default_net_type( const std::string& default_net_type) { /* Decode from net type string */; @@ -259,4 +274,52 @@ void VerilogTestbenchOption::set_verbose_output(const bool& enabled) { verbose_output_ = enabled; } +int VerilogTestbenchOption::set_simulator_type(const std::string& value) { + simulator_type_ = str2simulator_type(value); + return valid_simulator_type(simulator_type_); +} + +std::string VerilogTestbenchOption::simulator_type_all2str() const { + std::string full_types = "["; + for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG); + itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES); + ++itype) { + full_types += std::string(SIMULATOR_TYPE_STRING_[itype]) + std::string("|"); + } + full_types.pop_back(); + full_types += "]"; + return full_types; +} + +VerilogTestbenchOption::e_simulator_type +VerilogTestbenchOption::str2simulator_type(const std::string& type_str, + const bool& verbose) const { + for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG); + itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES); + ++itype) { + if (type_str == std::string(SIMULATOR_TYPE_STRING_[itype])) { + return static_cast(itype); + } + } + VTR_LOGV_ERROR(verbose, "Invalid simulator type! Expect %s\n", + simulator_type_all2str().c_str()); + return VerilogTestbenchOption::e_simulator_type::NUM_TYPES; +} + +std::string VerilogTestbenchOption::simulator_type2str( + const VerilogTestbenchOption::e_simulator_type& sim_type, + const bool& verbose) const { + if (!valid_simulator_type(sim_type)) { + VTR_LOGV_ERROR(verbose, "Invalid type for simulator! Expect %s\n", + simulator_type_all2str().c_str()); + return std::string(); + } + return std::string(SIMULATOR_TYPE_STRING_[size_t(sim_type)]); +} + +bool VerilogTestbenchOption::valid_simulator_type( + const VerilogTestbenchOption::e_simulator_type& sim_type) const { + return sim_type != VerilogTestbenchOption::e_simulator_type::NUM_TYPES; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h index 97d2e27fd..292fbd5d1 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h @@ -31,6 +31,16 @@ constexpr std::array * *******************************************************************/ class VerilogTestbenchOption { + /* Public types */ + public: + /* Embedded bitstream code style */ + enum class e_simulator_type { IVERILOG = 0, VCS, NUM_TYPES }; + /* Constants */ + private: + /* String version of simulator types. Used for debugging/error messages */ + std::array + SIMULATOR_TYPE_STRING_; + public: /* Public constructor */ /* Set default options */ VerilogTestbenchOption(); @@ -49,6 +59,7 @@ class VerilogTestbenchOption { std::string simulation_ini_path() const; bool explicit_port_mapping() const; bool include_signal_init() const; + bool dump_waveform() const; bool no_self_checking() const; e_verilog_default_net_type default_net_type() const; e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const; @@ -56,6 +67,7 @@ class VerilogTestbenchOption { bool time_stamp() const; bool use_relative_path() const; bool verbose_output() const; + e_simulator_type simulator_type() const; public: /* Public validator */ bool validate() const; @@ -87,6 +99,7 @@ class VerilogTestbenchOption { void set_print_simulation_ini(const std::string& simulation_ini_path); void set_explicit_port_mapping(const bool& enabled); void set_include_signal_init(const bool& enabled); + void set_dump_waveform(const bool& enabled); void set_default_net_type(const std::string& default_net_type); void set_time_unit(const float& time_unit); void set_embedded_bitstream_hdl_type( @@ -95,6 +108,18 @@ class VerilogTestbenchOption { void set_use_relative_path(const bool& enabled); void set_verbose_output(const bool& enabled); + /* @brief Create the simulator type by parsing a given string. Return error + * when failed */ + int set_simulator_type(const std::string& value); + + private: /* Private utility and validators */ + e_simulator_type str2simulator_type(const std::string& value, + const bool& verbose = false) const; + std::string simulator_type2str(const e_simulator_type& sim_type, + const bool& verbose = false) const; + std::string simulator_type_all2str() const; + bool valid_simulator_type(const e_simulator_type& sim_type) const; + private: /* Internal Data */ std::string output_directory_; std::string top_module_; @@ -109,8 +134,10 @@ class VerilogTestbenchOption { std::string simulation_ini_path_; bool explicit_port_mapping_; bool include_signal_init_; + bool dump_waveform_; e_verilog_default_net_type default_net_type_; e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_; + e_simulator_type simulator_type_; float time_unit_; bool time_stamp_; bool use_relative_path_; diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 4dbb879c9..1468a188a 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -383,9 +383,9 @@ void print_verilog_testbench_connect_fpga_ios( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ @@ -1344,4 +1344,34 @@ void print_verilog_testbench_signal_initialization( } } +/******************************************************************** + * Print waveform output commands: support both VCD and FSDB + *******************************************************************/ +void print_verilog_testbench_dump_waveform(std::fstream& fp, + const std::string& circuit_name, + const std::string& uut_name) { + /* Validate the file stream */ + valid_file_stream(fp); + + print_verilog_comment( + fp, std::string("------ Use " + std::string(VERILOG_FSDB_PREPROC_FLAG) + + " to enable FSDB waveform output -----")); + print_verilog_preprocessing_flag(fp, std::string(VERILOG_FSDB_PREPROC_FLAG)); + fp << "initial begin\n"; + fp << "\t$fsdbDumpfile(\"" << circuit_name << ".fsdb\");\n"; + fp << "\t$fsdbDumpvars(0, \"" << uut_name << "\");\n"; + fp << "end\n"; + print_verilog_endif(fp); + + print_verilog_comment( + fp, std::string("------ Use " + std::string(VERILOG_VCD_PREPROC_FLAG) + + " to enable VCD waveform output -----")); + print_verilog_preprocessing_flag(fp, std::string(VERILOG_VCD_PREPROC_FLAG)); + fp << "initial begin\n"; + fp << "\t$dumpfile(\"" << circuit_name << ".vcd\");\n"; + fp << "\t$dumpvars(0, \"" << uut_name << "\");\n"; + fp << "end\n"; + print_verilog_endif(fp); +} + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 243bd9904..b4b8bcac8 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -135,6 +135,10 @@ void print_verilog_testbench_signal_initialization( const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module, const bool& deposit_random_values); +void print_verilog_testbench_dump_waveform(std::fstream& fp, + const std::string& circuit_name, + const std::string& uut_name); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp index da32fc58c..9de47fe16 100644 --- a/openfpga/src/fpga_verilog/verilog_tile.cpp +++ b/openfpga/src/fpga_verilog/verilog_tile.cpp @@ -58,9 +58,7 @@ static int print_verilog_tile_module_netlist( options.time_stamp()); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, tile_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, tile_module, options); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index b8c302f21..9812e9db5 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -61,9 +61,7 @@ void print_verilog_core_module(NetlistManager& netlist_manager, options.time_stamp()); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, core_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, core_module, options); /* Add an empty line as a splitter */ fp << std::endl; @@ -127,9 +125,7 @@ void print_verilog_top_module(NetlistManager& netlist_manager, fp, std::string("Top-level Verilog module for FPGA"), options.time_stamp()); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, top_module, - options.explicit_port_mapping(), - options.default_net_type()); + write_verilog_module_to_file(fp, module_manager, top_module, options); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 2443abf5c..6a343bd42 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1423,7 +1423,8 @@ static int print_verilog_top_testbench_configuration_protocol_stimulus( const ModuleId& top_module, const bool& fast_configuration, const bool& bit_value_to_skip, const FabricBitstream& fabric_bitstream, const MemoryBankShiftRegisterBanks& blwl_sr_banks, - const float& prog_clock_period, const float& timescale) { + const float& prog_clock_period, const float& timescale, + const VerilogTestbenchOption::e_simulator_type sim_type) { /* Validate the file stream */ valid_file_stream(fp); @@ -1437,7 +1438,7 @@ static int print_verilog_top_testbench_configuration_protocol_stimulus( return print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus( fp, config_protocol, sim_settings, module_manager, top_module, fast_configuration, bit_value_to_skip, fabric_bitstream, blwl_sr_banks, - prog_clock_period, timescale); + prog_clock_period, timescale, sim_type); break; case CONFIG_MEM_MEMORY_BANK: case CONFIG_MEM_FRAME_BASED: { @@ -2564,7 +2565,7 @@ int print_verilog_full_testbench( status = print_verilog_top_testbench_configuration_protocol_stimulus( fp, config_protocol, simulation_parameters, module_manager, core_module, fast_configuration, bit_value_to_skip, fabric_bitstream, blwl_sr_banks, - prog_clock_period, VERILOG_SIM_TIMESCALE); + prog_clock_period, VERILOG_SIM_TIMESCALE, options.simulator_type()); if (status == CMD_EXEC_FATAL_ERROR) { return status; diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp index d4a211e89..675da19dd 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp @@ -317,7 +317,8 @@ void print_verilog_top_testbench_global_shift_register_clock_ports_stimuli( static void print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator( std::fstream& fp, const BasicPort& start_sr_port, - const BasicPort& sr_clock_port, const float& sr_clock_period) { + const BasicPort& sr_clock_port, const float& sr_clock_period, + const VerilogTestbenchOption::e_simulator_type sim_type) { /* Validate the file stream */ valid_file_stream(fp); @@ -345,10 +346,14 @@ print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generat fp << "end"; fp << std::endl; - fp << "\t"; - fp << generate_verilog_port_constant_values( - sr_clock_port, std::vector(sr_clock_port.get_width(), 0), true); - fp << ";" << std::endl; + // The following code does not work when using Synopsys VCS. Comment them out. + // See if iverilog is fine or not + if (sim_type == VerilogTestbenchOption::e_simulator_type::IVERILOG) { + fp << "\t"; + fp << generate_verilog_port_constant_values( + sr_clock_port, std::vector(sr_clock_port.get_width(), 0), true); + fp << ";" << std::endl; + } fp << "end"; fp << std::endl; @@ -453,7 +458,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus( const ModuleId& top_module, const bool& fast_configuration, const bool& bit_value_to_skip, const FabricBitstream& fabric_bitstream, const MemoryBankShiftRegisterBanks& blwl_sr_banks, - const float& prog_clock_period, const float& timescale) { + const float& prog_clock_period, const float& timescale, + const VerilogTestbenchOption::e_simulator_type sim_type) { ModulePortId en_port_id = module_manager.find_module_port( top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1); @@ -531,7 +537,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus( print_verilog_comment( fp, "----- BL Shift register virtual clock generator -----"); print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator( - fp, start_bl_sr_port, virtual_bl_sr_clock_port, bl_sr_clock_period); + fp, start_bl_sr_port, virtual_bl_sr_clock_port, bl_sr_clock_period, + sim_type); print_verilog_comment(fp, "----- BL Shift register clock generator -----"); @@ -543,7 +550,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus( print_verilog_comment( fp, "----- WL Shift register virtual clock generator -----"); print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator( - fp, start_wl_sr_port, virtual_wl_sr_clock_port, wl_sr_clock_period); + fp, start_wl_sr_port, virtual_wl_sr_clock_port, wl_sr_clock_period, + sim_type); print_verilog_comment(fp, "----- WL Shift register clock generator -----"); print_verilog_full_testbench_ql_memory_bank_shift_register_clock_generator( diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.h b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.h index dc93b9873..b47ce9359 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.h +++ b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.h @@ -54,7 +54,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus( const ModuleId& top_module, const bool& fast_configuration, const bool& bit_value_to_skip, const FabricBitstream& fabric_bitstream, const MemoryBankShiftRegisterBanks& blwl_sr_banks, - const float& prog_clock_period, const float& timescale); + const float& prog_clock_period, const float& timescale, + const VerilogTestbenchOption::e_simulator_type sim_type); /** * @brief Print stimulus for a FPGA fabric with a memory bank configuration diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index dd95205de..2dab191cd 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -831,6 +831,24 @@ void print_verilog_wire_constant_values( fp << ";" << std::endl; } +/******************************************************************** + * Generate a wire connection, that assigns constant values to a + * Verilog port + *******************************************************************/ +void print_verilog_wire_constant_values_bit_blast( + std::fstream& fp, const BasicPort& output_port, + const std::vector& const_values) { + /* Make sure we have a valid file handler*/ + VTR_ASSERT(true == valid_file_stream(fp)); + + for (size_t ipin : output_port.pins()) { + BasicPort curr_pin(output_port.get_name(), ipin, ipin); + print_verilog_wire_constant_values( + fp, curr_pin, + std::vector(curr_pin.get_width(), const_values[ipin])); + } +} + /******************************************************************** * Deposit constant values to a Verilog port *******************************************************************/ diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h index 665f191a2..cffd10425 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.h +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h @@ -123,6 +123,10 @@ void print_verilog_wire_constant_values( std::fstream& fp, const BasicPort& output_port, const std::vector& const_values); +void print_verilog_wire_constant_values_bit_blast( + std::fstream& fp, const BasicPort& output_port, + const std::vector& const_values); + void print_verilog_deposit_wire_constant_values( std::fstream& fp, const BasicPort& output_port, const std::vector& const_values); diff --git a/openfpga/src/repack/build_physical_truth_table.cpp b/openfpga/src/repack/build_physical_truth_table.cpp index 86a2c7aa4..67f258c34 100644 --- a/openfpga/src/repack/build_physical_truth_table.cpp +++ b/openfpga/src/repack/build_physical_truth_table.cpp @@ -138,8 +138,13 @@ static void build_physical_pb_lut_truth_tables( size_t(lut_pb_id), output_pin->to_string().c_str()); VTR_LOGV(verbose, "Input nets:\n"); for (auto input_net : input_nets) { - VTR_LOGV(verbose, "\t%s\n", - atom_ctx.nlist.net_name(input_net).c_str()); + if (AtomNetId::INVALID() == input_net) { + VTR_LOGV(verbose, "\tunconn\n"); + } else { + VTR_ASSERT(AtomNetId::INVALID() != input_net); + VTR_LOGV(verbose, "\t%s\n", + atom_ctx.nlist.net_name(input_net).c_str()); + } } VTR_LOGV(verbose, "Output nets:\n"); VTR_LOGV(verbose, "\t%s\n", @@ -236,6 +241,10 @@ void build_physical_lut_truth_tables( for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { PhysicalPb& physical_pb = cluster_annotation.mutable_physical_pb(blk_id); + VTR_LOGV( + verbose, + "Build truth tables for physical LUTs under clustered block '%s'...\n", + cluster_ctx.clb_nlist.block_name(blk_id).c_str()); /* Find the LUT physical pb id */ for (const PhysicalPbId& primitive_pb : physical_pb.primitive_pbs()) { CircuitModelId circuit_model = device_annotation.pb_type_circuit_model( diff --git a/openfpga/src/repack/lb_router_utils.cpp b/openfpga/src/repack/lb_router_utils.cpp index 45b1fce24..25c4399eb 100644 --- a/openfpga/src/repack/lb_router_utils.cpp +++ b/openfpga/src/repack/lb_router_utils.cpp @@ -92,10 +92,9 @@ void save_lb_router_results_to_physical_pb(PhysicalPb& phy_pb, const AtomNetId& atom_net = lb_router.net_atom_net_id(net); /* Print info to help debug */ - VTR_LOGV(verbose, "Save net '%s' to physical pb_graph_pin '%s.%s[%d]'\n", + VTR_LOGV(verbose, "Save net '%s' to physical pb_graph_pin '%s'\n", atom_netlist.net_name(atom_net).c_str(), - pb_graph_pin->parent_node->pb_type->name, - pb_graph_pin->port->name, pb_graph_pin->pin_number); + pb_graph_pin->to_string().c_str()); if (AtomNetId::INVALID() == phy_pb.pb_graph_pin_atom_net(pb_id, pb_graph_pin)) { diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 35f45d7a1..4f3dc460a 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -304,6 +304,33 @@ static std::vector find_pb_route_by_atom_net( return pb_route_indices; } +/*************************************************************************************** + * This function will find the actual routing traces of the demanded net + * There is a specific search space applied when searching the routing traces: + * - ONLY applicable to the pb_pin of top-level pb_graph_node + ***************************************************************************************/ +static std::vector find_pb_routes_by_atom_net_among_top_pb_pins( + const t_pb* pb, const AtomNetId& atom_net_id) { + std::vector pb_route_indices; + + std::vector candidate_pool; + for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) { + /* Bypass unused pins */ + if ((0 == pb->pb_route.count(pin)) || + (AtomNetId::INVALID() == pb->pb_route.at(pin).atom_net_id)) { + continue; + } + /* Get the driver pb pin id, it must be valid */ + if (atom_net_id != pb->pb_route.at(pin).atom_net_id) { + continue; + } + if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root()) { + candidate_pool.push_back(pin); + } + } + return candidate_pool; +} + /*************************************************************************************** * This function will find the actual routing traces of the demanded net * There is a specific search space applied when searching the routing traces: @@ -584,7 +611,6 @@ static void add_lb_router_nets( std::string(lb_type->pb_type->name), curr_pin))) { /* Find the net mapped to this pin in clustering results*/ AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; - std::vector pb_route_indices = find_pb_route_by_atom_net(pb, source_pb_pin, atom_net_id); VTR_ASSERT(1 == pb_route_indices.size()); @@ -640,9 +666,15 @@ static void add_lb_router_nets( BasicPort curr_pin(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number); + /* Be very careful! There is only one routing trace for the net, it should + * never be ignored! */ if ((ignored_atom_nets[atom_net_id]) && + (find_pb_routes_by_atom_net_among_top_pb_pins(pb, atom_net_id).size() > + 1) && (options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), curr_pin))) { + VTR_LOGV(verbose, "Skip net '%s' as it is global and set to be ignored\n", + atom_ctx.nlist.net_name(atom_net_id).c_str()); continue; } diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp index 73b5fd77a..39cd6ce44 100644 --- a/openfpga/src/tile_direct/build_tile_direct.cpp +++ b/openfpga/src/tile_direct/build_tile_direct.cpp @@ -60,14 +60,14 @@ static std::string parse_direct_port(const std::string& direct_tile_inf) { /*************************************************************************************** * Check if a pin is located on a given side of physical tile - * If the given side is NUM_SIDES, we will search all the sides + * If the given side is NUM_2D_SIDES, we will search all the sides ***************************************************************************************/ static bool is_pin_locate_at_physical_tile_side( t_physical_tile_type_ptr physical_tile, const size_t& pin_width_offset, const size_t& pin_height_offset, const size_t& pin_id, const e_side& pin_side) { - if (NUM_SIDES == pin_side) { - for (size_t side = 0; side < NUM_SIDES; ++side) { + if (NUM_2D_SIDES == pin_side) { + for (size_t side = 0; side < NUM_2D_SIDES; ++side) { if (true == physical_tile->pinloc[pin_width_offset][pin_height_offset] [side][pin_id]) { return true; @@ -197,7 +197,7 @@ static vtr::Point find_inter_direct_destination_coordinate( * Our search space will start from the next column * and ends at the RIGHT side of fabric */ - if (INTER_COLUMN == arch_direct.type(arch_direct_id)) { + if (e_direct_type::INTER_COLUMN == arch_direct.type(arch_direct_id)) { if (POSITIVE_DIR == arch_direct.x_dir(arch_direct_id)) { /* Our first search space will be in x-direction: * @@ -262,7 +262,7 @@ static vtr::Point find_inter_direct_destination_coordinate( * Our search space will start from the next column * and ends at the RIGHT side of fabric */ - if (INTER_ROW == arch_direct.type(arch_direct_id)) { + if (e_direct_type::INTER_ROW == arch_direct.type(arch_direct_id)) { if (POSITIVE_DIR == arch_direct.y_dir(arch_direct_id)) { /* Our first search space will be in y-direction: * @@ -326,10 +326,11 @@ static vtr::Point find_inter_direct_destination_coordinate( for (size_t ix : first_search_space) { std::vector> next_col_row_coords; for (size_t iy : second_search_space) { - if (INTER_COLUMN == arch_direct.type(arch_direct_id)) { + if (e_direct_type::INTER_COLUMN == arch_direct.type(arch_direct_id)) { next_col_row_coords.push_back(vtr::Point(ix, iy)); } else { - VTR_ASSERT(INTER_ROW == arch_direct.type(arch_direct_id)); + VTR_ASSERT(e_direct_type::INTER_ROW == + arch_direct.type(arch_direct_id)); /* For cross-row connection, our search space is flipped */ next_col_row_coords.push_back(vtr::Point(iy, ix)); } @@ -417,7 +418,7 @@ static void build_inner_column_row_tile_direct( } /* Search all the sides, the from pin may locate any side! - * Note: the vpr_direct.from_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.from_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -452,7 +453,7 @@ static void build_inner_column_row_tile_direct( } /* Search all the sides, the to pin may locate any side! - * Note: the vpr_direct.to_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.to_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -481,10 +482,10 @@ static void build_inner_column_row_tile_direct( "%s[%lu][%lu].%s[%lu] at side '%s'\n", from_tile_name.c_str(), x, y, from_tile_port.get_name().c_str(), from_pins[ipin], - SIDE_STRING[from_side], to_tile_name.c_str(), + TOTAL_2D_SIDE_STRINGS[from_side], to_tile_name.c_str(), to_grid_coord.x(), to_grid_coord.y(), to_tile_port.get_name().c_str(), to_pins[ipin], - SIDE_STRING[to_side]); + TOTAL_2D_SIDE_STRINGS[to_side]); TileDirectId tile_direct_id = tile_direct.add_direct( from_grid_coord, from_side, from_pins[ipin], to_grid_coord, to_side, to_pins[ipin]); @@ -549,8 +550,8 @@ static void build_inter_column_row_tile_direct( /* Go through the direct connection list, see if we need intra-column/row * connection here */ - if ((INTER_COLUMN != arch_direct.type(arch_direct_id)) && - (INTER_ROW != arch_direct.type(arch_direct_id))) { + if ((e_direct_type::INTER_COLUMN != arch_direct.type(arch_direct_id)) && + (e_direct_type::INTER_ROW != arch_direct.type(arch_direct_id))) { return; } /* For cross-column connection, we will search the first valid grid in each @@ -568,7 +569,7 @@ static void build_inter_column_row_tile_direct( * +------+ * */ - if (INTER_COLUMN == arch_direct.type(arch_direct_id)) { + if (e_direct_type::INTER_COLUMN == arch_direct.type(arch_direct_id)) { for (size_t ix = 1; ix < device_ctx.grid.width() - 1; ++ix) { std::vector> next_col_src_grid_coords; /* For negative y- direction, we should start from y = ny */ @@ -592,7 +593,7 @@ static void build_inter_column_row_tile_direct( } /* Search all the sides, the from pin may locate any side! - * Note: the vpr_direct.from_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.from_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -622,7 +623,7 @@ static void build_inter_column_row_tile_direct( } /* Search all the sides, the to pin may locate any side! - * Note: the vpr_direct.to_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.to_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -654,10 +655,10 @@ static void build_inter_column_row_tile_direct( "%s[%lu][%lu].%s[%lu] at side '%s'\n", from_tile_name.c_str(), from_grid_coord.x(), from_grid_coord.y(), from_tile_port.get_name().c_str(), - from_pins[ipin], SIDE_STRING[from_side], + from_pins[ipin], TOTAL_2D_SIDE_STRINGS[from_side], to_tile_name.c_str(), to_grid_coord.x(), to_grid_coord.y(), to_tile_port.get_name().c_str(), to_pins[ipin], - SIDE_STRING[to_side]); + TOTAL_2D_SIDE_STRINGS[to_side]); TileDirectId tile_direct_id = tile_direct.add_direct( from_grid_coord, from_side, from_pins[ipin], to_grid_coord, @@ -671,7 +672,7 @@ static void build_inter_column_row_tile_direct( } /* Reach here, it must be a cross-row connection */ - VTR_ASSERT(INTER_ROW == arch_direct.type(arch_direct_id)); + VTR_ASSERT(e_direct_type::INTER_ROW == arch_direct.type(arch_direct_id)); /* For cross-row connection, we will search the first valid grid in each * column from x = 1 to x = nx * @@ -703,7 +704,7 @@ static void build_inter_column_row_tile_direct( } /* Search all the sides, the from pin may locate any side! - * Note: the vpr_direct.from_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.from_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -733,7 +734,7 @@ static void build_inter_column_row_tile_direct( } /* Search all the sides, the to pin may locate any side! - * Note: the vpr_direct.to_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.to_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -765,10 +766,10 @@ static void build_inter_column_row_tile_direct( "at side '%s'\n", from_tile_name.c_str(), from_grid_coord.x(), from_grid_coord.y(), from_tile_port.get_name().c_str(), - from_pins[ipin], SIDE_STRING[from_side], + from_pins[ipin], TOTAL_2D_SIDE_STRINGS[from_side], to_tile_name.c_str(), to_grid_coord.x(), to_grid_coord.y(), to_tile_port.get_name().c_str(), to_pins[ipin], - SIDE_STRING[to_side]); + TOTAL_2D_SIDE_STRINGS[to_side]); TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord, from_side, from_pins[ipin], @@ -804,9 +805,14 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx, exit(1); } /* Build from original VPR arch definition */ - build_inner_column_row_tile_direct(tile_direct, - device_ctx.arch->Directs[idirect], - device_ctx, arch_direct_id, verbose); + if (e_direct_type::INNER_COLUMN_OR_ROW == + arch_direct.type(arch_direct_id)) { + build_inner_column_row_tile_direct(tile_direct, + device_ctx.arch->Directs[idirect], + device_ctx, arch_direct_id, verbose); + /* Skip those direct connections which belong part of a connection block + */ + } /* Build from OpenFPGA arch definition */ build_inter_column_row_tile_direct( tile_direct, device_ctx.arch->Directs[idirect], device_ctx, arch_direct, diff --git a/openfpga/src/utils/decoder_library_utils.cpp b/openfpga/src/utils/decoder_library_utils.cpp index d3232b7ae..54135a4db 100644 --- a/openfpga/src/utils/decoder_library_utils.cpp +++ b/openfpga/src/utils/decoder_library_utils.cpp @@ -77,7 +77,7 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size) { ***************************************************************************************/ size_t find_memory_decoder_addr_size(const size_t& num_mems) { return find_mux_local_decoder_addr_size( - find_memory_decoder_data_size(num_mems)); + find_memory_decoder_data_size(num_mems, 0, false)); } /*************************************************************************************** @@ -86,8 +86,18 @@ size_t find_memory_decoder_addr_size(const size_t& num_mems) { *lines and word lines, the number of data lines will be a square root of the *number of memory cells. ***************************************************************************************/ -size_t find_memory_decoder_data_size(const size_t& num_mems) { - return (size_t)std::ceil(std::sqrt((float)num_mems)); +size_t find_memory_decoder_data_size(const size_t& num_mems, + const size_t& defined_num_wl, + const bool is_bl) { + if (defined_num_wl == 0) { + return (size_t)std::ceil(std::sqrt((float)num_mems)); + } else { + if (is_bl) { + return find_memory_wl_decoder_data_size(num_mems, defined_num_wl); + } else { + return defined_num_wl; + } + } } /*************************************************************************************** diff --git a/openfpga/src/utils/decoder_library_utils.h b/openfpga/src/utils/decoder_library_utils.h index 51d6da6dd..63aa501a9 100644 --- a/openfpga/src/utils/decoder_library_utils.h +++ b/openfpga/src/utils/decoder_library_utils.h @@ -15,7 +15,9 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size); size_t find_memory_decoder_addr_size(const size_t& num_mems); -size_t find_memory_decoder_data_size(const size_t& num_mems); +size_t find_memory_decoder_data_size(const size_t& num_mems, + const size_t& defined_num_wl, + const bool is_bl); size_t find_memory_wl_decoder_data_size(const size_t& num_mems, const size_t& num_bls); diff --git a/openfpga/src/utils/memory_utils.cpp b/openfpga/src/utils/memory_utils.cpp index 0abf95b07..9dc799949 100644 --- a/openfpga/src/utils/memory_utils.cpp +++ b/openfpga/src/utils/memory_utils.cpp @@ -436,7 +436,8 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type, * - QL Memory decoders: Apply square root as BL/WLs will be grouped ********************************************************************/ size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, - const size_t& num_config_bits) { + const size_t& num_config_bits, + const size_t& defined_num_wl) { size_t sram_port_size = num_config_bits; switch (sram_orgz_type) { @@ -447,7 +448,8 @@ size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, sram_port_size = 1; break; case CONFIG_MEM_QL_MEMORY_BANK: - sram_port_size = find_memory_decoder_data_size(num_config_bits); + sram_port_size = + find_memory_decoder_data_size(num_config_bits, defined_num_wl, true); break; case CONFIG_MEM_MEMORY_BANK: break; diff --git a/openfpga/src/utils/memory_utils.h b/openfpga/src/utils/memory_utils.h index 184d0be74..a619c07fb 100644 --- a/openfpga/src/utils/memory_utils.h +++ b/openfpga/src/utils/memory_utils.h @@ -42,7 +42,8 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits); size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, - const size_t& num_config_bits); + const size_t& num_config_bits, + const size_t& defined_num_wl); /** * @brief Compute the number of configurable children to be skipped for a given diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index 70a62d148..4a52f46ff 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -419,11 +419,16 @@ void add_sram_ports_to_module_manager( void add_pb_sram_ports_to_module_manager( ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits) { + const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits, + const uint32_t defined_num_wl) { + if (defined_num_wl) { + // Only support defined_num_wl if the configuration mode is QL Memory Bank + VTR_ASSERT(sram_orgz_type == CONFIG_MEM_QL_MEMORY_BANK); + } std::vector sram_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type); size_t sram_port_size = - generate_pb_sram_port_size(sram_orgz_type, num_config_bits); + generate_pb_sram_port_size(sram_orgz_type, num_config_bits, defined_num_wl); /* Add ports to the module manager */ switch (sram_orgz_type) { diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h index f55f73402..0bcb59042 100644 --- a/openfpga/src/utils/module_manager_utils.h +++ b/openfpga/src/utils/module_manager_utils.h @@ -74,7 +74,8 @@ void add_sram_ports_to_module_manager( void add_pb_sram_ports_to_module_manager( ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits); + const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits, + const uint32_t defined_num_wl = 0); void add_primitive_pb_type_ports_to_module_manager( ModuleManager& module_manager, const ModuleId& module_id, diff --git a/openfpga/src/utils/openfpga_clustered_netlist_utils.cpp b/openfpga/src/utils/openfpga_clustered_netlist_utils.cpp new file mode 100644 index 000000000..e4823b873 --- /dev/null +++ b/openfpga/src/utils/openfpga_clustered_netlist_utils.cpp @@ -0,0 +1,35 @@ +/*************************************************************************************** + * This file includes most utilized functions that are used to acquire data from + * VPR clustered netlist (post-packing netlist) + ***************************************************************************************/ + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from vtrutil library */ +#include "openfpga_clustered_netlist_utils.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/*************************************************************************************** + * Find the names of all the atom blocks that drive clock nets + * This function will find if the block has been renamed due to contain + *sensitive characters that violates the Verilog syntax + ***************************************************************************************/ +std::vector find_clustered_netlist_global_nets( + const ClusteredNetlist& clb_nlist) { + std::vector gnets; + + for (ClusterNetId net_id : clb_nlist.nets()) { + if (clb_nlist.net_is_ignored(net_id)) { + gnets.push_back(net_id); + } + } + + return gnets; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/utils/openfpga_clustered_netlist_utils.h b/openfpga/src/utils/openfpga_clustered_netlist_utils.h new file mode 100644 index 000000000..252bd99f4 --- /dev/null +++ b/openfpga/src/utils/openfpga_clustered_netlist_utils.h @@ -0,0 +1,24 @@ +#ifndef OPENFPGA_CLUSTERED_NETLIST_UTILS_H +#define OPENFPGA_CLUSTERED_NETLIST_UTILS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include + +#include "clustered_netlist.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +std::vector find_clustered_netlist_global_nets( + const ClusteredNetlist& clb_nlist); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 1f539ffcf..f8f16db64 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -27,7 +27,7 @@ namespace openfpga { *******************************************************************/ std::vector find_physical_tile_pin_side( t_physical_tile_type_ptr physical_tile, const int& physical_pin, - const e_side& border_side) { + const e_side& border_side, const bool& perimeter_cb) { std::vector pin_sides; for (const e_side& side_cand : {TOP, RIGHT, BOTTOM, LEFT}) { int pin_width_offset = physical_tile->pin_width_offset[physical_pin]; @@ -40,17 +40,21 @@ std::vector find_physical_tile_pin_side( /* For regular grid, we should have pin only one side! * I/O grids: VPR creates the grid with duplicated pins on every side - * but the expected side (only used side) will be opposite side of the border - * side! + * - In regular cases: the expected side (only used side) will be on the + * opposite to the border side! + * - When perimeter cb is on, the expected sides can be on any sides except + * the border side. But we only expect 1 side */ - if (NUM_SIDES == border_side) { + if (NUM_2D_SIDES == border_side) { VTR_ASSERT(1 == pin_sides.size()); - } else { + } else if (!perimeter_cb) { SideManager side_manager(border_side); VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(), pin_sides.end(), side_manager.get_opposite())); pin_sides.clear(); pin_sides.push_back(side_manager.get_opposite()); + } else { + VTR_ASSERT(1 == pin_sides.size() && pin_sides[0] != border_side); } return pin_sides; @@ -88,10 +92,10 @@ std::set find_physical_io_tile_located_sides( /* Search the core part */ for (size_t ix = 1; ix < grids.width() - 1; ++ix) { for (size_t iy = 1; iy < grids.height() - 1; ++iy) { - /* If located in center, we add a NUM_SIDES and finish */ + /* If located in center, we add a NUM_2D_SIDES and finish */ if (physical_tile == grids.get_physical_type(t_physical_tile_loc(ix, iy, 0))) { - io_sides.insert(NUM_SIDES); + io_sides.insert(NUM_2D_SIDES); center_io = true; break; } @@ -108,7 +112,7 @@ std::set find_physical_io_tile_located_sides( for (const e_side& fpga_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[fpga_side]) { - /* If located in center, we add a NUM_SIDES and finish */ + /* If located in center, we add a NUM_2D_SIDES and finish */ if (physical_tile == grids.get_physical_type(t_physical_tile_loc( io_coordinate.x(), io_coordinate.y(), 0))) { io_sides.insert(fpga_side); @@ -141,9 +145,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, } PortParser tile_parser(pin_tokens[0]); BasicPort tile_info = tile_parser.port(); - if (tile_info.get_name() != std::string(physical_tile->name)) { - return pin_idx; - } if (!tile_info.is_valid()) { VTR_LOG_ERROR( "Invalid pin name '%s' whose subtile index is not valid, expect [0, " @@ -151,6 +152,10 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, pin_name.c_str(), physical_tile->capacity - 1); exit(1); } + /* Bypass unmatched subtiles*/ + if (tile_info.get_name() != std::string(physical_tile->name)) { + return pin_idx; + } /* precheck: return unfound pin if the subtile index does not match */ if (tile_info.get_width() != 1) { VTR_LOG_ERROR( @@ -159,13 +164,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, pin_name.c_str()); exit(1); } - if (tile_info.get_msb() > size_t(physical_tile->capacity) - 1) { - VTR_LOG_ERROR( - "Invalid pin name '%s' whose subtile index is out of range, expect [0, " - "%lu]\n", - pin_name.c_str(), physical_tile->capacity - 1); - exit(1); - } /* precheck: return unfound pin if the pin index does not match */ PortParser pin_parser(pin_tokens[1]); BasicPort pin_info = pin_parser.port(); @@ -179,8 +177,11 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, } /* Spot the subtile by using the index */ + size_t acc_pin_index = 0; for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) { + /* Bypass unmatched subtiles*/ if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) { + acc_pin_index += sub_tile.num_phy_pins; continue; } for (const t_physical_tile_port& sub_tile_port : sub_tile.ports) { @@ -203,8 +204,9 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, } /* Reach here, we get the port we want, return the accumulated index */ size_t accumulated_pin_idx = - sub_tile_port.absolute_first_pin_index + - sub_tile.num_phy_pins * (tile_info.get_lsb() - sub_tile.capacity.low) + + acc_pin_index + sub_tile_port.absolute_first_pin_index + + (sub_tile.num_phy_pins / sub_tile.capacity.total()) * + (tile_info.get_lsb() - sub_tile.capacity.low) + pin_info.get_lsb(); return accumulated_pin_idx; } diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.h b/openfpga/src/utils/openfpga_physical_tile_utils.h index 1ac98f321..68cb3972e 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.h +++ b/openfpga/src/utils/openfpga_physical_tile_utils.h @@ -20,7 +20,7 @@ namespace openfpga { std::vector find_physical_tile_pin_side( t_physical_tile_type_ptr physical_tile, const int& physical_pin, - const e_side& border_side); + const e_side& border_side, const bool& perimeter_cb); float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type, const int& pin); diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp index 12d5572e3..ddb8c954f 100644 --- a/openfpga/src/utils/physical_pb_utils.cpp +++ b/openfpga/src/utils/physical_pb_utils.cpp @@ -131,7 +131,8 @@ void alloc_physical_pb_from_pb_graph( static void update_primitive_physical_pb_pin_atom_net( PhysicalPb& phy_pb, const PhysicalPbId& primitive_pb, const t_pb_graph_pin* pb_graph_pin, const t_pb_routes& pb_route, - const VprDeviceAnnotation& device_annotation) { + const VprDeviceAnnotation& device_annotation, const AtomNetlist& atom_nlist, + const bool& verbose) { int node_index = pb_graph_pin->pin_count_in_cluster; if (pb_route.count(node_index)) { /* The pin is mapped to a net, find the original pin in the atom netlist */ @@ -144,15 +145,11 @@ static void update_primitive_physical_pb_pin_atom_net( device_annotation.physical_pb_graph_pin(pb_graph_pin); VTR_ASSERT(nullptr != physical_pb_graph_pin); - /* Print info to help debug - bool verbose = true; - VTR_LOGV(verbose, - "\nSynchronize net '%lu' to physical pb_graph_pin '%s.%s[%d]'\n", - size_t(atom_net), - pb_graph_pin->parent_node->pb_type->name, - pb_graph_pin->port->name, - pb_graph_pin->pin_number); - */ + if (AtomNetId::INVALID() != atom_net) { + VTR_LOGV(verbose, "Synchronize net '%s' to physical pb_graph_pin '%s'\n", + atom_nlist.net_name(atom_net).c_str(), + pb_graph_pin->to_string().c_str()); + } /* Check if the pin has been mapped to a net. * If yes, the atom net must be the same @@ -165,6 +162,11 @@ static void update_primitive_physical_pb_pin_atom_net( VTR_ASSERT(atom_net == phy_pb.pb_graph_pin_atom_net( primitive_pb, physical_pb_graph_pin)); } + } else { + VTR_LOGV(verbose, + "Skip as no valid routing traces if found on physical " + "pb_graph_pin '%s'\n", + pb_graph_pin->to_string().c_str()); } } @@ -175,22 +177,39 @@ static void synchronize_primitive_physical_pb_atom_nets( PhysicalPb& phy_pb, const PhysicalPbId& primitive_pb, const t_pb_graph_node* pb_graph_node, const t_pb_routes& pb_route, const AtomContext& atom_ctx, const AtomBlockId& atom_blk, - const VprDeviceAnnotation& device_annotation) { + const VprDeviceAnnotation& device_annotation, const bool& verbose) { /* Iterate over all the ports: input, output and clock */ + VTR_LOGV(verbose, "Synchronizing atom nets on pb_graph_node '%s'...\n", + pb_graph_node->hierarchical_type_name().c_str()); for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) { for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) { /* Port exists (some LUTs may have no input and hence no port in the atom * netlist) */ + VTR_LOGV(verbose, "Synchronizing atom nets on pb_graph_pin '%s'...\n", + pb_graph_node->input_pins[iport][ipin].to_string().c_str()); t_model_ports* model_port = pb_graph_node->input_pins[iport][ipin].port->model_port; + /* Special for LUTs, the model port is hidden under 1 level + * Do NOT do this. Net mapping on LUT inputs may be swapped during + * rerouting + * if (LUT_CLASS == pb_graph_node->pb_type->class_type) { + * VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); + * model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] + * .input_pins[iport][ipin] + * .port->model_port; + * } + */ + /* It seems that LUT port are no longer built with an internal model */ if (nullptr == model_port) { + VTR_LOGV(verbose, "Skip due to empty model port\n"); continue; } AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, model_port); if (!atom_port) { + VTR_LOGV(verbose, "Skip due to invalid port\n"); continue; } /* Find the atom nets mapped to the pin @@ -199,7 +218,7 @@ static void synchronize_primitive_physical_pb_atom_nets( */ update_primitive_physical_pb_pin_atom_net( phy_pb, primitive_pb, &(pb_graph_node->input_pins[iport][ipin]), - pb_route, device_annotation); + pb_route, device_annotation, atom_ctx.nlist, verbose); } } @@ -207,15 +226,29 @@ static void synchronize_primitive_physical_pb_atom_nets( for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) { /* Port exists (some LUTs may have no input and hence no port in the atom * netlist) */ + VTR_LOGV(verbose, "Synchronizing atom nets on pb_graph_pin '%s'...\n", + pb_graph_node->output_pins[iport][ipin].to_string().c_str()); t_model_ports* model_port = pb_graph_node->output_pins[iport][ipin].port->model_port; + /* Special for LUTs, the model port is hidden under 1 level + * Do NOT do this. Net mapping on LUT inputs may be swapped during + * rerouting + * if (LUT_CLASS == pb_graph_node->pb_type->class_type) { + * VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); + * model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] + * .output_pins[iport][ipin] + * .port->model_port; + * } + */ if (nullptr == model_port) { + VTR_LOGV(verbose, "Skip due to empty model port\n"); continue; } AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, model_port); if (!atom_port) { + VTR_LOGV(verbose, "Skip due to invalid port\n"); continue; } /* Find the atom nets mapped to the pin @@ -224,7 +257,7 @@ static void synchronize_primitive_physical_pb_atom_nets( */ update_primitive_physical_pb_pin_atom_net( phy_pb, primitive_pb, &(pb_graph_node->output_pins[iport][ipin]), - pb_route, device_annotation); + pb_route, device_annotation, atom_ctx.nlist, verbose); } } @@ -232,15 +265,19 @@ static void synchronize_primitive_physical_pb_atom_nets( for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) { /* Port exists (some LUTs may have no input and hence no port in the atom * netlist) */ + VTR_LOGV(verbose, "Synchronizing atom nets on pb_graph_pin '%s'...\n", + pb_graph_node->clock_pins[iport][ipin].to_string().c_str()); t_model_ports* model_port = pb_graph_node->clock_pins[iport][ipin].port->model_port; if (nullptr == model_port) { + VTR_LOGV(verbose, "Skip due to empty model port\n"); continue; } AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, model_port); if (!atom_port) { + VTR_LOGV(verbose, "Skip due to invalid port\n"); continue; } /* Find the atom nets mapped to the pin @@ -249,7 +286,7 @@ static void synchronize_primitive_physical_pb_atom_nets( */ update_primitive_physical_pb_pin_atom_net( phy_pb, primitive_pb, &(pb_graph_node->clock_pins[iport][ipin]), - pb_route, device_annotation); + pb_route, device_annotation, atom_ctx.nlist, verbose); } } } @@ -280,10 +317,8 @@ static void mark_physical_pb_wired_lut_outputs( VTR_ASSERT(nullptr != physical_pb_graph_pin); /* Print debug info */ - VTR_LOGV( - verbose, "Mark physical pb_graph pin '%s.%s[%d]' as wire LUT output\n", - physical_pb_graph_pin->parent_node->pb_type->name, - physical_pb_graph_pin->port->name, physical_pb_graph_pin->pin_number); + VTR_LOGV(verbose, "Mark physical pb_graph pin '%s' as wire LUT output\n", + physical_pb_graph_pin->to_string().c_str()); /* Label the pins in physical_pb as driven by wired LUT*/ phy_pb.set_wire_lut_output(primitive_pb, physical_pb_graph_pin, true); @@ -318,6 +353,9 @@ void rec_update_physical_pb_from_operating_pb( VTR_ASSERT(atom_blk); phy_pb.add_atom_block(physical_pb, atom_blk); + VTR_LOGV(verbose, "Update physical pb '%s' using atom block '%s'\n", + physical_pb_graph_node->hierarchical_type_name().c_str(), + atom_ctx.nlist.block_name(atom_blk).c_str()); /* if the operating pb type has bitstream annotation, * bind the bitstream value from atom block to the physical pb @@ -400,7 +438,7 @@ void rec_update_physical_pb_from_operating_pb( /* Iterate over ports and annotate the atom pins */ synchronize_primitive_physical_pb_atom_nets( phy_pb, physical_pb, pb_graph_node, pb_route, atom_ctx, atom_blk, - device_annotation); + device_annotation, verbose); return; } diff --git a/openfpga/src/utils/report_reference.cpp b/openfpga/src/utils/report_reference.cpp new file mode 100644 index 000000000..3a3bea935 --- /dev/null +++ b/openfpga/src/utils/report_reference.cpp @@ -0,0 +1,123 @@ +/*************************************************************************************** + * Output internal structure of module graph to XML format + ***************************************************************************************/ +/* Headers from system goes first */ +#include +#include +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from openfpgautil library */ +#include "command_exit_codes.h" +#include "openfpga_digest.h" +#include "openfpga_naming.h" +#include "report_reference.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Top-level function + *******************************************************************/ +int report_reference(const char* fname, const std::string& module_name, + const ModuleManager& module_manager, + const bool& include_time_stamp, const bool& verbose) { + vtr::ScopedStartFinishTimer timer("Report reference"); + + ModuleId parent_module = module_manager.find_module(module_name); + if (false == module_manager.valid_module_id(parent_module)) { + VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + + show_reference_count(parent_module, module_manager); + + return write_reference_to_file(fname, parent_module, module_manager, + include_time_stamp, verbose); +} + +/******************************************************************** + * show reference count of each child module under given parent module + *******************************************************************/ +void show_reference_count(const ModuleId& parent_module, + const ModuleManager& module_manager) { + VTR_LOG( + "----------------------------------------------------------------------\n"); + VTR_LOG( + "Module Count \n"); + VTR_LOG( + "--------------------------------------------------------------------- \n"); + size_t ref_cnt = 0; + for (ModuleId child_module : module_manager.child_modules(parent_module)) { + std::string child_module_name = module_manager.module_name(child_module); + std::vector child_inst_vec = + module_manager.child_module_instances(parent_module, child_module); + VTR_LOG("%-s %d\n", child_module_name.c_str(), child_inst_vec.size()); + ref_cnt += child_inst_vec.size(); + } + VTR_LOG( + "----------------------------------------------------------------------\n"); + VTR_LOG("Total: %zu modules %zu references\n", + module_manager.child_modules(parent_module).size(), ref_cnt); + VTR_LOG( + "----------------------------------------------------------------------\n"); +} + +/******************************************************************** + * write reference info to a given file in YAML format + *******************************************************************/ +int write_reference_to_file(const char* fname, const ModuleId& parent_module, + const ModuleManager& module_manager, + const bool& include_time_stamp, + const bool& verbose) { + std::fstream fp; + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + openfpga::check_file_stream(fname, fp); + + if (include_time_stamp) { + auto end = std::chrono::system_clock::now(); + std::time_t end_time = std::chrono::system_clock::to_time_t(end); + fp << "Date: " << std::ctime(&end_time) << std::endl; + } + + fp << "#the instance names are given during netlist generation" << std::endl; + + size_t ref_cnt = 0; + fp << "references:" << std::endl; + for (ModuleId child_module : module_manager.child_modules(parent_module)) { + std::string child_module_name = module_manager.module_name(child_module); + std::vector child_inst_vec = + module_manager.child_module_instances(parent_module, child_module); + fp << "- module: " << child_module_name.c_str() << std::endl + << " count: " << child_inst_vec.size() << std::endl + << " instances:" << std::endl; + for (size_t inst_id : child_inst_vec) { + std::string inst_name = + module_manager.instance_name(parent_module, child_module, inst_id); + fp << " - "; + if (true == inst_name.empty()) { + fp << generate_instance_name(child_module_name, inst_id) << std::endl; + } else { + fp << inst_name << std::endl; + } + } + ref_cnt += child_inst_vec.size(); + } + + if (verbose) { + fp << std::endl + << "Total: " << module_manager.child_modules(parent_module).size() + << " modules " << ref_cnt << " references" << std::endl; + } + + fp.close(); + return CMD_EXEC_SUCCESS; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/utils/report_reference.h b/openfpga/src/utils/report_reference.h new file mode 100644 index 000000000..2afd89cc0 --- /dev/null +++ b/openfpga/src/utils/report_reference.h @@ -0,0 +1,30 @@ +#ifndef REPORT_REFERENCE_H +#define REPORT_REFERENCE_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "module_manager.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { +int report_reference(const char* fname, const std::string& module_name, + const ModuleManager& module_manager, + const bool& include_time_stamp, const bool& verbose); + +void show_reference_count(const ModuleId& parent_module, + const ModuleManager& module_manager); + +int write_reference_to_file(const char* fname, const ModuleId& parent_module, + const ModuleManager& module_manager, + const bool& include_time_stamp, + const bool& verbose); +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/vpr_wrapper/vpr_main.cpp b/openfpga/src/vpr_wrapper/vpr_main.cpp index 940fc0644..c872a17a4 100644 --- a/openfpga/src/vpr_wrapper/vpr_main.cpp +++ b/openfpga/src/vpr_wrapper/vpr_main.cpp @@ -68,7 +68,7 @@ static int vpr(int argc, char** argv) { */ /* vpr_free_all(Arch, vpr_setup); */ - VTR_LOG("VPR suceeded\n"); + VTR_LOG("VPR succeeded\n"); } catch (const tatum::Error& tatum_error) { VTR_LOG_ERROR("%s\n", format_tatum_error(tatum_error).c_str()); diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v b/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v new file mode 100644 index 000000000..d939c7ab3 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v @@ -0,0 +1,21 @@ +///////////////////////////////////////// +// Functionality: A locally generated clock signal which is to test clock network with internal drivers +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module clk_cond(clk_i, clk_cond_i, d_i, q_o); + +input wire clk_cond_i; +input wire clk_i; +input wire d_i; +output reg q_o; + +wire int_clk; +assign int_clk = clk_cond_i & clk_i; + +always @(posedge int_clk) begin + q_o <= d_i; +end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v b/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v new file mode 100644 index 000000000..80814e49b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v @@ -0,0 +1,21 @@ +///////////////////////////////////////// +// Functionality: A register driven by a combinational logic with clk signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module clk_on_lut(a, b, q, out, clk); + +input wire clk; +input wire a; +input wire b; +output reg q; +output wire out; + +always @(posedge clk) begin + q <= a; +end + +assign out = b & clk; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v b/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v new file mode 100644 index 000000000..598d41dcf --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v @@ -0,0 +1,29 @@ +///////////////////////////////////////// +// Functionality: A register driven by a combinational logic with reset signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module rst_and_clk_on_lut(a, b, c, q, out0, out1, clk, rst); + +input wire rst; +input wire clk; +input wire a; +input wire b; +input wire c; +output reg q; +output wire out0; +output wire out1; + +always @(posedge rst or posedge clk) begin + if (rst) begin + q <= 0; + end else begin + q <= a; + end +end + +assign out0 = b & ~rst; +assign out1 = c & ~clk; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v b/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v new file mode 100644 index 000000000..fba40f3a7 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v @@ -0,0 +1,26 @@ +///////////////////////////////////////// +// Functionality: A locally generated reset signal which is to test clock network with internal drivers +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module rst_cond(rst_i, rst_cond_i, clk_i, d_i, q_o); + +input wire rst_cond_i; +input wire rst_i; +input wire clk_i; +input wire d_i; +output reg q_o; + +wire int_rst; +assign int_rst = rst_cond_i & rst_i; + +always @(posedge int_rst or posedge clk_i) begin + if (int_rst) begin + q_o <= 0; + end else begin + q_o <= d_i; + end +end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v new file mode 100644 index 000000000..33a8db5f3 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v @@ -0,0 +1,35 @@ +///////////////////////////////////////// +// Functionality: 4-bit version of A register driven by a combinational logic with reset signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module rst_on_lut_4bit(a, b0, b1, b2, b3, q, out0, out1, out2, out3, clk, rst); + +input wire rst; +input wire clk; +input wire a; +input wire b0; +input wire b1; +input wire b2; +input wire b3; +output reg q; +output wire out0; +output wire out1; +output wire out2; +output wire out3; + +always @(posedge rst or posedge clk) begin + if (rst) begin + q <= 0; + end else begin + q <= a; + end +end + +assign out0 = b0 & ~rst; +assign out1 = b1 & ~rst; +assign out2 = b2 & ~rst; +assign out3 = b3 & ~rst; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_8bit/rst_on_lut_8bit.v b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_8bit/rst_on_lut_8bit.v new file mode 100644 index 000000000..30c97205a --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_8bit/rst_on_lut_8bit.v @@ -0,0 +1,47 @@ +///////////////////////////////////////// +// Functionality: 8-bit version of A register driven by a combinational logic with reset signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module rst_on_lut_8bit(a, b0, b1, b2, b3, b4, b5, b6, b7, q, out0, out1, out2, out3, out4, out5, out6, out7, clk, rst); + +input wire rst; +input wire clk; +input wire a; +input wire b0; +input wire b1; +input wire b2; +input wire b3; +input wire b4; +input wire b5; +input wire b6; +input wire b7; +output reg q; +output wire out0; +output wire out1; +output wire out2; +output wire out3; +output wire out4; +output wire out5; +output wire out6; +output wire out7; + +always @(posedge rst or posedge clk) begin + if (rst) begin + q <= 0; + end else begin + q <= a; + end +end + +assign out0 = b0 & ~rst; +assign out1 = b1 & ~rst; +assign out2 = b2 & ~rst; +assign out3 = b3 & ~rst; +assign out4 = b4 & ~rst; +assign out5 = b5 & ~rst; +assign out6 = b6 & ~rst; +assign out7 = b7 & ~rst; + +endmodule diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index 5958d1b6b..5a43f561b 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -22,8 +22,6 @@ clb_blocks = "Netlist clb blocks: ([0-9]+)", str io_blocks = "Netlist io blocks: ([0-9]+)", str mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str memory_blocks = "Netlist memory blocks: ([0-9]+)", str -logic_delay = "Total logic delay: ([0-9.]+)", str -total_net_delay = "total net delay: ([0-9.]+)", str total_routing_area = "Total routing area: ([0-9.]+[e|E\+[0-9]+)", str total_logic_block_area = "Total used logic block area: ([0-9.]+[e|E\+[0-9]+)", str total_wire_length = "Total wirelength: ([0-9]+)", str @@ -31,7 +29,7 @@ packing_time = "Packing took ([0-9.]+) seconds", str placement_time = "Placement took ([0-9.]+) seconds", str routing_time = "Routing took ([0-9.]+) seconds", str average_net_length = "average net length: ([0-9.]+)", str -critical_path = "Final critical path: ([0-9.]+) ([a-z])s", scientific +critical_path = "Final critical path delay \(least slack\): ([0-9.]+) ([a-z])s", scientific total_routing_time = "Routing took ([0-9.]+) seconds", float [DEFAULT_PARSE_RESULT_POWER] diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf b/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf new file mode 100644 index 000000000..50bdfd1ff --- /dev/null +++ b/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf @@ -0,0 +1,76 @@ +# Standard Configuration Example +[CAD_TOOLS_PATH] +openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga +yosys_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys +misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc +odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe +abc_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys-abc +abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc +abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc +vpr_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/vpr/vpr +ace_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/ace2/ace +pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl +iverilog_path = iverilog +include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists + +[FLOW_SCRIPT_CONFIG] +valid_flows = vpr_blif,yosys_vpr + +[DEFAULT_PARSE_RESULT_VPR] +# parser format = , +clb_blocks = "Netlist clb blocks: ([0-9]+)", str +io_blocks = "Netlist io blocks: ([0-9]+)", str +mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str +memory_blocks = "Netlist memory blocks: ([0-9]+)", str +total_routing_area = "Total routing area: ([0-9.]+[e|E\+[0-9]+)", str +total_logic_block_area = "Total used logic block area: ([0-9.]+[e|E\+[0-9]+)", str +total_wire_length = "Total wirelength: ([0-9]+)", str +packing_time = "Packing took ([0-9.]+) seconds", str +placement_time = "Placement took ([0-9.]+) seconds", str +routing_time = "Routing took ([0-9.]+) seconds", str +average_net_length = "average net length: ([0-9.]+)", str +critical_path = "Final critical path delay \(least slack\): ([0-9.]+) ([a-z])s", scientific +vclk0_critical_path = "virtual_io_clock to clk0 CPD: ([0-9.]+) ([a-z])s", scientific +clk0_critical_path = "clk0 to clk0 CPD: ([0-9.]+) ([a-z])s", scientific +vclk1_critical_path = "virtual_io_clock to clk1 CPD: ([0-9.]+) ([a-z])s", scientific +clk1_critical_path = "clk1 to clk1 CPD: ([0-9.]+) ([a-z])s", scientific +total_routing_time = "Routing took ([0-9.]+) seconds", float + +[DEFAULT_PARSE_RESULT_POWER] +pb_type_power="PB Types\s+([0-9]+)", str +routing_power="Routing\s+([0-9]+)", str +switch_box_power="Switch Box\s+([0-9]+)", str +connection_box_power="Connection Box\s+([0-9]+)", str +primitives_power="Primitives\s+([0-9]+)", str +interc_structures_power="Interc Structures\s+([0-9]+)", str +lut6_power="^\s+lut6\s+([0-9]+)", str +ff_power="^\s+ff\s+([0-9]+)", str + +[INTERMIDIATE_FILE_PREFIX] +# Yosys files +yosys_out_blif=${PATH:TOP_MODULE}_yosys_out.blif +yosys_output=yosys_output.txt + +# ACE2 and intermidiate file +activity_file=${PATH:TOP_MODULE}_ace_out.act +ace_output_blif=${PATH:TOP_MODULE}_ace_out.blif +corrected_format_blif=${PATH:TOP_MODULE}.blif +blackbox_blif=${PATH:TOP_MODULE}_bb.blif + +# VPR Files +min_chann_vpr_output=${PATH:TOP_MODULE}_min_chan_width_vpr.txt +reroute_chan_vpr_output=${PATH:TOP_MODULE}_reroute_vpr.txt +fixed_chan_vpr_output=${PATH:TOP_MODULE}_fr_chan_width.txt +vpr_stat_parse_fn=vpr_stat.txt +vpr_power_stat_parse_fn=vpr_power_stat.txt +vpr_net_file=${PATH:TOP_MODULE}_vpr.net +vpr_place_file=${PATH:TOP_MODULE}_vpr.place +vpr_route_file=${PATH:TOP_MODULE}_vpr.route + +#Iverilog verification file +iverilog_output=iverilog_output.txt +vvp_output=vvp_sim_output.txt + +[CMD_ARGUMENT_DEPENDANCY] +vpr_fpga_verilog=vpr_fpga_verilog_dir|abc +vpr_fpga_verilog_dir=vpr_fpga_verilog diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index b23e837ec..6bd3535ed 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -29,6 +29,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f - registerable\_io: If I/Os are registerable (can be either combinational or sequential) - IoSubtile: If I/O block contains sub tiles (more compact with a higher density of I/Os) - stdcell: If circuit designs are built with standard cells only +- stdcell_laststage: If circuit designs are built with standard cells only. And the last stage uses a different standard cell - tree\_mux: If routing multiplexers are built with a tree-like structure - localClkGen: The clock signal of CLB can be generated by internal programmable resources - : The technology node which the delay numbers are extracted from. @@ -37,5 +38,6 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f * is the number of clocks * When specified, multiple clocks are in separated pins with different names - abspath: All the paths in the architecture file are absolute and hardcoded. +- ecb: *Enhanced Connection Block* where connection blocks includes feedback connections Other features are used in naming should be listed here. diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_IoSubtile_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_IoSubtile_cc_openfpga.xml new file mode 100644 index 000000000..043397186 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_IoSubtile_cc_openfpga.xml @@ -0,0 +1,214 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml new file mode 100644 index 000000000..f9d09c73e --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml @@ -0,0 +1,204 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml new file mode 100644 index 000000000..341bf52e2 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml @@ -0,0 +1,204 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml index 56186f37f..32f84fff8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml @@ -195,10 +195,10 @@ - + - - + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml index 90109d00b..91dd34815 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml new file mode 100644 index 000000000..8fbf05b1f --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml @@ -0,0 +1,206 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml new file mode 100644 index 000000000..12842a05b --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml index 254f3fcac..a3b49f374 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml @@ -210,7 +210,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 8cb766b67..51af075ea 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -210,7 +210,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index aaddef305..32996800e 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -222,7 +222,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml index f489b97f5..6d3e3c45f 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml @@ -228,7 +228,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 444615016..b6752970f 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 0fcbfba3f..203d8e179 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -232,7 +232,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml new file mode 100644 index 000000000..36d5dce05 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml @@ -0,0 +1,256 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml index 7a7154031..cc4d00f54 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml @@ -197,6 +197,7 @@ + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 81ae2b79d..50b4c6e6b 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -213,8 +213,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml index c19f4c2cf..f4b3b0733 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml @@ -217,8 +217,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 86cf97c3c..bd122d3c9 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -215,7 +215,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 0e503f00a..f889f2de6 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -230,7 +230,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index fa4ddb9be..8b89cf9a0 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -227,7 +227,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 35ac32ced..7e659a631 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -235,7 +235,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 3beae9929..b2d6da19d 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -236,7 +236,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index be02a50e5..09dcb1b50 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -211,7 +211,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml index a64e19c82..1f7f137c3 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml @@ -233,7 +233,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml index 0812ecff9..831cf161e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml @@ -234,7 +234,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml index 1997ab1f3..974a92928 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml @@ -237,7 +237,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 1d4a2cdb9..9cc2a0dfb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -237,7 +237,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 1ac39cda0..d0567bb2f 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -223,7 +223,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index 2ff4c6a0c..476850d6e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -233,7 +233,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml index dfe1c060e..55237a608 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml @@ -223,7 +223,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 3684157b6..50b7f9a34 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -211,8 +211,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 44470f17b..dbb527899 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -216,9 +216,9 @@ - - - + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 624868489..21622bc56 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -217,7 +217,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 48f45f94c..440d0a2ae 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -232,7 +232,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_laststage_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_laststage_mux_40nm_openfpga.xml new file mode 100644 index 000000000..024b4fc13 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_laststage_mux_40nm_openfpga.xml @@ -0,0 +1,236 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_cell_library/verilog/mux2.v b/openfpga_flow/openfpga_cell_library/verilog/mux2.v index fed7858ba..4326a0017 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/mux2.v +++ b/openfpga_flow/openfpga_cell_library/verilog/mux2.v @@ -54,6 +54,55 @@ module MUX2( endmodule +module MUX2D2( + // iVerilog is buggy on the 'input A' declaration when deposit initial + // values + input [0:0] AA, // Data input 0 + input [0:0] BB, // Data input 1 + input [0:0] SS0, // Select port + output [0:0] YY // Data output + ); + + assign YY = SS0 ? BB : AA; + +// Note: +// MUX2 appears will appear in LUTs, routing multiplexers, +// being a component in combinational loops +// To help convergence in simulation +// i.e., to avoid the X (undetermined) signals, +// the following timing constraints and signal initialization +// has to be added! + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (AA => YY) = (0.001, 0.001); + (BB => YY) = (0.001, 0.001); + (SS0 => YY) = (0.001, 0.001); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif + +`ifdef ENABLE_SIGNAL_INITIALIZATION +// ------ BEGIN driver initialization ----- + initial begin + `ifdef ENABLE_FORMAL_VERIFICATION + $deposit(AA, 1'b0); + $deposit(BB, 1'b0); + $deposit(SS0, 1'b0); + `else + $deposit(AA, $random); + $deposit(BB, $random); + $deposit(SS0, $random); + `endif + + end +// ------ END driver initialization ----- +`endif + +endmodule + + //----------------------------------------------------- // Design Name : CARRY_MUX2 // File Name : mux2.v diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga index 92cd639ca..24821bc91 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga @@ -22,7 +22,7 @@ append_clock_rr_graph link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges # Route clock based on clock network definition -route_clock_rr_graph +route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga new file mode 100644 index 000000000..489162d11 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \ + --clock_modeling ideal \ + --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \ + --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} \ + --read_vpr_constraints ${OPENFPGA_VPR_CONSTRAINT_FILE} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Read OpenFPGA clock architecture +read_openfpga_clock_arch -f ${OPENFPGA_CLOCK_ARCH_FILE} + +# Append clock network to vpr's routing resource graph +append_clock_rr_graph + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Route clock based on clock network definition +route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack --design_constraints ${OPENFPGA_REPACK_CONSTRAINTS_FILE} #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga new file mode 100644 index 000000000..f48be422f --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga @@ -0,0 +1,75 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \ + --clock_modeling ideal \ + --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \ + --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Read OpenFPGA clock architecture +read_openfpga_clock_arch -f ${OPENFPGA_CLOCK_ARCH_FILE} + +# Append clock network to vpr's routing resource graph +append_clock_rr_graph + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Route clock based on clock network definition +route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack --design_constraints ${OPENFPGA_REPACK_CONSTRAINTS_FILE} #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga new file mode 100644 index 000000000..b5e326b27 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga @@ -0,0 +1,78 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \ + --clock_modeling ideal \ + --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \ + --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} \ + --skip_sync_clustering_and_routing_results on + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Read OpenFPGA clock architecture +read_openfpga_clock_arch -f ${OPENFPGA_CLOCK_ARCH_FILE} + +# Append clock network to vpr's routing resource graph +append_clock_rr_graph + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +pb_pin_fixup ${OPENFPGA_PB_PIN_FIXUP_OPTIONS} + +# Route clock based on clock network definition +route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack --design_constraints ${OPENFPGA_REPACK_CONSTRAINTS_FILE} #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga index 83cc44860..4d9b21770 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga @@ -22,7 +22,7 @@ append_clock_rr_graph link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges # Route clock based on clock network definition -route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga new file mode 100644 index 000000000..ff7fd19d2 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga @@ -0,0 +1,73 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --constant_undriven_inputs ${OPENFPGA_VERILOG_UNDRIVEN_INPUT_TYPE} --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga new file mode 100644 index 000000000..85e9900e3 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga @@ -0,0 +1,73 @@ +# Run VPR for the 'and' design +# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped +# This is due to the Fc_in of clock port is set to 0 for global wiring +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga index cdb981da2..afe6032bd 100644 --- a/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga @@ -30,7 +30,8 @@ ${OPENFPGA_ADD_FPGA_CORE_MODULE} # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt +write_fabric_hierarchy --file ./config_mem.yaml --depth 1 --module * --filter *config_group_mem* --verbose --exclude_empty_modules +write_fabric_hierarchy --file ./mux_modules.txt --depth 1 --module (grid|cbx|cby|sb)* --filter *mux*_size([0-9]+) --verbose --exclude_empty_modules # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation diff --git a/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga index e7a07d61d..0ea39c4ea 100644 --- a/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga @@ -73,7 +73,7 @@ write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REF write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc # Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis +#write_analysis_sdc --file ./SDC_analysis # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga new file mode 100644 index 000000000..fe95685a5 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga @@ -0,0 +1,79 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +# Write fabric phyiscal pin location to file +write_fabric_pin_physical_location --file ${OPENFPGA_FABRIC_PIN_PHY_LOC_FILE} ${OPENFPGA_FABRIC_PIN_PHY_LOC_MODULE} --verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +#write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +#write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga index ba0553733..990476956 100644 --- a/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga @@ -27,11 +27,12 @@ build_fabric --compress_routing #--verbose # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt +write_fabric_hierarchy --file ${OPENFPGA_OUTPUT_DIR}/mux_modules.yaml --depth 1 --module (grid|cbx|cby|sb)* --filter *mux*_size([0-9]+) --verbose --exclude_empty_modules # Write the fabric I/O attributes to a file # This is used by pin constraint files write_fabric_io_info --file ${OPENFPGA_OUTPUT_DIR}/fabric_io_location.xml --verbose --no_time_stamp +write_fabric_pin_physical_location --file ${OPENFPGA_OUTPUT_DIR}/fabric_pin_phy_loc.xml --verbose --no_time_stamp --module * # Write gsb to XML write_gsb_to_xml --file ${OPENFPGA_OUTPUT_DIR}/gsb_xml --verbose @@ -65,7 +66,7 @@ write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp ${OPENFPGA_PRECONFIG_FABRIC_WRAPPER_DUMP_WAVEFORM} write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --use_relative_path --explicit_port_mapping --no_time_stamp # Write the SDC files for PnR backend diff --git a/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga new file mode 100644 index 000000000..bf3d3b4e1 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr_standalone ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --pack --write_rr_graph ${OPENFPGA_VPR_RR_GRAPH_FILE} +# Do NOT know why! If we run full flow using vpr_standlone, running vpr full flow again will cause packing errors! Should fix this later!!! +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --place --route --read_rr_graph ${OPENFPGA_VPR_RR_GRAPH_FILE} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --time_unit ns --flatten_names --file ./SDC +write_pnr_sdc --time_unit ns --flatten_names --hierarchical --file ./SDC_leaf + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga new file mode 100644 index 000000000..9114dac0a --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga @@ -0,0 +1,79 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# preload unique blocks from the provided file +read_unique_blocks --file ${READ_UNIQUE_BLOCKS} --verbose --type ${OPENFPGA_UNIQUE_BLOCK_FILE} + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga new file mode 100644 index 000000000..5718bd4e8 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga @@ -0,0 +1,82 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# preload unique blocks from the provided file +read_unique_blocks --file ${READ_UNIQUE_BLOCKS} --verbose --type ${OPENFPGA_UNIQUE_BLOCK_FILE_READ} + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +#write unique blocks to a format file +write_unique_blocks --file ./${WRITE_UNIQUE_BLOCKS} --verbose --type ${OPENFPGA_UNIQUE_BLOCK_FILE_WRITE} + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga new file mode 100644 index 000000000..f7e4d4f10 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga @@ -0,0 +1,37 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enabled frame view creation to save runtime and memory +# Note that this is turned on when bitstream generation +# is the ONLY purpose of the flow!!! +build_fabric --compress_routing --frame_view #--verbose + +# Report reference to a file +report_reference ${OPENFPGA_REPORT_REFERENCE_MODULE_OPTIONS} +report_reference ${OPENFPGA_REPORT_REFERENCE_VERBOSE_OPTIONS} +report_reference ${OPENFPGA_REPORT_REFERENCE_NO_TIME_STAMP_OPTIONS} + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_simulator_support_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_simulator_support_example_script.openfpga new file mode 100644 index 000000000..bf2a54c88 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_simulator_support_example_script.openfpga @@ -0,0 +1,71 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPGA_FAST_CONFIGURATION} + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION} ${OPENFPGA_SIMULATOR} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga new file mode 100644 index 000000000..f5fcbb960 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga @@ -0,0 +1,80 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +#write unique blocks file +write_unique_blocks --file ./${WRITE_UNIQUE_BLOCKS} --verbose --type ${OPENFPGA_UNIQUE_BLOCK_FILE} + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index e240b64dd..4e1226b0c 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## @@ -15,6 +14,20 @@ echo -e "Test source commands in openfpga shell" run-task basic_tests/source_command/source_string $@ run-task basic_tests/source_command/source_file $@ +echo -e "Testing preloading rr_graph" +run-task basic_tests/preload_rr_graph/preload_rr_graph_xml $@ +run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@ + +echo -e "Testing preloading unique blocks" +run-task basic_tests/preload_unique_blocks/write_unique_blocks_full_flow $@ +run-task basic_tests/preload_unique_blocks/read_unique_blocks_full_flow $@ +run-task basic_tests/preload_unique_blocks/read_write_unique_blocks $@ +run-task basic_tests/preload_unique_blocks/read_write_unique_blocks_bin $@ +run-task basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow $@ +run-task basic_tests/preload_unique_blocks/read_unique_blocks_bin $@ +run-task basic_tests/preload_unique_blocks/read_bin_write_xml $@ + + echo -e "Testing testbenches using fpga core wrapper" run-task basic_tests/full_testbench/fpga_core_wrapper $@ run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules $@ @@ -78,11 +91,15 @@ run-task basic_tests/full_testbench/ql_memory_bank $@ run-task basic_tests/full_testbench/ql_memory_bank_use_wlr $@ run-task basic_tests/full_testbench/multi_region_ql_memory_bank $@ run-task basic_tests/full_testbench/ql_memory_bank_flatten $@ +run-task basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl $@ run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr $@ run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@ run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@ run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain $@ +echo -e "Testing simulator support"; +run-task basic_tests/full_testbench/ql_memory_bank_shift_register_vcs $@ + echo -e "Testing testbenches without self checking features"; run-task basic_tests/full_testbench/full_testbench_without_self_checking $@ run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking $@ @@ -168,6 +185,8 @@ echo -e "Testing K4N4 support clock generation by internal resources"; run-task basic_tests/k4_series/k4n4_clk_gen $@ echo -e "Testing K4N4 support reset generation by internal resources"; run-task basic_tests/k4_series/k4n4_rst_gen $@ +echo -e "Testing enhanced connection blocks" +run-task basic_tests/k4_series/k4n4_ecb $@ echo -e "Testing different tile organizations"; echo -e "Testing tiles with pins only on top and left sides"; @@ -181,10 +200,17 @@ run-task basic_tests/tile_organization/tileable_io $@ echo -e "Testing tiles with I/O consisting of subtiles"; run-task basic_tests/tile_organization/io_subtile $@ run-task basic_tests/tile_organization/io_subtile_strong $@ +echo -e "Testing tiles with routing tracks around I/O"; +run-task basic_tests/tile_organization/perimeter_cb $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; run-task basic_tests/tile_organization/homo_fabric_tile $@ +run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@ +run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup $@ +run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@ @@ -192,6 +218,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile_global_tile_clock $@ run-task basic_tests/tile_organization/homo_fabric_tile_adder_chain $@ run-task basic_tests/tile_organization/homo_fabric_tile_clkntwk $@ run-task basic_tests/tile_organization/hetero_fabric_tile $@ +run-task basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig $@ echo -e "Testing group config block"; run-task basic_tests/group_config_block/group_config_block_homo_full_testbench $@ @@ -205,6 +232,7 @@ run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_glob echo -e "Module naming"; run-task basic_tests/module_naming/using_index $@ +run-task basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index $@ run-task basic_tests/module_naming/renaming_rules $@ run-task basic_tests/module_naming/renaming_rules_strong $@ run-task basic_tests/module_naming/renaming_rules_on_indexed_names $@ @@ -215,13 +243,28 @@ run-task basic_tests/global_tile_ports/global_tile_clock_subtile $@ run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge $@ run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_fabric_tile_group_config $@ run-task basic_tests/global_tile_ports/global_tile_reset $@ -run-task basic_tests/global_tile_ports/global_tile_4clock $@ +run-task basic_tests/global_tile_ports/global_tile_4clock --default_tool_path ${OPENFPGA_PATH}/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf $@ run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@ echo -e "Testing programmable clock architecture"; +run-task basic_tests/clock_network/homo_1clock_1reset_1layer_2entry $@ run-task basic_tests/clock_network/homo_1clock_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_dec $@ run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ run-task basic_tests/clock_network/homo_2clock_2layer $@ +run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ +run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry $@ +run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver $@ echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; run-task basic_tests/verific_test $@ @@ -249,6 +292,12 @@ run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@ run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@ run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@ +echo -e "Testing fabric pin physical location file" +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default $@ +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles $@ +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides $@ +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards $@ + echo -e "Testing bus group features"; run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping $@ run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping $@ @@ -276,6 +325,11 @@ echo -e "Testing output files without time stamp"; run-task basic_tests/no_time_stamp/device_1x1 $@ run-task basic_tests/no_time_stamp/device_4x4 $@ run-task basic_tests/no_time_stamp/no_cout_in_gsb $@ +run-task basic_tests/no_time_stamp/dump_waveform $@ + +echo -e "Testing report reference to file"; +run-task basic_tests/report_reference $@ + # Run git-diff to ensure no changes on the golden netlists # Switch to root path in case users are running the tests in another location cd ${OPENFPGA_PATH} diff --git a/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh index 1396d27c2..920239641 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh index 184eceee9..8fc5e022c 100755 --- a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## @@ -16,6 +15,9 @@ echo -e "Testing bitstream generation for an 48x48 FPGA device"; run-task fpga_bitstream/generate_bitstream/configuration_chain/device_48x48 $@ run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_48x48 $@ +echo -e "Testing bitstream generation for an 4x4 FPGA device (randomly overwrite fabric bits)"; +run-task fpga_bitstream/overwrite_bitstream/device_4x4 $@ + echo -e "Testing bitstream generation for an 96x96 FPGA device"; run-task fpga_bitstream/generate_bitstream/configuration_chain/device_96x96 $@ run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_72x72 $@ @@ -29,6 +31,7 @@ run-task fpga_bitstream/load_external_architecture_bitstream $@ echo -e "Testing repacker capability in identifying wire LUTs"; run-task fpga_bitstream/repack_wire_lut $@ run-task fpga_bitstream/repack_wire_lut_strong $@ +run-task fpga_bitstream/repack_ignore_nets $@ echo -e "Testing overloading default paths for programmable interconnect when generating bitstream"; run-task fpga_bitstream/overload_mux_default_path $@ @@ -52,3 +55,6 @@ run-task fpga_bitstream/filter_value0 $@ run-task fpga_bitstream/filter_value1 $@ run-task fpga_bitstream/path_only $@ run-task fpga_bitstream/value_only $@ + +echo -e "Testing extracting mode bits for DSP blocks when generating bitstream"; +run-task fpga_bitstream/extract_dsp_mode_bit $@ diff --git a/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh index 084b0ea20..6760cf9fe 100755 --- a/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh index c003f5d93..dee7d4f96 100755 --- a/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 46bf5cba9..6d6cb4829 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## @@ -85,6 +84,7 @@ run-task fpga_verilog/mux_design/tree_structure $@ echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2"; run-task fpga_verilog/mux_design/stdcell_mux2 $@ +run-task fpga_verilog/mux_design/stdcell_mux2_last_stage $@ echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders"; run-task fpga_verilog/mux_design/local_encoder $@ @@ -118,6 +118,13 @@ run-task fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_w echo -e "Testing explicit Verilog generation"; run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire $@ +echo -e "Testing undriven net wiring in Verilog generation"; +run-task fpga_verilog/verilog_netlist_formats/undriven_input_none $@ +run-task fpga_verilog/verilog_netlist_formats/undriven_input_bus0 $@ +run-task fpga_verilog/verilog_netlist_formats/undriven_input_bus1 $@ +run-task fpga_verilog/verilog_netlist_formats/undriven_input_bit0 $@ +run-task fpga_verilog/verilog_netlist_formats/undriven_input_bit1 $@ + echo -e "Testing Verilog generation with flatten routing modules"; run-task fpga_verilog/flatten_routing $@ diff --git a/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh index 4b37f6da7..ddbce4590 100755 --- a/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index cb7b41252..b5903ed95 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh index 2279a5c86..18eee18e2 100755 --- a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh index 8bbc32436..99ca2c4c5 100755 --- a/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/scripts/arch_file_updater.py b/openfpga_flow/scripts/arch_file_updater.py index 3538ec7f3..1ef9c3786 100644 --- a/openfpga_flow/scripts/arch_file_updater.py +++ b/openfpga_flow/scripts/arch_file_updater.py @@ -26,6 +26,7 @@ error_codes = {"SUCCESS": 0, "ERROR": 1, "OPTION_ERROR": 2, "FILE_ERROR": 3} ##################################################################### logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.INFO) + ##################################################################### # Upgrade an architecture XML file from version 1.1 syntax to version 1.2 # Change rules: diff --git a/openfpga_flow/scripts/io_sequence_visualizer.py b/openfpga_flow/scripts/io_sequence_visualizer.py index d80acf1f2..cf435f217 100644 --- a/openfpga_flow/scripts/io_sequence_visualizer.py +++ b/openfpga_flow/scripts/io_sequence_visualizer.py @@ -13,6 +13,7 @@ This example demonstrates the ``OpenFPGA_Arch`` class which parses the Author: Ganesh Gore """ + import math import svgwrite from svgwrite.container import Group diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 23a655e02..1cb3bc8a6 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -89,6 +89,12 @@ parser.add_argument( default=os.path.join(openfpga_base_dir, "tmp"), help="Directory to store intermidiate file & final results", ) +parser.add_argument( + "--default_tool_path", + type=str, + default=os.path.join(flow_script_dir, os.pardir, "misc", "fpgaflow_default_tool_path.conf"), + help="The configuraton file contains paths to tools as well as keywords to be extracted from logs", +) parser.add_argument( "--openfpga_shell_template", type=str, @@ -332,8 +338,8 @@ ExecTime = {} def main(): logger.debug("Script Launched in " + os.getcwd()) - check_required_file() - read_script_config() + check_required_file(args.default_tool_path) + read_script_config(args.default_tool_path) validate_command_line_arguments() prepare_run_directory(args.run_dir) if args.fpga_flow == "yosys_vpr": @@ -394,26 +400,22 @@ def main(): # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -def check_required_file(): +def check_required_file(default_tool_path): """Function ensure existace of all required files for the script""" files_dict = { - "CAD TOOL PATH": os.path.join( - flow_script_dir, os.pardir, "misc", "fpgaflow_default_tool_path.conf" - ), + "CAD TOOL PATH": default_tool_path, } for filename, filepath in files_dict.items(): if not os.path.isfile(filepath): - clean_up_and_exit("Not able to locate default file " + filename) + clean_up_and_exit("Not able to locate default file " + filename + " under " + filepath) -def read_script_config(): +def read_script_config(default_tool_path): """This fucntion reads default CAD tools path from configuration file""" global config, cad_tools config = ConfigParser(interpolation=ExtendedInterpolation()) config.read_dict(script_env_vars) - default_cad_tool_conf = os.path.join( - flow_script_dir, os.pardir, "misc", "fpgaflow_default_tool_path.conf" - ) + default_cad_tool_conf = default_tool_path config.read_file(open(default_cad_tool_conf)) if args.flow_config: config.read_file(open(args.flow_config)) @@ -672,9 +674,11 @@ def create_yosys_params(): ys_params["READ_HDL_FILE"] += " ".join( [ "verific", - "-L " + ys_params["VERIFIC_SEARCH_LIB"] - if "VERIFIC_SEARCH_LIB" in ys_params - else "", + ( + "-L " + ys_params["VERIFIC_SEARCH_LIB"] + if "VERIFIC_SEARCH_LIB" in ys_params + else "" + ), standard, " ".join([shlex.quote(src) for src in sources]), "\n", @@ -905,18 +909,18 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"): resultDict = {} for name, value in config.items(section): reg_string, filt_function = value.split(",") - match = re.search(reg_string[1:-1], vpr_log) - if match: + reg_result = re.findall(reg_string[1:-1], vpr_log) + if reg_result: try: if "lambda" in filt_function.strip(): eval("ParseFunction = " + filt_function.strip()) - extract_val = ParseFunction(**match.groups()) + extract_val = ParseFunction(reg_result) elif filt_function.strip() == "int": - extract_val = int(match.group(1)) + extract_val = int(reg_result[-1]) elif filt_function.strip() == "float": - extract_val = float(match.group(1)) + extract_val = float(reg_result[-1]) elif filt_function.strip() == "str": - extract_val = str(match.group(1)) + extract_val = str(reg_result[-1]) elif filt_function.strip() == "scientific": try: mult = { @@ -926,12 +930,12 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"): "K": 1e-3, "M": 1e-6, "G": 1e-9, - }.get(match.group(2)[0], 1) + }.get(reg_result[-1][1], 1) except: mult = 1 - extract_val = float(match.group(1)) * mult + extract_val = float(reg_result[-1][0]) * mult else: - extract_val = match.group(1) + extract_val = reg_result[-1] except: logger.exception("Filter failed") extract_val = "Filter Failed" diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index c021eebf7..966468eb1 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -48,6 +48,7 @@ logger = logging.getLogger("OpenFPGA_Task_logs") # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Read commandline arguments # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +task_script_dir = os.path.dirname(os.path.abspath(__file__)) parser = argparse.ArgumentParser() parser.add_argument("tasks", nargs="+") parser.add_argument( @@ -76,12 +77,17 @@ parser.add_argument("--continue_on_fail", action="store_true", help="Exit script parser.add_argument( "--show_thread_logs", action="store_true", help="Skips logs from running thread" ) +parser.add_argument( + "--default_tool_path", + type=str, + default=os.path.join(task_script_dir, os.pardir, "misc", "fpgaflow_default_tool_path.conf"), + help="The configuraton file contains paths to tools as well as keywords to be extracted from logs", +) args = parser.parse_args() # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Read script configuration file # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -task_script_dir = os.path.dirname(os.path.abspath(__file__)) script_env_vars = { "PATH": { "OPENFPGA_FLOW_PATH": task_script_dir, @@ -407,6 +413,7 @@ def generate_each_task_actions(taskname): task_conf=task_conf, ) command += ["--flow_config", curr_task_conf_file] + command += ["--default_tool_path", args.default_tool_path] flow_run_cmd_list.append( { "arch": arch, diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..60f1bfb36 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/task.conf new file mode 100644 index 000000000..554a53d64 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..3f499fedf --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf new file mode 100644 index 000000000..554a53d64 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..89f030970 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf new file mode 100644 index 000000000..014465ced --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..3f499fedf --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf new file mode 100644 index 000000000..622f0328e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options=--disable_unused_spines + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml new file mode 100644 index 000000000..270ca7f33 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml new file mode 100644 index 000000000..d2df1756d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_clk_cond.xml new file mode 100644 index 000000000..903c4bfac --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_clk_cond.xml @@ -0,0 +1,9 @@ + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_rst_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_rst_cond.xml new file mode 100644 index 000000000..55e49733f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_rst_cond.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/task.conf new file mode 100644 index 000000000..a4841a1ae --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/task.conf @@ -0,0 +1,57 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= +openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = clk_cond +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_cond.xml +bench0_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml +bench0_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml + +bench1_top = rst_cond +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_cond.xml +bench1_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_rst_cond.xml +bench1_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml new file mode 100644 index 000000000..f7a7dccd5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml new file mode 100644 index 000000000..8ae00e08f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml new file mode 100644 index 000000000..481e88a60 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml new file mode 100644 index 000000000..a89b25a17 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_cond.xml new file mode 100644 index 000000000..903c4bfac --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_cond.xml @@ -0,0 +1,9 @@ + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_rst_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_rst_cond.xml new file mode 100644 index 000000000..55e49733f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_rst_cond.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf new file mode 100644 index 000000000..a4841a1ae --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -0,0 +1,57 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= +openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = clk_cond +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_cond.xml +bench0_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml +bench0_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml + +bench1_top = rst_cond +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_cond.xml +bench1_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_rst_cond.xml +bench1_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_clk_cond.xml new file mode 100644 index 000000000..f9b30b022 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_clk_cond.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_rst_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_rst_cond.xml new file mode 100644 index 000000000..3c6f27aef --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_rst_cond.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..b91512914 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_clk.xml new file mode 100644 index 000000000..f0b871511 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml new file mode 100644 index 000000000..15df5148e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst_and_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst_and_clk.xml new file mode 100644 index 000000000..15df5148e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst_and_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf new file mode 100644 index 000000000..a3d9b1a48 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf @@ -0,0 +1,56 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = rst_on_lut +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst.xml + +bench1_top = clk_on_lut +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml + +bench2_top = rst_and_clk_on_lut +bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..b91512914 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_clk.xml new file mode 100644 index 000000000..f0b871511 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst.xml new file mode 100644 index 000000000..15df5148e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst_and_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst_and_clk.xml new file mode 100644 index 000000000..15df5148e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/pin_constraints_rst_and_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf new file mode 100644 index 000000000..0dad873c1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf @@ -0,0 +1,57 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= +openfpga_pb_pin_fixup_options=--verbose + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = rst_on_lut +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst.xml + +bench1_top = clk_on_lut +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml + +bench2_top = rst_and_clk_on_lut +bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..b91512914 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_clk.xml new file mode 100644 index 000000000..f0b871511 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst.xml new file mode 100644 index 000000000..15df5148e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst_and_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst_and_clk.xml new file mode 100644 index 000000000..15df5148e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst_and_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf new file mode 100644 index 000000000..64ee22a50 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf @@ -0,0 +1,59 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= +openfpga_pb_pin_fixup_options=--map_global_net_to_msb --verbose + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = rst_on_lut +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst.xml + +bench1_top = clk_on_lut +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml +# Triggered a bug in VPR, when route_chan_width=40, it failed +bench1_openfpga_vpr_route_chan_width=44 + +bench2_top = rst_and_clk_on_lut +bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..41a1aed69 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf new file mode 100644 index 000000000..554a53d64 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..cfdb727a1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/task.conf new file mode 100644 index 000000000..9237ad156 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_TileOrgzTr_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/clk_arch_1clk_1rst_3layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/clk_arch_1clk_1rst_3layer.xml new file mode 100644 index 000000000..e7ff2bd18 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/clk_arch_1clk_1rst_3layer.xml @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/task.conf new file mode 100644 index 000000000..7633d87d5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_3layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/clk_arch_1clk_1rst_3layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/clk_arch_1clk_1rst_3layer.xml new file mode 100644 index 000000000..e7ff2bd18 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/clk_arch_1clk_1rst_3layer.xml @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/task.conf new file mode 100644 index 000000000..62745b0e3 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_3layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options=--disable_unused_trees --disable_unused_spines + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml index 0570406fd..6f289dbf4 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml @@ -1,5 +1,5 @@ - - + + @@ -11,7 +11,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf index b05af260f..295943e3e 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf @@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=24 openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/dummy_repack_constraints.xml openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/dummy_pin_constraints.xml +openfpga_route_clock_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml index 0570406fd..6f289dbf4 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml @@ -1,5 +1,5 @@ - - + + @@ -11,7 +11,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf index ef0ce93fd..f42445c51 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf @@ -22,6 +22,7 @@ openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=24 +openfpga_route_clock_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml index 46fec8fd5..3ef33c270 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml @@ -1,5 +1,5 @@ - - + + @@ -11,8 +11,8 @@ - - + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml index eb0c4435a..f32f6afde 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml @@ -1,5 +1,4 @@ - diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf index 190ff11e0..d75606c31 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf @@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=24 openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml +openfpga_route_clock_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml new file mode 100644 index 000000000..3ef33c270 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/pin_constraints.xml new file mode 100644 index 000000000..1989d1eea --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml new file mode 100644 index 000000000..f32f6afde --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/task.conf new file mode 100644 index 000000000..d08fcf15a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_2clk_2layer.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=24 +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml +openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml +openfpga_route_clock_options=--disable_unused_trees --disable_unused_spines + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_latch + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml new file mode 100644 index 000000000..3ef33c270 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/pin_constraints.xml new file mode 100644 index 000000000..1989d1eea --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml new file mode 100644 index 000000000..f32f6afde --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/task.conf new file mode 100644 index 000000000..8e58aec0c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_2clk_2layer.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=24 +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml +openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml +openfpga_route_clock_options=--disable_unused_trees + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_latch + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl/config/task.conf new file mode 100644 index 000000000..8e56d8437 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl/config/task.conf @@ -0,0 +1,45 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_shift_register_vcs/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_shift_register_vcs/config/task.conf new file mode 100644 index 000000000..2b7f51a6c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_shift_register_vcs/config/task.conf @@ -0,0 +1,47 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_simulator_support_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml + +openfpga_vpr_device_layout= +openfpga_fast_configuration= +openfpga_simulator=--simulator vcs + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf index 8676f91ba..9e5d2f460 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=auto +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf index d75851ad9..d6172bb2f 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2_hybrid_io +openfpga_vpr_route_chan_width=20 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge/config/task.conf index adbbaa2cb..062cdd91f 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClkMergeSubtilePort_registerable_io_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2_hybrid_io +openfpga_vpr_route_chan_width=60 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf new file mode 100644 index 000000000..035b92ed7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_pbPinFixup_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/clk_arch_1clk_2layer.xml new file mode 100644 index 000000000..2b85f88cd --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/clk_arch_1clk_2layer.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/task.conf b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/task.conf new file mode 100644 index 000000000..245ac9b9f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml --name_module_using_index +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/config/task.conf b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/config/task.conf index f1e22ed97..50daf4584 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/config/task.conf @@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_device_layout = auto openfpga_vpr_route_chan_width = 26 openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp +openfpga_preconfig_fabric_wrapper_dump_waveform= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index c0daea5f7..5d9e929e2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.4628907144 + #0.809066534 clk[0] <= !clk[0]; end end @@ -106,7 +106,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #6.480470181 + #11.32693195 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index fa1a05891..06fd83ed4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,19 +9,20 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 9.25781396e-10 -waveform {0 4.62890698e-10} +create_clock clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[11] -set_input_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[14] -set_output_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[1] +set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[11] +set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[14] +set_output_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[12] ################################################## # Disable timing for unused I/Os ################################################## set_disable_timing gfpga_pad_GPIO_PAD[0] +set_disable_timing gfpga_pad_GPIO_PAD[1] set_disable_timing gfpga_pad_GPIO_PAD[2] set_disable_timing gfpga_pad_GPIO_PAD[3] set_disable_timing gfpga_pad_GPIO_PAD[4] @@ -31,7 +32,6 @@ set_disable_timing gfpga_pad_GPIO_PAD[7] set_disable_timing gfpga_pad_GPIO_PAD[8] set_disable_timing gfpga_pad_GPIO_PAD[9] set_disable_timing gfpga_pad_GPIO_PAD[10] -set_disable_timing gfpga_pad_GPIO_PAD[12] set_disable_timing gfpga_pad_GPIO_PAD[13] set_disable_timing gfpga_pad_GPIO_PAD[15] set_disable_timing gfpga_pad_GPIO_PAD[16] @@ -57,16 +57,24 @@ set_disable_timing gfpga_pad_GPIO_PAD[31] set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -77,6 +85,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -91,30 +103,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -156,11 +156,9 @@ set_disable_timing cbx_1__0_/chanx_left_in[7] set_disable_timing cbx_1__0_/chanx_right_in[7] set_disable_timing cbx_1__0_/chanx_left_in[8] set_disable_timing cbx_1__0_/chanx_right_in[8] -set_disable_timing cbx_1__0_/chanx_left_in[9] set_disable_timing cbx_1__0_/chanx_right_in[9] set_disable_timing cbx_1__0_/chanx_left_in[10] set_disable_timing cbx_1__0_/chanx_right_in[10] -set_disable_timing cbx_1__0_/chanx_left_in[11] set_disable_timing cbx_1__0_/chanx_right_in[11] set_disable_timing cbx_1__0_/chanx_left_in[12] set_disable_timing cbx_1__0_/chanx_right_in[12] @@ -182,11 +180,9 @@ set_disable_timing cbx_1__0_/chanx_left_out[7] set_disable_timing cbx_1__0_/chanx_right_out[7] set_disable_timing cbx_1__0_/chanx_left_out[8] set_disable_timing cbx_1__0_/chanx_right_out[8] -set_disable_timing cbx_1__0_/chanx_left_out[9] set_disable_timing cbx_1__0_/chanx_right_out[9] set_disable_timing cbx_1__0_/chanx_left_out[10] set_disable_timing cbx_1__0_/chanx_right_out[10] -set_disable_timing cbx_1__0_/chanx_left_out[11] set_disable_timing cbx_1__0_/chanx_right_out[11] set_disable_timing cbx_1__0_/chanx_left_out[12] set_disable_timing cbx_1__0_/chanx_right_out[12] @@ -276,7 +272,6 @@ set_disable_timing cbx_1__1_/chanx_left_in[1] set_disable_timing cbx_1__1_/chanx_left_in[2] set_disable_timing cbx_1__1_/chanx_right_in[2] set_disable_timing cbx_1__1_/chanx_left_in[3] -set_disable_timing cbx_1__1_/chanx_right_in[3] set_disable_timing cbx_1__1_/chanx_left_in[4] set_disable_timing cbx_1__1_/chanx_right_in[4] set_disable_timing cbx_1__1_/chanx_left_in[5] @@ -301,7 +296,6 @@ set_disable_timing cbx_1__1_/chanx_left_out[1] set_disable_timing cbx_1__1_/chanx_left_out[2] set_disable_timing cbx_1__1_/chanx_right_out[2] set_disable_timing cbx_1__1_/chanx_left_out[3] -set_disable_timing cbx_1__1_/chanx_right_out[3] set_disable_timing cbx_1__1_/chanx_left_out[4] set_disable_timing cbx_1__1_/chanx_right_out[4] set_disable_timing cbx_1__1_/chanx_left_out[5] @@ -321,6 +315,7 @@ set_disable_timing cbx_1__1_/chanx_right_out[11] set_disable_timing cbx_1__1_/chanx_left_out[12] set_disable_timing cbx_1__1_/chanx_right_out[12] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] @@ -339,6 +334,7 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[0] set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[3] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[1] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[2] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[0] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[0] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[3] @@ -415,11 +411,9 @@ set_disable_timing cby_0__1_/chany_top_in[6] set_disable_timing cby_0__1_/chany_bottom_in[7] set_disable_timing cby_0__1_/chany_top_in[7] set_disable_timing cby_0__1_/chany_bottom_in[8] -set_disable_timing cby_0__1_/chany_top_in[8] set_disable_timing cby_0__1_/chany_bottom_in[9] set_disable_timing cby_0__1_/chany_top_in[9] set_disable_timing cby_0__1_/chany_bottom_in[10] -set_disable_timing cby_0__1_/chany_top_in[10] set_disable_timing cby_0__1_/chany_bottom_in[11] set_disable_timing cby_0__1_/chany_top_in[11] set_disable_timing cby_0__1_/chany_bottom_in[12] @@ -441,11 +435,9 @@ set_disable_timing cby_0__1_/chany_top_out[6] set_disable_timing cby_0__1_/chany_bottom_out[7] set_disable_timing cby_0__1_/chany_top_out[7] set_disable_timing cby_0__1_/chany_bottom_out[8] -set_disable_timing cby_0__1_/chany_top_out[8] set_disable_timing cby_0__1_/chany_bottom_out[9] set_disable_timing cby_0__1_/chany_top_out[9] set_disable_timing cby_0__1_/chany_bottom_out[10] -set_disable_timing cby_0__1_/chany_top_out[10] set_disable_timing cby_0__1_/chany_bottom_out[11] set_disable_timing cby_0__1_/chany_top_out[11] set_disable_timing cby_0__1_/chany_bottom_out[12] @@ -526,11 +518,9 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4] set_disable_timing cby_1__1_/chany_top_in[0] set_disable_timing cby_1__1_/chany_bottom_in[1] set_disable_timing cby_1__1_/chany_top_in[1] -set_disable_timing cby_1__1_/chany_bottom_in[2] set_disable_timing cby_1__1_/chany_top_in[2] set_disable_timing cby_1__1_/chany_bottom_in[3] set_disable_timing cby_1__1_/chany_top_in[3] -set_disable_timing cby_1__1_/chany_bottom_in[4] set_disable_timing cby_1__1_/chany_top_in[4] set_disable_timing cby_1__1_/chany_bottom_in[5] set_disable_timing cby_1__1_/chany_top_in[5] @@ -549,11 +539,9 @@ set_disable_timing cby_1__1_/chany_top_in[12] set_disable_timing cby_1__1_/chany_top_out[0] set_disable_timing cby_1__1_/chany_bottom_out[1] set_disable_timing cby_1__1_/chany_top_out[1] -set_disable_timing cby_1__1_/chany_bottom_out[2] set_disable_timing cby_1__1_/chany_top_out[2] set_disable_timing cby_1__1_/chany_bottom_out[3] set_disable_timing cby_1__1_/chany_top_out[3] -set_disable_timing cby_1__1_/chany_bottom_out[4] set_disable_timing cby_1__1_/chany_top_out[4] set_disable_timing cby_1__1_/chany_bottom_out[5] set_disable_timing cby_1__1_/chany_top_out[5] @@ -573,7 +561,6 @@ set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_out set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] -set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] @@ -602,7 +589,6 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1] set_disable_timing cby_1__1_/mux_left_ipin_3/in[2] set_disable_timing cby_1__1_/mux_left_ipin_4/in[0] set_disable_timing cby_1__1_/mux_right_ipin_2/in[0] -set_disable_timing cby_1__1_/mux_left_ipin_4/in[3] set_disable_timing cby_1__1_/mux_left_ipin_5/in[1] set_disable_timing cby_1__1_/mux_left_ipin_4/in[2] set_disable_timing cby_1__1_/mux_left_ipin_5/in[0] @@ -662,11 +648,9 @@ set_disable_timing sb_0__0_/chany_top_in[6] set_disable_timing sb_0__0_/chany_top_out[7] set_disable_timing sb_0__0_/chany_top_in[7] set_disable_timing sb_0__0_/chany_top_out[8] -set_disable_timing sb_0__0_/chany_top_in[8] set_disable_timing sb_0__0_/chany_top_out[9] set_disable_timing sb_0__0_/chany_top_in[9] set_disable_timing sb_0__0_/chany_top_out[10] -set_disable_timing sb_0__0_/chany_top_in[10] set_disable_timing sb_0__0_/chany_top_out[11] set_disable_timing sb_0__0_/chany_top_in[11] set_disable_timing sb_0__0_/chany_top_out[12] @@ -689,11 +673,9 @@ set_disable_timing sb_0__0_/chanx_right_out[7] set_disable_timing sb_0__0_/chanx_right_in[7] set_disable_timing sb_0__0_/chanx_right_out[8] set_disable_timing sb_0__0_/chanx_right_in[8] -set_disable_timing sb_0__0_/chanx_right_out[9] set_disable_timing sb_0__0_/chanx_right_in[9] set_disable_timing sb_0__0_/chanx_right_out[10] set_disable_timing sb_0__0_/chanx_right_in[10] -set_disable_timing sb_0__0_/chanx_right_out[11] set_disable_timing sb_0__0_/chanx_right_in[11] set_disable_timing sb_0__0_/chanx_right_out[12] set_disable_timing sb_0__0_/chanx_right_in[12] @@ -775,9 +757,7 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0] set_disable_timing sb_0__0_/mux_right_track_12/in[0] set_disable_timing sb_0__0_/mux_right_track_14/in[0] set_disable_timing sb_0__0_/mux_right_track_16/in[0] -set_disable_timing sb_0__0_/mux_right_track_18/in[0] set_disable_timing sb_0__0_/mux_right_track_20/in[0] -set_disable_timing sb_0__0_/mux_right_track_22/in[0] set_disable_timing sb_0__0_/mux_right_track_24/in[0] set_disable_timing sb_0__0_/mux_right_track_0/in[0] set_disable_timing sb_0__0_/mux_top_track_24/in[2] @@ -802,7 +782,6 @@ set_disable_timing sb_0__1_/chanx_right_out[1] set_disable_timing sb_0__1_/chanx_right_out[2] set_disable_timing sb_0__1_/chanx_right_in[2] set_disable_timing sb_0__1_/chanx_right_out[3] -set_disable_timing sb_0__1_/chanx_right_in[3] set_disable_timing sb_0__1_/chanx_right_out[4] set_disable_timing sb_0__1_/chanx_right_in[4] set_disable_timing sb_0__1_/chanx_right_out[5] @@ -838,11 +817,9 @@ set_disable_timing sb_0__1_/chany_bottom_out[6] set_disable_timing sb_0__1_/chany_bottom_in[7] set_disable_timing sb_0__1_/chany_bottom_out[7] set_disable_timing sb_0__1_/chany_bottom_in[8] -set_disable_timing sb_0__1_/chany_bottom_out[8] set_disable_timing sb_0__1_/chany_bottom_in[9] set_disable_timing sb_0__1_/chany_bottom_out[9] set_disable_timing sb_0__1_/chany_bottom_in[10] -set_disable_timing sb_0__1_/chany_bottom_out[10] set_disable_timing sb_0__1_/chany_bottom_in[11] set_disable_timing sb_0__1_/chany_bottom_out[11] set_disable_timing sb_0__1_/chany_bottom_in[12] @@ -916,9 +893,7 @@ set_disable_timing sb_0__1_/mux_bottom_track_3/in[3] set_disable_timing sb_0__1_/mux_bottom_track_15/in[3] set_disable_timing sb_0__1_/mux_bottom_track_17/in[2] set_disable_timing sb_0__1_/mux_bottom_track_23/in[0] -set_disable_timing sb_0__1_/mux_bottom_track_21/in[0] set_disable_timing sb_0__1_/mux_bottom_track_19/in[0] -set_disable_timing sb_0__1_/mux_bottom_track_17/in[0] set_disable_timing sb_0__1_/mux_bottom_track_15/in[0] set_disable_timing sb_0__1_/mux_bottom_track_13/in[0] set_disable_timing sb_0__1_/mux_bottom_track_11/in[0] @@ -947,11 +922,9 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2] set_disable_timing sb_1__0_/chany_top_in[0] set_disable_timing sb_1__0_/chany_top_out[1] set_disable_timing sb_1__0_/chany_top_in[1] -set_disable_timing sb_1__0_/chany_top_out[2] set_disable_timing sb_1__0_/chany_top_in[2] set_disable_timing sb_1__0_/chany_top_out[3] set_disable_timing sb_1__0_/chany_top_in[3] -set_disable_timing sb_1__0_/chany_top_out[4] set_disable_timing sb_1__0_/chany_top_in[4] set_disable_timing sb_1__0_/chany_top_out[5] set_disable_timing sb_1__0_/chany_top_in[5] @@ -985,11 +958,9 @@ set_disable_timing sb_1__0_/chanx_left_in[7] set_disable_timing sb_1__0_/chanx_left_out[7] set_disable_timing sb_1__0_/chanx_left_in[8] set_disable_timing sb_1__0_/chanx_left_out[8] -set_disable_timing sb_1__0_/chanx_left_in[9] set_disable_timing sb_1__0_/chanx_left_out[9] set_disable_timing sb_1__0_/chanx_left_in[10] set_disable_timing sb_1__0_/chanx_left_out[10] -set_disable_timing sb_1__0_/chanx_left_in[11] set_disable_timing sb_1__0_/chanx_left_out[11] set_disable_timing sb_1__0_/chanx_left_in[12] set_disable_timing sb_1__0_/chanx_left_out[12] @@ -1079,9 +1050,7 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2] set_disable_timing sb_1__0_/mux_top_track_14/in[3] set_disable_timing sb_1__0_/mux_top_track_12/in[2] set_disable_timing sb_1__0_/mux_top_track_10/in[2] -set_disable_timing sb_1__0_/mux_top_track_8/in[2] set_disable_timing sb_1__0_/mux_top_track_6/in[2] -set_disable_timing sb_1__0_/mux_top_track_4/in[2] set_disable_timing sb_1__0_/mux_top_track_2/in[3] ################################################## # Disable timing for Switch block sb_1__1_ @@ -1089,11 +1058,9 @@ set_disable_timing sb_1__0_/mux_top_track_2/in[3] set_disable_timing sb_1__1_/chany_bottom_out[0] set_disable_timing sb_1__1_/chany_bottom_in[1] set_disable_timing sb_1__1_/chany_bottom_out[1] -set_disable_timing sb_1__1_/chany_bottom_in[2] set_disable_timing sb_1__1_/chany_bottom_out[2] set_disable_timing sb_1__1_/chany_bottom_in[3] set_disable_timing sb_1__1_/chany_bottom_out[3] -set_disable_timing sb_1__1_/chany_bottom_in[4] set_disable_timing sb_1__1_/chany_bottom_out[4] set_disable_timing sb_1__1_/chany_bottom_in[5] set_disable_timing sb_1__1_/chany_bottom_out[5] @@ -1115,7 +1082,6 @@ set_disable_timing sb_1__1_/chanx_left_in[1] set_disable_timing sb_1__1_/chanx_left_in[2] set_disable_timing sb_1__1_/chanx_left_out[2] set_disable_timing sb_1__1_/chanx_left_in[3] -set_disable_timing sb_1__1_/chanx_left_out[3] set_disable_timing sb_1__1_/chanx_left_in[4] set_disable_timing sb_1__1_/chanx_left_out[4] set_disable_timing sb_1__1_/chanx_left_in[5] @@ -1200,7 +1166,6 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3] set_disable_timing sb_1__1_/mux_left_track_15/in[2] set_disable_timing sb_1__1_/mux_left_track_17/in[2] set_disable_timing sb_1__1_/mux_left_track_5/in[0] -set_disable_timing sb_1__1_/mux_left_track_7/in[0] set_disable_timing sb_1__1_/mux_left_track_9/in[0] set_disable_timing sb_1__1_/mux_left_track_11/in[0] set_disable_timing sb_1__1_/mux_left_track_13/in[0] @@ -1466,20 +1431,16 @@ set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/* ####################################### set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused resources in grid[1][2][1] +# Disable Timing for unused grid[1][2][1] ####################################### ####################################### -# Disable unused pins for pb_graph_node io[0] +# Disable all the ports for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/io_inpad[0] +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/* ####################################### -# Disable unused mux_inputs for pb_graph_node io[0] +# Disable all the ports for pb_graph_node iopad[0] ####################################### -set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1//direct_interc_0_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* ####################################### # Disable Timing for unused grid[1][2][2] ####################################### @@ -1598,16 +1559,20 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc ####################################### set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] ####################################### -# Disable Timing for unused grid[2][1][4] +# Disable Timing for unused resources in grid[2][1][4] ####################################### ####################################### -# Disable all the ports for pb_graph_node io[0] +# Disable unused pins for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/* +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0] ####################################### -# Disable all the ports for pb_graph_node iopad[0] +# Disable unused mux_inputs for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] ####################################### # Disable Timing for unused grid[2][1][5] ####################################### diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 53f34c9c4..5608bef83 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -45,11 +45,12 @@ wire [0:0] clk_fm; // ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[14] ----- assign gfpga_pad_GPIO_PAD_fm[14] = b[0]; -// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] ----- - assign c[0] = gfpga_pad_GPIO_PAD_fm[1]; +// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] ----- + assign c[0] = gfpga_pad_GPIO_PAD_fm[12]; // ----- Wire unused FPGA I/Os to constants ----- assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[1] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0; @@ -59,7 +60,6 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0; @@ -132,8 +132,8 @@ initial begin force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; - force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; @@ -154,8 +154,8 @@ initial begin force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; @@ -238,12 +238,12 @@ initial begin force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; @@ -288,12 +288,12 @@ initial begin force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; @@ -302,12 +302,12 @@ initial begin force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; @@ -382,8 +382,8 @@ initial begin force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; @@ -426,8 +426,8 @@ initial begin force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = 3'b001; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = 3'b110; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}}; @@ -474,8 +474,8 @@ initial begin force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}}; diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc index df2b04e23..5a3b9e3df 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,346 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5 @@ -465,84 +125,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/s set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 @@ -725,8 +309,424 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_ set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index 022a20fcf..8cd7edd67 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,16 +6,24 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -26,6 +34,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -40,30 +52,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit index 3387708eb..f116aa10c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -155,6 +155,9 @@ 0 0 0 +1 +0 +1 0 0 0 @@ -219,6 +222,211 @@ 0 0 0 +1 +1 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -251,202 +459,7 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -1 -1 -1 -1 -1 -1 -0 -1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 0 0 0 @@ -454,29 +467,13 @@ 0 0 0 +1 +1 +1 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 +1 0 0 1 @@ -512,19 +509,22 @@ 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml index 4edf9cf2b..12a7a85bd 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -314,11 +314,11 @@ - + - + @@ -344,721 +344,721 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml index 1b1ecfa0d..283d346ab 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml @@ -553,7 +553,7 @@ - + @@ -731,7 +731,7 @@ - + @@ -1480,15 +1480,15 @@ - + - + - - - + + + @@ -1516,15 +1516,15 @@ - + - + - - - + + + @@ -1961,16 +1961,16 @@ - + - + - - - + + + @@ -2002,11 +2002,11 @@ - + - - - + + + @@ -2098,13 +2098,13 @@ - + - + - - + + @@ -2136,13 +2136,13 @@ - + - + - - + + @@ -2864,16 +2864,16 @@ - + - + - - - + + + @@ -2902,7 +2902,7 @@ - + @@ -3128,7 +3128,7 @@ - + @@ -3174,7 +3174,7 @@ - + @@ -3266,7 +3266,7 @@ - + @@ -3287,7 +3287,7 @@ - + @@ -3341,12 +3341,12 @@ - + - + - + @@ -3382,7 +3382,7 @@ - + @@ -3403,7 +3403,7 @@ - + @@ -3541,7 +3541,7 @@ - + @@ -3616,7 +3616,7 @@ - + @@ -3662,7 +3662,7 @@ - + @@ -3754,7 +3754,7 @@ - + @@ -3775,7 +3775,7 @@ - + @@ -3845,7 +3845,7 @@ - + @@ -3866,7 +3866,7 @@ - + @@ -3891,18 +3891,18 @@ - + - + - - + + - + @@ -3912,7 +3912,7 @@ - + @@ -4004,7 +4004,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml new file mode 100644 index 000000000..603d120a5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml @@ -0,0 +1,644 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v index c8c3d7300..e0098e212 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v @@ -162,7 +162,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -206,7 +206,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -284,7 +284,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:12]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:12]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -338,7 +338,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:12]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:12]), .ccff_tail(sb_1__0__0_ccff_tail)); @@ -365,7 +365,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]), .chanx_left_out(sb_1__1__0_chanx_left_out[0:12]), .ccff_tail(sb_1__1__0_ccff_tail)); @@ -414,7 +414,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:12]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:12]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_0__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -433,7 +433,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:12]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:12]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_1__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc index 0cf7373f8..c169fa409 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 9.25781396e-10 -waveform {0 4.62890698e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index 99aadddf5..1943afce4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index eefaf5cd9..d4af896d6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml index 97758d454..6a92006a5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml @@ -1,132 +1,132 @@ - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - + - + - + - - + + - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - - + + + - - - + + + - - + + - + - + - + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml index 750160da5..24b0e8590 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml @@ -1,130 +1,130 @@ - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - + - + - + - - + + - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml index 22e827258..10e1516e5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml @@ -1,132 +1,132 @@ - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - + - + - + - + - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - - + + + - - - + + + - - + + - + - + - + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml index 483099103..7725a1d9d 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml @@ -1,130 +1,130 @@ - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - + - + - + - - + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - + - + - + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 5ecb11950..0e17019b1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index edec22d72..010e9b689 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/mux_modules.yaml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/mux_modules.yaml new file mode 100644 index 000000000..5180e81ee --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/mux_modules.yaml @@ -0,0 +1,24 @@ +sb_0__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_0__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_1__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_1__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +cbx_1__0_: + - mux_tree_tapbuf_size6 +cbx_1__1_: + - mux_tree_tapbuf_size6 +cby_0__1_: + - mux_tree_tapbuf_size6 +cby_1__1_: + - mux_tree_tapbuf_size6 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml index 89523007a..9e63dda8a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml @@ -5,5 +5,5 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/config/task.conf b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/config/task.conf index 0a79fa359..8514c1877 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/config/task.conf @@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_device_layout = 4x4 openfpga_vpr_route_chan_width = 20 openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp +openfpga_preconfig_fabric_wrapper_dump_waveform= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index 40a28f3da..b7419a519 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.6573184729 + #0.782782793 clk[0] <= !clk[0]; end end @@ -106,7 +106,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #9.202458382 + #10.95895958 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 7053e16d9..99d159133 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,14 +9,14 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10} +create_clock clk[0] -period 1.565565566e-09 -waveform {0 7.82782783e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[38] -set_input_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[58] -set_output_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[17] +set_input_delay -clock clk[0] -max 1.565565566e-09 gfpga_pad_GPIO_PAD[79] +set_input_delay -clock clk[0] -max 1.565565566e-09 gfpga_pad_GPIO_PAD[74] +set_output_delay -clock clk[0] -max 1.565565566e-09 gfpga_pad_GPIO_PAD[17] ################################################## # Disable timing for unused I/Os @@ -58,6 +58,7 @@ set_disable_timing gfpga_pad_GPIO_PAD[34] set_disable_timing gfpga_pad_GPIO_PAD[35] set_disable_timing gfpga_pad_GPIO_PAD[36] set_disable_timing gfpga_pad_GPIO_PAD[37] +set_disable_timing gfpga_pad_GPIO_PAD[38] set_disable_timing gfpga_pad_GPIO_PAD[39] set_disable_timing gfpga_pad_GPIO_PAD[40] set_disable_timing gfpga_pad_GPIO_PAD[41] @@ -77,6 +78,7 @@ set_disable_timing gfpga_pad_GPIO_PAD[54] set_disable_timing gfpga_pad_GPIO_PAD[55] set_disable_timing gfpga_pad_GPIO_PAD[56] set_disable_timing gfpga_pad_GPIO_PAD[57] +set_disable_timing gfpga_pad_GPIO_PAD[58] set_disable_timing gfpga_pad_GPIO_PAD[59] set_disable_timing gfpga_pad_GPIO_PAD[60] set_disable_timing gfpga_pad_GPIO_PAD[61] @@ -92,12 +94,10 @@ set_disable_timing gfpga_pad_GPIO_PAD[70] set_disable_timing gfpga_pad_GPIO_PAD[71] set_disable_timing gfpga_pad_GPIO_PAD[72] set_disable_timing gfpga_pad_GPIO_PAD[73] -set_disable_timing gfpga_pad_GPIO_PAD[74] set_disable_timing gfpga_pad_GPIO_PAD[75] set_disable_timing gfpga_pad_GPIO_PAD[76] set_disable_timing gfpga_pad_GPIO_PAD[77] set_disable_timing gfpga_pad_GPIO_PAD[78] -set_disable_timing gfpga_pad_GPIO_PAD[79] set_disable_timing gfpga_pad_GPIO_PAD[80] set_disable_timing gfpga_pad_GPIO_PAD[81] set_disable_timing gfpga_pad_GPIO_PAD[82] @@ -153,48 +153,44 @@ set_disable_timing gfpga_pad_GPIO_PAD[127] set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -207,12 +203,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q @@ -221,6 +221,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -231,6 +239,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -247,6 +257,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -255,32 +273,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -293,8 +295,6 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN ################################################## # Disable timing for Connection block cbx_1__0_ ################################################## @@ -468,6 +468,7 @@ set_disable_timing cbx_1__2_/chanx_right_in[0] set_disable_timing cbx_1__2_/chanx_left_in[1] set_disable_timing cbx_1__2_/chanx_right_in[1] set_disable_timing cbx_1__2_/chanx_left_in[2] +set_disable_timing cbx_1__2_/chanx_right_in[2] set_disable_timing cbx_1__2_/chanx_left_in[3] set_disable_timing cbx_1__2_/chanx_right_in[3] set_disable_timing cbx_1__2_/chanx_left_in[4] @@ -477,6 +478,7 @@ set_disable_timing cbx_1__2_/chanx_right_in[5] set_disable_timing cbx_1__2_/chanx_left_in[6] set_disable_timing cbx_1__2_/chanx_right_in[6] set_disable_timing cbx_1__2_/chanx_left_in[7] +set_disable_timing cbx_1__2_/chanx_right_in[7] set_disable_timing cbx_1__2_/chanx_left_in[8] set_disable_timing cbx_1__2_/chanx_right_in[8] set_disable_timing cbx_1__2_/chanx_left_in[9] @@ -486,6 +488,7 @@ set_disable_timing cbx_1__2_/chanx_right_out[0] set_disable_timing cbx_1__2_/chanx_left_out[1] set_disable_timing cbx_1__2_/chanx_right_out[1] set_disable_timing cbx_1__2_/chanx_left_out[2] +set_disable_timing cbx_1__2_/chanx_right_out[2] set_disable_timing cbx_1__2_/chanx_left_out[3] set_disable_timing cbx_1__2_/chanx_right_out[3] set_disable_timing cbx_1__2_/chanx_left_out[4] @@ -495,6 +498,7 @@ set_disable_timing cbx_1__2_/chanx_right_out[5] set_disable_timing cbx_1__2_/chanx_left_out[6] set_disable_timing cbx_1__2_/chanx_right_out[6] set_disable_timing cbx_1__2_/chanx_left_out[7] +set_disable_timing cbx_1__2_/chanx_right_out[7] set_disable_timing cbx_1__2_/chanx_left_out[8] set_disable_timing cbx_1__2_/chanx_right_out[8] set_disable_timing cbx_1__2_/chanx_left_out[9] @@ -712,7 +716,6 @@ set_disable_timing cbx_2__0_/chanx_right_in[7] set_disable_timing cbx_2__0_/chanx_left_in[8] set_disable_timing cbx_2__0_/chanx_right_in[8] set_disable_timing cbx_2__0_/chanx_left_in[9] -set_disable_timing cbx_2__0_/chanx_right_in[9] set_disable_timing cbx_2__0_/chanx_left_out[0] set_disable_timing cbx_2__0_/chanx_right_out[0] set_disable_timing cbx_2__0_/chanx_left_out[1] @@ -732,7 +735,6 @@ set_disable_timing cbx_2__0_/chanx_right_out[7] set_disable_timing cbx_2__0_/chanx_left_out[8] set_disable_timing cbx_2__0_/chanx_right_out[8] set_disable_timing cbx_2__0_/chanx_left_out[9] -set_disable_timing cbx_2__0_/chanx_right_out[9] set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] @@ -796,6 +798,7 @@ set_disable_timing cbx_2__1_/chanx_right_in[1] set_disable_timing cbx_2__1_/chanx_left_in[2] set_disable_timing cbx_2__1_/chanx_right_in[2] set_disable_timing cbx_2__1_/chanx_left_in[3] +set_disable_timing cbx_2__1_/chanx_right_in[3] set_disable_timing cbx_2__1_/chanx_left_in[4] set_disable_timing cbx_2__1_/chanx_right_in[4] set_disable_timing cbx_2__1_/chanx_left_in[5] @@ -815,6 +818,7 @@ set_disable_timing cbx_2__1_/chanx_right_out[1] set_disable_timing cbx_2__1_/chanx_left_out[2] set_disable_timing cbx_2__1_/chanx_right_out[2] set_disable_timing cbx_2__1_/chanx_left_out[3] +set_disable_timing cbx_2__1_/chanx_right_out[3] set_disable_timing cbx_2__1_/chanx_left_out[4] set_disable_timing cbx_2__1_/chanx_right_out[4] set_disable_timing cbx_2__1_/chanx_left_out[5] @@ -859,6 +863,7 @@ set_disable_timing cbx_2__1_/mux_top_ipin_1/in[2] set_disable_timing cbx_2__2_/chanx_left_in[0] set_disable_timing cbx_2__2_/chanx_right_in[0] set_disable_timing cbx_2__2_/chanx_left_in[1] +set_disable_timing cbx_2__2_/chanx_right_in[1] set_disable_timing cbx_2__2_/chanx_left_in[2] set_disable_timing cbx_2__2_/chanx_right_in[2] set_disable_timing cbx_2__2_/chanx_left_in[3] @@ -868,15 +873,16 @@ set_disable_timing cbx_2__2_/chanx_right_in[4] set_disable_timing cbx_2__2_/chanx_left_in[5] set_disable_timing cbx_2__2_/chanx_right_in[5] set_disable_timing cbx_2__2_/chanx_left_in[6] +set_disable_timing cbx_2__2_/chanx_right_in[6] set_disable_timing cbx_2__2_/chanx_left_in[7] set_disable_timing cbx_2__2_/chanx_right_in[7] set_disable_timing cbx_2__2_/chanx_left_in[8] set_disable_timing cbx_2__2_/chanx_right_in[8] set_disable_timing cbx_2__2_/chanx_left_in[9] -set_disable_timing cbx_2__2_/chanx_right_in[9] set_disable_timing cbx_2__2_/chanx_left_out[0] set_disable_timing cbx_2__2_/chanx_right_out[0] set_disable_timing cbx_2__2_/chanx_left_out[1] +set_disable_timing cbx_2__2_/chanx_right_out[1] set_disable_timing cbx_2__2_/chanx_left_out[2] set_disable_timing cbx_2__2_/chanx_right_out[2] set_disable_timing cbx_2__2_/chanx_left_out[3] @@ -886,12 +892,12 @@ set_disable_timing cbx_2__2_/chanx_right_out[4] set_disable_timing cbx_2__2_/chanx_left_out[5] set_disable_timing cbx_2__2_/chanx_right_out[5] set_disable_timing cbx_2__2_/chanx_left_out[6] +set_disable_timing cbx_2__2_/chanx_right_out[6] set_disable_timing cbx_2__2_/chanx_left_out[7] set_disable_timing cbx_2__2_/chanx_right_out[7] set_disable_timing cbx_2__2_/chanx_left_out[8] set_disable_timing cbx_2__2_/chanx_right_out[8] set_disable_timing cbx_2__2_/chanx_left_out[9] -set_disable_timing cbx_2__2_/chanx_right_out[9] set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] @@ -936,10 +942,10 @@ set_disable_timing cbx_2__3_/chanx_right_in[5] set_disable_timing cbx_2__3_/chanx_left_in[6] set_disable_timing cbx_2__3_/chanx_right_in[6] set_disable_timing cbx_2__3_/chanx_left_in[7] +set_disable_timing cbx_2__3_/chanx_right_in[7] set_disable_timing cbx_2__3_/chanx_left_in[8] set_disable_timing cbx_2__3_/chanx_right_in[8] set_disable_timing cbx_2__3_/chanx_left_in[9] -set_disable_timing cbx_2__3_/chanx_right_in[9] set_disable_timing cbx_2__3_/chanx_left_out[0] set_disable_timing cbx_2__3_/chanx_right_out[0] set_disable_timing cbx_2__3_/chanx_left_out[1] @@ -955,10 +961,10 @@ set_disable_timing cbx_2__3_/chanx_right_out[5] set_disable_timing cbx_2__3_/chanx_left_out[6] set_disable_timing cbx_2__3_/chanx_right_out[6] set_disable_timing cbx_2__3_/chanx_left_out[7] +set_disable_timing cbx_2__3_/chanx_right_out[7] set_disable_timing cbx_2__3_/chanx_left_out[8] set_disable_timing cbx_2__3_/chanx_right_out[8] set_disable_timing cbx_2__3_/chanx_left_out[9] -set_disable_timing cbx_2__3_/chanx_right_out[9] set_disable_timing cbx_2__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_2__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_2__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] @@ -1082,7 +1088,6 @@ set_disable_timing cbx_2__4_/mux_top_ipin_1/in[2] ################################################## # Disable timing for Connection block cbx_1__0_ ################################################## -set_disable_timing cbx_3__0_/chanx_left_in[0] set_disable_timing cbx_3__0_/chanx_right_in[0] set_disable_timing cbx_3__0_/chanx_left_in[1] set_disable_timing cbx_3__0_/chanx_right_in[1] @@ -1099,10 +1104,8 @@ set_disable_timing cbx_3__0_/chanx_right_in[6] set_disable_timing cbx_3__0_/chanx_left_in[7] set_disable_timing cbx_3__0_/chanx_right_in[7] set_disable_timing cbx_3__0_/chanx_left_in[8] -set_disable_timing cbx_3__0_/chanx_right_in[8] set_disable_timing cbx_3__0_/chanx_left_in[9] set_disable_timing cbx_3__0_/chanx_right_in[9] -set_disable_timing cbx_3__0_/chanx_left_out[0] set_disable_timing cbx_3__0_/chanx_right_out[0] set_disable_timing cbx_3__0_/chanx_left_out[1] set_disable_timing cbx_3__0_/chanx_right_out[1] @@ -1119,7 +1122,6 @@ set_disable_timing cbx_3__0_/chanx_right_out[6] set_disable_timing cbx_3__0_/chanx_left_out[7] set_disable_timing cbx_3__0_/chanx_right_out[7] set_disable_timing cbx_3__0_/chanx_left_out[8] -set_disable_timing cbx_3__0_/chanx_right_out[8] set_disable_timing cbx_3__0_/chanx_left_out[9] set_disable_timing cbx_3__0_/chanx_right_out[9] set_disable_timing cbx_3__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] @@ -1178,11 +1180,11 @@ set_disable_timing cbx_3__0_/mux_top_ipin_6/in[2] ################################################## # Disable timing for Connection block cbx_1__1_ ################################################## -set_disable_timing cbx_3__1_/chanx_left_in[0] set_disable_timing cbx_3__1_/chanx_right_in[0] set_disable_timing cbx_3__1_/chanx_left_in[1] set_disable_timing cbx_3__1_/chanx_right_in[1] set_disable_timing cbx_3__1_/chanx_left_in[2] +set_disable_timing cbx_3__1_/chanx_right_in[2] set_disable_timing cbx_3__1_/chanx_left_in[3] set_disable_timing cbx_3__1_/chanx_right_in[3] set_disable_timing cbx_3__1_/chanx_left_in[4] @@ -1197,11 +1199,11 @@ set_disable_timing cbx_3__1_/chanx_left_in[8] set_disable_timing cbx_3__1_/chanx_right_in[8] set_disable_timing cbx_3__1_/chanx_left_in[9] set_disable_timing cbx_3__1_/chanx_right_in[9] -set_disable_timing cbx_3__1_/chanx_left_out[0] set_disable_timing cbx_3__1_/chanx_right_out[0] set_disable_timing cbx_3__1_/chanx_left_out[1] set_disable_timing cbx_3__1_/chanx_right_out[1] set_disable_timing cbx_3__1_/chanx_left_out[2] +set_disable_timing cbx_3__1_/chanx_right_out[2] set_disable_timing cbx_3__1_/chanx_left_out[3] set_disable_timing cbx_3__1_/chanx_right_out[3] set_disable_timing cbx_3__1_/chanx_left_out[4] @@ -1216,13 +1218,11 @@ set_disable_timing cbx_3__1_/chanx_left_out[8] set_disable_timing cbx_3__1_/chanx_right_out[8] set_disable_timing cbx_3__1_/chanx_left_out[9] set_disable_timing cbx_3__1_/chanx_right_out[9] -set_disable_timing cbx_3__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_3__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_3__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] set_disable_timing cbx_3__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] set_disable_timing cbx_3__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] set_disable_timing cbx_3__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] -set_disable_timing cbx_3__1_/mux_bottom_ipin_0/in[1] set_disable_timing cbx_3__1_/mux_bottom_ipin_0/in[0] set_disable_timing cbx_3__1_/mux_bottom_ipin_1/in[1] set_disable_timing cbx_3__1_/mux_bottom_ipin_1/in[0] @@ -1246,6 +1246,7 @@ set_disable_timing cbx_3__1_/mux_top_ipin_1/in[2] # Disable timing for Connection block cbx_1__1_ ################################################## set_disable_timing cbx_3__2_/chanx_left_in[0] +set_disable_timing cbx_3__2_/chanx_right_in[0] set_disable_timing cbx_3__2_/chanx_left_in[1] set_disable_timing cbx_3__2_/chanx_right_in[1] set_disable_timing cbx_3__2_/chanx_left_in[2] @@ -1255,15 +1256,16 @@ set_disable_timing cbx_3__2_/chanx_right_in[3] set_disable_timing cbx_3__2_/chanx_left_in[4] set_disable_timing cbx_3__2_/chanx_right_in[4] set_disable_timing cbx_3__2_/chanx_left_in[5] +set_disable_timing cbx_3__2_/chanx_right_in[5] set_disable_timing cbx_3__2_/chanx_left_in[6] set_disable_timing cbx_3__2_/chanx_right_in[6] set_disable_timing cbx_3__2_/chanx_left_in[7] set_disable_timing cbx_3__2_/chanx_right_in[7] set_disable_timing cbx_3__2_/chanx_left_in[8] -set_disable_timing cbx_3__2_/chanx_right_in[8] set_disable_timing cbx_3__2_/chanx_left_in[9] set_disable_timing cbx_3__2_/chanx_right_in[9] set_disable_timing cbx_3__2_/chanx_left_out[0] +set_disable_timing cbx_3__2_/chanx_right_out[0] set_disable_timing cbx_3__2_/chanx_left_out[1] set_disable_timing cbx_3__2_/chanx_right_out[1] set_disable_timing cbx_3__2_/chanx_left_out[2] @@ -1273,18 +1275,17 @@ set_disable_timing cbx_3__2_/chanx_right_out[3] set_disable_timing cbx_3__2_/chanx_left_out[4] set_disable_timing cbx_3__2_/chanx_right_out[4] set_disable_timing cbx_3__2_/chanx_left_out[5] +set_disable_timing cbx_3__2_/chanx_right_out[5] set_disable_timing cbx_3__2_/chanx_left_out[6] set_disable_timing cbx_3__2_/chanx_right_out[6] set_disable_timing cbx_3__2_/chanx_left_out[7] set_disable_timing cbx_3__2_/chanx_right_out[7] set_disable_timing cbx_3__2_/chanx_left_out[8] -set_disable_timing cbx_3__2_/chanx_right_out[8] set_disable_timing cbx_3__2_/chanx_left_out[9] set_disable_timing cbx_3__2_/chanx_right_out[9] set_disable_timing cbx_3__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_3__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_3__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] -set_disable_timing cbx_3__2_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] set_disable_timing cbx_3__2_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] set_disable_timing cbx_3__2_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] set_disable_timing cbx_3__2_/mux_bottom_ipin_0/in[1] @@ -1304,7 +1305,6 @@ set_disable_timing cbx_3__2_/mux_top_ipin_2/in[0] set_disable_timing cbx_3__2_/mux_bottom_ipin_2/in[3] set_disable_timing cbx_3__2_/mux_bottom_ipin_2/in[2] set_disable_timing cbx_3__2_/mux_top_ipin_0/in[3] -set_disable_timing cbx_3__2_/mux_top_ipin_0/in[2] set_disable_timing cbx_3__2_/mux_top_ipin_1/in[3] set_disable_timing cbx_3__2_/mux_top_ipin_1/in[2] ################################################## @@ -1323,10 +1323,10 @@ set_disable_timing cbx_3__3_/chanx_right_in[4] set_disable_timing cbx_3__3_/chanx_left_in[5] set_disable_timing cbx_3__3_/chanx_right_in[5] set_disable_timing cbx_3__3_/chanx_left_in[6] +set_disable_timing cbx_3__3_/chanx_right_in[6] set_disable_timing cbx_3__3_/chanx_left_in[7] set_disable_timing cbx_3__3_/chanx_right_in[7] set_disable_timing cbx_3__3_/chanx_left_in[8] -set_disable_timing cbx_3__3_/chanx_right_in[8] set_disable_timing cbx_3__3_/chanx_left_in[9] set_disable_timing cbx_3__3_/chanx_right_in[9] set_disable_timing cbx_3__3_/chanx_left_out[0] @@ -1342,10 +1342,10 @@ set_disable_timing cbx_3__3_/chanx_right_out[4] set_disable_timing cbx_3__3_/chanx_left_out[5] set_disable_timing cbx_3__3_/chanx_right_out[5] set_disable_timing cbx_3__3_/chanx_left_out[6] +set_disable_timing cbx_3__3_/chanx_right_out[6] set_disable_timing cbx_3__3_/chanx_left_out[7] set_disable_timing cbx_3__3_/chanx_right_out[7] set_disable_timing cbx_3__3_/chanx_left_out[8] -set_disable_timing cbx_3__3_/chanx_right_out[8] set_disable_timing cbx_3__3_/chanx_left_out[9] set_disable_timing cbx_3__3_/chanx_right_out[9] set_disable_timing cbx_3__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] @@ -1471,7 +1471,6 @@ set_disable_timing cbx_3__4_/mux_top_ipin_1/in[2] ################################################## set_disable_timing cbx_4__0_/chanx_left_in[0] set_disable_timing cbx_4__0_/chanx_right_in[0] -set_disable_timing cbx_4__0_/chanx_left_in[1] set_disable_timing cbx_4__0_/chanx_right_in[1] set_disable_timing cbx_4__0_/chanx_left_in[2] set_disable_timing cbx_4__0_/chanx_right_in[2] @@ -1491,7 +1490,6 @@ set_disable_timing cbx_4__0_/chanx_left_in[9] set_disable_timing cbx_4__0_/chanx_right_in[9] set_disable_timing cbx_4__0_/chanx_left_out[0] set_disable_timing cbx_4__0_/chanx_right_out[0] -set_disable_timing cbx_4__0_/chanx_left_out[1] set_disable_timing cbx_4__0_/chanx_right_out[1] set_disable_timing cbx_4__0_/chanx_left_out[2] set_disable_timing cbx_4__0_/chanx_right_out[2] @@ -1567,7 +1565,7 @@ set_disable_timing cbx_4__0_/mux_top_ipin_6/in[2] ################################################## set_disable_timing cbx_4__1_/chanx_left_in[0] set_disable_timing cbx_4__1_/chanx_right_in[0] -set_disable_timing cbx_4__1_/chanx_left_in[1] +set_disable_timing cbx_4__1_/chanx_right_in[1] set_disable_timing cbx_4__1_/chanx_left_in[2] set_disable_timing cbx_4__1_/chanx_right_in[2] set_disable_timing cbx_4__1_/chanx_left_in[3] @@ -1586,7 +1584,7 @@ set_disable_timing cbx_4__1_/chanx_left_in[9] set_disable_timing cbx_4__1_/chanx_right_in[9] set_disable_timing cbx_4__1_/chanx_left_out[0] set_disable_timing cbx_4__1_/chanx_right_out[0] -set_disable_timing cbx_4__1_/chanx_left_out[1] +set_disable_timing cbx_4__1_/chanx_right_out[1] set_disable_timing cbx_4__1_/chanx_left_out[2] set_disable_timing cbx_4__1_/chanx_right_out[2] set_disable_timing cbx_4__1_/chanx_left_out[3] @@ -1641,6 +1639,7 @@ set_disable_timing cbx_4__2_/chanx_right_in[2] set_disable_timing cbx_4__2_/chanx_left_in[3] set_disable_timing cbx_4__2_/chanx_right_in[3] set_disable_timing cbx_4__2_/chanx_left_in[4] +set_disable_timing cbx_4__2_/chanx_right_in[4] set_disable_timing cbx_4__2_/chanx_left_in[5] set_disable_timing cbx_4__2_/chanx_right_in[5] set_disable_timing cbx_4__2_/chanx_left_in[6] @@ -1660,6 +1659,7 @@ set_disable_timing cbx_4__2_/chanx_right_out[2] set_disable_timing cbx_4__2_/chanx_left_out[3] set_disable_timing cbx_4__2_/chanx_right_out[3] set_disable_timing cbx_4__2_/chanx_left_out[4] +set_disable_timing cbx_4__2_/chanx_right_out[4] set_disable_timing cbx_4__2_/chanx_left_out[5] set_disable_timing cbx_4__2_/chanx_right_out[5] set_disable_timing cbx_4__2_/chanx_left_out[6] @@ -1710,6 +1710,7 @@ set_disable_timing cbx_4__3_/chanx_right_in[3] set_disable_timing cbx_4__3_/chanx_left_in[4] set_disable_timing cbx_4__3_/chanx_right_in[4] set_disable_timing cbx_4__3_/chanx_left_in[5] +set_disable_timing cbx_4__3_/chanx_right_in[5] set_disable_timing cbx_4__3_/chanx_left_in[6] set_disable_timing cbx_4__3_/chanx_right_in[6] set_disable_timing cbx_4__3_/chanx_left_in[7] @@ -1729,6 +1730,7 @@ set_disable_timing cbx_4__3_/chanx_right_out[3] set_disable_timing cbx_4__3_/chanx_left_out[4] set_disable_timing cbx_4__3_/chanx_right_out[4] set_disable_timing cbx_4__3_/chanx_left_out[5] +set_disable_timing cbx_4__3_/chanx_right_out[5] set_disable_timing cbx_4__3_/chanx_left_out[6] set_disable_timing cbx_4__3_/chanx_right_out[6] set_disable_timing cbx_4__3_/chanx_left_out[7] @@ -1742,6 +1744,7 @@ set_disable_timing cbx_4__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6 set_disable_timing cbx_4__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] set_disable_timing cbx_4__3_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] set_disable_timing cbx_4__3_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] +set_disable_timing cbx_4__3_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[1] set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[0] set_disable_timing cbx_4__3_/mux_bottom_ipin_1/in[1] @@ -1755,6 +1758,7 @@ set_disable_timing cbx_4__3_/mux_top_ipin_1/in[0] set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[3] set_disable_timing cbx_4__3_/mux_top_ipin_2/in[1] set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[2] +set_disable_timing cbx_4__3_/mux_top_ipin_2/in[0] set_disable_timing cbx_4__3_/mux_bottom_ipin_2/in[3] set_disable_timing cbx_4__3_/mux_bottom_ipin_2/in[2] set_disable_timing cbx_4__3_/mux_top_ipin_0/in[3] @@ -2346,6 +2350,7 @@ set_disable_timing cby_1__2_/mux_right_ipin_0/in[2] ################################################## # Disable timing for Connection block cby_1__1_ ################################################## +set_disable_timing cby_1__3_/chany_bottom_in[0] set_disable_timing cby_1__3_/chany_top_in[0] set_disable_timing cby_1__3_/chany_bottom_in[1] set_disable_timing cby_1__3_/chany_top_in[1] @@ -2365,6 +2370,7 @@ set_disable_timing cby_1__3_/chany_bottom_in[8] set_disable_timing cby_1__3_/chany_top_in[8] set_disable_timing cby_1__3_/chany_bottom_in[9] set_disable_timing cby_1__3_/chany_top_in[9] +set_disable_timing cby_1__3_/chany_bottom_out[0] set_disable_timing cby_1__3_/chany_top_out[0] set_disable_timing cby_1__3_/chany_bottom_out[1] set_disable_timing cby_1__3_/chany_top_out[1] @@ -2408,12 +2414,12 @@ set_disable_timing cby_1__3_/mux_right_ipin_0/in[2] ################################################## set_disable_timing cby_1__4_/chany_bottom_in[0] set_disable_timing cby_1__4_/chany_top_in[0] +set_disable_timing cby_1__4_/chany_bottom_in[1] set_disable_timing cby_1__4_/chany_top_in[1] set_disable_timing cby_1__4_/chany_bottom_in[2] set_disable_timing cby_1__4_/chany_top_in[2] set_disable_timing cby_1__4_/chany_bottom_in[3] set_disable_timing cby_1__4_/chany_top_in[3] -set_disable_timing cby_1__4_/chany_bottom_in[4] set_disable_timing cby_1__4_/chany_top_in[4] set_disable_timing cby_1__4_/chany_bottom_in[5] set_disable_timing cby_1__4_/chany_top_in[5] @@ -2427,12 +2433,12 @@ set_disable_timing cby_1__4_/chany_bottom_in[9] set_disable_timing cby_1__4_/chany_top_in[9] set_disable_timing cby_1__4_/chany_bottom_out[0] set_disable_timing cby_1__4_/chany_top_out[0] +set_disable_timing cby_1__4_/chany_bottom_out[1] set_disable_timing cby_1__4_/chany_top_out[1] set_disable_timing cby_1__4_/chany_bottom_out[2] set_disable_timing cby_1__4_/chany_top_out[2] set_disable_timing cby_1__4_/chany_bottom_out[3] set_disable_timing cby_1__4_/chany_top_out[3] -set_disable_timing cby_1__4_/chany_bottom_out[4] set_disable_timing cby_1__4_/chany_top_out[4] set_disable_timing cby_1__4_/chany_bottom_out[5] set_disable_timing cby_1__4_/chany_top_out[5] @@ -2476,7 +2482,6 @@ set_disable_timing cby_2__1_/chany_bottom_in[3] set_disable_timing cby_2__1_/chany_top_in[3] set_disable_timing cby_2__1_/chany_bottom_in[4] set_disable_timing cby_2__1_/chany_top_in[4] -set_disable_timing cby_2__1_/chany_bottom_in[5] set_disable_timing cby_2__1_/chany_top_in[5] set_disable_timing cby_2__1_/chany_bottom_in[6] set_disable_timing cby_2__1_/chany_top_in[6] @@ -2496,7 +2501,6 @@ set_disable_timing cby_2__1_/chany_bottom_out[3] set_disable_timing cby_2__1_/chany_top_out[3] set_disable_timing cby_2__1_/chany_bottom_out[4] set_disable_timing cby_2__1_/chany_top_out[4] -set_disable_timing cby_2__1_/chany_bottom_out[5] set_disable_timing cby_2__1_/chany_top_out[5] set_disable_timing cby_2__1_/chany_bottom_out[6] set_disable_timing cby_2__1_/chany_top_out[6] @@ -2540,7 +2544,6 @@ set_disable_timing cby_2__2_/chany_bottom_in[4] set_disable_timing cby_2__2_/chany_top_in[4] set_disable_timing cby_2__2_/chany_bottom_in[5] set_disable_timing cby_2__2_/chany_top_in[5] -set_disable_timing cby_2__2_/chany_bottom_in[6] set_disable_timing cby_2__2_/chany_top_in[6] set_disable_timing cby_2__2_/chany_bottom_in[7] set_disable_timing cby_2__2_/chany_top_in[7] @@ -2560,7 +2563,6 @@ set_disable_timing cby_2__2_/chany_bottom_out[4] set_disable_timing cby_2__2_/chany_top_out[4] set_disable_timing cby_2__2_/chany_bottom_out[5] set_disable_timing cby_2__2_/chany_top_out[5] -set_disable_timing cby_2__2_/chany_bottom_out[6] set_disable_timing cby_2__2_/chany_top_out[6] set_disable_timing cby_2__2_/chany_bottom_out[7] set_disable_timing cby_2__2_/chany_top_out[7] @@ -2604,7 +2606,6 @@ set_disable_timing cby_2__3_/chany_bottom_in[5] set_disable_timing cby_2__3_/chany_top_in[5] set_disable_timing cby_2__3_/chany_bottom_in[6] set_disable_timing cby_2__3_/chany_top_in[6] -set_disable_timing cby_2__3_/chany_bottom_in[7] set_disable_timing cby_2__3_/chany_top_in[7] set_disable_timing cby_2__3_/chany_bottom_in[8] set_disable_timing cby_2__3_/chany_top_in[8] @@ -2624,7 +2625,6 @@ set_disable_timing cby_2__3_/chany_bottom_out[5] set_disable_timing cby_2__3_/chany_top_out[5] set_disable_timing cby_2__3_/chany_bottom_out[6] set_disable_timing cby_2__3_/chany_top_out[6] -set_disable_timing cby_2__3_/chany_bottom_out[7] set_disable_timing cby_2__3_/chany_top_out[7] set_disable_timing cby_2__3_/chany_bottom_out[8] set_disable_timing cby_2__3_/chany_top_out[8] @@ -2714,7 +2714,6 @@ set_disable_timing cby_2__4_/mux_right_ipin_0/in[2] ################################################## # Disable timing for Connection block cby_1__1_ ################################################## -set_disable_timing cby_3__1_/chany_bottom_in[0] set_disable_timing cby_3__1_/chany_top_in[0] set_disable_timing cby_3__1_/chany_bottom_in[1] set_disable_timing cby_3__1_/chany_top_in[1] @@ -2734,7 +2733,6 @@ set_disable_timing cby_3__1_/chany_bottom_in[8] set_disable_timing cby_3__1_/chany_top_in[8] set_disable_timing cby_3__1_/chany_bottom_in[9] set_disable_timing cby_3__1_/chany_top_in[9] -set_disable_timing cby_3__1_/chany_bottom_out[0] set_disable_timing cby_3__1_/chany_top_out[0] set_disable_timing cby_3__1_/chany_bottom_out[1] set_disable_timing cby_3__1_/chany_top_out[1] @@ -2777,7 +2775,6 @@ set_disable_timing cby_3__1_/mux_right_ipin_0/in[2] # Disable timing for Connection block cby_1__1_ ################################################## set_disable_timing cby_3__2_/chany_top_in[0] -set_disable_timing cby_3__2_/chany_bottom_in[1] set_disable_timing cby_3__2_/chany_top_in[1] set_disable_timing cby_3__2_/chany_bottom_in[2] set_disable_timing cby_3__2_/chany_top_in[2] @@ -2796,7 +2793,6 @@ set_disable_timing cby_3__2_/chany_top_in[8] set_disable_timing cby_3__2_/chany_bottom_in[9] set_disable_timing cby_3__2_/chany_top_in[9] set_disable_timing cby_3__2_/chany_top_out[0] -set_disable_timing cby_3__2_/chany_bottom_out[1] set_disable_timing cby_3__2_/chany_top_out[1] set_disable_timing cby_3__2_/chany_bottom_out[2] set_disable_timing cby_3__2_/chany_top_out[2] @@ -2839,7 +2835,6 @@ set_disable_timing cby_3__2_/mux_right_ipin_0/in[2] set_disable_timing cby_3__3_/chany_bottom_in[0] set_disable_timing cby_3__3_/chany_top_in[0] set_disable_timing cby_3__3_/chany_top_in[1] -set_disable_timing cby_3__3_/chany_bottom_in[2] set_disable_timing cby_3__3_/chany_top_in[2] set_disable_timing cby_3__3_/chany_bottom_in[3] set_disable_timing cby_3__3_/chany_top_in[3] @@ -2858,7 +2853,6 @@ set_disable_timing cby_3__3_/chany_top_in[9] set_disable_timing cby_3__3_/chany_bottom_out[0] set_disable_timing cby_3__3_/chany_top_out[0] set_disable_timing cby_3__3_/chany_top_out[1] -set_disable_timing cby_3__3_/chany_bottom_out[2] set_disable_timing cby_3__3_/chany_top_out[2] set_disable_timing cby_3__3_/chany_bottom_out[3] set_disable_timing cby_3__3_/chany_top_out[3] @@ -2875,11 +2869,13 @@ set_disable_timing cby_3__3_/chany_top_out[8] set_disable_timing cby_3__3_/chany_bottom_out[9] set_disable_timing cby_3__3_/chany_top_out[9] set_disable_timing cby_3__3_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] +set_disable_timing cby_3__3_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] set_disable_timing cby_3__3_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] set_disable_timing cby_3__3_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] set_disable_timing cby_3__3_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] set_disable_timing cby_3__3_/mux_left_ipin_0/in[1] set_disable_timing cby_3__3_/mux_left_ipin_0/in[0] +set_disable_timing cby_3__3_/mux_left_ipin_1/in[1] set_disable_timing cby_3__3_/mux_left_ipin_1/in[0] set_disable_timing cby_3__3_/mux_right_ipin_0/in[1] set_disable_timing cby_3__3_/mux_right_ipin_0/in[0] @@ -2899,7 +2895,6 @@ set_disable_timing cby_3__4_/chany_top_in[0] set_disable_timing cby_3__4_/chany_bottom_in[1] set_disable_timing cby_3__4_/chany_top_in[1] set_disable_timing cby_3__4_/chany_top_in[2] -set_disable_timing cby_3__4_/chany_bottom_in[3] set_disable_timing cby_3__4_/chany_top_in[3] set_disable_timing cby_3__4_/chany_bottom_in[4] set_disable_timing cby_3__4_/chany_top_in[4] @@ -2918,7 +2913,6 @@ set_disable_timing cby_3__4_/chany_top_out[0] set_disable_timing cby_3__4_/chany_bottom_out[1] set_disable_timing cby_3__4_/chany_top_out[1] set_disable_timing cby_3__4_/chany_top_out[2] -set_disable_timing cby_3__4_/chany_bottom_out[3] set_disable_timing cby_3__4_/chany_top_out[3] set_disable_timing cby_3__4_/chany_bottom_out[4] set_disable_timing cby_3__4_/chany_top_out[4] @@ -2960,6 +2954,7 @@ set_disable_timing cby_4__1_/chany_bottom_in[1] set_disable_timing cby_4__1_/chany_top_in[1] set_disable_timing cby_4__1_/chany_bottom_in[2] set_disable_timing cby_4__1_/chany_top_in[2] +set_disable_timing cby_4__1_/chany_bottom_in[3] set_disable_timing cby_4__1_/chany_top_in[3] set_disable_timing cby_4__1_/chany_bottom_in[4] set_disable_timing cby_4__1_/chany_top_in[4] @@ -2979,6 +2974,7 @@ set_disable_timing cby_4__1_/chany_bottom_out[1] set_disable_timing cby_4__1_/chany_top_out[1] set_disable_timing cby_4__1_/chany_bottom_out[2] set_disable_timing cby_4__1_/chany_top_out[2] +set_disable_timing cby_4__1_/chany_bottom_out[3] set_disable_timing cby_4__1_/chany_top_out[3] set_disable_timing cby_4__1_/chany_bottom_out[4] set_disable_timing cby_4__1_/chany_top_out[4] @@ -3065,6 +3061,7 @@ set_disable_timing cby_4__2_/chany_top_in[7] set_disable_timing cby_4__2_/chany_bottom_in[8] set_disable_timing cby_4__2_/chany_top_in[8] set_disable_timing cby_4__2_/chany_bottom_in[9] +set_disable_timing cby_4__2_/chany_top_in[9] set_disable_timing cby_4__2_/chany_bottom_out[0] set_disable_timing cby_4__2_/chany_top_out[0] set_disable_timing cby_4__2_/chany_bottom_out[1] @@ -3084,6 +3081,7 @@ set_disable_timing cby_4__2_/chany_top_out[7] set_disable_timing cby_4__2_/chany_bottom_out[8] set_disable_timing cby_4__2_/chany_top_out[8] set_disable_timing cby_4__2_/chany_bottom_out[9] +set_disable_timing cby_4__2_/chany_top_out[9] set_disable_timing cby_4__2_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] set_disable_timing cby_4__2_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cby_4__2_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] @@ -3153,7 +3151,9 @@ set_disable_timing cby_4__3_/chany_top_in[5] set_disable_timing cby_4__3_/chany_bottom_in[6] set_disable_timing cby_4__3_/chany_top_in[6] set_disable_timing cby_4__3_/chany_bottom_in[7] +set_disable_timing cby_4__3_/chany_top_in[7] set_disable_timing cby_4__3_/chany_bottom_in[8] +set_disable_timing cby_4__3_/chany_top_in[8] set_disable_timing cby_4__3_/chany_bottom_in[9] set_disable_timing cby_4__3_/chany_top_in[9] set_disable_timing cby_4__3_/chany_bottom_out[0] @@ -3171,7 +3171,9 @@ set_disable_timing cby_4__3_/chany_top_out[5] set_disable_timing cby_4__3_/chany_bottom_out[6] set_disable_timing cby_4__3_/chany_top_out[6] set_disable_timing cby_4__3_/chany_bottom_out[7] +set_disable_timing cby_4__3_/chany_top_out[7] set_disable_timing cby_4__3_/chany_bottom_out[8] +set_disable_timing cby_4__3_/chany_top_out[8] set_disable_timing cby_4__3_/chany_bottom_out[9] set_disable_timing cby_4__3_/chany_top_out[9] set_disable_timing cby_4__3_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] @@ -3241,6 +3243,7 @@ set_disable_timing cby_4__4_/chany_top_in[4] set_disable_timing cby_4__4_/chany_bottom_in[5] set_disable_timing cby_4__4_/chany_top_in[5] set_disable_timing cby_4__4_/chany_bottom_in[6] +set_disable_timing cby_4__4_/chany_top_in[6] set_disable_timing cby_4__4_/chany_bottom_in[7] set_disable_timing cby_4__4_/chany_top_in[7] set_disable_timing cby_4__4_/chany_bottom_in[8] @@ -3260,6 +3263,7 @@ set_disable_timing cby_4__4_/chany_top_out[4] set_disable_timing cby_4__4_/chany_bottom_out[5] set_disable_timing cby_4__4_/chany_top_out[5] set_disable_timing cby_4__4_/chany_bottom_out[6] +set_disable_timing cby_4__4_/chany_top_out[6] set_disable_timing cby_4__4_/chany_bottom_out[7] set_disable_timing cby_4__4_/chany_top_out[7] set_disable_timing cby_4__4_/chany_bottom_out[8] @@ -3598,6 +3602,7 @@ set_disable_timing sb_0__2_/chanx_right_in[0] set_disable_timing sb_0__2_/chanx_right_out[1] set_disable_timing sb_0__2_/chanx_right_in[1] set_disable_timing sb_0__2_/chanx_right_out[2] +set_disable_timing sb_0__2_/chanx_right_in[2] set_disable_timing sb_0__2_/chanx_right_out[3] set_disable_timing sb_0__2_/chanx_right_in[3] set_disable_timing sb_0__2_/chanx_right_out[4] @@ -3607,6 +3612,7 @@ set_disable_timing sb_0__2_/chanx_right_in[5] set_disable_timing sb_0__2_/chanx_right_out[6] set_disable_timing sb_0__2_/chanx_right_in[6] set_disable_timing sb_0__2_/chanx_right_out[7] +set_disable_timing sb_0__2_/chanx_right_in[7] set_disable_timing sb_0__2_/chanx_right_out[8] set_disable_timing sb_0__2_/chanx_right_in[8] set_disable_timing sb_0__2_/chanx_right_out[9] @@ -4019,7 +4025,6 @@ set_disable_timing sb_1__0_/chanx_right_in[7] set_disable_timing sb_1__0_/chanx_right_out[8] set_disable_timing sb_1__0_/chanx_right_in[8] set_disable_timing sb_1__0_/chanx_right_out[9] -set_disable_timing sb_1__0_/chanx_right_in[9] set_disable_timing sb_1__0_/chanx_left_in[0] set_disable_timing sb_1__0_/chanx_left_out[0] set_disable_timing sb_1__0_/chanx_left_in[1] @@ -4160,6 +4165,7 @@ set_disable_timing sb_1__1_/chanx_right_in[1] set_disable_timing sb_1__1_/chanx_right_out[2] set_disable_timing sb_1__1_/chanx_right_in[2] set_disable_timing sb_1__1_/chanx_right_out[3] +set_disable_timing sb_1__1_/chanx_right_in[3] set_disable_timing sb_1__1_/chanx_right_out[4] set_disable_timing sb_1__1_/chanx_right_in[4] set_disable_timing sb_1__1_/chanx_right_out[5] @@ -4339,6 +4345,7 @@ set_disable_timing sb_1__1_/mux_bottom_track_9/in[9] ################################################## # Disable timing for Switch block sb_1__1_ ################################################## +set_disable_timing sb_1__2_/chany_top_out[0] set_disable_timing sb_1__2_/chany_top_in[0] set_disable_timing sb_1__2_/chany_top_out[1] set_disable_timing sb_1__2_/chany_top_in[1] @@ -4361,6 +4368,7 @@ set_disable_timing sb_1__2_/chany_top_in[9] set_disable_timing sb_1__2_/chanx_right_out[0] set_disable_timing sb_1__2_/chanx_right_in[0] set_disable_timing sb_1__2_/chanx_right_out[1] +set_disable_timing sb_1__2_/chanx_right_in[1] set_disable_timing sb_1__2_/chanx_right_out[2] set_disable_timing sb_1__2_/chanx_right_in[2] set_disable_timing sb_1__2_/chanx_right_out[3] @@ -4370,12 +4378,12 @@ set_disable_timing sb_1__2_/chanx_right_in[4] set_disable_timing sb_1__2_/chanx_right_out[5] set_disable_timing sb_1__2_/chanx_right_in[5] set_disable_timing sb_1__2_/chanx_right_out[6] +set_disable_timing sb_1__2_/chanx_right_in[6] set_disable_timing sb_1__2_/chanx_right_out[7] set_disable_timing sb_1__2_/chanx_right_in[7] set_disable_timing sb_1__2_/chanx_right_out[8] set_disable_timing sb_1__2_/chanx_right_in[8] set_disable_timing sb_1__2_/chanx_right_out[9] -set_disable_timing sb_1__2_/chanx_right_in[9] set_disable_timing sb_1__2_/chany_bottom_in[0] set_disable_timing sb_1__2_/chany_bottom_out[0] set_disable_timing sb_1__2_/chany_bottom_in[1] @@ -4401,6 +4409,7 @@ set_disable_timing sb_1__2_/chanx_left_out[0] set_disable_timing sb_1__2_/chanx_left_in[1] set_disable_timing sb_1__2_/chanx_left_out[1] set_disable_timing sb_1__2_/chanx_left_in[2] +set_disable_timing sb_1__2_/chanx_left_out[2] set_disable_timing sb_1__2_/chanx_left_in[3] set_disable_timing sb_1__2_/chanx_left_out[3] set_disable_timing sb_1__2_/chanx_left_in[4] @@ -4410,6 +4419,7 @@ set_disable_timing sb_1__2_/chanx_left_out[5] set_disable_timing sb_1__2_/chanx_left_in[6] set_disable_timing sb_1__2_/chanx_left_out[6] set_disable_timing sb_1__2_/chanx_left_in[7] +set_disable_timing sb_1__2_/chanx_left_out[7] set_disable_timing sb_1__2_/chanx_left_in[8] set_disable_timing sb_1__2_/chanx_left_out[8] set_disable_timing sb_1__2_/chanx_left_in[9] @@ -4460,6 +4470,7 @@ set_disable_timing sb_1__2_/mux_left_track_9/in[2] set_disable_timing sb_1__2_/mux_top_track_16/in[0] set_disable_timing sb_1__2_/mux_bottom_track_9/in[2] set_disable_timing sb_1__2_/mux_left_track_1/in[4] +set_disable_timing sb_1__2_/mux_top_track_0/in[1] set_disable_timing sb_1__2_/mux_bottom_track_1/in[3] set_disable_timing sb_1__2_/mux_left_track_9/in[3] set_disable_timing sb_1__2_/mux_top_track_8/in[1] @@ -4542,12 +4553,12 @@ set_disable_timing sb_1__2_/mux_bottom_track_9/in[9] ################################################## set_disable_timing sb_1__3_/chany_top_out[0] set_disable_timing sb_1__3_/chany_top_in[0] +set_disable_timing sb_1__3_/chany_top_out[1] set_disable_timing sb_1__3_/chany_top_in[1] set_disable_timing sb_1__3_/chany_top_out[2] set_disable_timing sb_1__3_/chany_top_in[2] set_disable_timing sb_1__3_/chany_top_out[3] set_disable_timing sb_1__3_/chany_top_in[3] -set_disable_timing sb_1__3_/chany_top_out[4] set_disable_timing sb_1__3_/chany_top_in[4] set_disable_timing sb_1__3_/chany_top_out[5] set_disable_timing sb_1__3_/chany_top_in[5] @@ -4574,10 +4585,11 @@ set_disable_timing sb_1__3_/chanx_right_in[5] set_disable_timing sb_1__3_/chanx_right_out[6] set_disable_timing sb_1__3_/chanx_right_in[6] set_disable_timing sb_1__3_/chanx_right_out[7] +set_disable_timing sb_1__3_/chanx_right_in[7] set_disable_timing sb_1__3_/chanx_right_out[8] set_disable_timing sb_1__3_/chanx_right_in[8] set_disable_timing sb_1__3_/chanx_right_out[9] -set_disable_timing sb_1__3_/chanx_right_in[9] +set_disable_timing sb_1__3_/chany_bottom_in[0] set_disable_timing sb_1__3_/chany_bottom_out[0] set_disable_timing sb_1__3_/chany_bottom_in[1] set_disable_timing sb_1__3_/chany_bottom_out[1] @@ -4685,7 +4697,6 @@ set_disable_timing sb_1__3_/mux_bottom_track_1/in[5] set_disable_timing sb_1__3_/mux_top_track_16/in[3] set_disable_timing sb_1__3_/mux_bottom_track_9/in[5] set_disable_timing sb_1__3_/mux_left_track_1/in[6] -set_disable_timing sb_1__3_/mux_top_track_8/in[3] set_disable_timing sb_1__3_/mux_bottom_track_17/in[4] set_disable_timing sb_1__3_/mux_top_track_0/in[4] set_disable_timing sb_1__3_/mux_right_track_8/in[5] @@ -4765,12 +4776,12 @@ set_disable_timing sb_1__4_/chanx_right_out[9] set_disable_timing sb_1__4_/chanx_right_in[9] set_disable_timing sb_1__4_/chany_bottom_in[0] set_disable_timing sb_1__4_/chany_bottom_out[0] +set_disable_timing sb_1__4_/chany_bottom_in[1] set_disable_timing sb_1__4_/chany_bottom_out[1] set_disable_timing sb_1__4_/chany_bottom_in[2] set_disable_timing sb_1__4_/chany_bottom_out[2] set_disable_timing sb_1__4_/chany_bottom_in[3] set_disable_timing sb_1__4_/chany_bottom_out[3] -set_disable_timing sb_1__4_/chany_bottom_in[4] set_disable_timing sb_1__4_/chany_bottom_out[4] set_disable_timing sb_1__4_/chany_bottom_in[5] set_disable_timing sb_1__4_/chany_bottom_out[5] @@ -4861,12 +4872,12 @@ set_disable_timing sb_1__4_/mux_left_track_1/in[2] set_disable_timing sb_1__4_/mux_bottom_track_13/in[1] set_disable_timing sb_1__4_/mux_right_track_8/in[3] set_disable_timing sb_1__4_/mux_left_track_9/in[2] +set_disable_timing sb_1__4_/mux_right_track_0/in[3] set_disable_timing sb_1__4_/mux_left_track_17/in[2] set_disable_timing sb_1__4_/mux_right_track_16/in[3] set_disable_timing sb_1__4_/mux_left_track_1/in[3] set_disable_timing sb_1__4_/mux_right_track_8/in[4] set_disable_timing sb_1__4_/mux_left_track_9/in[3] -set_disable_timing sb_1__4_/mux_right_track_0/in[4] set_disable_timing sb_1__4_/mux_left_track_17/in[3] set_disable_timing sb_1__4_/mux_right_track_16/in[4] set_disable_timing sb_1__4_/mux_left_track_1/in[4] @@ -4908,7 +4919,6 @@ set_disable_timing sb_2__0_/chany_top_out[3] set_disable_timing sb_2__0_/chany_top_in[3] set_disable_timing sb_2__0_/chany_top_out[4] set_disable_timing sb_2__0_/chany_top_in[4] -set_disable_timing sb_2__0_/chany_top_out[5] set_disable_timing sb_2__0_/chany_top_in[5] set_disable_timing sb_2__0_/chany_top_out[6] set_disable_timing sb_2__0_/chany_top_in[6] @@ -4918,7 +4928,6 @@ set_disable_timing sb_2__0_/chany_top_out[8] set_disable_timing sb_2__0_/chany_top_in[8] set_disable_timing sb_2__0_/chany_top_out[9] set_disable_timing sb_2__0_/chany_top_in[9] -set_disable_timing sb_2__0_/chanx_right_out[0] set_disable_timing sb_2__0_/chanx_right_in[0] set_disable_timing sb_2__0_/chanx_right_out[1] set_disable_timing sb_2__0_/chanx_right_in[1] @@ -4935,7 +4944,6 @@ set_disable_timing sb_2__0_/chanx_right_in[6] set_disable_timing sb_2__0_/chanx_right_out[7] set_disable_timing sb_2__0_/chanx_right_in[7] set_disable_timing sb_2__0_/chanx_right_out[8] -set_disable_timing sb_2__0_/chanx_right_in[8] set_disable_timing sb_2__0_/chanx_right_out[9] set_disable_timing sb_2__0_/chanx_right_in[9] set_disable_timing sb_2__0_/chanx_left_in[0] @@ -4957,18 +4965,15 @@ set_disable_timing sb_2__0_/chanx_left_out[7] set_disable_timing sb_2__0_/chanx_left_in[8] set_disable_timing sb_2__0_/chanx_left_out[8] set_disable_timing sb_2__0_/chanx_left_in[9] -set_disable_timing sb_2__0_/chanx_left_out[9] set_disable_timing sb_2__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_2__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_2__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_2__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] @@ -4983,7 +4988,6 @@ set_disable_timing sb_2__0_/mux_top_track_2/in[0] set_disable_timing sb_2__0_/mux_right_track_0/in[3] set_disable_timing sb_2__0_/mux_right_track_8/in[4] set_disable_timing sb_2__0_/mux_right_track_16/in[3] -set_disable_timing sb_2__0_/mux_right_track_0/in[4] set_disable_timing sb_2__0_/mux_right_track_8/in[5] set_disable_timing sb_2__0_/mux_right_track_16/in[4] set_disable_timing sb_2__0_/mux_right_track_0/in[5] @@ -5030,7 +5034,6 @@ set_disable_timing sb_2__0_/mux_left_track_9/in[4] set_disable_timing sb_2__0_/mux_top_track_8/in[0] set_disable_timing sb_2__0_/mux_left_track_17/in[4] set_disable_timing sb_2__0_/mux_top_track_0/in[2] -set_disable_timing sb_2__0_/mux_top_track_10/in[0] set_disable_timing sb_2__0_/mux_left_track_1/in[6] set_disable_timing sb_2__0_/mux_top_track_2/in[2] set_disable_timing sb_2__0_/mux_top_track_0/in[3] @@ -5063,7 +5066,6 @@ set_disable_timing sb_2__1_/chany_top_out[4] set_disable_timing sb_2__1_/chany_top_in[4] set_disable_timing sb_2__1_/chany_top_out[5] set_disable_timing sb_2__1_/chany_top_in[5] -set_disable_timing sb_2__1_/chany_top_out[6] set_disable_timing sb_2__1_/chany_top_in[6] set_disable_timing sb_2__1_/chany_top_out[7] set_disable_timing sb_2__1_/chany_top_in[7] @@ -5071,11 +5073,11 @@ set_disable_timing sb_2__1_/chany_top_out[8] set_disable_timing sb_2__1_/chany_top_in[8] set_disable_timing sb_2__1_/chany_top_out[9] set_disable_timing sb_2__1_/chany_top_in[9] -set_disable_timing sb_2__1_/chanx_right_out[0] set_disable_timing sb_2__1_/chanx_right_in[0] set_disable_timing sb_2__1_/chanx_right_out[1] set_disable_timing sb_2__1_/chanx_right_in[1] set_disable_timing sb_2__1_/chanx_right_out[2] +set_disable_timing sb_2__1_/chanx_right_in[2] set_disable_timing sb_2__1_/chanx_right_out[3] set_disable_timing sb_2__1_/chanx_right_in[3] set_disable_timing sb_2__1_/chanx_right_out[4] @@ -5100,7 +5102,6 @@ set_disable_timing sb_2__1_/chany_bottom_in[3] set_disable_timing sb_2__1_/chany_bottom_out[3] set_disable_timing sb_2__1_/chany_bottom_in[4] set_disable_timing sb_2__1_/chany_bottom_out[4] -set_disable_timing sb_2__1_/chany_bottom_in[5] set_disable_timing sb_2__1_/chany_bottom_out[5] set_disable_timing sb_2__1_/chany_bottom_in[6] set_disable_timing sb_2__1_/chany_bottom_out[6] @@ -5117,6 +5118,7 @@ set_disable_timing sb_2__1_/chanx_left_out[1] set_disable_timing sb_2__1_/chanx_left_in[2] set_disable_timing sb_2__1_/chanx_left_out[2] set_disable_timing sb_2__1_/chanx_left_in[3] +set_disable_timing sb_2__1_/chanx_left_out[3] set_disable_timing sb_2__1_/chanx_left_in[4] set_disable_timing sb_2__1_/chanx_left_out[4] set_disable_timing sb_2__1_/chanx_left_in[5] @@ -5214,7 +5216,6 @@ set_disable_timing sb_2__1_/mux_top_track_0/in[5] set_disable_timing sb_2__1_/mux_right_track_8/in[7] set_disable_timing sb_2__1_/mux_left_track_9/in[7] set_disable_timing sb_2__1_/mux_top_track_8/in[5] -set_disable_timing sb_2__1_/mux_right_track_0/in[5] set_disable_timing sb_2__1_/mux_left_track_17/in[6] set_disable_timing sb_2__1_/mux_top_track_16/in[5] set_disable_timing sb_2__1_/mux_right_track_16/in[4] @@ -5270,13 +5271,13 @@ set_disable_timing sb_2__2_/chany_top_out[5] set_disable_timing sb_2__2_/chany_top_in[5] set_disable_timing sb_2__2_/chany_top_out[6] set_disable_timing sb_2__2_/chany_top_in[6] -set_disable_timing sb_2__2_/chany_top_out[7] set_disable_timing sb_2__2_/chany_top_in[7] set_disable_timing sb_2__2_/chany_top_out[8] set_disable_timing sb_2__2_/chany_top_in[8] set_disable_timing sb_2__2_/chany_top_out[9] set_disable_timing sb_2__2_/chany_top_in[9] set_disable_timing sb_2__2_/chanx_right_out[0] +set_disable_timing sb_2__2_/chanx_right_in[0] set_disable_timing sb_2__2_/chanx_right_out[1] set_disable_timing sb_2__2_/chanx_right_in[1] set_disable_timing sb_2__2_/chanx_right_out[2] @@ -5286,12 +5287,12 @@ set_disable_timing sb_2__2_/chanx_right_in[3] set_disable_timing sb_2__2_/chanx_right_out[4] set_disable_timing sb_2__2_/chanx_right_in[4] set_disable_timing sb_2__2_/chanx_right_out[5] +set_disable_timing sb_2__2_/chanx_right_in[5] set_disable_timing sb_2__2_/chanx_right_out[6] set_disable_timing sb_2__2_/chanx_right_in[6] set_disable_timing sb_2__2_/chanx_right_out[7] set_disable_timing sb_2__2_/chanx_right_in[7] set_disable_timing sb_2__2_/chanx_right_out[8] -set_disable_timing sb_2__2_/chanx_right_in[8] set_disable_timing sb_2__2_/chanx_right_out[9] set_disable_timing sb_2__2_/chanx_right_in[9] set_disable_timing sb_2__2_/chany_bottom_in[0] @@ -5306,7 +5307,6 @@ set_disable_timing sb_2__2_/chany_bottom_in[4] set_disable_timing sb_2__2_/chany_bottom_out[4] set_disable_timing sb_2__2_/chany_bottom_in[5] set_disable_timing sb_2__2_/chany_bottom_out[5] -set_disable_timing sb_2__2_/chany_bottom_in[6] set_disable_timing sb_2__2_/chany_bottom_out[6] set_disable_timing sb_2__2_/chany_bottom_in[7] set_disable_timing sb_2__2_/chany_bottom_out[7] @@ -5317,6 +5317,7 @@ set_disable_timing sb_2__2_/chany_bottom_out[9] set_disable_timing sb_2__2_/chanx_left_in[0] set_disable_timing sb_2__2_/chanx_left_out[0] set_disable_timing sb_2__2_/chanx_left_in[1] +set_disable_timing sb_2__2_/chanx_left_out[1] set_disable_timing sb_2__2_/chanx_left_in[2] set_disable_timing sb_2__2_/chanx_left_out[2] set_disable_timing sb_2__2_/chanx_left_in[3] @@ -5326,12 +5327,12 @@ set_disable_timing sb_2__2_/chanx_left_out[4] set_disable_timing sb_2__2_/chanx_left_in[5] set_disable_timing sb_2__2_/chanx_left_out[5] set_disable_timing sb_2__2_/chanx_left_in[6] +set_disable_timing sb_2__2_/chanx_left_out[6] set_disable_timing sb_2__2_/chanx_left_in[7] set_disable_timing sb_2__2_/chanx_left_out[7] set_disable_timing sb_2__2_/chanx_left_in[8] set_disable_timing sb_2__2_/chanx_left_out[8] set_disable_timing sb_2__2_/chanx_left_in[9] -set_disable_timing sb_2__2_/chanx_left_out[9] set_disable_timing sb_2__2_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_2__2_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_2__2_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] @@ -5492,10 +5493,10 @@ set_disable_timing sb_2__3_/chanx_right_in[4] set_disable_timing sb_2__3_/chanx_right_out[5] set_disable_timing sb_2__3_/chanx_right_in[5] set_disable_timing sb_2__3_/chanx_right_out[6] +set_disable_timing sb_2__3_/chanx_right_in[6] set_disable_timing sb_2__3_/chanx_right_out[7] set_disable_timing sb_2__3_/chanx_right_in[7] set_disable_timing sb_2__3_/chanx_right_out[8] -set_disable_timing sb_2__3_/chanx_right_in[8] set_disable_timing sb_2__3_/chanx_right_out[9] set_disable_timing sb_2__3_/chanx_right_in[9] set_disable_timing sb_2__3_/chany_bottom_in[0] @@ -5512,7 +5513,6 @@ set_disable_timing sb_2__3_/chany_bottom_in[5] set_disable_timing sb_2__3_/chany_bottom_out[5] set_disable_timing sb_2__3_/chany_bottom_in[6] set_disable_timing sb_2__3_/chany_bottom_out[6] -set_disable_timing sb_2__3_/chany_bottom_in[7] set_disable_timing sb_2__3_/chany_bottom_out[7] set_disable_timing sb_2__3_/chany_bottom_in[8] set_disable_timing sb_2__3_/chany_bottom_out[8] @@ -5533,10 +5533,10 @@ set_disable_timing sb_2__3_/chanx_left_out[5] set_disable_timing sb_2__3_/chanx_left_in[6] set_disable_timing sb_2__3_/chanx_left_out[6] set_disable_timing sb_2__3_/chanx_left_in[7] +set_disable_timing sb_2__3_/chanx_left_out[7] set_disable_timing sb_2__3_/chanx_left_in[8] set_disable_timing sb_2__3_/chanx_left_out[8] set_disable_timing sb_2__3_/chanx_left_in[9] -set_disable_timing sb_2__3_/chanx_left_out[9] set_disable_timing sb_2__3_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_2__3_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_2__3_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] @@ -5819,7 +5819,6 @@ set_disable_timing sb_2__4_/mux_bottom_track_3/in[2] ################################################## # Disable timing for Switch block sb_1__0_ ################################################## -set_disable_timing sb_3__0_/chany_top_out[0] set_disable_timing sb_3__0_/chany_top_in[0] set_disable_timing sb_3__0_/chany_top_out[1] set_disable_timing sb_3__0_/chany_top_in[1] @@ -5841,7 +5840,6 @@ set_disable_timing sb_3__0_/chany_top_out[9] set_disable_timing sb_3__0_/chany_top_in[9] set_disable_timing sb_3__0_/chanx_right_out[0] set_disable_timing sb_3__0_/chanx_right_in[0] -set_disable_timing sb_3__0_/chanx_right_out[1] set_disable_timing sb_3__0_/chanx_right_in[1] set_disable_timing sb_3__0_/chanx_right_out[2] set_disable_timing sb_3__0_/chanx_right_in[2] @@ -5859,7 +5857,6 @@ set_disable_timing sb_3__0_/chanx_right_out[8] set_disable_timing sb_3__0_/chanx_right_in[8] set_disable_timing sb_3__0_/chanx_right_out[9] set_disable_timing sb_3__0_/chanx_right_in[9] -set_disable_timing sb_3__0_/chanx_left_in[0] set_disable_timing sb_3__0_/chanx_left_out[0] set_disable_timing sb_3__0_/chanx_left_in[1] set_disable_timing sb_3__0_/chanx_left_out[1] @@ -5876,7 +5873,6 @@ set_disable_timing sb_3__0_/chanx_left_out[6] set_disable_timing sb_3__0_/chanx_left_in[7] set_disable_timing sb_3__0_/chanx_left_out[7] set_disable_timing sb_3__0_/chanx_left_in[8] -set_disable_timing sb_3__0_/chanx_left_out[8] set_disable_timing sb_3__0_/chanx_left_in[9] set_disable_timing sb_3__0_/chanx_left_out[9] set_disable_timing sb_3__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] @@ -5893,12 +5889,10 @@ set_disable_timing sb_3__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pi set_disable_timing sb_3__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_3__0_/mux_top_track_0/in[0] set_disable_timing sb_3__0_/mux_top_track_2/in[0] set_disable_timing sb_3__0_/mux_right_track_0/in[3] @@ -5918,7 +5912,6 @@ set_disable_timing sb_3__0_/mux_left_track_9/in[6] set_disable_timing sb_3__0_/mux_left_track_17/in[6] set_disable_timing sb_3__0_/mux_left_track_1/in[9] set_disable_timing sb_3__0_/mux_left_track_9/in[7] -set_disable_timing sb_3__0_/mux_left_track_17/in[7] set_disable_timing sb_3__0_/mux_right_track_8/in[0] set_disable_timing sb_3__0_/mux_left_track_1/in[0] set_disable_timing sb_3__0_/mux_right_track_16/in[0] @@ -5954,7 +5947,6 @@ set_disable_timing sb_3__0_/mux_top_track_0/in[2] set_disable_timing sb_3__0_/mux_top_track_10/in[0] set_disable_timing sb_3__0_/mux_left_track_1/in[6] set_disable_timing sb_3__0_/mux_top_track_2/in[2] -set_disable_timing sb_3__0_/mux_top_track_0/in[3] set_disable_timing sb_3__0_/mux_right_track_0/in[6] set_disable_timing sb_3__0_/mux_top_track_18/in[2] set_disable_timing sb_3__0_/mux_right_track_8/in[7] @@ -5973,7 +5965,6 @@ set_disable_timing sb_3__0_/mux_top_track_16/in[1] # Disable timing for Switch block sb_1__1_ ################################################## set_disable_timing sb_3__1_/chany_top_in[0] -set_disable_timing sb_3__1_/chany_top_out[1] set_disable_timing sb_3__1_/chany_top_in[1] set_disable_timing sb_3__1_/chany_top_out[2] set_disable_timing sb_3__1_/chany_top_in[2] @@ -5993,7 +5984,7 @@ set_disable_timing sb_3__1_/chany_top_out[9] set_disable_timing sb_3__1_/chany_top_in[9] set_disable_timing sb_3__1_/chanx_right_out[0] set_disable_timing sb_3__1_/chanx_right_in[0] -set_disable_timing sb_3__1_/chanx_right_out[1] +set_disable_timing sb_3__1_/chanx_right_in[1] set_disable_timing sb_3__1_/chanx_right_out[2] set_disable_timing sb_3__1_/chanx_right_in[2] set_disable_timing sb_3__1_/chanx_right_out[3] @@ -6010,7 +6001,6 @@ set_disable_timing sb_3__1_/chanx_right_out[8] set_disable_timing sb_3__1_/chanx_right_in[8] set_disable_timing sb_3__1_/chanx_right_out[9] set_disable_timing sb_3__1_/chanx_right_in[9] -set_disable_timing sb_3__1_/chany_bottom_in[0] set_disable_timing sb_3__1_/chany_bottom_out[0] set_disable_timing sb_3__1_/chany_bottom_in[1] set_disable_timing sb_3__1_/chany_bottom_out[1] @@ -6030,11 +6020,11 @@ set_disable_timing sb_3__1_/chany_bottom_in[8] set_disable_timing sb_3__1_/chany_bottom_out[8] set_disable_timing sb_3__1_/chany_bottom_in[9] set_disable_timing sb_3__1_/chany_bottom_out[9] -set_disable_timing sb_3__1_/chanx_left_in[0] set_disable_timing sb_3__1_/chanx_left_out[0] set_disable_timing sb_3__1_/chanx_left_in[1] set_disable_timing sb_3__1_/chanx_left_out[1] set_disable_timing sb_3__1_/chanx_left_in[2] +set_disable_timing sb_3__1_/chanx_left_out[2] set_disable_timing sb_3__1_/chanx_left_in[3] set_disable_timing sb_3__1_/chanx_left_out[3] set_disable_timing sb_3__1_/chanx_left_in[4] @@ -6049,7 +6039,6 @@ set_disable_timing sb_3__1_/chanx_left_in[8] set_disable_timing sb_3__1_/chanx_left_out[8] set_disable_timing sb_3__1_/chanx_left_in[9] set_disable_timing sb_3__1_/chanx_left_out[9] -set_disable_timing sb_3__1_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_3__1_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_3__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] @@ -6057,7 +6046,6 @@ set_disable_timing sb_3__1_/bottom_right_grid_left_width_0_height_0_subtile_0__p set_disable_timing sb_3__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_3__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -set_disable_timing sb_3__1_/mux_top_track_0/in[0] set_disable_timing sb_3__1_/mux_top_track_8/in[0] set_disable_timing sb_3__1_/mux_right_track_0/in[3] set_disable_timing sb_3__1_/mux_right_track_8/in[4] @@ -6095,6 +6083,7 @@ set_disable_timing sb_3__1_/mux_left_track_9/in[2] set_disable_timing sb_3__1_/mux_top_track_16/in[0] set_disable_timing sb_3__1_/mux_bottom_track_9/in[2] set_disable_timing sb_3__1_/mux_left_track_1/in[4] +set_disable_timing sb_3__1_/mux_top_track_0/in[1] set_disable_timing sb_3__1_/mux_bottom_track_1/in[3] set_disable_timing sb_3__1_/mux_left_track_9/in[3] set_disable_timing sb_3__1_/mux_top_track_8/in[1] @@ -6178,7 +6167,6 @@ set_disable_timing sb_3__1_/mux_bottom_track_9/in[9] set_disable_timing sb_3__2_/chany_top_out[0] set_disable_timing sb_3__2_/chany_top_in[0] set_disable_timing sb_3__2_/chany_top_in[1] -set_disable_timing sb_3__2_/chany_top_out[2] set_disable_timing sb_3__2_/chany_top_in[2] set_disable_timing sb_3__2_/chany_top_out[3] set_disable_timing sb_3__2_/chany_top_in[3] @@ -6203,6 +6191,7 @@ set_disable_timing sb_3__2_/chanx_right_in[2] set_disable_timing sb_3__2_/chanx_right_out[3] set_disable_timing sb_3__2_/chanx_right_in[3] set_disable_timing sb_3__2_/chanx_right_out[4] +set_disable_timing sb_3__2_/chanx_right_in[4] set_disable_timing sb_3__2_/chanx_right_out[5] set_disable_timing sb_3__2_/chanx_right_in[5] set_disable_timing sb_3__2_/chanx_right_out[6] @@ -6214,7 +6203,6 @@ set_disable_timing sb_3__2_/chanx_right_in[8] set_disable_timing sb_3__2_/chanx_right_out[9] set_disable_timing sb_3__2_/chanx_right_in[9] set_disable_timing sb_3__2_/chany_bottom_out[0] -set_disable_timing sb_3__2_/chany_bottom_in[1] set_disable_timing sb_3__2_/chany_bottom_out[1] set_disable_timing sb_3__2_/chany_bottom_in[2] set_disable_timing sb_3__2_/chany_bottom_out[2] @@ -6233,6 +6221,7 @@ set_disable_timing sb_3__2_/chany_bottom_out[8] set_disable_timing sb_3__2_/chany_bottom_in[9] set_disable_timing sb_3__2_/chany_bottom_out[9] set_disable_timing sb_3__2_/chanx_left_in[0] +set_disable_timing sb_3__2_/chanx_left_out[0] set_disable_timing sb_3__2_/chanx_left_in[1] set_disable_timing sb_3__2_/chanx_left_out[1] set_disable_timing sb_3__2_/chanx_left_in[2] @@ -6242,12 +6231,12 @@ set_disable_timing sb_3__2_/chanx_left_out[3] set_disable_timing sb_3__2_/chanx_left_in[4] set_disable_timing sb_3__2_/chanx_left_out[4] set_disable_timing sb_3__2_/chanx_left_in[5] +set_disable_timing sb_3__2_/chanx_left_out[5] set_disable_timing sb_3__2_/chanx_left_in[6] set_disable_timing sb_3__2_/chanx_left_out[6] set_disable_timing sb_3__2_/chanx_left_in[7] set_disable_timing sb_3__2_/chanx_left_out[7] set_disable_timing sb_3__2_/chanx_left_in[8] -set_disable_timing sb_3__2_/chanx_left_out[8] set_disable_timing sb_3__2_/chanx_left_in[9] set_disable_timing sb_3__2_/chanx_left_out[9] set_disable_timing sb_3__2_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] @@ -6255,7 +6244,6 @@ set_disable_timing sb_3__2_/top_right_grid_left_width_0_height_0_subtile_0__pin_ set_disable_timing sb_3__2_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__2_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] set_disable_timing sb_3__2_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -set_disable_timing sb_3__2_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_3__2_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__2_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] set_disable_timing sb_3__2_/mux_top_track_0/in[0] @@ -6306,6 +6294,7 @@ set_disable_timing sb_3__2_/mux_top_track_16/in[1] set_disable_timing sb_3__2_/mux_bottom_track_9/in[3] set_disable_timing sb_3__2_/mux_top_track_16/in[2] set_disable_timing sb_3__2_/mux_bottom_track_9/in[4] +set_disable_timing sb_3__2_/mux_left_track_1/in[5] set_disable_timing sb_3__2_/mux_top_track_0/in[2] set_disable_timing sb_3__2_/mux_bottom_track_1/in[4] set_disable_timing sb_3__2_/mux_left_track_9/in[4] @@ -6324,7 +6313,6 @@ set_disable_timing sb_3__2_/mux_right_track_8/in[5] set_disable_timing sb_3__2_/mux_left_track_9/in[5] set_disable_timing sb_3__2_/mux_top_track_8/in[4] set_disable_timing sb_3__2_/mux_right_track_0/in[4] -set_disable_timing sb_3__2_/mux_left_track_17/in[5] set_disable_timing sb_3__2_/mux_top_track_16/in[4] set_disable_timing sb_3__2_/mux_right_track_16/in[3] set_disable_timing sb_3__2_/mux_left_track_1/in[7] @@ -6381,7 +6369,6 @@ set_disable_timing sb_3__3_/chany_top_in[0] set_disable_timing sb_3__3_/chany_top_out[1] set_disable_timing sb_3__3_/chany_top_in[1] set_disable_timing sb_3__3_/chany_top_in[2] -set_disable_timing sb_3__3_/chany_top_out[3] set_disable_timing sb_3__3_/chany_top_in[3] set_disable_timing sb_3__3_/chany_top_out[4] set_disable_timing sb_3__3_/chany_top_in[4] @@ -6406,6 +6393,7 @@ set_disable_timing sb_3__3_/chanx_right_in[3] set_disable_timing sb_3__3_/chanx_right_out[4] set_disable_timing sb_3__3_/chanx_right_in[4] set_disable_timing sb_3__3_/chanx_right_out[5] +set_disable_timing sb_3__3_/chanx_right_in[5] set_disable_timing sb_3__3_/chanx_right_out[6] set_disable_timing sb_3__3_/chanx_right_in[6] set_disable_timing sb_3__3_/chanx_right_out[7] @@ -6417,7 +6405,6 @@ set_disable_timing sb_3__3_/chanx_right_in[9] set_disable_timing sb_3__3_/chany_bottom_in[0] set_disable_timing sb_3__3_/chany_bottom_out[0] set_disable_timing sb_3__3_/chany_bottom_out[1] -set_disable_timing sb_3__3_/chany_bottom_in[2] set_disable_timing sb_3__3_/chany_bottom_out[2] set_disable_timing sb_3__3_/chany_bottom_in[3] set_disable_timing sb_3__3_/chany_bottom_out[3] @@ -6446,10 +6433,10 @@ set_disable_timing sb_3__3_/chanx_left_out[4] set_disable_timing sb_3__3_/chanx_left_in[5] set_disable_timing sb_3__3_/chanx_left_out[5] set_disable_timing sb_3__3_/chanx_left_in[6] +set_disable_timing sb_3__3_/chanx_left_out[6] set_disable_timing sb_3__3_/chanx_left_in[7] set_disable_timing sb_3__3_/chanx_left_out[7] set_disable_timing sb_3__3_/chanx_left_in[8] -set_disable_timing sb_3__3_/chanx_left_out[8] set_disable_timing sb_3__3_/chanx_left_in[9] set_disable_timing sb_3__3_/chanx_left_out[9] set_disable_timing sb_3__3_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] @@ -6527,7 +6514,6 @@ set_disable_timing sb_3__3_/mux_right_track_8/in[5] set_disable_timing sb_3__3_/mux_left_track_9/in[5] set_disable_timing sb_3__3_/mux_top_track_8/in[4] set_disable_timing sb_3__3_/mux_right_track_0/in[4] -set_disable_timing sb_3__3_/mux_left_track_17/in[5] set_disable_timing sb_3__3_/mux_top_track_16/in[4] set_disable_timing sb_3__3_/mux_right_track_16/in[3] set_disable_timing sb_3__3_/mux_left_track_1/in[7] @@ -6603,7 +6589,6 @@ set_disable_timing sb_3__4_/chany_bottom_out[0] set_disable_timing sb_3__4_/chany_bottom_in[1] set_disable_timing sb_3__4_/chany_bottom_out[1] set_disable_timing sb_3__4_/chany_bottom_out[2] -set_disable_timing sb_3__4_/chany_bottom_in[3] set_disable_timing sb_3__4_/chany_bottom_out[3] set_disable_timing sb_3__4_/chany_bottom_in[4] set_disable_timing sb_3__4_/chany_bottom_out[4] @@ -6739,6 +6724,7 @@ set_disable_timing sb_4__0_/chany_top_out[1] set_disable_timing sb_4__0_/chany_top_in[1] set_disable_timing sb_4__0_/chany_top_out[2] set_disable_timing sb_4__0_/chany_top_in[2] +set_disable_timing sb_4__0_/chany_top_out[3] set_disable_timing sb_4__0_/chany_top_in[3] set_disable_timing sb_4__0_/chany_top_out[4] set_disable_timing sb_4__0_/chany_top_in[4] @@ -6754,7 +6740,6 @@ set_disable_timing sb_4__0_/chany_top_out[9] set_disable_timing sb_4__0_/chany_top_in[9] set_disable_timing sb_4__0_/chanx_left_in[0] set_disable_timing sb_4__0_/chanx_left_out[0] -set_disable_timing sb_4__0_/chanx_left_in[1] set_disable_timing sb_4__0_/chanx_left_out[1] set_disable_timing sb_4__0_/chanx_left_in[2] set_disable_timing sb_4__0_/chanx_left_out[2] @@ -6775,6 +6760,7 @@ set_disable_timing sb_4__0_/chanx_left_out[9] set_disable_timing sb_4__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] @@ -6792,6 +6778,7 @@ set_disable_timing sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin set_disable_timing sb_4__0_/mux_top_track_0/in[0] set_disable_timing sb_4__0_/mux_top_track_2/in[0] set_disable_timing sb_4__0_/mux_top_track_4/in[0] +set_disable_timing sb_4__0_/mux_top_track_6/in[0] set_disable_timing sb_4__0_/mux_top_track_8/in[0] set_disable_timing sb_4__0_/mux_top_track_10/in[0] set_disable_timing sb_4__0_/mux_top_track_12/in[0] @@ -6846,12 +6833,14 @@ set_disable_timing sb_4__1_/chany_top_in[7] set_disable_timing sb_4__1_/chany_top_out[8] set_disable_timing sb_4__1_/chany_top_in[8] set_disable_timing sb_4__1_/chany_top_out[9] +set_disable_timing sb_4__1_/chany_top_in[9] set_disable_timing sb_4__1_/chany_bottom_in[0] set_disable_timing sb_4__1_/chany_bottom_out[0] set_disable_timing sb_4__1_/chany_bottom_in[1] set_disable_timing sb_4__1_/chany_bottom_out[1] set_disable_timing sb_4__1_/chany_bottom_in[2] set_disable_timing sb_4__1_/chany_bottom_out[2] +set_disable_timing sb_4__1_/chany_bottom_in[3] set_disable_timing sb_4__1_/chany_bottom_out[3] set_disable_timing sb_4__1_/chany_bottom_in[4] set_disable_timing sb_4__1_/chany_bottom_out[4] @@ -6867,7 +6856,7 @@ set_disable_timing sb_4__1_/chany_bottom_in[9] set_disable_timing sb_4__1_/chany_bottom_out[9] set_disable_timing sb_4__1_/chanx_left_in[0] set_disable_timing sb_4__1_/chanx_left_out[0] -set_disable_timing sb_4__1_/chanx_left_in[1] +set_disable_timing sb_4__1_/chanx_left_out[1] set_disable_timing sb_4__1_/chanx_left_in[2] set_disable_timing sb_4__1_/chanx_left_out[2] set_disable_timing sb_4__1_/chanx_left_in[3] @@ -6895,6 +6884,7 @@ set_disable_timing sb_4__1_/top_right_grid_left_width_0_height_0_subtile_6__pin_ set_disable_timing sb_4__1_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] @@ -6946,6 +6936,7 @@ set_disable_timing sb_4__1_/mux_top_track_8/in[3] set_disable_timing sb_4__1_/mux_left_track_5/in[0] set_disable_timing sb_4__1_/mux_top_track_16/in[3] set_disable_timing sb_4__1_/mux_left_track_7/in[0] +set_disable_timing sb_4__1_/mux_left_track_3/in[1] set_disable_timing sb_4__1_/mux_top_track_0/in[4] set_disable_timing sb_4__1_/mux_left_track_9/in[1] set_disable_timing sb_4__1_/mux_top_track_8/in[4] @@ -6994,7 +6985,9 @@ set_disable_timing sb_4__2_/chany_top_in[5] set_disable_timing sb_4__2_/chany_top_out[6] set_disable_timing sb_4__2_/chany_top_in[6] set_disable_timing sb_4__2_/chany_top_out[7] +set_disable_timing sb_4__2_/chany_top_in[7] set_disable_timing sb_4__2_/chany_top_out[8] +set_disable_timing sb_4__2_/chany_top_in[8] set_disable_timing sb_4__2_/chany_top_out[9] set_disable_timing sb_4__2_/chany_top_in[9] set_disable_timing sb_4__2_/chany_bottom_in[0] @@ -7016,6 +7009,7 @@ set_disable_timing sb_4__2_/chany_bottom_out[7] set_disable_timing sb_4__2_/chany_bottom_in[8] set_disable_timing sb_4__2_/chany_bottom_out[8] set_disable_timing sb_4__2_/chany_bottom_in[9] +set_disable_timing sb_4__2_/chany_bottom_out[9] set_disable_timing sb_4__2_/chanx_left_in[0] set_disable_timing sb_4__2_/chanx_left_out[0] set_disable_timing sb_4__2_/chanx_left_in[1] @@ -7025,6 +7019,7 @@ set_disable_timing sb_4__2_/chanx_left_out[2] set_disable_timing sb_4__2_/chanx_left_in[3] set_disable_timing sb_4__2_/chanx_left_out[3] set_disable_timing sb_4__2_/chanx_left_in[4] +set_disable_timing sb_4__2_/chanx_left_out[4] set_disable_timing sb_4__2_/chanx_left_in[5] set_disable_timing sb_4__2_/chanx_left_out[5] set_disable_timing sb_4__2_/chanx_left_in[6] @@ -7035,6 +7030,7 @@ set_disable_timing sb_4__2_/chanx_left_in[8] set_disable_timing sb_4__2_/chanx_left_out[8] set_disable_timing sb_4__2_/chanx_left_in[9] set_disable_timing sb_4__2_/chanx_left_out[9] +set_disable_timing sb_4__2_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_4__2_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_4__2_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] set_disable_timing sb_4__2_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] @@ -7089,6 +7085,7 @@ set_disable_timing sb_4__2_/mux_bottom_track_17/in[1] set_disable_timing sb_4__2_/mux_left_track_11/in[0] set_disable_timing sb_4__2_/mux_left_track_19/in[1] set_disable_timing sb_4__2_/mux_bottom_track_1/in[2] +set_disable_timing sb_4__2_/mux_left_track_9/in[0] set_disable_timing sb_4__2_/mux_left_track_17/in[1] set_disable_timing sb_4__2_/mux_top_track_0/in[3] set_disable_timing sb_4__2_/mux_left_track_3/in[0] @@ -7143,6 +7140,7 @@ set_disable_timing sb_4__3_/chany_top_in[4] set_disable_timing sb_4__3_/chany_top_out[5] set_disable_timing sb_4__3_/chany_top_in[5] set_disable_timing sb_4__3_/chany_top_out[6] +set_disable_timing sb_4__3_/chany_top_in[6] set_disable_timing sb_4__3_/chany_top_out[7] set_disable_timing sb_4__3_/chany_top_in[7] set_disable_timing sb_4__3_/chany_top_out[8] @@ -7164,7 +7162,9 @@ set_disable_timing sb_4__3_/chany_bottom_out[5] set_disable_timing sb_4__3_/chany_bottom_in[6] set_disable_timing sb_4__3_/chany_bottom_out[6] set_disable_timing sb_4__3_/chany_bottom_in[7] +set_disable_timing sb_4__3_/chany_bottom_out[7] set_disable_timing sb_4__3_/chany_bottom_in[8] +set_disable_timing sb_4__3_/chany_bottom_out[8] set_disable_timing sb_4__3_/chany_bottom_in[9] set_disable_timing sb_4__3_/chany_bottom_out[9] set_disable_timing sb_4__3_/chanx_left_in[0] @@ -7178,6 +7178,7 @@ set_disable_timing sb_4__3_/chanx_left_out[3] set_disable_timing sb_4__3_/chanx_left_in[4] set_disable_timing sb_4__3_/chanx_left_out[4] set_disable_timing sb_4__3_/chanx_left_in[5] +set_disable_timing sb_4__3_/chanx_left_out[5] set_disable_timing sb_4__3_/chanx_left_in[6] set_disable_timing sb_4__3_/chanx_left_out[6] set_disable_timing sb_4__3_/chanx_left_in[7] @@ -7193,6 +7194,7 @@ set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_2__pin_ set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] @@ -7202,6 +7204,7 @@ set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_4__p set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_4__3_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_4__3_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_4__3_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] set_disable_timing sb_4__3_/mux_top_track_0/in[0] @@ -7221,6 +7224,7 @@ set_disable_timing sb_4__3_/mux_bottom_track_9/in[3] set_disable_timing sb_4__3_/mux_bottom_track_17/in[3] set_disable_timing sb_4__3_/mux_bottom_track_1/in[5] set_disable_timing sb_4__3_/mux_bottom_track_9/in[4] +set_disable_timing sb_4__3_/mux_bottom_track_17/in[4] set_disable_timing sb_4__3_/mux_left_track_1/in[2] set_disable_timing sb_4__3_/mux_left_track_3/in[2] set_disable_timing sb_4__3_/mux_bottom_track_1/in[0] @@ -7235,6 +7239,7 @@ set_disable_timing sb_4__3_/mux_left_track_15/in[0] set_disable_timing sb_4__3_/mux_bottom_track_9/in[1] set_disable_timing sb_4__3_/mux_left_track_13/in[0] set_disable_timing sb_4__3_/mux_bottom_track_17/in[1] +set_disable_timing sb_4__3_/mux_left_track_11/in[0] set_disable_timing sb_4__3_/mux_left_track_19/in[1] set_disable_timing sb_4__3_/mux_bottom_track_1/in[2] set_disable_timing sb_4__3_/mux_left_track_9/in[0] @@ -7292,6 +7297,7 @@ set_disable_timing sb_4__4_/chany_bottom_out[4] set_disable_timing sb_4__4_/chany_bottom_in[5] set_disable_timing sb_4__4_/chany_bottom_out[5] set_disable_timing sb_4__4_/chany_bottom_in[6] +set_disable_timing sb_4__4_/chany_bottom_out[6] set_disable_timing sb_4__4_/chany_bottom_in[7] set_disable_timing sb_4__4_/chany_bottom_out[7] set_disable_timing sb_4__4_/chany_bottom_in[8] @@ -7323,6 +7329,7 @@ set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_2__p set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_4__4_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] @@ -7340,6 +7347,7 @@ set_disable_timing sb_4__4_/mux_bottom_track_5/in[0] set_disable_timing sb_4__4_/mux_bottom_track_7/in[0] set_disable_timing sb_4__4_/mux_bottom_track_9/in[0] set_disable_timing sb_4__4_/mux_bottom_track_11/in[0] +set_disable_timing sb_4__4_/mux_bottom_track_13/in[0] set_disable_timing sb_4__4_/mux_bottom_track_15/in[0] set_disable_timing sb_4__4_/mux_bottom_track_17/in[0] set_disable_timing sb_4__4_/mux_left_track_1/in[1] @@ -8039,76 +8047,229 @@ set_disable_timing grid_clb_3__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_ # Disable Timing for grid[3][2] ####################################### ####################################### -# Disable Timing for unused grid[3][2][0] +# Disable Timing for unused resources in grid[3][2][0] ####################################### ####################################### -# Disable all the ports for pb_graph_node clb[0] +# Disable unused pins for pb_graph_node clb[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[4] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[5] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[6] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[7] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[8] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[9] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_O[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_O[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_O[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_clk[0] ####################################### -# Disable all the ports for pb_graph_node fle[0] +# Disable unused mux_inputs for pb_graph_node clb[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[7] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//direct_interc_7_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13] ####################################### -# Disable all the ports for pb_graph_node ble4[0] +# Disable unused pins for pb_graph_node fle[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0] ####################################### -# Disable all the ports for pb_graph_node lut4[0] +# Disable unused mux_inputs for pb_graph_node fle[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0] ####################################### -# Disable all the ports for pb_graph_node ff[0] +# Disable unused pins for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] ####################################### -# Disable all the ports for pb_graph_node fle[1] +# Disable unused mux_inputs for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] ####################################### -# Disable all the ports for pb_graph_node ble4[0] +# Disable unused pins for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] ####################################### -# Disable all the ports for pb_graph_node lut4[0] +# Disable unused pins for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] ####################################### -# Disable all the ports for pb_graph_node ff[0] +# Disable unused pins for pb_graph_node fle[1] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0] ####################################### -# Disable all the ports for pb_graph_node fle[2] +# Disable unused mux_inputs for pb_graph_node fle[1] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0] ####################################### -# Disable all the ports for pb_graph_node ble4[0] +# Disable unused pins for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] ####################################### -# Disable all the ports for pb_graph_node lut4[0] +# Disable unused mux_inputs for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] ####################################### -# Disable all the ports for pb_graph_node ff[0] +# Disable unused pins for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] ####################################### -# Disable all the ports for pb_graph_node fle[3] +# Disable unused pins for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] ####################################### -# Disable all the ports for pb_graph_node ble4[0] +# Disable unused pins for pb_graph_node fle[2] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0] ####################################### -# Disable all the ports for pb_graph_node lut4[0] +# Disable unused mux_inputs for pb_graph_node fle[2] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0] ####################################### -# Disable all the ports for pb_graph_node ff[0] +# Disable unused pins for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable unused pins for pb_graph_node fle[3] +####################################### +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[3] +####################################### +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_5_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] ####################################### # Disable Timing for grid[3][3] ####################################### @@ -8409,229 +8570,76 @@ set_disable_timing grid_clb_4__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_ # Disable Timing for grid[4][3] ####################################### ####################################### -# Disable Timing for unused resources in grid[4][3][0] +# Disable Timing for unused grid[4][3][0] ####################################### ####################################### -# Disable unused pins for pb_graph_node clb[0] +# Disable all the ports for pb_graph_node clb[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[4] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[5] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[6] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[9] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_O[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_O[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_O[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_clk[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/* ####################################### -# Disable unused mux_inputs for pb_graph_node clb[0] +# Disable all the ports for pb_graph_node fle[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//direct_interc_7_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/* ####################################### -# Disable unused pins for pb_graph_node fle[0] +# Disable all the ports for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node fle[0] +# Disable all the ports for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* ####################################### -# Disable unused pins for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node fle[1] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/* ####################################### -# Disable unused pins for pb_graph_node lut4[0] +# Disable all the ports for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* ####################################### -# Disable unused pins for pb_graph_node ff[0] +# Disable all the ports for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* ####################################### -# Disable unused pins for pb_graph_node fle[1] +# Disable all the ports for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node fle[1] +# Disable all the ports for pb_graph_node fle[2] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/* ####################################### -# Disable unused pins for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* ####################################### -# Disable unused pins for pb_graph_node lut4[0] +# Disable all the ports for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* ####################################### -# Disable unused pins for pb_graph_node ff[0] +# Disable all the ports for pb_graph_node fle[3] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/* ####################################### -# Disable unused pins for pb_graph_node fle[2] +# Disable all the ports for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node fle[2] +# Disable all the ports for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* ####################################### -# Disable unused pins for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] -####################################### -# Disable unused mux_inputs for pb_graph_node ble4[0] -####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] -####################################### -# Disable unused pins for pb_graph_node lut4[0] -####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] -####################################### -# Disable unused pins for pb_graph_node ff[0] -####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] -####################################### -# Disable unused pins for pb_graph_node fle[3] -####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0] -####################################### -# Disable unused mux_inputs for pb_graph_node fle[3] -####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_5_/in[0] -####################################### -# Disable unused pins for pb_graph_node ble4[0] -####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] -####################################### -# Disable unused mux_inputs for pb_graph_node ble4[0] -####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] -####################################### -# Disable unused pins for pb_graph_node lut4[0] -####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] -####################################### -# Disable unused pins for pb_graph_node ff[0] -####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* ####################################### # Disable Timing for grid[4][4] ####################################### @@ -9144,20 +9152,16 @@ set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__5/* ####################################### set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused resources in grid[5][4][6] +# Disable Timing for unused grid[5][4][6] ####################################### ####################################### -# Disable unused pins for pb_graph_node io[0] +# Disable all the ports for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/io_outpad[0] +set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/* ####################################### -# Disable unused mux_inputs for pb_graph_node io[0] +# Disable all the ports for pb_graph_node iopad[0] ####################################### -set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6//direct_interc_1_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] +set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* ####################################### # Disable Timing for unused grid[5][4][7] ####################################### @@ -9377,20 +9381,16 @@ set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__1/* ####################################### set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused resources in grid[5][1][2] +# Disable Timing for unused grid[5][1][2] ####################################### ####################################### -# Disable unused pins for pb_graph_node io[0] +# Disable all the ports for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/io_outpad[0] +set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/* ####################################### -# Disable unused mux_inputs for pb_graph_node io[0] +# Disable all the ports for pb_graph_node iopad[0] ####################################### -set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2//direct_interc_1_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] +set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* ####################################### # Disable Timing for unused grid[5][1][3] ####################################### @@ -9563,16 +9563,20 @@ set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__1/* ####################################### set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused grid[3][0][2] +# Disable Timing for unused resources in grid[3][0][2] ####################################### ####################################### -# Disable all the ports for pb_graph_node io[0] +# Disable unused pins for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2/* +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2/io_outpad[0] ####################################### -# Disable all the ports for pb_graph_node iopad[0] +# Disable unused mux_inputs for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] ####################################### # Disable Timing for unused grid[3][0][3] ####################################### @@ -9618,16 +9622,20 @@ set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__6/* ####################################### set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused grid[3][0][7] +# Disable Timing for unused resources in grid[3][0][7] ####################################### ####################################### -# Disable all the ports for pb_graph_node io[0] +# Disable unused pins for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7/* +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7/io_outpad[0] ####################################### -# Disable all the ports for pb_graph_node iopad[0] +# Disable unused mux_inputs for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] ####################################### # Disable Timing for grid[2][0] ####################################### diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 737c52a99..2e6d979ed 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -39,11 +39,11 @@ wire [0:0] clk_fm; // ----- End Connect Global ports of FPGA top module ----- // ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- -// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[38] ----- - assign gfpga_pad_GPIO_PAD_fm[38] = a[0]; +// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[79] ----- + assign gfpga_pad_GPIO_PAD_fm[79] = a[0]; -// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[58] ----- - assign gfpga_pad_GPIO_PAD_fm[58] = b[0]; +// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[74] ----- + assign gfpga_pad_GPIO_PAD_fm[74] = b[0]; // ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[17] ----- assign c[0] = gfpga_pad_GPIO_PAD_fm[17]; @@ -86,6 +86,7 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0; @@ -105,6 +106,7 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[55] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[56] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[57] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[58] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[59] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[60] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[61] = 1'b0; @@ -120,12 +122,10 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[71] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[72] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[73] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[74] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[75] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[76] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[77] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[78] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[79] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[80] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[81] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[82] = 1'b0; @@ -622,10 +622,10 @@ initial begin force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}}; @@ -650,14 +650,14 @@ initial begin force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b1011; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b0100; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_3__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; force U0_formal_verification.grid_clb_3__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; force U0_formal_verification.grid_clb_3__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; @@ -862,10 +862,10 @@ initial begin force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}}; @@ -890,14 +890,14 @@ initial begin force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b1110; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b0001; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0001; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1110; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; @@ -1406,8 +1406,8 @@ initial begin force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = 4'b0111; - force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = 4'b1000; + force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__2_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1432,8 +1432,8 @@ initial begin force U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__3_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__3_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_out[0:3] = 4'b0011; + force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_outb[0:3] = 4'b1100; force U0_formal_verification.sb_1__3_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__3_.mem_top_track_16.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__3_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; @@ -1454,8 +1454,8 @@ initial begin force U0_formal_verification.sb_1__3_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = 4'b0011; - force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = 4'b1100; + force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = 4'b0101; + force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = 4'b1010; force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__4_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1492,14 +1492,14 @@ initial begin force U0_formal_verification.sb_2__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_2__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_2__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_2__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_out[0:3] = 4'b0101; + force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_outb[0:3] = 4'b1010; force U0_formal_verification.sb_2__0_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_2__0_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__0_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1516,8 +1516,8 @@ initial begin force U0_formal_verification.sb_2__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_out[0:3] = 4'b0101; + force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_outb[0:3] = 4'b1010; force U0_formal_verification.sb_2__1_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_2__1_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__1_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1614,8 +1614,8 @@ initial begin force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = 3'b001; + force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = 3'b110; force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_3__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; @@ -1636,10 +1636,10 @@ initial begin force U0_formal_verification.sb_3__0_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__0_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__0_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = 4'b0111; - force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = 4'b1000; + force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_out[0:3] = 4'b0100; + force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_outb[0:3] = 4'b1011; + force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1680,12 +1680,12 @@ initial begin force U0_formal_verification.sb_3__2_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = 4'b0101; - force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = 4'b1010; + force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_out[0:3] = 4'b0110; + force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_outb[0:3] = 4'b1001; force U0_formal_verification.sb_3__3_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__3_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__3_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; @@ -1708,8 +1708,8 @@ initial begin force U0_formal_verification.sb_3__3_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__3_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__3_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_out[0:3] = 4'b0110; + force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_outb[0:3] = 4'b1001; force U0_formal_verification.sb_3__4_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__4_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__4_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; @@ -1748,8 +1748,8 @@ initial begin force U0_formal_verification.sb_4__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; @@ -1792,8 +1792,8 @@ initial begin force U0_formal_verification.sb_4__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = 2'b01; - force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = 2'b10; + force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; @@ -1830,8 +1830,8 @@ initial begin force U0_formal_verification.sb_4__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; @@ -1852,8 +1852,8 @@ initial begin force U0_formal_verification.sb_4__3_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = 4'b0101; - force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = 4'b1010; + force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__3_.mem_left_track_3.mem_out[0:1] = {2{1'b0}}; @@ -1864,8 +1864,8 @@ initial begin force U0_formal_verification.sb_4__3_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__3_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; @@ -1886,8 +1886,8 @@ initial begin force U0_formal_verification.sb_4__4_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; @@ -2092,8 +2092,8 @@ initial begin force U0_formal_verification.cbx_3__0_.mem_top_ipin_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_3__0_.mem_top_ipin_7.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_3__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_1.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; @@ -2110,8 +2110,8 @@ initial begin force U0_formal_verification.cbx_3__2_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cbx_3__2_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_3__2_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_out[0:2] = 3'b010; + force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_outb[0:2] = 3'b101; force U0_formal_verification.cbx_3__2_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_3__2_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_3__2_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}}; @@ -2206,8 +2206,8 @@ initial begin force U0_formal_verification.cbx_4__3_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = 2'b01; - force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = 2'b10; + force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}}; @@ -2412,8 +2412,8 @@ initial begin force U0_formal_verification.cby_3__2_.mem_right_ipin_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_3__3_.mem_right_ipin_1.mem_out[0:1] = {2{1'b0}}; diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc index bc1f632f0..a44bb6090 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,1324 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/D 5 @@ -1399,82 +81,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/s set_min_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 @@ -1613,8 +221,1352 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_ set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -1909,148 +1861,136 @@ set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -2345,148 +2285,136 @@ set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -2781,144 +2709,128 @@ set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -3251,128 +3163,128 @@ set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -3705,136 +3617,136 @@ set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -4129,136 +4041,136 @@ set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -4553,136 +4465,136 @@ set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -4977,136 +4889,136 @@ set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -5401,136 +5313,136 @@ set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -5825,136 +5737,136 @@ set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -6249,128 +6161,128 @@ set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -6703,128 +6615,144 @@ set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_2_/D 5 @@ -7157,136 +7085,160 @@ set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_2_/D 5 @@ -7581,136 +7533,160 @@ set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_2_/D 5 @@ -8005,136 +7981,160 @@ set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index 3c755b028..e644f9251 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,48 +6,44 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -60,12 +56,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q @@ -74,6 +74,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -84,6 +92,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -100,6 +110,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -108,32 +126,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -146,5 +148,3 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit index fc17891b4..d9dd037df 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -221,7 +221,9 @@ 0 0 0 +1 0 +1 0 0 0 @@ -621,6 +623,9 @@ 0 0 0 +1 +1 +1 0 0 0 @@ -804,7 +809,6 @@ 0 0 0 -1 0 0 0 @@ -828,8 +832,6 @@ 0 0 0 -1 -1 0 0 0 @@ -840,9 +842,7 @@ 0 0 0 -1 0 -1 0 0 0 @@ -864,7 +864,6 @@ 0 0 0 -1 0 0 0 @@ -877,9 +876,6 @@ 0 0 0 -1 -1 -1 0 0 0 @@ -928,7 +924,6 @@ 0 0 0 -1 0 0 0 @@ -939,13 +934,9 @@ 0 0 0 -1 0 -1 0 -1 0 -1 0 0 0 @@ -1057,8 +1048,6 @@ 0 0 0 -1 -1 0 0 0 @@ -1234,8 +1223,6 @@ 0 0 0 -1 -1 0 0 0 @@ -1263,9 +1250,7 @@ 0 0 0 -1 0 -1 0 0 0 @@ -1315,6 +1300,8 @@ 0 0 0 +1 +1 0 0 0 @@ -1723,9 +1710,6 @@ 0 0 0 -1 -1 -1 0 0 0 @@ -1779,6 +1763,8 @@ 0 0 0 +1 +1 0 0 0 @@ -2209,6 +2195,10 @@ 0 0 0 +1 +1 +1 +1 0 0 0 @@ -2217,7 +2207,10 @@ 0 0 0 +1 +1 0 +1 0 0 0 @@ -2266,6 +2259,7 @@ 0 0 0 +1 0 0 0 @@ -2276,9 +2270,13 @@ 0 0 0 +1 0 +1 0 +1 0 +1 0 0 0 @@ -2351,6 +2349,9 @@ 0 0 0 +1 +0 +0 0 0 0 @@ -2359,7 +2360,6 @@ 0 0 0 -1 1 1 0 @@ -2562,7 +2562,6 @@ 0 0 0 -1 0 0 0 @@ -2817,8 +2816,6 @@ 0 0 0 -1 -1 0 0 0 @@ -3025,6 +3022,19 @@ 0 0 0 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -3059,6 +3069,10 @@ 0 0 0 +1 +1 +1 +1 0 0 0 @@ -3255,6 +3269,10 @@ 0 0 0 +1 +0 +1 +0 0 0 0 @@ -3552,6 +3570,10 @@ 0 0 0 +0 +0 +0 +0 1 1 1 @@ -3779,7 +3801,78 @@ 0 0 0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 0 0 0 @@ -3819,15 +3912,6 @@ 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -0 0 0 0 @@ -3857,6 +3941,14 @@ 0 0 0 +1 +1 +1 +1 +1 +1 +1 +1 0 0 0 @@ -3891,6 +3983,7 @@ 0 0 0 +1 0 0 0 @@ -3899,18 +3992,8 @@ 0 0 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 @@ -3933,8 +4016,17 @@ 0 0 0 +1 0 0 +1 +1 +1 +1 +1 +1 +1 +1 0 0 0 @@ -3988,11 +4080,6 @@ 0 0 1 -1 -1 -1 -1 -1 0 1 0 @@ -4001,6 +4088,8 @@ 0 0 0 +1 +1 0 0 0 @@ -4008,19 +4097,11 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 +1 +1 +1 +1 1 1 1 @@ -4071,14 +4152,6 @@ 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 @@ -4133,81 +4206,8 @@ 0 0 0 -1 -1 -0 -0 -0 -0 0 0 0 0 0 -0 -0 -0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml index 10e19c6be..09709736b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -302,8129 +302,8129 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml index fd78aece6..6cbbd83af 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml @@ -4533,13 +4533,13 @@ - + - + - + - + @@ -4561,12 +4561,16 @@ - + + + + + - + - + @@ -4782,14 +4786,30 @@ + + + + + + + + + + + + + + + + - + - - + + - - + + @@ -4833,14 +4853,30 @@ + + + + + + + + + + + + + + + + - + - - - - - + + + + + @@ -6953,13 +6989,13 @@ - + - + - + - + @@ -6981,16 +7017,12 @@ - - - - - + - + - + @@ -7206,29 +7238,13 @@ - - - - - - - - - - - - - - - - - + - - - - + + + + @@ -7273,30 +7289,14 @@ - - - - - - - - - - - - - - - - - + - + - + @@ -10515,7 +10515,7 @@ - + @@ -10540,7 +10540,7 @@ - + @@ -10744,7 +10744,7 @@ - + @@ -10795,7 +10795,7 @@ - + @@ -11482,7 +11482,7 @@ - + @@ -11793,7 +11793,7 @@ - + @@ -11933,7 +11933,7 @@ - + @@ -12071,7 +12071,7 @@ - + @@ -12083,13 +12083,13 @@ - + - + - - - + + + @@ -12101,8 +12101,8 @@ - - + + @@ -12239,7 +12239,7 @@ - + @@ -12295,8 +12295,8 @@ - - + + @@ -12351,7 +12351,7 @@ - + @@ -12380,7 +12380,7 @@ - + @@ -12407,8 +12407,8 @@ - - + + @@ -12436,7 +12436,7 @@ - + @@ -12444,13 +12444,13 @@ - + - + - - + + @@ -12520,7 +12520,7 @@ - + @@ -12575,7 +12575,7 @@ - + @@ -12630,7 +12630,7 @@ - + @@ -12687,7 +12687,7 @@ - + @@ -12741,8 +12741,8 @@ - - + + @@ -12751,10 +12751,10 @@ - + - - + + @@ -13056,8 +13056,8 @@ - - + + @@ -13141,15 +13141,15 @@ - + - + - - - + + + @@ -13202,20 +13202,20 @@ - + - + - + - + - + @@ -13257,7 +13257,7 @@ - + @@ -13284,7 +13284,7 @@ - + @@ -13390,11 +13390,11 @@ - + - + @@ -13448,20 +13448,20 @@ - + - + - + - + - + @@ -13584,7 +13584,7 @@ - + @@ -13669,10 +13669,10 @@ - + - + @@ -13696,7 +13696,7 @@ - + @@ -13750,12 +13750,12 @@ - + - + - + @@ -13838,7 +13838,7 @@ - + @@ -13864,7 +13864,7 @@ - + @@ -13890,10 +13890,10 @@ - + - + @@ -13947,11 +13947,11 @@ - + - + - + @@ -13976,7 +13976,7 @@ - + @@ -14059,7 +14059,7 @@ - + @@ -14087,7 +14087,7 @@ - + @@ -14117,7 +14117,7 @@ - + @@ -14227,7 +14227,7 @@ - + @@ -14253,7 +14253,7 @@ - + @@ -14283,7 +14283,7 @@ - + @@ -14338,10 +14338,10 @@ - + - + @@ -14709,16 +14709,16 @@ - + - + - + - + @@ -14828,7 +14828,7 @@ - + @@ -14910,7 +14910,7 @@ - + @@ -14963,14 +14963,14 @@ - + - + - + - + @@ -14984,23 +14984,23 @@ - - + + - + - + - + - - + + @@ -15074,7 +15074,7 @@ - + @@ -15100,7 +15100,7 @@ - + @@ -15153,7 +15153,7 @@ - + @@ -15211,7 +15211,7 @@ - + @@ -15265,9 +15265,9 @@ - + - + @@ -15322,7 +15322,7 @@ - + @@ -15351,7 +15351,7 @@ - + @@ -15376,7 +15376,7 @@ - + @@ -15405,7 +15405,7 @@ - + @@ -15434,7 +15434,7 @@ - + @@ -15511,6 +15511,229 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -15533,229 +15756,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -15795,7 +15795,7 @@ - + @@ -15822,7 +15822,7 @@ - + @@ -15908,7 +15908,7 @@ - + @@ -15934,7 +15934,7 @@ - + @@ -15963,17 +15963,17 @@ - + - + - + - - + + @@ -16017,7 +16017,7 @@ - + @@ -16043,7 +16043,7 @@ - + @@ -16251,7 +16251,7 @@ - + @@ -16278,7 +16278,7 @@ - + @@ -16384,15 +16384,15 @@ - + - + - - - + + + @@ -16715,7 +16715,7 @@ - + @@ -16742,7 +16742,7 @@ - + @@ -16791,7 +16791,7 @@ - + @@ -16836,15 +16836,15 @@ - + - + - + - + @@ -16963,7 +16963,7 @@ - + @@ -17000,7 +17000,7 @@ - + @@ -17082,7 +17082,7 @@ - + @@ -17234,15 +17234,15 @@ - + - + - - - + + + @@ -17325,7 +17325,7 @@ - + @@ -17374,7 +17374,7 @@ - + @@ -17478,23 +17478,23 @@ - + - + - + - + - + - + @@ -17596,15 +17596,15 @@ - + - + - - - + + + @@ -17796,15 +17796,15 @@ - + - + - - - + + + @@ -18406,9 +18406,9 @@ - + - + @@ -18924,7 +18924,7 @@ - + @@ -19029,7 +19029,7 @@ - + @@ -19131,7 +19131,7 @@ - + @@ -19214,7 +19214,7 @@ - + @@ -19276,7 +19276,7 @@ - + @@ -19356,7 +19356,7 @@ - + @@ -19398,7 +19398,7 @@ - + @@ -19666,7 +19666,7 @@ - + @@ -19729,7 +19729,7 @@ - + @@ -19768,7 +19768,7 @@ - + @@ -19834,7 +19834,7 @@ - + @@ -19873,7 +19873,7 @@ - + @@ -19896,18 +19896,18 @@ - + - + - - - - + + + + @@ -19936,7 +19936,7 @@ - + @@ -20019,9 +20019,9 @@ - + - + @@ -20081,14 +20081,14 @@ - + - + - + - + @@ -20121,7 +20121,7 @@ - + @@ -20203,7 +20203,7 @@ - + @@ -20513,7 +20513,7 @@ - + @@ -20615,7 +20615,7 @@ - + @@ -20743,8 +20743,8 @@ - - + + @@ -20926,7 +20926,7 @@ - + @@ -20969,7 +20969,7 @@ - + @@ -21069,14 +21069,14 @@ - + - + - + - + @@ -22350,7 +22350,7 @@ - + @@ -22469,7 +22469,7 @@ - + @@ -22526,7 +22526,7 @@ - + @@ -22548,7 +22548,7 @@ - + @@ -22783,7 +22783,7 @@ - + @@ -22938,7 +22938,7 @@ - + @@ -23036,7 +23036,7 @@ - + @@ -23057,7 +23057,7 @@ - + @@ -23155,15 +23155,15 @@ - + - + - - - + + + @@ -23173,7 +23173,7 @@ - + @@ -23271,7 +23271,7 @@ - + @@ -23292,7 +23292,7 @@ - + @@ -23393,7 +23393,7 @@ - + @@ -23498,7 +23498,7 @@ - + @@ -23644,7 +23644,7 @@ - + @@ -23747,7 +23747,7 @@ - + @@ -23829,7 +23829,7 @@ - + @@ -23850,7 +23850,7 @@ - + @@ -23934,7 +23934,7 @@ - + @@ -23955,7 +23955,7 @@ - + @@ -24035,7 +24035,7 @@ - + @@ -24140,7 +24140,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml new file mode 100644 index 000000000..e30e971a2 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml @@ -0,0 +1,1061 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v index 560ad7620..8d1c9cd5f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v @@ -807,7 +807,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__0_ccff_tail), + .ccff_head(grid_io_top_1_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -829,7 +829,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__1_ccff_tail), + .ccff_head(grid_io_top_2_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -851,7 +851,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__2_ccff_tail), + .ccff_head(grid_io_top_3_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -873,7 +873,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__3_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -983,7 +983,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_1_ccff_tail), + .ccff_head(cbx_1__0__3_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1005,7 +1005,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_2_ccff_tail), + .ccff_head(cbx_1__0__2_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1027,7 +1027,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_3_ccff_tail), + .ccff_head(cbx_1__0__1_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1049,7 +1049,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1538,7 +1538,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_1_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:9]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:9]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -1568,7 +1568,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_2_ccff_tail), + .ccff_head(grid_io_left_1_ccff_tail), .chany_top_out(sb_0__1__0_chany_top_out[0:9]), .chanx_right_out(sb_0__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:9]), @@ -1599,7 +1599,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_3_ccff_tail), + .ccff_head(grid_io_left_2_ccff_tail), .chany_top_out(sb_0__1__1_chany_top_out[0:9]), .chanx_right_out(sb_0__1__1_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__1_chany_bottom_out[0:9]), @@ -1630,7 +1630,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__4__0_ccff_tail), + .ccff_head(grid_io_left_3_ccff_tail), .chany_top_out(sb_0__1__2_chany_top_out[0:9]), .chanx_right_out(sb_0__1__2_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__2_chany_bottom_out[0:9]), @@ -1688,7 +1688,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:9]), .chanx_right_out(sb_1__0__0_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:9]), @@ -1719,7 +1719,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_0_ccff_tail), + .ccff_head(grid_io_bottom_3_ccff_tail), .chany_top_out(sb_1__0__1_chany_top_out[0:9]), .chanx_right_out(sb_1__0__1_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__1_chanx_left_out[0:9]), @@ -1750,7 +1750,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_4_ccff_tail), + .ccff_head(grid_io_bottom_2_ccff_tail), .chany_top_out(sb_1__0__2_chany_top_out[0:9]), .chanx_right_out(sb_1__0__2_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__2_chanx_left_out[0:9]), @@ -1770,7 +1770,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__0_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_5_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_top_out(sb_1__1__0_chany_top_out[0:9]), .chanx_right_out(sb_1__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:9]), @@ -1791,7 +1791,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__1_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_1_ccff_tail), + .ccff_head(grid_clb_5_ccff_tail), .chany_top_out(sb_1__1__1_chany_top_out[0:9]), .chanx_right_out(sb_1__1__1_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__1_chany_bottom_out[0:9]), @@ -1812,7 +1812,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__2_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_7_ccff_tail), + .ccff_head(grid_clb_1_ccff_tail), .chany_top_out(sb_1__1__2_chany_top_out[0:9]), .chanx_right_out(sb_1__1__2_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__2_chany_bottom_out[0:9]), @@ -1833,7 +1833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__3_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_9_ccff_tail), + .ccff_head(grid_clb_0_ccff_tail), .chany_top_out(sb_1__1__3_chany_top_out[0:9]), .chanx_right_out(sb_1__1__3_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__3_chany_bottom_out[0:9]), @@ -1854,7 +1854,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__4_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_2_ccff_tail), + .ccff_head(grid_clb_9_ccff_tail), .chany_top_out(sb_1__1__4_chany_top_out[0:9]), .chanx_right_out(sb_1__1__4_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__4_chany_bottom_out[0:9]), @@ -1875,7 +1875,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__5_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_11_ccff_tail), + .ccff_head(grid_clb_2_ccff_tail), .chany_top_out(sb_1__1__5_chany_top_out[0:9]), .chanx_right_out(sb_1__1__5_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__5_chany_bottom_out[0:9]), @@ -1896,7 +1896,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__6_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_13_ccff_tail), + .ccff_head(grid_clb_4_ccff_tail), .chany_top_out(sb_1__1__6_chany_top_out[0:9]), .chanx_right_out(sb_1__1__6_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__6_chany_bottom_out[0:9]), @@ -1917,7 +1917,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__7_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_6_ccff_tail), + .ccff_head(grid_clb_13_ccff_tail), .chany_top_out(sb_1__1__7_chany_top_out[0:9]), .chanx_right_out(sb_1__1__7_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__7_chany_bottom_out[0:9]), @@ -1938,7 +1938,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__8_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_15_ccff_tail), + .ccff_head(grid_clb_6_ccff_tail), .chany_top_out(sb_1__1__8_chany_top_out[0:9]), .chanx_right_out(sb_1__1__8_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__8_chany_bottom_out[0:9]), @@ -1970,7 +1970,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_top_1_ccff_tail), + .ccff_head(grid_clb_7_ccff_tail), .chanx_right_out(sb_1__4__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__4__0_chany_bottom_out[0:9]), .chanx_left_out(sb_1__4__0_chanx_left_out[0:9]), @@ -2001,7 +2001,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_top_2_ccff_tail), + .ccff_head(grid_clb_11_ccff_tail), .chanx_right_out(sb_1__4__1_chanx_right_out[0:9]), .chany_bottom_out(sb_1__4__1_chany_bottom_out[0:9]), .chanx_left_out(sb_1__4__1_chanx_left_out[0:9]), @@ -2032,7 +2032,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_top_3_ccff_tail), + .ccff_head(grid_clb_15_ccff_tail), .chanx_right_out(sb_1__4__2_chanx_right_out[0:9]), .chany_bottom_out(sb_1__4__2_chany_bottom_out[0:9]), .chanx_left_out(sb_1__4__2_chanx_left_out[0:9]), @@ -2060,7 +2060,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_8_ccff_tail), + .ccff_head(grid_io_bottom_1_ccff_tail), .chany_top_out(sb_4__0__0_chany_top_out[0:9]), .chanx_left_out(sb_4__0__0_chanx_left_out[0:9]), .ccff_tail(sb_4__0__0_ccff_tail)); @@ -2090,7 +2090,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__9_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_12_ccff_tail), + .ccff_head(grid_clb_8_ccff_tail), .chany_top_out(sb_4__1__0_chany_top_out[0:9]), .chany_bottom_out(sb_4__1__0_chany_bottom_out[0:9]), .chanx_left_out(sb_4__1__0_chanx_left_out[0:9]), @@ -2121,7 +2121,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__10_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_10_ccff_tail), + .ccff_head(grid_clb_12_ccff_tail), .chany_top_out(sb_4__1__1_chany_top_out[0:9]), .chany_bottom_out(sb_4__1__1_chany_bottom_out[0:9]), .chanx_left_out(sb_4__1__1_chanx_left_out[0:9]), @@ -2152,7 +2152,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__11_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_14_ccff_tail), + .ccff_head(grid_clb_10_ccff_tail), .chany_top_out(sb_4__1__2_chany_top_out[0:9]), .chany_bottom_out(sb_4__1__2_chany_bottom_out[0:9]), .chanx_left_out(sb_4__1__2_chanx_left_out[0:9]), @@ -2180,7 +2180,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_clb_14_ccff_tail), .chany_bottom_out(sb_4__4__0_chany_bottom_out[0:9]), .chanx_left_out(sb_4__4__0_chanx_left_out[0:9]), .ccff_tail(sb_4__4__0_ccff_tail)); @@ -2529,7 +2529,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:9]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2548,7 +2548,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__0_chany_top_out[0:9]), .chany_top_in(sb_0__1__1_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(sb_0__1__1_ccff_tail), .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2567,7 +2567,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__1_chany_top_out[0:9]), .chany_top_in(sb_0__1__2_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__1_ccff_tail), + .ccff_head(sb_0__1__2_ccff_tail), .chany_bottom_out(cby_0__1__2_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__2_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2586,7 +2586,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__2_chany_top_out[0:9]), .chany_top_in(sb_0__4__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__2_ccff_tail), + .ccff_head(sb_0__4__0_ccff_tail), .chany_bottom_out(cby_0__1__3_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__3_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2605,7 +2605,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:9]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2619,7 +2619,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__0_chany_top_out[0:9]), .chany_top_in(sb_1__1__1_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(cbx_1__1__1_ccff_tail), .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2633,7 +2633,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__1_chany_top_out[0:9]), .chany_top_in(sb_1__1__2_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__1_ccff_tail), + .ccff_head(cbx_1__1__2_ccff_tail), .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__2_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2647,7 +2647,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__2_chany_top_out[0:9]), .chany_top_in(sb_1__4__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__2_ccff_tail), + .ccff_head(cbx_1__4__0_ccff_tail), .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__3_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2661,7 +2661,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__1_chany_top_out[0:9]), .chany_top_in(sb_1__1__3_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__1_ccff_tail), + .ccff_head(cbx_1__1__3_ccff_tail), .chany_bottom_out(cby_1__1__4_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__4_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__4_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2675,7 +2675,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__3_chany_top_out[0:9]), .chany_top_in(sb_1__1__4_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__3_ccff_tail), + .ccff_head(cbx_1__1__4_ccff_tail), .chany_bottom_out(cby_1__1__5_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__5_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__5_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2689,7 +2689,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__4_chany_top_out[0:9]), .chany_top_in(sb_1__1__5_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__4_ccff_tail), + .ccff_head(cbx_1__1__5_ccff_tail), .chany_bottom_out(cby_1__1__6_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__6_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__6_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2703,7 +2703,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__5_chany_top_out[0:9]), .chany_top_in(sb_1__4__1_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__5_ccff_tail), + .ccff_head(cbx_1__4__1_ccff_tail), .chany_bottom_out(cby_1__1__7_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__7_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__7_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2717,7 +2717,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__2_chany_top_out[0:9]), .chany_top_in(sb_1__1__6_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__2_ccff_tail), + .ccff_head(cbx_1__1__6_ccff_tail), .chany_bottom_out(cby_1__1__8_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__8_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__8_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2731,7 +2731,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__6_chany_top_out[0:9]), .chany_top_in(sb_1__1__7_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__6_ccff_tail), + .ccff_head(cbx_1__1__7_ccff_tail), .chany_bottom_out(cby_1__1__9_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__9_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__9_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2745,7 +2745,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__7_chany_top_out[0:9]), .chany_top_in(sb_1__1__8_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__7_ccff_tail), + .ccff_head(cbx_1__1__8_ccff_tail), .chany_bottom_out(cby_1__1__10_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__10_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__10_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2759,7 +2759,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__8_chany_top_out[0:9]), .chany_top_in(sb_1__4__2_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__8_ccff_tail), + .ccff_head(cbx_1__4__2_ccff_tail), .chany_bottom_out(cby_1__1__11_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__11_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__11_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2773,7 +2773,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__0__0_chany_top_out[0:9]), .chany_top_in(sb_4__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__3_ccff_tail), + .ccff_head(cbx_1__1__9_ccff_tail), .chany_bottom_out(cby_4__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -2793,7 +2793,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__1__0_chany_top_out[0:9]), .chany_top_in(sb_4__1__1_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__9_ccff_tail), + .ccff_head(cbx_1__1__10_ccff_tail), .chany_bottom_out(cby_4__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -2813,7 +2813,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__1__1_chany_top_out[0:9]), .chany_top_in(sb_4__1__2_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__10_ccff_tail), + .ccff_head(cbx_1__1__11_ccff_tail), .chany_bottom_out(cby_4__1__2_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__2_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -2833,7 +2833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__1__2_chany_top_out[0:9]), .chany_top_in(sb_4__4__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__11_ccff_tail), + .ccff_head(cbx_1__4__3_ccff_tail), .chany_bottom_out(cby_4__1__3_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__3_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc index 0f5e878af..d55c32a26 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 1.565565566e-09 -waveform {0 7.82782783e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index a9421575e..07928fe3f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml index 2b935694f..ce309ecbf 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml index 5dc83d65a..6131cf308 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml index 82f30d5b4..9691260da 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index 685366747..e3e56cf32 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml index af800832a..4050ce7e4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml index ee71fb230..cf7a01345 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml index 00d00a5fd..4faa064fa 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml index c93bbf890..18b761b42 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml index de31ff3cc..6b602276f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml index e10d1106b..cfdad6f99 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml index cd54a99c7..1e6dabda1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml index e3f7a395c..8abb31ff2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml index 4f8024349..709dbbb2e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml index c19441be6..c5573a4b5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml index 102048421..e2de46537 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml index f3007ec85..f86ea9caa 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml index 9f589a7be..0d5b16c52 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml index f9e0b6a9c..a3d189670 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml index dea12ded1..3646dcf7a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml index 5b8aaa29e..2eb261e42 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml @@ -1,38 +1,38 @@ - + - + - + - + - + - + - + - + - + @@ -40,39 +40,39 @@ - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml index 0942b3fef..c3143bad3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -39,9 +39,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -102,9 +102,9 @@ - - - + + + @@ -122,9 +122,9 @@ - - - + + + @@ -141,9 +141,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml index f2d096157..71df950e0 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -39,9 +39,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -102,9 +102,9 @@ - - - + + + @@ -122,9 +122,9 @@ - - - + + + @@ -141,9 +141,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__3_.xml index 8ff0435ff..651f17b42 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__3_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -39,9 +39,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -102,9 +102,9 @@ - - - + + + @@ -122,9 +122,9 @@ - - - + + + @@ -141,9 +141,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__4_.xml index ed55dccd1..2c9833855 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__4_.xml @@ -1,38 +1,38 @@ - + - + - + - + - + - + - + - + - + @@ -40,39 +40,39 @@ - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml index 2c59dc413..1616d818a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml @@ -1,13 +1,13 @@ - + - + @@ -45,9 +45,9 @@ - - - + + + @@ -66,9 +66,9 @@ - - - + + + @@ -85,9 +85,9 @@ - - - + + + @@ -102,9 +102,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml index 1234f6b19..6db375e4b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml index ea27be117..42aff2b61 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__3_.xml index 07e35b230..9b60f95f5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__3_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__4_.xml index 81983daa6..bc2901f73 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__4_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -101,9 +101,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml index ae777c8a1..bb04d7917 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml @@ -1,13 +1,13 @@ - + - + @@ -45,9 +45,9 @@ - - - + + + @@ -66,9 +66,9 @@ - - - + + + @@ -85,9 +85,9 @@ - - - + + + @@ -102,9 +102,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml index 01a132814..8ec5b638b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml index e57c4777c..3c805285b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__3_.xml index 42d409d65..e377195bc 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__3_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__4_.xml index f7b656277..58a624fb3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__4_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -101,9 +101,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__0_.xml index 0e15d91bf..e55a850e7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__0_.xml @@ -1,13 +1,13 @@ - + - + @@ -45,9 +45,9 @@ - - - + + + @@ -66,9 +66,9 @@ - - - + + + @@ -85,9 +85,9 @@ - - - + + + @@ -102,9 +102,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__1_.xml index 57ee9f1b3..afecf8514 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__1_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__2_.xml index ed94af807..89b614956 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__2_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__3_.xml index 233917eae..00f859e39 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__3_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__4_.xml index 784ab10d7..05eed197e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__4_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -101,9 +101,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__0_.xml index bd9e172e7..962a9f6b9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__0_.xml @@ -1,38 +1,38 @@ - + - + - + - + - + - + - + - + - + @@ -40,39 +40,39 @@ - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__1_.xml index 37b4d5474..bf33c82ca 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__1_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -21,9 +21,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -56,9 +56,9 @@ - - - + + + @@ -75,9 +75,9 @@ - - - + + + @@ -94,9 +94,9 @@ - - - + + + @@ -108,12 +108,12 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__2_.xml index f36ebf9dc..d19778757 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__2_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -21,9 +21,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -56,9 +56,9 @@ - - - + + + @@ -75,9 +75,9 @@ - - - + + + @@ -94,9 +94,9 @@ - - - + + + @@ -108,12 +108,12 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__3_.xml index 9d949aba7..ddda52b6e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__3_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -21,9 +21,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -56,9 +56,9 @@ - - - + + + @@ -75,9 +75,9 @@ - - - + + + @@ -94,9 +94,9 @@ - - - + + + @@ -108,12 +108,12 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__4_.xml index 9ebabf7f5..6314d9a29 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__4_.xml @@ -1,38 +1,38 @@ - + - + - + - + - + - + - + - + - + @@ -40,39 +40,39 @@ - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 793b5628b..e2b960d51 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml index 4533c39bc..f63dde147 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml index 176b9f5f6..dff12bf3c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml index bee8e919c..1eb7f09a9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index 11fbfd51f..682749130 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml index 0026bd554..7a5e114c5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml index 50006d9d2..e514f592d 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml index 4063f260e..ec581676c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml index 488bff99b..d65b5ca5c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml index ea86b5480..b69d7bd68 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml index c3ac067bd..15ba71944 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml index 387479a35..5a77185a4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml index a3b68c168..47a94e7cd 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml index 83e9f50db..414f19d95 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml index ccaa1b7fb..b4b8d746e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml index df8bca3f2..146fe9653 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml index 20f9f7b50..763e7a89a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml index d533a55a7..e98acc918 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml index c9874c86b..655ea8946 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml index 52722e4bb..5847f5e49 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/mux_modules.yaml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/mux_modules.yaml new file mode 100644 index 000000000..2d7d586c9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/mux_modules.yaml @@ -0,0 +1,55 @@ +sb_0__0_: + - mux_tree_tapbuf_size2 +sb_0__1_: + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size8 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_0__4_: + - mux_tree_tapbuf_size2 +sb_1__0_: + - mux_tree_tapbuf_size5 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size8 + - mux_tree_tapbuf_size10 +sb_1__1_: + - mux_tree_tapbuf_size11 + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size10 + - mux_tree_tapbuf_size8 +sb_1__4_: + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size8 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_4__0_: + - mux_tree_tapbuf_size2 +sb_4__1_: + - mux_tree_tapbuf_size10 + - mux_tree_tapbuf_size8 + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_4__4_: + - mux_tree_tapbuf_size2 +cbx_1__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cbx_1__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cbx_1__4_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cby_0__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cby_1__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cby_4__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml index b9d5872be..b39a64d74 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml @@ -3,7 +3,7 @@ --> - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/config/task.conf b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/config/task.conf new file mode 100644 index 000000000..702110f40 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_abspath_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout = auto +openfpga_vpr_route_chan_width = 26 +openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp +openfpga_preconfig_fabric_wrapper_dump_waveform=--dump_waveform + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v new file mode 100644 index 000000000..5d9e929e2 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -0,0 +1,120 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: FPGA Verilog Testbench for Formal Top-level netlist of Design: and2 +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +module and2_top_formal_verification_random_tb; +// ----- Default clock port is added here since benchmark does not contain one ------- + reg [0:0] clk; + +// ----- Shared inputs ------- + reg [0:0] a; + reg [0:0] b; + +// ----- FPGA fabric outputs ------- + wire [0:0] c_gfpga; + +// ----- Benchmark outputs ------- + wire [0:0] c_bench; + +// ----- Output vectors checking flags ------- + reg [0:0] c_flag; + +// ----- Error counter ------- + integer nb_error= 0; + +// ----- FPGA fabric instanciation ------- + and2_top_formal_verification FPGA_DUT( + .a(a), + .b(b), + .c(c_gfpga) + ); +// ----- End FPGA Fabric Instanication ------- + +// ----- Reference Benchmark Instanication ------- + and2 REF_DUT( + .a(a), + .b(b), + .c(c_bench) + ); +// ----- End reference Benchmark Instanication ------- + +// ----- Clock 'clk' Initialization ------- + initial begin + clk[0] <= 1'b0; + while(1) begin + #0.809066534 + clk[0] <= !clk[0]; + end + end + +// ----- Begin reset signal generation ----- +// ----- End reset signal generation ----- + +// ----- Input Initialization ------- + initial begin + a <= 1'b0; + b <= 1'b0; + + c_flag[0] <= 1'b0; + end + +// ----- Input Stimulus ------- + always@(negedge clk[0]) begin + a <= $random; + b <= $random; + end + +// ----- Begin checking output vectors ------- +// ----- Skip the first falling edge of clock, it is for initialization ------- + reg [0:0] sim_start; + + always@(negedge clk[0]) begin + if (1'b1 == sim_start[0]) begin + sim_start[0] <= ~sim_start[0]; + end else +begin + if(!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin + c_flag <= 1'b1; + end else begin + c_flag<= 1'b0; + end + end + end + + always@(posedge c_flag) begin + if(c_flag) begin + nb_error = nb_error + 1; + $display("Mismatch on c_gfpga at time = %t", $realtime); + end + end + + +// ----- Begin output waveform to VCD file------- + initial begin + $dumpfile("and2_formal.vcd"); + $dumpvars(1, and2_top_formal_verification_random_tb); + end +// ----- END output waveform to VCD file ------- + +initial begin + sim_start[0] <= 1'b1; + $timeformat(-9, 2, "ns", 20); + $display("Simulation start"); +// ----- Can be changed by the user for his/her need ------- + #11.32693195 + if(nb_error == 0) begin + $display("Simulation Succeed"); + end else begin + $display("Simulation Failed with %d error(s)", nb_error); + end + $finish; +end + +endmodule +// ----- END Verilog module for and2_top_formal_verification_random_tb ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc new file mode 100644 index 000000000..06fd83ed4 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -0,0 +1,1794 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain for Timing/Power analysis on the mapped FPGA +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +################################################## +# Create clock +################################################## +create_clock clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} + +################################################## +# Create input and output delays for used I/Os +################################################## +set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[11] +set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[14] +set_output_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[12] + +################################################## +# Disable timing for unused I/Os +################################################## +set_disable_timing gfpga_pad_GPIO_PAD[0] +set_disable_timing gfpga_pad_GPIO_PAD[1] +set_disable_timing gfpga_pad_GPIO_PAD[2] +set_disable_timing gfpga_pad_GPIO_PAD[3] +set_disable_timing gfpga_pad_GPIO_PAD[4] +set_disable_timing gfpga_pad_GPIO_PAD[5] +set_disable_timing gfpga_pad_GPIO_PAD[6] +set_disable_timing gfpga_pad_GPIO_PAD[7] +set_disable_timing gfpga_pad_GPIO_PAD[8] +set_disable_timing gfpga_pad_GPIO_PAD[9] +set_disable_timing gfpga_pad_GPIO_PAD[10] +set_disable_timing gfpga_pad_GPIO_PAD[13] +set_disable_timing gfpga_pad_GPIO_PAD[15] +set_disable_timing gfpga_pad_GPIO_PAD[16] +set_disable_timing gfpga_pad_GPIO_PAD[17] +set_disable_timing gfpga_pad_GPIO_PAD[18] +set_disable_timing gfpga_pad_GPIO_PAD[19] +set_disable_timing gfpga_pad_GPIO_PAD[20] +set_disable_timing gfpga_pad_GPIO_PAD[21] +set_disable_timing gfpga_pad_GPIO_PAD[22] +set_disable_timing gfpga_pad_GPIO_PAD[23] +set_disable_timing gfpga_pad_GPIO_PAD[24] +set_disable_timing gfpga_pad_GPIO_PAD[25] +set_disable_timing gfpga_pad_GPIO_PAD[26] +set_disable_timing gfpga_pad_GPIO_PAD[27] +set_disable_timing gfpga_pad_GPIO_PAD[28] +set_disable_timing gfpga_pad_GPIO_PAD[29] +set_disable_timing gfpga_pad_GPIO_PAD[30] +set_disable_timing gfpga_pad_GPIO_PAD[31] + +################################################## +# Disable timing for global ports +################################################## +set_disable_timing set[0] +set_disable_timing reset[0] +set_disable_timing prog_clk[0] +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN +################################################## +# Disable timing for Connection block cbx_1__0_ +################################################## +set_disable_timing cbx_1__0_/chanx_left_in[0] +set_disable_timing cbx_1__0_/chanx_right_in[0] +set_disable_timing cbx_1__0_/chanx_left_in[1] +set_disable_timing cbx_1__0_/chanx_right_in[1] +set_disable_timing cbx_1__0_/chanx_left_in[2] +set_disable_timing cbx_1__0_/chanx_right_in[2] +set_disable_timing cbx_1__0_/chanx_left_in[3] +set_disable_timing cbx_1__0_/chanx_right_in[3] +set_disable_timing cbx_1__0_/chanx_left_in[4] +set_disable_timing cbx_1__0_/chanx_right_in[4] +set_disable_timing cbx_1__0_/chanx_left_in[5] +set_disable_timing cbx_1__0_/chanx_right_in[5] +set_disable_timing cbx_1__0_/chanx_left_in[6] +set_disable_timing cbx_1__0_/chanx_right_in[6] +set_disable_timing cbx_1__0_/chanx_left_in[7] +set_disable_timing cbx_1__0_/chanx_right_in[7] +set_disable_timing cbx_1__0_/chanx_left_in[8] +set_disable_timing cbx_1__0_/chanx_right_in[8] +set_disable_timing cbx_1__0_/chanx_right_in[9] +set_disable_timing cbx_1__0_/chanx_left_in[10] +set_disable_timing cbx_1__0_/chanx_right_in[10] +set_disable_timing cbx_1__0_/chanx_right_in[11] +set_disable_timing cbx_1__0_/chanx_left_in[12] +set_disable_timing cbx_1__0_/chanx_right_in[12] +set_disable_timing cbx_1__0_/chanx_left_out[0] +set_disable_timing cbx_1__0_/chanx_right_out[0] +set_disable_timing cbx_1__0_/chanx_left_out[1] +set_disable_timing cbx_1__0_/chanx_right_out[1] +set_disable_timing cbx_1__0_/chanx_left_out[2] +set_disable_timing cbx_1__0_/chanx_right_out[2] +set_disable_timing cbx_1__0_/chanx_left_out[3] +set_disable_timing cbx_1__0_/chanx_right_out[3] +set_disable_timing cbx_1__0_/chanx_left_out[4] +set_disable_timing cbx_1__0_/chanx_right_out[4] +set_disable_timing cbx_1__0_/chanx_left_out[5] +set_disable_timing cbx_1__0_/chanx_right_out[5] +set_disable_timing cbx_1__0_/chanx_left_out[6] +set_disable_timing cbx_1__0_/chanx_right_out[6] +set_disable_timing cbx_1__0_/chanx_left_out[7] +set_disable_timing cbx_1__0_/chanx_right_out[7] +set_disable_timing cbx_1__0_/chanx_left_out[8] +set_disable_timing cbx_1__0_/chanx_right_out[8] +set_disable_timing cbx_1__0_/chanx_right_out[9] +set_disable_timing cbx_1__0_/chanx_left_out[10] +set_disable_timing cbx_1__0_/chanx_right_out[10] +set_disable_timing cbx_1__0_/chanx_right_out[11] +set_disable_timing cbx_1__0_/chanx_left_out[12] +set_disable_timing cbx_1__0_/chanx_right_out[12] +set_disable_timing cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] +set_disable_timing cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] +set_disable_timing cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[1] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[1] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[3] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[1] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[2] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[1] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[3] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[2] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[3] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[2] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[3] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[4] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[5] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[4] +################################################## +# Disable timing for Connection block cbx_1__1_ +################################################## +set_disable_timing cbx_1__1_/chanx_left_in[0] +set_disable_timing cbx_1__1_/chanx_right_in[0] +set_disable_timing cbx_1__1_/chanx_left_in[1] +set_disable_timing cbx_1__1_/chanx_left_in[2] +set_disable_timing cbx_1__1_/chanx_right_in[2] +set_disable_timing cbx_1__1_/chanx_left_in[3] +set_disable_timing cbx_1__1_/chanx_left_in[4] +set_disable_timing cbx_1__1_/chanx_right_in[4] +set_disable_timing cbx_1__1_/chanx_left_in[5] +set_disable_timing cbx_1__1_/chanx_right_in[5] +set_disable_timing cbx_1__1_/chanx_left_in[6] +set_disable_timing cbx_1__1_/chanx_right_in[6] +set_disable_timing cbx_1__1_/chanx_left_in[7] +set_disable_timing cbx_1__1_/chanx_right_in[7] +set_disable_timing cbx_1__1_/chanx_left_in[8] +set_disable_timing cbx_1__1_/chanx_right_in[8] +set_disable_timing cbx_1__1_/chanx_left_in[9] +set_disable_timing cbx_1__1_/chanx_right_in[9] +set_disable_timing cbx_1__1_/chanx_left_in[10] +set_disable_timing cbx_1__1_/chanx_right_in[10] +set_disable_timing cbx_1__1_/chanx_left_in[11] +set_disable_timing cbx_1__1_/chanx_right_in[11] +set_disable_timing cbx_1__1_/chanx_left_in[12] +set_disable_timing cbx_1__1_/chanx_right_in[12] +set_disable_timing cbx_1__1_/chanx_left_out[0] +set_disable_timing cbx_1__1_/chanx_right_out[0] +set_disable_timing cbx_1__1_/chanx_left_out[1] +set_disable_timing cbx_1__1_/chanx_left_out[2] +set_disable_timing cbx_1__1_/chanx_right_out[2] +set_disable_timing cbx_1__1_/chanx_left_out[3] +set_disable_timing cbx_1__1_/chanx_left_out[4] +set_disable_timing cbx_1__1_/chanx_right_out[4] +set_disable_timing cbx_1__1_/chanx_left_out[5] +set_disable_timing cbx_1__1_/chanx_right_out[5] +set_disable_timing cbx_1__1_/chanx_left_out[6] +set_disable_timing cbx_1__1_/chanx_right_out[6] +set_disable_timing cbx_1__1_/chanx_left_out[7] +set_disable_timing cbx_1__1_/chanx_right_out[7] +set_disable_timing cbx_1__1_/chanx_left_out[8] +set_disable_timing cbx_1__1_/chanx_right_out[8] +set_disable_timing cbx_1__1_/chanx_left_out[9] +set_disable_timing cbx_1__1_/chanx_right_out[9] +set_disable_timing cbx_1__1_/chanx_left_out[10] +set_disable_timing cbx_1__1_/chanx_right_out[10] +set_disable_timing cbx_1__1_/chanx_left_out[11] +set_disable_timing cbx_1__1_/chanx_right_out[11] +set_disable_timing cbx_1__1_/chanx_left_out[12] +set_disable_timing cbx_1__1_/chanx_right_out[12] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] +set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] +set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[1] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[0] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[1] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[0] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[1] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[0] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[4] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[4] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[4] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[4] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[4] +################################################## +# Disable timing for Connection block cby_0__1_ +################################################## +set_disable_timing cby_0__1_/chany_bottom_in[0] +set_disable_timing cby_0__1_/chany_top_in[0] +set_disable_timing cby_0__1_/chany_bottom_in[1] +set_disable_timing cby_0__1_/chany_top_in[1] +set_disable_timing cby_0__1_/chany_bottom_in[2] +set_disable_timing cby_0__1_/chany_top_in[2] +set_disable_timing cby_0__1_/chany_bottom_in[3] +set_disable_timing cby_0__1_/chany_top_in[3] +set_disable_timing cby_0__1_/chany_bottom_in[4] +set_disable_timing cby_0__1_/chany_top_in[4] +set_disable_timing cby_0__1_/chany_bottom_in[5] +set_disable_timing cby_0__1_/chany_top_in[5] +set_disable_timing cby_0__1_/chany_bottom_in[6] +set_disable_timing cby_0__1_/chany_top_in[6] +set_disable_timing cby_0__1_/chany_bottom_in[7] +set_disable_timing cby_0__1_/chany_top_in[7] +set_disable_timing cby_0__1_/chany_bottom_in[8] +set_disable_timing cby_0__1_/chany_bottom_in[9] +set_disable_timing cby_0__1_/chany_top_in[9] +set_disable_timing cby_0__1_/chany_bottom_in[10] +set_disable_timing cby_0__1_/chany_bottom_in[11] +set_disable_timing cby_0__1_/chany_top_in[11] +set_disable_timing cby_0__1_/chany_bottom_in[12] +set_disable_timing cby_0__1_/chany_top_in[12] +set_disable_timing cby_0__1_/chany_bottom_out[0] +set_disable_timing cby_0__1_/chany_top_out[0] +set_disable_timing cby_0__1_/chany_bottom_out[1] +set_disable_timing cby_0__1_/chany_top_out[1] +set_disable_timing cby_0__1_/chany_bottom_out[2] +set_disable_timing cby_0__1_/chany_top_out[2] +set_disable_timing cby_0__1_/chany_bottom_out[3] +set_disable_timing cby_0__1_/chany_top_out[3] +set_disable_timing cby_0__1_/chany_bottom_out[4] +set_disable_timing cby_0__1_/chany_top_out[4] +set_disable_timing cby_0__1_/chany_bottom_out[5] +set_disable_timing cby_0__1_/chany_top_out[5] +set_disable_timing cby_0__1_/chany_bottom_out[6] +set_disable_timing cby_0__1_/chany_top_out[6] +set_disable_timing cby_0__1_/chany_bottom_out[7] +set_disable_timing cby_0__1_/chany_top_out[7] +set_disable_timing cby_0__1_/chany_bottom_out[8] +set_disable_timing cby_0__1_/chany_bottom_out[9] +set_disable_timing cby_0__1_/chany_top_out[9] +set_disable_timing cby_0__1_/chany_bottom_out[10] +set_disable_timing cby_0__1_/chany_bottom_out[11] +set_disable_timing cby_0__1_/chany_top_out[11] +set_disable_timing cby_0__1_/chany_bottom_out[12] +set_disable_timing cby_0__1_/chany_top_out[12] +set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] +set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[1] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[1] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[0] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[0] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[1] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[0] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[3] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[2] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[3] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[4] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[5] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[4] +################################################## +# Disable timing for Connection block cby_1__1_ +################################################## +set_disable_timing cby_1__1_/chany_top_in[0] +set_disable_timing cby_1__1_/chany_bottom_in[1] +set_disable_timing cby_1__1_/chany_top_in[1] +set_disable_timing cby_1__1_/chany_top_in[2] +set_disable_timing cby_1__1_/chany_bottom_in[3] +set_disable_timing cby_1__1_/chany_top_in[3] +set_disable_timing cby_1__1_/chany_top_in[4] +set_disable_timing cby_1__1_/chany_bottom_in[5] +set_disable_timing cby_1__1_/chany_top_in[5] +set_disable_timing cby_1__1_/chany_bottom_in[6] +set_disable_timing cby_1__1_/chany_top_in[6] +set_disable_timing cby_1__1_/chany_top_in[7] +set_disable_timing cby_1__1_/chany_bottom_in[8] +set_disable_timing cby_1__1_/chany_top_in[8] +set_disable_timing cby_1__1_/chany_bottom_in[9] +set_disable_timing cby_1__1_/chany_top_in[9] +set_disable_timing cby_1__1_/chany_top_in[10] +set_disable_timing cby_1__1_/chany_bottom_in[11] +set_disable_timing cby_1__1_/chany_top_in[11] +set_disable_timing cby_1__1_/chany_bottom_in[12] +set_disable_timing cby_1__1_/chany_top_in[12] +set_disable_timing cby_1__1_/chany_top_out[0] +set_disable_timing cby_1__1_/chany_bottom_out[1] +set_disable_timing cby_1__1_/chany_top_out[1] +set_disable_timing cby_1__1_/chany_top_out[2] +set_disable_timing cby_1__1_/chany_bottom_out[3] +set_disable_timing cby_1__1_/chany_top_out[3] +set_disable_timing cby_1__1_/chany_top_out[4] +set_disable_timing cby_1__1_/chany_bottom_out[5] +set_disable_timing cby_1__1_/chany_top_out[5] +set_disable_timing cby_1__1_/chany_bottom_out[6] +set_disable_timing cby_1__1_/chany_top_out[6] +set_disable_timing cby_1__1_/chany_top_out[7] +set_disable_timing cby_1__1_/chany_bottom_out[8] +set_disable_timing cby_1__1_/chany_top_out[8] +set_disable_timing cby_1__1_/chany_bottom_out[9] +set_disable_timing cby_1__1_/chany_top_out[9] +set_disable_timing cby_1__1_/chany_top_out[10] +set_disable_timing cby_1__1_/chany_bottom_out[11] +set_disable_timing cby_1__1_/chany_top_out[11] +set_disable_timing cby_1__1_/chany_bottom_out[12] +set_disable_timing cby_1__1_/chany_top_out[12] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] +set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[1] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[0] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[1] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[0] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[1] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[0] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[4] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[5] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[5] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[5] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[5] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[4] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[4] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[4] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[4] +################################################## +# Disable timing for Switch block sb_0__0_ +################################################## +set_disable_timing sb_0__0_/chany_top_out[0] +set_disable_timing sb_0__0_/chany_top_in[0] +set_disable_timing sb_0__0_/chany_top_out[1] +set_disable_timing sb_0__0_/chany_top_in[1] +set_disable_timing sb_0__0_/chany_top_out[2] +set_disable_timing sb_0__0_/chany_top_in[2] +set_disable_timing sb_0__0_/chany_top_out[3] +set_disable_timing sb_0__0_/chany_top_in[3] +set_disable_timing sb_0__0_/chany_top_out[4] +set_disable_timing sb_0__0_/chany_top_in[4] +set_disable_timing sb_0__0_/chany_top_out[5] +set_disable_timing sb_0__0_/chany_top_in[5] +set_disable_timing sb_0__0_/chany_top_out[6] +set_disable_timing sb_0__0_/chany_top_in[6] +set_disable_timing sb_0__0_/chany_top_out[7] +set_disable_timing sb_0__0_/chany_top_in[7] +set_disable_timing sb_0__0_/chany_top_out[8] +set_disable_timing sb_0__0_/chany_top_out[9] +set_disable_timing sb_0__0_/chany_top_in[9] +set_disable_timing sb_0__0_/chany_top_out[10] +set_disable_timing sb_0__0_/chany_top_out[11] +set_disable_timing sb_0__0_/chany_top_in[11] +set_disable_timing sb_0__0_/chany_top_out[12] +set_disable_timing sb_0__0_/chany_top_in[12] +set_disable_timing sb_0__0_/chanx_right_out[0] +set_disable_timing sb_0__0_/chanx_right_in[0] +set_disable_timing sb_0__0_/chanx_right_out[1] +set_disable_timing sb_0__0_/chanx_right_in[1] +set_disable_timing sb_0__0_/chanx_right_out[2] +set_disable_timing sb_0__0_/chanx_right_in[2] +set_disable_timing sb_0__0_/chanx_right_out[3] +set_disable_timing sb_0__0_/chanx_right_in[3] +set_disable_timing sb_0__0_/chanx_right_out[4] +set_disable_timing sb_0__0_/chanx_right_in[4] +set_disable_timing sb_0__0_/chanx_right_out[5] +set_disable_timing sb_0__0_/chanx_right_in[5] +set_disable_timing sb_0__0_/chanx_right_out[6] +set_disable_timing sb_0__0_/chanx_right_in[6] +set_disable_timing sb_0__0_/chanx_right_out[7] +set_disable_timing sb_0__0_/chanx_right_in[7] +set_disable_timing sb_0__0_/chanx_right_out[8] +set_disable_timing sb_0__0_/chanx_right_in[8] +set_disable_timing sb_0__0_/chanx_right_in[9] +set_disable_timing sb_0__0_/chanx_right_out[10] +set_disable_timing sb_0__0_/chanx_right_in[10] +set_disable_timing sb_0__0_/chanx_right_in[11] +set_disable_timing sb_0__0_/chanx_right_out[12] +set_disable_timing sb_0__0_/chanx_right_in[12] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] +set_disable_timing sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_0__0_/mux_top_track_0/in[0] +set_disable_timing sb_0__0_/mux_top_track_12/in[0] +set_disable_timing sb_0__0_/mux_top_track_24/in[0] +set_disable_timing sb_0__0_/mux_top_track_0/in[1] +set_disable_timing sb_0__0_/mux_top_track_2/in[0] +set_disable_timing sb_0__0_/mux_top_track_14/in[0] +set_disable_timing sb_0__0_/mux_top_track_2/in[1] +set_disable_timing sb_0__0_/mux_top_track_4/in[0] +set_disable_timing sb_0__0_/mux_top_track_16/in[0] +set_disable_timing sb_0__0_/mux_top_track_4/in[1] +set_disable_timing sb_0__0_/mux_top_track_6/in[0] +set_disable_timing sb_0__0_/mux_top_track_18/in[0] +set_disable_timing sb_0__0_/mux_top_track_6/in[1] +set_disable_timing sb_0__0_/mux_top_track_8/in[0] +set_disable_timing sb_0__0_/mux_top_track_20/in[0] +set_disable_timing sb_0__0_/mux_top_track_8/in[1] +set_disable_timing sb_0__0_/mux_top_track_10/in[0] +set_disable_timing sb_0__0_/mux_top_track_22/in[0] +set_disable_timing sb_0__0_/mux_top_track_10/in[1] +set_disable_timing sb_0__0_/mux_top_track_12/in[1] +set_disable_timing sb_0__0_/mux_top_track_24/in[1] +set_disable_timing sb_0__0_/mux_top_track_0/in[2] +set_disable_timing sb_0__0_/mux_top_track_12/in[2] +set_disable_timing sb_0__0_/mux_top_track_14/in[1] +set_disable_timing sb_0__0_/mux_top_track_16/in[1] +set_disable_timing sb_0__0_/mux_right_track_0/in[1] +set_disable_timing sb_0__0_/mux_right_track_12/in[1] +set_disable_timing sb_0__0_/mux_right_track_24/in[1] +set_disable_timing sb_0__0_/mux_right_track_0/in[2] +set_disable_timing sb_0__0_/mux_right_track_2/in[1] +set_disable_timing sb_0__0_/mux_right_track_14/in[1] +set_disable_timing sb_0__0_/mux_right_track_2/in[2] +set_disable_timing sb_0__0_/mux_right_track_4/in[1] +set_disable_timing sb_0__0_/mux_right_track_16/in[1] +set_disable_timing sb_0__0_/mux_right_track_4/in[2] +set_disable_timing sb_0__0_/mux_right_track_6/in[1] +set_disable_timing sb_0__0_/mux_right_track_18/in[1] +set_disable_timing sb_0__0_/mux_right_track_6/in[2] +set_disable_timing sb_0__0_/mux_right_track_8/in[1] +set_disable_timing sb_0__0_/mux_right_track_20/in[1] +set_disable_timing sb_0__0_/mux_right_track_8/in[2] +set_disable_timing sb_0__0_/mux_right_track_10/in[1] +set_disable_timing sb_0__0_/mux_right_track_22/in[1] +set_disable_timing sb_0__0_/mux_right_track_10/in[2] +set_disable_timing sb_0__0_/mux_right_track_12/in[2] +set_disable_timing sb_0__0_/mux_right_track_24/in[2] +set_disable_timing sb_0__0_/mux_right_track_0/in[3] +set_disable_timing sb_0__0_/mux_right_track_12/in[3] +set_disable_timing sb_0__0_/mux_right_track_14/in[2] +set_disable_timing sb_0__0_/mux_right_track_2/in[3] +set_disable_timing sb_0__0_/mux_right_track_14/in[3] +set_disable_timing sb_0__0_/mux_right_track_16/in[2] +set_disable_timing sb_0__0_/mux_right_track_2/in[0] +set_disable_timing sb_0__0_/mux_right_track_4/in[0] +set_disable_timing sb_0__0_/mux_right_track_6/in[0] +set_disable_timing sb_0__0_/mux_right_track_8/in[0] +set_disable_timing sb_0__0_/mux_right_track_10/in[0] +set_disable_timing sb_0__0_/mux_right_track_12/in[0] +set_disable_timing sb_0__0_/mux_right_track_14/in[0] +set_disable_timing sb_0__0_/mux_right_track_16/in[0] +set_disable_timing sb_0__0_/mux_right_track_20/in[0] +set_disable_timing sb_0__0_/mux_right_track_24/in[0] +set_disable_timing sb_0__0_/mux_right_track_0/in[0] +set_disable_timing sb_0__0_/mux_top_track_24/in[2] +set_disable_timing sb_0__0_/mux_top_track_0/in[3] +set_disable_timing sb_0__0_/mux_top_track_2/in[2] +set_disable_timing sb_0__0_/mux_top_track_4/in[2] +set_disable_timing sb_0__0_/mux_top_track_6/in[2] +set_disable_timing sb_0__0_/mux_top_track_8/in[2] +set_disable_timing sb_0__0_/mux_top_track_10/in[2] +set_disable_timing sb_0__0_/mux_top_track_12/in[3] +set_disable_timing sb_0__0_/mux_top_track_14/in[2] +set_disable_timing sb_0__0_/mux_top_track_16/in[2] +set_disable_timing sb_0__0_/mux_top_track_18/in[1] +set_disable_timing sb_0__0_/mux_top_track_20/in[1] +set_disable_timing sb_0__0_/mux_top_track_22/in[1] +################################################## +# Disable timing for Switch block sb_0__1_ +################################################## +set_disable_timing sb_0__1_/chanx_right_out[0] +set_disable_timing sb_0__1_/chanx_right_in[0] +set_disable_timing sb_0__1_/chanx_right_out[1] +set_disable_timing sb_0__1_/chanx_right_out[2] +set_disable_timing sb_0__1_/chanx_right_in[2] +set_disable_timing sb_0__1_/chanx_right_out[3] +set_disable_timing sb_0__1_/chanx_right_out[4] +set_disable_timing sb_0__1_/chanx_right_in[4] +set_disable_timing sb_0__1_/chanx_right_out[5] +set_disable_timing sb_0__1_/chanx_right_in[5] +set_disable_timing sb_0__1_/chanx_right_out[6] +set_disable_timing sb_0__1_/chanx_right_in[6] +set_disable_timing sb_0__1_/chanx_right_out[7] +set_disable_timing sb_0__1_/chanx_right_in[7] +set_disable_timing sb_0__1_/chanx_right_out[8] +set_disable_timing sb_0__1_/chanx_right_in[8] +set_disable_timing sb_0__1_/chanx_right_out[9] +set_disable_timing sb_0__1_/chanx_right_in[9] +set_disable_timing sb_0__1_/chanx_right_out[10] +set_disable_timing sb_0__1_/chanx_right_in[10] +set_disable_timing sb_0__1_/chanx_right_out[11] +set_disable_timing sb_0__1_/chanx_right_in[11] +set_disable_timing sb_0__1_/chanx_right_out[12] +set_disable_timing sb_0__1_/chanx_right_in[12] +set_disable_timing sb_0__1_/chany_bottom_in[0] +set_disable_timing sb_0__1_/chany_bottom_out[0] +set_disable_timing sb_0__1_/chany_bottom_in[1] +set_disable_timing sb_0__1_/chany_bottom_out[1] +set_disable_timing sb_0__1_/chany_bottom_in[2] +set_disable_timing sb_0__1_/chany_bottom_out[2] +set_disable_timing sb_0__1_/chany_bottom_in[3] +set_disable_timing sb_0__1_/chany_bottom_out[3] +set_disable_timing sb_0__1_/chany_bottom_in[4] +set_disable_timing sb_0__1_/chany_bottom_out[4] +set_disable_timing sb_0__1_/chany_bottom_in[5] +set_disable_timing sb_0__1_/chany_bottom_out[5] +set_disable_timing sb_0__1_/chany_bottom_in[6] +set_disable_timing sb_0__1_/chany_bottom_out[6] +set_disable_timing sb_0__1_/chany_bottom_in[7] +set_disable_timing sb_0__1_/chany_bottom_out[7] +set_disable_timing sb_0__1_/chany_bottom_in[8] +set_disable_timing sb_0__1_/chany_bottom_in[9] +set_disable_timing sb_0__1_/chany_bottom_out[9] +set_disable_timing sb_0__1_/chany_bottom_in[10] +set_disable_timing sb_0__1_/chany_bottom_in[11] +set_disable_timing sb_0__1_/chany_bottom_out[11] +set_disable_timing sb_0__1_/chany_bottom_in[12] +set_disable_timing sb_0__1_/chany_bottom_out[12] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] +set_disable_timing sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_0__1_/mux_right_track_0/in[0] +set_disable_timing sb_0__1_/mux_right_track_12/in[0] +set_disable_timing sb_0__1_/mux_right_track_24/in[0] +set_disable_timing sb_0__1_/mux_right_track_0/in[1] +set_disable_timing sb_0__1_/mux_right_track_2/in[0] +set_disable_timing sb_0__1_/mux_right_track_14/in[0] +set_disable_timing sb_0__1_/mux_right_track_2/in[1] +set_disable_timing sb_0__1_/mux_right_track_4/in[0] +set_disable_timing sb_0__1_/mux_right_track_16/in[0] +set_disable_timing sb_0__1_/mux_right_track_4/in[1] +set_disable_timing sb_0__1_/mux_right_track_6/in[0] +set_disable_timing sb_0__1_/mux_right_track_18/in[0] +set_disable_timing sb_0__1_/mux_right_track_6/in[1] +set_disable_timing sb_0__1_/mux_right_track_8/in[0] +set_disable_timing sb_0__1_/mux_right_track_20/in[0] +set_disable_timing sb_0__1_/mux_right_track_8/in[1] +set_disable_timing sb_0__1_/mux_right_track_10/in[0] +set_disable_timing sb_0__1_/mux_right_track_22/in[0] +set_disable_timing sb_0__1_/mux_right_track_10/in[1] +set_disable_timing sb_0__1_/mux_right_track_12/in[1] +set_disable_timing sb_0__1_/mux_right_track_24/in[1] +set_disable_timing sb_0__1_/mux_right_track_0/in[2] +set_disable_timing sb_0__1_/mux_right_track_12/in[2] +set_disable_timing sb_0__1_/mux_right_track_14/in[1] +set_disable_timing sb_0__1_/mux_right_track_16/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_1/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_1/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_3/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_15/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_3/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_5/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_17/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_5/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_7/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_19/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_7/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_9/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_21/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_9/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_11/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_23/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_11/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_13/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_25/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_1/in[3] +set_disable_timing sb_0__1_/mux_bottom_track_13/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_15/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_3/in[3] +set_disable_timing sb_0__1_/mux_bottom_track_15/in[3] +set_disable_timing sb_0__1_/mux_bottom_track_17/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_23/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_19/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_15/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_13/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_11/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_9/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_7/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_5/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_3/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_1/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_25/in[0] +set_disable_timing sb_0__1_/mux_right_track_22/in[1] +set_disable_timing sb_0__1_/mux_right_track_20/in[1] +set_disable_timing sb_0__1_/mux_right_track_18/in[1] +set_disable_timing sb_0__1_/mux_right_track_16/in[2] +set_disable_timing sb_0__1_/mux_right_track_14/in[2] +set_disable_timing sb_0__1_/mux_right_track_12/in[3] +set_disable_timing sb_0__1_/mux_right_track_10/in[2] +set_disable_timing sb_0__1_/mux_right_track_8/in[2] +set_disable_timing sb_0__1_/mux_right_track_6/in[2] +set_disable_timing sb_0__1_/mux_right_track_4/in[2] +set_disable_timing sb_0__1_/mux_right_track_2/in[2] +set_disable_timing sb_0__1_/mux_right_track_0/in[3] +set_disable_timing sb_0__1_/mux_right_track_24/in[2] +################################################## +# Disable timing for Switch block sb_1__0_ +################################################## +set_disable_timing sb_1__0_/chany_top_in[0] +set_disable_timing sb_1__0_/chany_top_out[1] +set_disable_timing sb_1__0_/chany_top_in[1] +set_disable_timing sb_1__0_/chany_top_in[2] +set_disable_timing sb_1__0_/chany_top_out[3] +set_disable_timing sb_1__0_/chany_top_in[3] +set_disable_timing sb_1__0_/chany_top_in[4] +set_disable_timing sb_1__0_/chany_top_out[5] +set_disable_timing sb_1__0_/chany_top_in[5] +set_disable_timing sb_1__0_/chany_top_out[6] +set_disable_timing sb_1__0_/chany_top_in[6] +set_disable_timing sb_1__0_/chany_top_in[7] +set_disable_timing sb_1__0_/chany_top_out[8] +set_disable_timing sb_1__0_/chany_top_in[8] +set_disable_timing sb_1__0_/chany_top_out[9] +set_disable_timing sb_1__0_/chany_top_in[9] +set_disable_timing sb_1__0_/chany_top_in[10] +set_disable_timing sb_1__0_/chany_top_out[11] +set_disable_timing sb_1__0_/chany_top_in[11] +set_disable_timing sb_1__0_/chany_top_out[12] +set_disable_timing sb_1__0_/chany_top_in[12] +set_disable_timing sb_1__0_/chanx_left_in[0] +set_disable_timing sb_1__0_/chanx_left_out[0] +set_disable_timing sb_1__0_/chanx_left_in[1] +set_disable_timing sb_1__0_/chanx_left_out[1] +set_disable_timing sb_1__0_/chanx_left_in[2] +set_disable_timing sb_1__0_/chanx_left_out[2] +set_disable_timing sb_1__0_/chanx_left_in[3] +set_disable_timing sb_1__0_/chanx_left_out[3] +set_disable_timing sb_1__0_/chanx_left_in[4] +set_disable_timing sb_1__0_/chanx_left_out[4] +set_disable_timing sb_1__0_/chanx_left_in[5] +set_disable_timing sb_1__0_/chanx_left_out[5] +set_disable_timing sb_1__0_/chanx_left_in[6] +set_disable_timing sb_1__0_/chanx_left_out[6] +set_disable_timing sb_1__0_/chanx_left_in[7] +set_disable_timing sb_1__0_/chanx_left_out[7] +set_disable_timing sb_1__0_/chanx_left_in[8] +set_disable_timing sb_1__0_/chanx_left_out[8] +set_disable_timing sb_1__0_/chanx_left_out[9] +set_disable_timing sb_1__0_/chanx_left_in[10] +set_disable_timing sb_1__0_/chanx_left_out[10] +set_disable_timing sb_1__0_/chanx_left_out[11] +set_disable_timing sb_1__0_/chanx_left_in[12] +set_disable_timing sb_1__0_/chanx_left_out[12] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_1__0_/mux_top_track_0/in[1] +set_disable_timing sb_1__0_/mux_top_track_2/in[0] +set_disable_timing sb_1__0_/mux_top_track_14/in[0] +set_disable_timing sb_1__0_/mux_top_track_2/in[1] +set_disable_timing sb_1__0_/mux_top_track_4/in[0] +set_disable_timing sb_1__0_/mux_top_track_16/in[0] +set_disable_timing sb_1__0_/mux_top_track_4/in[1] +set_disable_timing sb_1__0_/mux_top_track_6/in[0] +set_disable_timing sb_1__0_/mux_top_track_18/in[0] +set_disable_timing sb_1__0_/mux_top_track_6/in[1] +set_disable_timing sb_1__0_/mux_top_track_8/in[0] +set_disable_timing sb_1__0_/mux_top_track_8/in[1] +set_disable_timing sb_1__0_/mux_top_track_10/in[0] +set_disable_timing sb_1__0_/mux_top_track_22/in[0] +set_disable_timing sb_1__0_/mux_top_track_10/in[1] +set_disable_timing sb_1__0_/mux_top_track_12/in[0] +set_disable_timing sb_1__0_/mux_top_track_24/in[0] +set_disable_timing sb_1__0_/mux_top_track_0/in[2] +set_disable_timing sb_1__0_/mux_top_track_12/in[1] +set_disable_timing sb_1__0_/mux_top_track_2/in[2] +set_disable_timing sb_1__0_/mux_top_track_14/in[2] +set_disable_timing sb_1__0_/mux_top_track_16/in[1] +set_disable_timing sb_1__0_/mux_left_track_1/in[1] +set_disable_timing sb_1__0_/mux_left_track_13/in[1] +set_disable_timing sb_1__0_/mux_left_track_25/in[1] +set_disable_timing sb_1__0_/mux_left_track_1/in[2] +set_disable_timing sb_1__0_/mux_left_track_3/in[1] +set_disable_timing sb_1__0_/mux_left_track_15/in[1] +set_disable_timing sb_1__0_/mux_left_track_3/in[2] +set_disable_timing sb_1__0_/mux_left_track_5/in[1] +set_disable_timing sb_1__0_/mux_left_track_17/in[1] +set_disable_timing sb_1__0_/mux_left_track_5/in[2] +set_disable_timing sb_1__0_/mux_left_track_7/in[1] +set_disable_timing sb_1__0_/mux_left_track_19/in[1] +set_disable_timing sb_1__0_/mux_left_track_7/in[2] +set_disable_timing sb_1__0_/mux_left_track_9/in[1] +set_disable_timing sb_1__0_/mux_left_track_21/in[1] +set_disable_timing sb_1__0_/mux_left_track_9/in[2] +set_disable_timing sb_1__0_/mux_left_track_11/in[1] +set_disable_timing sb_1__0_/mux_left_track_23/in[1] +set_disable_timing sb_1__0_/mux_left_track_11/in[2] +set_disable_timing sb_1__0_/mux_left_track_13/in[2] +set_disable_timing sb_1__0_/mux_left_track_25/in[2] +set_disable_timing sb_1__0_/mux_left_track_1/in[3] +set_disable_timing sb_1__0_/mux_left_track_13/in[3] +set_disable_timing sb_1__0_/mux_left_track_15/in[2] +set_disable_timing sb_1__0_/mux_left_track_3/in[3] +set_disable_timing sb_1__0_/mux_left_track_15/in[3] +set_disable_timing sb_1__0_/mux_left_track_17/in[2] +set_disable_timing sb_1__0_/mux_left_track_1/in[0] +set_disable_timing sb_1__0_/mux_left_track_25/in[0] +set_disable_timing sb_1__0_/mux_left_track_23/in[0] +set_disable_timing sb_1__0_/mux_left_track_21/in[0] +set_disable_timing sb_1__0_/mux_left_track_19/in[0] +set_disable_timing sb_1__0_/mux_left_track_17/in[0] +set_disable_timing sb_1__0_/mux_left_track_15/in[0] +set_disable_timing sb_1__0_/mux_left_track_13/in[0] +set_disable_timing sb_1__0_/mux_left_track_11/in[0] +set_disable_timing sb_1__0_/mux_left_track_9/in[0] +set_disable_timing sb_1__0_/mux_left_track_7/in[0] +set_disable_timing sb_1__0_/mux_left_track_5/in[0] +set_disable_timing sb_1__0_/mux_left_track_3/in[0] +set_disable_timing sb_1__0_/mux_top_track_0/in[3] +set_disable_timing sb_1__0_/mux_top_track_24/in[1] +set_disable_timing sb_1__0_/mux_top_track_22/in[1] +set_disable_timing sb_1__0_/mux_top_track_20/in[1] +set_disable_timing sb_1__0_/mux_top_track_18/in[1] +set_disable_timing sb_1__0_/mux_top_track_16/in[2] +set_disable_timing sb_1__0_/mux_top_track_14/in[3] +set_disable_timing sb_1__0_/mux_top_track_12/in[2] +set_disable_timing sb_1__0_/mux_top_track_10/in[2] +set_disable_timing sb_1__0_/mux_top_track_6/in[2] +set_disable_timing sb_1__0_/mux_top_track_2/in[3] +################################################## +# Disable timing for Switch block sb_1__1_ +################################################## +set_disable_timing sb_1__1_/chany_bottom_out[0] +set_disable_timing sb_1__1_/chany_bottom_in[1] +set_disable_timing sb_1__1_/chany_bottom_out[1] +set_disable_timing sb_1__1_/chany_bottom_out[2] +set_disable_timing sb_1__1_/chany_bottom_in[3] +set_disable_timing sb_1__1_/chany_bottom_out[3] +set_disable_timing sb_1__1_/chany_bottom_out[4] +set_disable_timing sb_1__1_/chany_bottom_in[5] +set_disable_timing sb_1__1_/chany_bottom_out[5] +set_disable_timing sb_1__1_/chany_bottom_in[6] +set_disable_timing sb_1__1_/chany_bottom_out[6] +set_disable_timing sb_1__1_/chany_bottom_out[7] +set_disable_timing sb_1__1_/chany_bottom_in[8] +set_disable_timing sb_1__1_/chany_bottom_out[8] +set_disable_timing sb_1__1_/chany_bottom_in[9] +set_disable_timing sb_1__1_/chany_bottom_out[9] +set_disable_timing sb_1__1_/chany_bottom_out[10] +set_disable_timing sb_1__1_/chany_bottom_in[11] +set_disable_timing sb_1__1_/chany_bottom_out[11] +set_disable_timing sb_1__1_/chany_bottom_in[12] +set_disable_timing sb_1__1_/chany_bottom_out[12] +set_disable_timing sb_1__1_/chanx_left_in[0] +set_disable_timing sb_1__1_/chanx_left_out[0] +set_disable_timing sb_1__1_/chanx_left_in[1] +set_disable_timing sb_1__1_/chanx_left_in[2] +set_disable_timing sb_1__1_/chanx_left_out[2] +set_disable_timing sb_1__1_/chanx_left_in[3] +set_disable_timing sb_1__1_/chanx_left_in[4] +set_disable_timing sb_1__1_/chanx_left_out[4] +set_disable_timing sb_1__1_/chanx_left_in[5] +set_disable_timing sb_1__1_/chanx_left_out[5] +set_disable_timing sb_1__1_/chanx_left_in[6] +set_disable_timing sb_1__1_/chanx_left_out[6] +set_disable_timing sb_1__1_/chanx_left_in[7] +set_disable_timing sb_1__1_/chanx_left_out[7] +set_disable_timing sb_1__1_/chanx_left_in[8] +set_disable_timing sb_1__1_/chanx_left_out[8] +set_disable_timing sb_1__1_/chanx_left_in[9] +set_disable_timing sb_1__1_/chanx_left_out[9] +set_disable_timing sb_1__1_/chanx_left_in[10] +set_disable_timing sb_1__1_/chanx_left_out[10] +set_disable_timing sb_1__1_/chanx_left_in[11] +set_disable_timing sb_1__1_/chanx_left_out[11] +set_disable_timing sb_1__1_/chanx_left_in[12] +set_disable_timing sb_1__1_/chanx_left_out[12] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] +set_disable_timing sb_1__1_/mux_bottom_track_1/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_13/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_25/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_1/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_3/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_15/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_3/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_5/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_17/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_5/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_7/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_19/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_7/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_9/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_21/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_9/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_11/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_23/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_11/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_13/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_25/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_1/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_13/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_15/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_17/in[1] +set_disable_timing sb_1__1_/mux_left_track_1/in[1] +set_disable_timing sb_1__1_/mux_left_track_13/in[1] +set_disable_timing sb_1__1_/mux_left_track_25/in[1] +set_disable_timing sb_1__1_/mux_left_track_1/in[2] +set_disable_timing sb_1__1_/mux_left_track_3/in[1] +set_disable_timing sb_1__1_/mux_left_track_15/in[1] +set_disable_timing sb_1__1_/mux_left_track_3/in[2] +set_disable_timing sb_1__1_/mux_left_track_5/in[1] +set_disable_timing sb_1__1_/mux_left_track_17/in[1] +set_disable_timing sb_1__1_/mux_left_track_5/in[2] +set_disable_timing sb_1__1_/mux_left_track_7/in[1] +set_disable_timing sb_1__1_/mux_left_track_19/in[1] +set_disable_timing sb_1__1_/mux_left_track_7/in[2] +set_disable_timing sb_1__1_/mux_left_track_9/in[1] +set_disable_timing sb_1__1_/mux_left_track_21/in[1] +set_disable_timing sb_1__1_/mux_left_track_9/in[2] +set_disable_timing sb_1__1_/mux_left_track_11/in[1] +set_disable_timing sb_1__1_/mux_left_track_23/in[1] +set_disable_timing sb_1__1_/mux_left_track_11/in[2] +set_disable_timing sb_1__1_/mux_left_track_13/in[2] +set_disable_timing sb_1__1_/mux_left_track_25/in[2] +set_disable_timing sb_1__1_/mux_left_track_1/in[3] +set_disable_timing sb_1__1_/mux_left_track_13/in[3] +set_disable_timing sb_1__1_/mux_left_track_15/in[2] +set_disable_timing sb_1__1_/mux_left_track_17/in[2] +set_disable_timing sb_1__1_/mux_left_track_5/in[0] +set_disable_timing sb_1__1_/mux_left_track_9/in[0] +set_disable_timing sb_1__1_/mux_left_track_11/in[0] +set_disable_timing sb_1__1_/mux_left_track_13/in[0] +set_disable_timing sb_1__1_/mux_left_track_15/in[0] +set_disable_timing sb_1__1_/mux_left_track_17/in[0] +set_disable_timing sb_1__1_/mux_left_track_19/in[0] +set_disable_timing sb_1__1_/mux_left_track_21/in[0] +set_disable_timing sb_1__1_/mux_left_track_23/in[0] +set_disable_timing sb_1__1_/mux_left_track_25/in[0] +set_disable_timing sb_1__1_/mux_left_track_1/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_25/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_1/in[3] +set_disable_timing sb_1__1_/mux_bottom_track_3/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_5/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_7/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_9/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_11/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_13/in[3] +set_disable_timing sb_1__1_/mux_bottom_track_15/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_17/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_19/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_21/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_23/in[1] +####################################### +# Disable Timing for grid[1][1] +####################################### +####################################### +# Disable Timing for unused resources in grid[1][1][0] +####################################### +####################################### +# Disable unused pins for pb_graph_node clb[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[4] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[5] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[6] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[7] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[8] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node clb[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[7] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//direct_interc_7_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13] +####################################### +# Disable unused pins for pb_graph_node fle[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable unused pins for pb_graph_node fle[1] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[1] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable unused pins for pb_graph_node fle[2] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[2] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable unused pins for pb_graph_node fle[3] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[3] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_5_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable Timing for grid[1][2] +####################################### +####################################### +# Disable Timing for unused grid[1][2][0] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][1] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][2] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__2/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][3] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__3/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][4] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__4/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][5] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__5/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][6] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__6/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][7] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__7/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for grid[2][1] +####################################### +####################################### +# Disable Timing for unused grid[2][1][0] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__0/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[2][1][1] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__1/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[2][1][2] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused resources in grid[2][1][3] +####################################### +####################################### +# Disable unused pins for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/io_outpad[0] +####################################### +# Disable unused mux_inputs for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] +####################################### +# Disable Timing for unused resources in grid[2][1][4] +####################################### +####################################### +# Disable unused pins for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0] +####################################### +# Disable unused mux_inputs for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] +####################################### +# Disable Timing for unused grid[2][1][5] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__5/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused resources in grid[2][1][6] +####################################### +####################################### +# Disable unused pins for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/io_outpad[0] +####################################### +# Disable unused mux_inputs for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] +####################################### +# Disable Timing for unused grid[2][1][7] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for grid[1][0] +####################################### +####################################### +# Disable Timing for unused grid[1][0][0] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__0/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][1] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__1/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][2] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__2/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][3] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__3/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][4] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__4/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][5] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__5/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][6] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__6/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][7] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__7/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for grid[0][1] +####################################### +####################################### +# Disable Timing for unused grid[0][1][0] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][1] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][2] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][3] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][4] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__4/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][5] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__5/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][6] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__6/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][7] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__7/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_include_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_include_netlists.v new file mode 100644 index 000000000..69009dff8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_include_netlists.v @@ -0,0 +1,16 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include fabric top-level netlists ----- +`include "fabric_netlists.v" + +`include "and2_output_verilog.v" + +`include "and2_top_formal_verification.v" +`include "and2_formal_random_top_tb.v" diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v new file mode 100644 index 000000000..0e26d2bc1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -0,0 +1,513 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog netlist for pre-configured FPGA fabric by design: and2 +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +module and2_top_formal_verification ( +input [0:0] a, +input [0:0] b, +output [0:0] c); + +// ----- Local wires for FPGA fabric ----- +wire [0:31] gfpga_pad_GPIO_PAD_fm; +wire [0:0] ccff_head_fm; +wire [0:0] ccff_tail_fm; +wire [0:0] prog_clk_fm; +wire [0:0] set_fm; +wire [0:0] reset_fm; +wire [0:0] clk_fm; + +// ----- FPGA top-level module to be capsulated ----- + fpga_top U0_formal_verification ( + .prog_clk(prog_clk_fm[0]), + .set(set_fm[0]), + .reset(reset_fm[0]), + .clk(clk_fm[0]), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD_fm[0:31]), + .ccff_head(ccff_head_fm[0]), + .ccff_tail(ccff_tail_fm[0])); + +// ----- Begin Connect Global ports of FPGA top module ----- + assign set_fm[0] = 1'b0; + assign reset_fm[0] = 1'b0; + assign clk_fm[0] = 1'b0; + assign prog_clk_fm[0] = 1'b0; +// ----- End Connect Global ports of FPGA top module ----- + +// ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- +// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] ----- + assign gfpga_pad_GPIO_PAD_fm[11] = a[0]; + +// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[14] ----- + assign gfpga_pad_GPIO_PAD_fm[14] = b[0]; + +// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] ----- + assign c[0] = gfpga_pad_GPIO_PAD_fm[12]; + +// ----- Wire unused FPGA I/Os to constants ----- + assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[1] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[5] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[6] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[19] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[20] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[21] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[30] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[31] = 1'b0; + +// ----- Begin load bitstream to configuration memories ----- +// ----- Begin assign bitstream to configuration memories ----- +initial begin + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_2.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_3.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_1.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_2.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_3.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_1.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0110; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1001; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0111; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_12.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_12.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01; + force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01; + force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:2] = 3'b011; + force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:2] = 3'b100; + force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_4.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_5.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_6.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_7.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010; + force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = 3'b101; + force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = 3'b010; + force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = 3'b110; + force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:2] = 3'b001; +end +// ----- End assign bitstream to configuration memories ----- +// ----- End load bitstream to configuration memories ----- +// ------ Use DUMP_FSDB to enable FSDB waveform output ----- +`ifdef DUMP_FSDB +initial begin + $fsdbDumpfile("and2.fsdb"); + $fsdbDumpvars(0, "U0_formal_verification"); +end +`endif +// ------ Use DUMP_VCD to enable VCD waveform output ----- +`ifdef DUMP_VCD +initial begin + $dumpfile("and2.vcd"); + $dumpvars(0, "U0_formal_verification"); +end +`endif +endmodule +// ----- END Verilog module for and2_top_formal_verification ----- + +//----- Default net type ----- +`default_nettype wire + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/bitstream_distribution.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/bitstream_distribution.xml new file mode 100644 index 000000000..34701b8fb --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/bitstream_distribution.xml @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__0_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__0_.sdc new file mode 100644 index 000000000..01be1d8ca --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__0_.sdc @@ -0,0 +1,105 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cbx_1__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__1_.sdc new file mode 100644 index 000000000..414bba436 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__1_.sdc @@ -0,0 +1,105 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cbx_1__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_0__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_0__1_.sdc new file mode 100644 index 000000000..c5f0741b7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_0__1_.sdc @@ -0,0 +1,99 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cby_0__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_1__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_1__1_.sdc new file mode 100644 index 000000000..c033fd624 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_1__1_.sdc @@ -0,0 +1,105 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cby_1__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc new file mode 100644 index 000000000..5a3b9e3df --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -0,0 +1,1065 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for configurable chains used in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time ns + +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_2_/Q -to fpga_top/sb_0__0_/mem_top_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_2_/Q -to fpga_top/sb_0__0_/mem_top_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_20/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_20/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_20/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_20/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_22/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_22/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_24/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_24/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_20/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_20/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_20/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_20/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_22/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_22/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_22/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_22/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_24/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_24/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc new file mode 100644 index 000000000..8cd7edd67 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -0,0 +1,86 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable configurable memory outputs for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configure_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configure_ports.sdc new file mode 100644 index 000000000..8b39a842d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configure_ports.sdc @@ -0,0 +1,82 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable configuration outputs of all the programmable cells for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_*_/sram +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_*_/sram_inv +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram_inv +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram_inv +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram_inv +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_routing_multiplexer_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_routing_multiplexer_outputs.sdc new file mode 100644 index 000000000..b8ed3a616 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_routing_multiplexer_outputs.sdc @@ -0,0 +1,42 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable routing multiplexer outputs for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/out +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/out +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/out diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_sb_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_sb_outputs.sdc new file mode 100644 index 000000000..f8c3c394f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_sb_outputs.sdc @@ -0,0 +1,32 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable Switch Block outputs for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +set_disable_timing fpga_top/sb_*__*_/chany_top_out + +set_disable_timing fpga_top/sb_*__*_/chanx_right_out + +set_disable_timing fpga_top/sb_*__*_/ccff_tail + +set_disable_timing fpga_top/sb_*__*_/chanx_right_out + +set_disable_timing fpga_top/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_top/sb_*__*_/ccff_tail + +set_disable_timing fpga_top/sb_*__*_/chany_top_out + +set_disable_timing fpga_top/sb_*__*_/chanx_left_out + +set_disable_timing fpga_top/sb_*__*_/ccff_tail + +set_disable_timing fpga_top/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_top/sb_*__*_/chanx_left_out + +set_disable_timing fpga_top/sb_*__*_/ccff_tail + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit new file mode 100644 index 000000000..f116aa10c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -0,0 +1,530 @@ +// Fabric bitstream +// Bitstream length: 527 +// Bitstream width (LSB -> MSB): 1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +1 +0 +1 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +1 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +1 +0 +0 +0 +1 +1 +1 +0 +0 +1 +1 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml new file mode 100644 index 000000000..12a7a85bd --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -0,0 +1,1064 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml new file mode 100644 index 000000000..283d346ab --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml @@ -0,0 +1,4047 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_io_location.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_io_location.xml new file mode 100644 index 000000000..e7000bde6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_io_location.xml @@ -0,0 +1,39 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_netlists.v new file mode 100644 index 000000000..053caefe2 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_netlists.v @@ -0,0 +1,52 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Fabric Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ------ Include defines: preproc flags ----- +`include "fpga_defines.v" + +// ------ Include user-defined netlists ----- +`include "openfpga_flow/openfpga_cell_library/verilog/dff.v" +`include "openfpga_flow/openfpga_cell_library/verilog/gpio.v" +// ------ Include primitive module netlists ----- +`include "sub_module/inv_buf_passgate.v" +`include "sub_module/arch_encoder.v" +`include "sub_module/local_encoder.v" +`include "sub_module/mux_primitives.v" +`include "sub_module/muxes.v" +`include "sub_module/luts.v" +`include "sub_module/wires.v" +`include "sub_module/memories.v" +`include "sub_module/shift_register_banks.v" + +// ------ Include logic block netlists ----- +`include "lb/logical_tile_io_mode_physical__iopad.v" +`include "lb/logical_tile_io_mode_io_.v" +`include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v" +`include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v" +`include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v" +`include "lb/logical_tile_clb_mode_default__fle.v" +`include "lb/logical_tile_clb_mode_clb_.v" +`include "lb/grid_io_top.v" +`include "lb/grid_io_right.v" +`include "lb/grid_io_bottom.v" +`include "lb/grid_io_left.v" +`include "lb/grid_clb.v" + +// ------ Include routing module netlists ----- +`include "routing/sb_0__0_.v" +`include "routing/sb_0__1_.v" +`include "routing/sb_1__0_.v" +`include "routing/sb_1__1_.v" +`include "routing/cbx_1__0_.v" +`include "routing/cbx_1__1_.v" +`include "routing/cby_0__1_.v" +`include "routing/cby_1__1_.v" + +// ------ Include tile module netlists ----- + +// ------ Include fabric top-level netlists ----- +`include "fpga_top.v" + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml new file mode 100644 index 000000000..603d120a5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml @@ -0,0 +1,644 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_defines.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_defines.v new file mode 100644 index 000000000..82aab8ef1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_defines.v @@ -0,0 +1,8 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Preprocessing flags to enable/disable features in FPGA Verilog modules +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +`define ENABLE_TIMING 1 + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v new file mode 100644 index 000000000..e0098e212 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v @@ -0,0 +1,460 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Top-level Verilog module for FPGA +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for fpga_top ----- +module fpga_top(prog_clk, + set, + reset, + clk, + gfpga_pad_GPIO_PAD, + ccff_head, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- GPIO PORTS ----- +inout [0:31] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_; +wire [0:0] cbx_1__0__0_ccff_tail; +wire [0:12] cbx_1__0__0_chanx_left_out; +wire [0:12] cbx_1__0__0_chanx_right_out; +wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_; +wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_; +wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_; +wire [0:0] cbx_1__1__0_ccff_tail; +wire [0:12] cbx_1__1__0_chanx_left_out; +wire [0:12] cbx_1__1__0_chanx_right_out; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_; +wire [0:0] cby_0__1__0_ccff_tail; +wire [0:12] cby_0__1__0_chany_bottom_out; +wire [0:12] cby_0__1__0_chany_top_out; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_; +wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_; +wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_; +wire [0:0] cby_1__1__0_ccff_tail; +wire [0:12] cby_1__1__0_chany_bottom_out; +wire [0:12] cby_1__1__0_chany_top_out; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_; +wire [0:0] grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_io_bottom_0_ccff_tail; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_; +wire [0:0] grid_io_left_0_ccff_tail; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_; +wire [0:0] grid_io_right_0_ccff_tail; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_; +wire [0:0] grid_io_top_0_ccff_tail; +wire [0:0] sb_0__0__0_ccff_tail; +wire [0:12] sb_0__0__0_chanx_right_out; +wire [0:12] sb_0__0__0_chany_top_out; +wire [0:0] sb_0__1__0_ccff_tail; +wire [0:12] sb_0__1__0_chanx_right_out; +wire [0:12] sb_0__1__0_chany_bottom_out; +wire [0:0] sb_1__0__0_ccff_tail; +wire [0:12] sb_1__0__0_chanx_left_out; +wire [0:12] sb_1__0__0_chany_top_out; +wire [0:0] sb_1__1__0_ccff_tail; +wire [0:12] sb_1__1__0_chanx_left_out; +wire [0:12] sb_1__1__0_chany_bottom_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + grid_io_top grid_io_top_1__2_ ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0:7]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_), + .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), + .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), + .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(grid_io_right_0_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_), + .bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), + .bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), + .bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(grid_io_top_0_ccff_tail)); + + grid_io_right grid_io_right_2__1_ ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[8:15]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_), + .left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_), + .left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_), + .left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(grid_io_bottom_0_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_), + .left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_), + .left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_), + .left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(grid_io_right_0_ccff_tail)); + + grid_io_bottom grid_io_bottom_1__0_ ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[16:23]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_), + .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), + .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), + .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(cbx_1__0__0_ccff_tail), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_), + .top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), + .top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), + .top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(grid_io_bottom_0_ccff_tail)); + + grid_io_left grid_io_left_0__1_ ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[24:31]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_), + .right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_), + .right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_), + .right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(cby_0__1__0_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_), + .right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), + .right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), + .right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(grid_io_left_0_ccff_tail)); + + grid_clb grid_clb_1__1_ ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_), + .top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_), + .top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_), + .right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_), + .right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_), + .right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_), + .bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_), + .bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_), + .bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_), + .left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), + .left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_), + .ccff_head(cby_1__1__0_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_), + .bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_), + .left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_), + .ccff_tail(ccff_tail)); + + sb_0__0_ sb_0__0_ ( + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__0_chany_bottom_out[0:12]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_), + .chanx_right_in(cbx_1__0__0_chanx_left_out[0:12]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_head(ccff_head), + .chany_top_out(sb_0__0__0_chany_top_out[0:12]), + .chanx_right_out(sb_0__0__0_chanx_right_out[0:12]), + .ccff_tail(sb_0__0__0_ccff_tail)); + + sb_0__1_ sb_0__1_ ( + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__1__0_chanx_left_out[0:12]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .chany_bottom_in(cby_0__1__0_chany_top_out[0:12]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_head(grid_io_top_0_ccff_tail), + .chanx_right_out(sb_0__1__0_chanx_right_out[0:12]), + .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:12]), + .ccff_tail(sb_0__1__0_ccff_tail)); + + sb_1__0_ sb_1__0_ ( + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__0_chany_bottom_out[0:12]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_), + .chanx_left_in(cbx_1__0__0_chanx_right_out[0:12]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_head(sb_0__0__0_ccff_tail), + .chany_top_out(sb_1__0__0_chany_top_out[0:12]), + .chanx_left_out(sb_1__0__0_chanx_left_out[0:12]), + .ccff_tail(sb_1__0__0_ccff_tail)); + + sb_1__1_ sb_1__1_ ( + .prog_clk(prog_clk), + .chany_bottom_in(cby_1__1__0_chany_top_out[0:12]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_), + .chanx_left_in(cbx_1__1__0_chanx_right_out[0:12]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .ccff_head(grid_io_left_0_ccff_tail), + .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]), + .chanx_left_out(sb_1__1__0_chanx_left_out[0:12]), + .ccff_tail(sb_1__1__0_ccff_tail)); + + cbx_1__0_ cbx_1__0_ ( + .prog_clk(prog_clk), + .chanx_left_in(sb_0__0__0_chanx_right_out[0:12]), + .chanx_right_in(sb_1__0__0_chanx_left_out[0:12]), + .ccff_head(sb_1__0__0_ccff_tail), + .chanx_left_out(cbx_1__0__0_chanx_left_out[0:12]), + .chanx_right_out(cbx_1__0__0_chanx_right_out[0:12]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_), + .top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_), + .top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_tail(cbx_1__0__0_ccff_tail)); + + cbx_1__1_ cbx_1__1_ ( + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__0_chanx_right_out[0:12]), + .chanx_right_in(sb_1__1__0_chanx_left_out[0:12]), + .ccff_head(sb_1__1__0_ccff_tail), + .chanx_left_out(cbx_1__1__0_chanx_left_out[0:12]), + .chanx_right_out(cbx_1__1__0_chanx_right_out[0:12]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_), + .ccff_tail(cbx_1__1__0_ccff_tail)); + + cby_0__1_ cby_0__1_ ( + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__0__0_chany_top_out[0:12]), + .chany_top_in(sb_0__1__0_chany_bottom_out[0:12]), + .ccff_head(sb_0__1__0_ccff_tail), + .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]), + .chany_top_out(cby_0__1__0_chany_top_out[0:12]), + .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), + .right_grid_left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_tail(cby_0__1__0_ccff_tail)); + + cby_1__1_ cby_1__1_ ( + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__0_chany_top_out[0:12]), + .chany_top_in(sb_1__1__0_chany_bottom_out[0:12]), + .ccff_head(cbx_1__1__0_ccff_tail), + .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]), + .chany_top_out(cby_1__1__0_chany_top_out[0:12]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_), + .left_grid_right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_), + .ccff_tail(cby_1__1__0_ccff_tail)); + +endmodule +// ----- END Verilog module for fpga_top ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc new file mode 100644 index 000000000..c169fa409 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc @@ -0,0 +1,21 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Clock contraints for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +################################################## +# Create clock +################################################## +create_clock -name clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} [get_ports {clk[0]}] +################################################## +# Create programmable clock +################################################## +create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}] diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml new file mode 100644 index 000000000..88ecd4adb --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml new file mode 100644 index 000000000..e65930df0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml new file mode 100644 index 000000000..39781ad36 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml new file mode 100644 index 000000000..660956573 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml new file mode 100644 index 000000000..1943afce4 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml new file mode 100644 index 000000000..f0437dd4b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml new file mode 100644 index 000000000..d4af896d6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml new file mode 100644 index 000000000..fe935ebef --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml new file mode 100644 index 000000000..6a92006a5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml new file mode 100644 index 000000000..24b0e8590 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml new file mode 100644 index 000000000..10e1516e5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml new file mode 100644 index 000000000..7725a1d9d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml new file mode 100644 index 000000000..88ecd4adb --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml new file mode 100644 index 000000000..e65930df0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml new file mode 100644 index 000000000..1bb2753a1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml new file mode 100644 index 000000000..aa95d1a45 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml new file mode 100644 index 000000000..0e17019b1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml new file mode 100644 index 000000000..f0437dd4b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml new file mode 100644 index 000000000..010e9b689 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml new file mode 100644 index 000000000..fe935ebef --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml new file mode 100644 index 000000000..e1012a9b1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml new file mode 100644 index 000000000..18eb5f107 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml new file mode 100644 index 000000000..fcf4a8552 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml new file mode 100644 index 000000000..86d1919ea --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_clb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_clb.v new file mode 100644 index 000000000..d7433dd3f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_clb.v @@ -0,0 +1,110 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: clb] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_clb ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_clb ----- +module grid_clb(prog_clk, + set, + reset, + clk, + top_width_0_height_0_subtile_0__pin_I_0_, + top_width_0_height_0_subtile_0__pin_I_4_, + top_width_0_height_0_subtile_0__pin_I_8_, + right_width_0_height_0_subtile_0__pin_I_1_, + right_width_0_height_0_subtile_0__pin_I_5_, + right_width_0_height_0_subtile_0__pin_I_9_, + bottom_width_0_height_0_subtile_0__pin_I_2_, + bottom_width_0_height_0_subtile_0__pin_I_6_, + bottom_width_0_height_0_subtile_0__pin_clk_0_, + left_width_0_height_0_subtile_0__pin_I_3_, + left_width_0_height_0_subtile_0__pin_I_7_, + ccff_head, + top_width_0_height_0_subtile_0__pin_O_2_, + right_width_0_height_0_subtile_0__pin_O_3_, + bottom_width_0_height_0_subtile_0__pin_O_0_, + left_width_0_height_0_subtile_0__pin_O_1_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_0__pin_I_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_0__pin_I_4_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_0__pin_I_8_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_0__pin_I_1_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_0__pin_I_5_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_0__pin_I_9_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_0__pin_I_2_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_0__pin_I_6_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_0__pin_clk_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_0__pin_I_3_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_0__pin_I_7_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_0__pin_O_2_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_0__pin_O_3_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_0__pin_O_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_0__pin_O_1_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .clb_I({top_width_0_height_0_subtile_0__pin_I_0_, right_width_0_height_0_subtile_0__pin_I_1_, bottom_width_0_height_0_subtile_0__pin_I_2_, left_width_0_height_0_subtile_0__pin_I_3_, top_width_0_height_0_subtile_0__pin_I_4_, right_width_0_height_0_subtile_0__pin_I_5_, bottom_width_0_height_0_subtile_0__pin_I_6_, left_width_0_height_0_subtile_0__pin_I_7_, top_width_0_height_0_subtile_0__pin_I_8_, right_width_0_height_0_subtile_0__pin_I_9_}), + .clb_clk(bottom_width_0_height_0_subtile_0__pin_clk_0_), + .ccff_head(ccff_head), + .clb_O({bottom_width_0_height_0_subtile_0__pin_O_0_, left_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, right_width_0_height_0_subtile_0__pin_O_3_}), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_clb ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_clb ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_bottom.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_bottom.v new file mode 100644 index 000000000..9ff8b229f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_bottom.v @@ -0,0 +1,167 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: io] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_io_bottom ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_io_bottom ----- +module grid_io_bottom(prog_clk, + gfpga_pad_GPIO_PAD, + top_width_0_height_0_subtile_0__pin_outpad_0_, + top_width_0_height_0_subtile_1__pin_outpad_0_, + top_width_0_height_0_subtile_2__pin_outpad_0_, + top_width_0_height_0_subtile_3__pin_outpad_0_, + top_width_0_height_0_subtile_4__pin_outpad_0_, + top_width_0_height_0_subtile_5__pin_outpad_0_, + top_width_0_height_0_subtile_6__pin_outpad_0_, + top_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_head, + top_width_0_height_0_subtile_0__pin_inpad_0_, + top_width_0_height_0_subtile_1__pin_inpad_0_, + top_width_0_height_0_subtile_2__pin_inpad_0_, + top_width_0_height_0_subtile_3__pin_inpad_0_, + top_width_0_height_0_subtile_4__pin_inpad_0_, + top_width_0_height_0_subtile_5__pin_inpad_0_, + top_width_0_height_0_subtile_6__pin_inpad_0_, + top_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:7] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]), + .io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]), + .io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]), + .io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]), + .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]), + .io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]), + .io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]), + .io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__5_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]), + .io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__6_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_io_bottom ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_io_bottom ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_left.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_left.v new file mode 100644 index 000000000..f93e0c6ea --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_left.v @@ -0,0 +1,167 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: io] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_io_left ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_io_left ----- +module grid_io_left(prog_clk, + gfpga_pad_GPIO_PAD, + right_width_0_height_0_subtile_0__pin_outpad_0_, + right_width_0_height_0_subtile_1__pin_outpad_0_, + right_width_0_height_0_subtile_2__pin_outpad_0_, + right_width_0_height_0_subtile_3__pin_outpad_0_, + right_width_0_height_0_subtile_4__pin_outpad_0_, + right_width_0_height_0_subtile_5__pin_outpad_0_, + right_width_0_height_0_subtile_6__pin_outpad_0_, + right_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_head, + right_width_0_height_0_subtile_0__pin_inpad_0_, + right_width_0_height_0_subtile_1__pin_inpad_0_, + right_width_0_height_0_subtile_2__pin_inpad_0_, + right_width_0_height_0_subtile_3__pin_inpad_0_, + right_width_0_height_0_subtile_4__pin_inpad_0_, + right_width_0_height_0_subtile_5__pin_inpad_0_, + right_width_0_height_0_subtile_6__pin_inpad_0_, + right_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:7] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_1__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_2__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_3__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_4__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_5__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_6__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_7__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_4__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_5__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_6__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_7__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]), + .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]), + .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]), + .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]), + .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]), + .io_outpad(right_width_0_height_0_subtile_4__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_4__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]), + .io_outpad(right_width_0_height_0_subtile_5__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_5__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]), + .io_outpad(right_width_0_height_0_subtile_6__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__5_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_6__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]), + .io_outpad(right_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__6_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_io_left ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_io_left ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_right.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_right.v new file mode 100644 index 000000000..9d0a0f05f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_right.v @@ -0,0 +1,167 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: io] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_io_right ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_io_right ----- +module grid_io_right(prog_clk, + gfpga_pad_GPIO_PAD, + left_width_0_height_0_subtile_0__pin_outpad_0_, + left_width_0_height_0_subtile_1__pin_outpad_0_, + left_width_0_height_0_subtile_2__pin_outpad_0_, + left_width_0_height_0_subtile_3__pin_outpad_0_, + left_width_0_height_0_subtile_4__pin_outpad_0_, + left_width_0_height_0_subtile_5__pin_outpad_0_, + left_width_0_height_0_subtile_6__pin_outpad_0_, + left_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_head, + left_width_0_height_0_subtile_0__pin_inpad_0_, + left_width_0_height_0_subtile_1__pin_inpad_0_, + left_width_0_height_0_subtile_2__pin_inpad_0_, + left_width_0_height_0_subtile_3__pin_inpad_0_, + left_width_0_height_0_subtile_4__pin_inpad_0_, + left_width_0_height_0_subtile_5__pin_inpad_0_, + left_width_0_height_0_subtile_6__pin_inpad_0_, + left_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:7] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]), + .io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]), + .io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]), + .io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]), + .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]), + .io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]), + .io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]), + .io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__5_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]), + .io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__6_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_io_right ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_io_right ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_top.v new file mode 100644 index 000000000..af8760fc5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_top.v @@ -0,0 +1,167 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: io] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_io_top ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_io_top ----- +module grid_io_top(prog_clk, + gfpga_pad_GPIO_PAD, + bottom_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_width_0_height_0_subtile_3__pin_outpad_0_, + bottom_width_0_height_0_subtile_4__pin_outpad_0_, + bottom_width_0_height_0_subtile_5__pin_outpad_0_, + bottom_width_0_height_0_subtile_6__pin_outpad_0_, + bottom_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_head, + bottom_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_width_0_height_0_subtile_4__pin_inpad_0_, + bottom_width_0_height_0_subtile_5__pin_inpad_0_, + bottom_width_0_height_0_subtile_6__pin_inpad_0_, + bottom_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:7] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_1__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_2__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_3__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_4__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_5__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_6__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_7__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_4__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_5__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_6__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_7__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]), + .io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]), + .io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]), + .io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]), + .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]), + .io_outpad(bottom_width_0_height_0_subtile_4__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_4__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]), + .io_outpad(bottom_width_0_height_0_subtile_5__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_5__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]), + .io_outpad(bottom_width_0_height_0_subtile_6__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__5_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_6__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]), + .io_outpad(bottom_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__6_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_io_top ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_io_top ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v new file mode 100644 index 000000000..796a7b82a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v @@ -0,0 +1,424 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for pb_type: clb +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Physical programmable logic block Verilog module: clb ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_clb_ ----- +module logical_tile_clb_mode_clb_(prog_clk, + set, + reset, + clk, + clb_I, + clb_clk, + ccff_head, + clb_O, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:9] clb_I; +//----- INPUT PORTS ----- +input [0:0] clb_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:3] clb_O; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:9] clb_I; +wire [0:0] clb_clk; +wire [0:3] clb_O; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] direct_interc_6_out; +wire [0:0] direct_interc_7_out; +wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out; +wire [0:0] mux_tree_size14_0_out; +wire [0:3] mux_tree_size14_0_sram; +wire [0:3] mux_tree_size14_0_sram_inv; +wire [0:0] mux_tree_size14_10_out; +wire [0:3] mux_tree_size14_10_sram; +wire [0:3] mux_tree_size14_10_sram_inv; +wire [0:0] mux_tree_size14_11_out; +wire [0:3] mux_tree_size14_11_sram; +wire [0:3] mux_tree_size14_11_sram_inv; +wire [0:0] mux_tree_size14_12_out; +wire [0:3] mux_tree_size14_12_sram; +wire [0:3] mux_tree_size14_12_sram_inv; +wire [0:0] mux_tree_size14_13_out; +wire [0:3] mux_tree_size14_13_sram; +wire [0:3] mux_tree_size14_13_sram_inv; +wire [0:0] mux_tree_size14_14_out; +wire [0:3] mux_tree_size14_14_sram; +wire [0:3] mux_tree_size14_14_sram_inv; +wire [0:0] mux_tree_size14_15_out; +wire [0:3] mux_tree_size14_15_sram; +wire [0:3] mux_tree_size14_15_sram_inv; +wire [0:0] mux_tree_size14_1_out; +wire [0:3] mux_tree_size14_1_sram; +wire [0:3] mux_tree_size14_1_sram_inv; +wire [0:0] mux_tree_size14_2_out; +wire [0:3] mux_tree_size14_2_sram; +wire [0:3] mux_tree_size14_2_sram_inv; +wire [0:0] mux_tree_size14_3_out; +wire [0:3] mux_tree_size14_3_sram; +wire [0:3] mux_tree_size14_3_sram_inv; +wire [0:0] mux_tree_size14_4_out; +wire [0:3] mux_tree_size14_4_sram; +wire [0:3] mux_tree_size14_4_sram_inv; +wire [0:0] mux_tree_size14_5_out; +wire [0:3] mux_tree_size14_5_sram; +wire [0:3] mux_tree_size14_5_sram_inv; +wire [0:0] mux_tree_size14_6_out; +wire [0:3] mux_tree_size14_6_sram; +wire [0:3] mux_tree_size14_6_sram_inv; +wire [0:0] mux_tree_size14_7_out; +wire [0:3] mux_tree_size14_7_sram; +wire [0:3] mux_tree_size14_7_sram_inv; +wire [0:0] mux_tree_size14_8_out; +wire [0:3] mux_tree_size14_8_sram; +wire [0:3] mux_tree_size14_8_sram_inv; +wire [0:0] mux_tree_size14_9_out; +wire [0:3] mux_tree_size14_9_sram; +wire [0:3] mux_tree_size14_9_sram_inv; +wire [0:0] mux_tree_size14_mem_0_ccff_tail; +wire [0:0] mux_tree_size14_mem_10_ccff_tail; +wire [0:0] mux_tree_size14_mem_11_ccff_tail; +wire [0:0] mux_tree_size14_mem_12_ccff_tail; +wire [0:0] mux_tree_size14_mem_13_ccff_tail; +wire [0:0] mux_tree_size14_mem_14_ccff_tail; +wire [0:0] mux_tree_size14_mem_1_ccff_tail; +wire [0:0] mux_tree_size14_mem_2_ccff_tail; +wire [0:0] mux_tree_size14_mem_3_ccff_tail; +wire [0:0] mux_tree_size14_mem_4_ccff_tail; +wire [0:0] mux_tree_size14_mem_5_ccff_tail; +wire [0:0] mux_tree_size14_mem_6_ccff_tail; +wire [0:0] mux_tree_size14_mem_7_ccff_tail; +wire [0:0] mux_tree_size14_mem_8_ccff_tail; +wire [0:0] mux_tree_size14_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .fle_in({mux_tree_size14_0_out, mux_tree_size14_1_out, mux_tree_size14_2_out, mux_tree_size14_3_out}), + .fle_clk(direct_interc_4_out), + .ccff_head(ccff_head), + .fle_out(logical_tile_clb_mode_default__fle_0_fle_out), + .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail)); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .fle_in({mux_tree_size14_4_out, mux_tree_size14_5_out, mux_tree_size14_6_out, mux_tree_size14_7_out}), + .fle_clk(direct_interc_5_out), + .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_1_fle_out), + .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail)); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .fle_in({mux_tree_size14_8_out, mux_tree_size14_9_out, mux_tree_size14_10_out, mux_tree_size14_11_out}), + .fle_clk(direct_interc_6_out), + .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_2_fle_out), + .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail)); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .fle_in({mux_tree_size14_12_out, mux_tree_size14_13_out, mux_tree_size14_14_out, mux_tree_size14_15_out}), + .fle_clk(direct_interc_7_out), + .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_3_fle_out), + .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail)); + + direct_interc direct_interc_0_ ( + .in(logical_tile_clb_mode_default__fle_0_fle_out), + .out(clb_O[0])); + + direct_interc direct_interc_1_ ( + .in(logical_tile_clb_mode_default__fle_1_fle_out), + .out(clb_O[1])); + + direct_interc direct_interc_2_ ( + .in(logical_tile_clb_mode_default__fle_2_fle_out), + .out(clb_O[2])); + + direct_interc direct_interc_3_ ( + .in(logical_tile_clb_mode_default__fle_3_fle_out), + .out(clb_O[3])); + + direct_interc direct_interc_4_ ( + .in(clb_clk), + .out(direct_interc_4_out)); + + direct_interc direct_interc_5_ ( + .in(clb_clk), + .out(direct_interc_5_out)); + + direct_interc direct_interc_6_ ( + .in(clb_clk), + .out(direct_interc_6_out)); + + direct_interc direct_interc_7_ ( + .in(clb_clk), + .out(direct_interc_7_out)); + + mux_tree_size14 mux_fle_0_in_0 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_0_sram[0:3]), + .sram_inv(mux_tree_size14_0_sram_inv[0:3]), + .out(mux_tree_size14_0_out)); + + mux_tree_size14 mux_fle_0_in_1 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_1_sram[0:3]), + .sram_inv(mux_tree_size14_1_sram_inv[0:3]), + .out(mux_tree_size14_1_out)); + + mux_tree_size14 mux_fle_0_in_2 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_2_sram[0:3]), + .sram_inv(mux_tree_size14_2_sram_inv[0:3]), + .out(mux_tree_size14_2_out)); + + mux_tree_size14 mux_fle_0_in_3 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_3_sram[0:3]), + .sram_inv(mux_tree_size14_3_sram_inv[0:3]), + .out(mux_tree_size14_3_out)); + + mux_tree_size14 mux_fle_1_in_0 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_4_sram[0:3]), + .sram_inv(mux_tree_size14_4_sram_inv[0:3]), + .out(mux_tree_size14_4_out)); + + mux_tree_size14 mux_fle_1_in_1 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_5_sram[0:3]), + .sram_inv(mux_tree_size14_5_sram_inv[0:3]), + .out(mux_tree_size14_5_out)); + + mux_tree_size14 mux_fle_1_in_2 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_6_sram[0:3]), + .sram_inv(mux_tree_size14_6_sram_inv[0:3]), + .out(mux_tree_size14_6_out)); + + mux_tree_size14 mux_fle_1_in_3 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_7_sram[0:3]), + .sram_inv(mux_tree_size14_7_sram_inv[0:3]), + .out(mux_tree_size14_7_out)); + + mux_tree_size14 mux_fle_2_in_0 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_8_sram[0:3]), + .sram_inv(mux_tree_size14_8_sram_inv[0:3]), + .out(mux_tree_size14_8_out)); + + mux_tree_size14 mux_fle_2_in_1 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_9_sram[0:3]), + .sram_inv(mux_tree_size14_9_sram_inv[0:3]), + .out(mux_tree_size14_9_out)); + + mux_tree_size14 mux_fle_2_in_2 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_10_sram[0:3]), + .sram_inv(mux_tree_size14_10_sram_inv[0:3]), + .out(mux_tree_size14_10_out)); + + mux_tree_size14 mux_fle_2_in_3 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_11_sram[0:3]), + .sram_inv(mux_tree_size14_11_sram_inv[0:3]), + .out(mux_tree_size14_11_out)); + + mux_tree_size14 mux_fle_3_in_0 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_12_sram[0:3]), + .sram_inv(mux_tree_size14_12_sram_inv[0:3]), + .out(mux_tree_size14_12_out)); + + mux_tree_size14 mux_fle_3_in_1 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_13_sram[0:3]), + .sram_inv(mux_tree_size14_13_sram_inv[0:3]), + .out(mux_tree_size14_13_out)); + + mux_tree_size14 mux_fle_3_in_2 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_14_sram[0:3]), + .sram_inv(mux_tree_size14_14_sram_inv[0:3]), + .out(mux_tree_size14_14_out)); + + mux_tree_size14 mux_fle_3_in_3 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_15_sram[0:3]), + .sram_inv(mux_tree_size14_15_sram_inv[0:3]), + .out(mux_tree_size14_15_out)); + + mux_tree_size14_mem mem_fle_0_in_0 ( + .prog_clk(prog_clk), + .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail), + .ccff_tail(mux_tree_size14_mem_0_ccff_tail), + .mem_out(mux_tree_size14_0_sram[0:3]), + .mem_outb(mux_tree_size14_0_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_0_in_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_0_ccff_tail), + .ccff_tail(mux_tree_size14_mem_1_ccff_tail), + .mem_out(mux_tree_size14_1_sram[0:3]), + .mem_outb(mux_tree_size14_1_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_0_in_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_1_ccff_tail), + .ccff_tail(mux_tree_size14_mem_2_ccff_tail), + .mem_out(mux_tree_size14_2_sram[0:3]), + .mem_outb(mux_tree_size14_2_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_0_in_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_2_ccff_tail), + .ccff_tail(mux_tree_size14_mem_3_ccff_tail), + .mem_out(mux_tree_size14_3_sram[0:3]), + .mem_outb(mux_tree_size14_3_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_1_in_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_3_ccff_tail), + .ccff_tail(mux_tree_size14_mem_4_ccff_tail), + .mem_out(mux_tree_size14_4_sram[0:3]), + .mem_outb(mux_tree_size14_4_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_1_in_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_4_ccff_tail), + .ccff_tail(mux_tree_size14_mem_5_ccff_tail), + .mem_out(mux_tree_size14_5_sram[0:3]), + .mem_outb(mux_tree_size14_5_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_1_in_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_5_ccff_tail), + .ccff_tail(mux_tree_size14_mem_6_ccff_tail), + .mem_out(mux_tree_size14_6_sram[0:3]), + .mem_outb(mux_tree_size14_6_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_1_in_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_6_ccff_tail), + .ccff_tail(mux_tree_size14_mem_7_ccff_tail), + .mem_out(mux_tree_size14_7_sram[0:3]), + .mem_outb(mux_tree_size14_7_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_2_in_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_7_ccff_tail), + .ccff_tail(mux_tree_size14_mem_8_ccff_tail), + .mem_out(mux_tree_size14_8_sram[0:3]), + .mem_outb(mux_tree_size14_8_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_2_in_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_8_ccff_tail), + .ccff_tail(mux_tree_size14_mem_9_ccff_tail), + .mem_out(mux_tree_size14_9_sram[0:3]), + .mem_outb(mux_tree_size14_9_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_2_in_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_9_ccff_tail), + .ccff_tail(mux_tree_size14_mem_10_ccff_tail), + .mem_out(mux_tree_size14_10_sram[0:3]), + .mem_outb(mux_tree_size14_10_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_2_in_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_10_ccff_tail), + .ccff_tail(mux_tree_size14_mem_11_ccff_tail), + .mem_out(mux_tree_size14_11_sram[0:3]), + .mem_outb(mux_tree_size14_11_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_3_in_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_11_ccff_tail), + .ccff_tail(mux_tree_size14_mem_12_ccff_tail), + .mem_out(mux_tree_size14_12_sram[0:3]), + .mem_outb(mux_tree_size14_12_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_3_in_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_12_ccff_tail), + .ccff_tail(mux_tree_size14_mem_13_ccff_tail), + .mem_out(mux_tree_size14_13_sram[0:3]), + .mem_outb(mux_tree_size14_13_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_3_in_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_13_ccff_tail), + .ccff_tail(mux_tree_size14_mem_14_ccff_tail), + .mem_out(mux_tree_size14_14_sram[0:3]), + .mem_outb(mux_tree_size14_14_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_3_in_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_14_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_size14_15_sram[0:3]), + .mem_outb(mux_tree_size14_15_sram_inv[0:3])); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_clb_ ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Physical programmable logic block Verilog module: clb ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v new file mode 100644 index 000000000..555071020 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v @@ -0,0 +1,106 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for pb_type: fle +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Physical programmable logic block Verilog module: fle ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_default__fle ----- +module logical_tile_clb_mode_default__fle(prog_clk, + set, + reset, + clk, + fle_in, + fle_clk, + ccff_head, + fle_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:3] fle_in; +//----- INPUT PORTS ----- +input [0:0] fle_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] fle_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:3] fle_in; +wire [0:0] fle_clk; +wire [0:0] fle_out; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] direct_interc_1_out; +wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_3_out; +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .ble4_in({direct_interc_1_out, direct_interc_2_out, direct_interc_3_out, direct_interc_4_out}), + .ble4_clk(direct_interc_5_out), + .ccff_head(ccff_head), + .ble4_out(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out), + .ccff_tail(ccff_tail)); + + direct_interc direct_interc_0_ ( + .in(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out), + .out(fle_out)); + + direct_interc direct_interc_1_ ( + .in(fle_in[0]), + .out(direct_interc_1_out)); + + direct_interc direct_interc_2_ ( + .in(fle_in[1]), + .out(direct_interc_2_out)); + + direct_interc direct_interc_3_ ( + .in(fle_in[2]), + .out(direct_interc_3_out)); + + direct_interc direct_interc_4_ ( + .in(fle_in[3]), + .out(direct_interc_4_out)); + + direct_interc direct_interc_5_ ( + .in(fle_clk), + .out(direct_interc_5_out)); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_default__fle ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Physical programmable logic block Verilog module: fle ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v new file mode 100644 index 000000000..aab763fac --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v @@ -0,0 +1,128 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for pb_type: ble4 +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Physical programmable logic block Verilog module: ble4 ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 ----- +module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4(prog_clk, + set, + reset, + clk, + ble4_in, + ble4_clk, + ccff_head, + ble4_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:3] ble4_in; +//----- INPUT PORTS ----- +input [0:0] ble4_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ble4_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:3] ble4_in; +wire [0:0] ble4_clk; +wire [0:0] ble4_out; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] direct_interc_0_out; +wire [0:0] direct_interc_1_out; +wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_3_out; +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q; +wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0 ( + .prog_clk(prog_clk), + .lut4_in({direct_interc_0_out, direct_interc_1_out, direct_interc_2_out, direct_interc_3_out}), + .ccff_head(ccff_head), + .lut4_out(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail)); + + logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0 ( + .set(set), + .reset(reset), + .clk(clk), + .ff_D(direct_interc_4_out), + .ff_Q(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q), + .ff_clk(direct_interc_5_out)); + + mux_tree_tapbuf_size2 mux_ble4_out_0 ( + .in({logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(ble4_out)); + + mux_tree_tapbuf_size2_mem mem_ble4_out_0 ( + .prog_clk(prog_clk), + .ccff_head(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + direct_interc direct_interc_0_ ( + .in(ble4_in[0]), + .out(direct_interc_0_out)); + + direct_interc direct_interc_1_ ( + .in(ble4_in[1]), + .out(direct_interc_1_out)); + + direct_interc direct_interc_2_ ( + .in(ble4_in[2]), + .out(direct_interc_2_out)); + + direct_interc direct_interc_3_ ( + .in(ble4_in[3]), + .out(direct_interc_3_out)); + + direct_interc direct_interc_4_ ( + .in(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out), + .out(direct_interc_4_out)); + + direct_interc direct_interc_5_ ( + .in(ble4_clk), + .out(direct_interc_5_out)); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Physical programmable logic block Verilog module: ble4 ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v new file mode 100644 index 000000000..fe3b6bc84 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v @@ -0,0 +1,61 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for primitive pb_type: ff +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff ----- +module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff(set, + reset, + clk, + ff_D, + ff_Q, + ff_clk); +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:0] ff_D; +//----- OUTPUT PORTS ----- +output [0:0] ff_Q; +//----- CLOCK PORTS ----- +input [0:0] ff_clk; + +//----- BEGIN wire-connection ports ----- +wire [0:0] ff_D; +wire [0:0] ff_Q; +wire [0:0] ff_clk; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + DFFSRQ DFFSRQ_0_ ( + .SET(set), + .RST(reset), + .CK(clk), + .D(ff_D), + .Q(ff_Q)); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v new file mode 100644 index 000000000..ae00bb2cc --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v @@ -0,0 +1,65 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for primitive pb_type: lut4 +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 ----- +module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4(prog_clk, + lut4_in, + ccff_head, + lut4_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:3] lut4_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] lut4_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:3] lut4_in; +wire [0:0] lut4_out; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:15] lut4_0_sram; +wire [0:15] lut4_0_sram_inv; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + lut4 lut4_0_ ( + .in(lut4_in[0:3]), + .sram(lut4_0_sram[0:15]), + .sram_inv(lut4_0_sram_inv[0:15]), + .out(lut4_out)); + + lut4_DFF_mem lut4_DFF_mem ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .mem_out(lut4_0_sram[0:15]), + .mem_outb(lut4_0_sram_inv[0:15])); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v new file mode 100644 index 000000000..c1298dab4 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v @@ -0,0 +1,73 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for pb_type: io +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Physical programmable logic block Verilog module: io ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_io_mode_io_ ----- +module logical_tile_io_mode_io_(prog_clk, + gfpga_pad_GPIO_PAD, + io_outpad, + ccff_head, + io_inpad, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:0] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] io_outpad; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] io_inpad; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:0] io_outpad; +wire [0:0] io_inpad; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] direct_interc_1_out; +wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD), + .iopad_outpad(direct_interc_1_out), + .ccff_head(ccff_head), + .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad), + .ccff_tail(ccff_tail)); + + direct_interc direct_interc_0_ ( + .in(logical_tile_io_mode_physical__iopad_0_iopad_inpad), + .out(io_inpad)); + + direct_interc direct_interc_1_ ( + .in(io_outpad), + .out(direct_interc_1_out)); + +endmodule +// ----- END Verilog module for logical_tile_io_mode_io_ ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Physical programmable logic block Verilog module: io ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v new file mode 100644 index 000000000..3fe49ce2f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v @@ -0,0 +1,68 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for primitive pb_type: iopad +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_io_mode_physical__iopad ----- +module logical_tile_io_mode_physical__iopad(prog_clk, + gfpga_pad_GPIO_PAD, + iopad_outpad, + ccff_head, + iopad_inpad, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:0] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] iopad_outpad; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] iopad_inpad; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:0] iopad_outpad; +wire [0:0] iopad_inpad; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] GPIO_0_DIR; +wire [0:0] GPIO_DFF_mem_undriven_mem_outb; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + GPIO GPIO_0_ ( + .PAD(gfpga_pad_GPIO_PAD), + .A(iopad_outpad), + .DIR(GPIO_0_DIR), + .Y(iopad_inpad)); + + GPIO_DFF_mem GPIO_DFF_mem ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .mem_out(GPIO_0_DIR), + .mem_outb(GPIO_DFF_mem_undriven_mem_outb)); + +endmodule +// ----- END Verilog module for logical_tile_io_mode_physical__iopad ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_clb_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_clb_.sdc new file mode 100644 index 000000000..926bf0463 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_clb_.sdc @@ -0,0 +1,237 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle.sdc new file mode 100644 index 000000000..985595883 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle.sdc @@ -0,0 +1,13 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.sdc new file mode 100644 index 000000000..c960efbee --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.sdc @@ -0,0 +1,15 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] 4.500000025e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] 2.500000033e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.sdc new file mode 100644 index 000000000..c83672cad --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.sdc @@ -0,0 +1,13 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.sdc new file mode 100644 index 000000000..fd273c6be --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.sdc @@ -0,0 +1,21 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_io_mode_io_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_io_mode_io_.sdc new file mode 100644 index 000000000..891a7bfef --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_io_mode_io_.sdc @@ -0,0 +1,15 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/grid_io_left/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left/logical_tile_io_mode_io__0/io_inpad[0] 4.243000049e-11 +set_max_delay -from fpga_top/grid_io_left/logical_tile_io_mode_io__0/io_outpad[0] -to fpga_top/grid_io_left/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/mux_modules.yaml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/mux_modules.yaml new file mode 100644 index 000000000..5180e81ee --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/mux_modules.yaml @@ -0,0 +1,24 @@ +sb_0__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_0__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_1__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_1__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +cbx_1__0_: + - mux_tree_tapbuf_size6 +cbx_1__1_: + - mux_tree_tapbuf_size6 +cby_0__1_: + - mux_tree_tapbuf_size6 +cby_1__1_: + - mux_tree_tapbuf_size6 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml new file mode 100644 index 000000000..9e63dda8a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml @@ -0,0 +1,9 @@ + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__0_.v new file mode 100644 index 000000000..9090e22db --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__0_.v @@ -0,0 +1,367 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cbx_1__0_ ----- +module cbx_1__0_(prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_, + top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_, + top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chanx_left_in; +//----- INPUT PORTS ----- +input [0:12] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_10_sram; +wire [0:2] mux_tree_tapbuf_size6_10_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[0] = chanx_left_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[1] = chanx_left_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[2] = chanx_left_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[3] = chanx_left_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[4] = chanx_left_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[5] = chanx_left_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[6] = chanx_left_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[7] = chanx_left_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[8] = chanx_left_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[9] = chanx_left_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[10] = chanx_left_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[11] = chanx_left_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[12] = chanx_left_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[0] = chanx_right_in[0]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[1] = chanx_right_in[1]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[2] = chanx_right_in[2]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[3] = chanx_right_in[3]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[4] = chanx_right_in[4]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[5] = chanx_right_in[5]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[6] = chanx_right_in[6]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[7] = chanx_right_in[7]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[8] = chanx_right_in[8]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[9] = chanx_right_in[9]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[10] = chanx_right_in[10]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[11] = chanx_right_in[11]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[12] = chanx_right_in[12]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size6 mux_bottom_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_1 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_2 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_0 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_1 ( + .in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_2 ( + .in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_3 ( + .in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_4 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_5 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_6 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_7 ( + .in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size6_10_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_)); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2])); + +endmodule +// ----- END Verilog module for cbx_1__0_ ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__1_.v new file mode 100644 index 000000000..3e96c8986 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__1_.v @@ -0,0 +1,367 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cbx_1__1_ ----- +module cbx_1__1_(prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chanx_left_in; +//----- INPUT PORTS ----- +input [0:12] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_10_sram; +wire [0:2] mux_tree_tapbuf_size6_10_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[0] = chanx_left_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[1] = chanx_left_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[2] = chanx_left_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[3] = chanx_left_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[4] = chanx_left_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[5] = chanx_left_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[6] = chanx_left_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[7] = chanx_left_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[8] = chanx_left_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[9] = chanx_left_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[10] = chanx_left_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[11] = chanx_left_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[12] = chanx_left_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[0] = chanx_right_in[0]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[1] = chanx_right_in[1]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[2] = chanx_right_in[2]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[3] = chanx_right_in[3]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[4] = chanx_right_in[4]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[5] = chanx_right_in[5]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[6] = chanx_right_in[6]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[7] = chanx_right_in[7]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[8] = chanx_right_in[8]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[9] = chanx_right_in[9]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[10] = chanx_right_in[10]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[11] = chanx_right_in[11]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[12] = chanx_right_in[12]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size6 mux_bottom_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_1 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_2 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_3 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_4 ( + .in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_5 ( + .in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_6 ( + .in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_7 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_0 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_1 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_)); + + mux_tree_tapbuf_size6 mux_top_ipin_2 ( + .in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size6_10_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_)); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2])); + +endmodule +// ----- END Verilog module for cbx_1__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_0__1_.v new file mode 100644 index 000000000..67f8756a9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_0__1_.v @@ -0,0 +1,348 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[0][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cby_0__1_ ----- +module cby_0__1_(prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + right_grid_left_width_0_height_0_subtile_0__pin_I_3_, + right_grid_left_width_0_height_0_subtile_0__pin_I_7_, + left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:12] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:12] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_3_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_7_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[0] = chany_bottom_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[1] = chany_bottom_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[2] = chany_bottom_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[3] = chany_bottom_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[4] = chany_bottom_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[5] = chany_bottom_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[6] = chany_bottom_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[7] = chany_bottom_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[8] = chany_bottom_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[9] = chany_bottom_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[10] = chany_bottom_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[11] = chany_bottom_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[12] = chany_bottom_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[0] = chany_top_in[0]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[1] = chany_top_in[1]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[2] = chany_top_in[2]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[3] = chany_top_in[3]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[4] = chany_top_in[4]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[5] = chany_top_in[5]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[6] = chany_top_in[6]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[7] = chany_top_in[7]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[8] = chany_top_in[8]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[9] = chany_top_in[9]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[10] = chany_top_in[10]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[11] = chany_top_in[11]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[12] = chany_top_in[12]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size6 mux_left_ipin_0 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_0__pin_I_3_)); + + mux_tree_tapbuf_size6 mux_left_ipin_1 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_0__pin_I_7_)); + + mux_tree_tapbuf_size6 mux_right_ipin_0 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_1 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_2 ( + .in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_3 ( + .in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_4 ( + .in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_5 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_6 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_7 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_)); + + mux_tree_tapbuf_size6_mem mem_left_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2])); + +endmodule +// ----- END Verilog module for cby_0__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_1__1_.v new file mode 100644 index 000000000..5a9c566f8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_1__1_.v @@ -0,0 +1,367 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cby_1__1_ ----- +module cby_1__1_(prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I_5_, + left_grid_right_width_0_height_0_subtile_0__pin_I_9_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:12] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:12] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_9_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_10_sram; +wire [0:2] mux_tree_tapbuf_size6_10_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[0] = chany_bottom_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[1] = chany_bottom_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[2] = chany_bottom_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[3] = chany_bottom_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[4] = chany_bottom_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[5] = chany_bottom_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[6] = chany_bottom_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[7] = chany_bottom_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[8] = chany_bottom_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[9] = chany_bottom_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[10] = chany_bottom_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[11] = chany_bottom_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[12] = chany_bottom_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[0] = chany_top_in[0]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[1] = chany_top_in[1]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[2] = chany_top_in[2]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[3] = chany_top_in[3]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[4] = chany_top_in[4]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[5] = chany_top_in[5]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[6] = chany_top_in[6]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[7] = chany_top_in[7]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[8] = chany_top_in[8]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[9] = chany_top_in[9]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[10] = chany_top_in[10]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[11] = chany_top_in[11]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[12] = chany_top_in[12]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size6 mux_left_ipin_0 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_1 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_2 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_3 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_4 ( + .in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_5 ( + .in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_6 ( + .in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_7 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_0 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_)); + + mux_tree_tapbuf_size6 mux_right_ipin_1 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_)); + + mux_tree_tapbuf_size6 mux_right_ipin_2 ( + .in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[10], chany_top_in[10]}), + .sram(mux_tree_tapbuf_size6_10_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I_9_)); + + mux_tree_tapbuf_size6_mem mem_left_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2])); + +endmodule +// ----- END Verilog module for cby_1__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__0_.v new file mode 100644 index 000000000..6e5f094d9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__0_.v @@ -0,0 +1,523 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[0][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_0__0_ ----- +module sb_0__0_(prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:12] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_12_sram; +wire [0:1] mux_tree_tapbuf_size3_12_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_13_sram; +wire [0:1] mux_tree_tapbuf_size3_13_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_5_sram; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size4 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[1]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size4 mux_top_track_12 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size4 mux_right_track_0 ( + .in({chany_top_in[12], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size4 mux_right_track_2 ( + .in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size4 mux_right_track_12 ( + .in({chany_top_in[5], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size4 mux_right_track_14 ( + .in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), + .out(chanx_right_out[7])); + + mux_tree_tapbuf_size4_mem mem_top_track_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_12 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_12 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_14 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_top_track_2 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[2]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size3 mux_top_track_4 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[3]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size3 mux_top_track_6 ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[4]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size3 mux_top_track_8 ( + .in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[5]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size3 mux_top_track_10 ( + .in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[6]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size3 mux_top_track_14 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_top_out[7])); + + mux_tree_tapbuf_size3 mux_top_track_16 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size3 mux_top_track_24 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[0]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size3 mux_right_track_4 ( + .in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size3 mux_right_track_6 ( + .in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size3 mux_right_track_8 ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size3 mux_right_track_10 ( + .in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size3 mux_right_track_16 ( + .in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size3 mux_right_track_24 ( + .in({chany_top_in[11], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size3_mem mem_top_track_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_8 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_10 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_14 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_16 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_24 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_10 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_16 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_24 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_top_track_18 ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[9])); + + mux_tree_tapbuf_size2 mux_top_track_20 ( + .in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[11]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size2 mux_top_track_22 ( + .in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[11])); + + mux_tree_tapbuf_size2 mux_right_track_18 ( + .in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_right_out[9])); + + mux_tree_tapbuf_size2 mux_right_track_20 ( + .in({chany_top_in[9], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size2 mux_right_track_22 ( + .in({chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_right_out[11])); + + mux_tree_tapbuf_size2_mem mem_top_track_18 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_20 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_22 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_18 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_20 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_22 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + +endmodule +// ----- END Verilog module for sb_0__0_ ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__1_.v new file mode 100644 index 000000000..221ac87b1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__1_.v @@ -0,0 +1,523 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[0][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_0__1_ ----- +module sb_0__1_(prog_clk, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_head, + chanx_right_out, + chany_bottom_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:12] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:12] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_12_sram; +wire [0:1] mux_tree_tapbuf_size3_12_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_13_sram; +wire [0:1] mux_tree_tapbuf_size3_13_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size4 mux_right_track_0 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size4 mux_right_track_12 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size4 mux_bottom_track_1 ( + .in({chanx_right_in[11], bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size4 mux_bottom_track_3 ( + .in({chanx_right_in[10], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size4 mux_bottom_track_15 ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .out(chany_bottom_out[7])); + + mux_tree_tapbuf_size4_mem mem_right_track_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_12 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_15 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_right_track_2 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size3 mux_right_track_4 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size3 mux_right_track_6 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size3 mux_right_track_8 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size3 mux_right_track_10 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size3 mux_right_track_14 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chanx_right_out[7])); + + mux_tree_tapbuf_size3 mux_right_track_16 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size3 mux_right_track_24 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size3 mux_bottom_track_5 ( + .in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size3 mux_bottom_track_7 ( + .in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size3 mux_bottom_track_9 ( + .in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size3 mux_bottom_track_11 ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size3 mux_bottom_track_13 ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size3 mux_bottom_track_17 ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size3_mem mem_right_track_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_10 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_14 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_16 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_24 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_11 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_13 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_17 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_right_track_18 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_right_out[9])); + + mux_tree_tapbuf_size2 mux_right_track_20 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size2 mux_right_track_22 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chanx_right_out[11])); + + mux_tree_tapbuf_size2 mux_bottom_track_19 ( + .in({chanx_right_in[2], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_bottom_out[9])); + + mux_tree_tapbuf_size2 mux_bottom_track_21 ( + .in({chanx_right_in[1], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size2 mux_bottom_track_23 ( + .in({chanx_right_in[0], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_bottom_out[11])); + + mux_tree_tapbuf_size2 mux_bottom_track_25 ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size2_mem mem_right_track_18 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_20 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_22 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_21 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_23 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + +endmodule +// ----- END Verilog module for sb_0__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__0_.v new file mode 100644 index 000000000..b9385b247 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__0_.v @@ -0,0 +1,523 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[1][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_1__0_ ----- +module sb_1__0_(prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:12] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_5_sram; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_6_sram; +wire [0:2] mux_tree_tapbuf_size4_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size4 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size4 mux_top_track_2 ( + .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size4 mux_top_track_14 ( + .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chany_top_out[7])); + + mux_tree_tapbuf_size4 mux_left_track_1 ( + .in({chany_top_in[0], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size4 mux_left_track_3 ( + .in({chany_top_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size4 mux_left_track_13 ( + .in({chany_top_in[7], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size4 mux_left_track_15 ( + .in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]), + .out(chanx_left_out[7])); + + mux_tree_tapbuf_size4_mem mem_top_track_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_14 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_13 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_15 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_top_track_4 ( + .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size3 mux_top_track_6 ( + .in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size3 mux_top_track_8 ( + .in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size3 mux_top_track_10 ( + .in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size3 mux_top_track_12 ( + .in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size3 mux_top_track_16 ( + .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size3 mux_left_track_5 ( + .in({chany_top_in[11], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size3 mux_left_track_7 ( + .in({chany_top_in[10], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size3 mux_left_track_9 ( + .in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size3 mux_left_track_11 ( + .in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size3 mux_left_track_17 ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size3 mux_left_track_25 ( + .in({chany_top_in[1], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size3_mem mem_top_track_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_8 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_10 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_12 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_16 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_9 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_11 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_17 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_top_track_18 ( + .in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[9])); + + mux_tree_tapbuf_size2 mux_top_track_20 ( + .in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size2 mux_top_track_22 ( + .in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[11])); + + mux_tree_tapbuf_size2 mux_top_track_24 ( + .in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size2 mux_left_track_19 ( + .in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_left_out[9])); + + mux_tree_tapbuf_size2 mux_left_track_21 ( + .in({chany_top_in[3], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size2 mux_left_track_23 ( + .in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chanx_left_out[11])); + + mux_tree_tapbuf_size2_mem mem_top_track_18 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_20 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_22 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_24 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_19 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_21 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_23 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + +endmodule +// ----- END Verilog module for sb_1__0_ ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__1_.v new file mode 100644 index 000000000..f8bcc9d61 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__1_.v @@ -0,0 +1,523 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[1][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_1__1_ ----- +module sb_1__1_(prog_clk, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + ccff_head, + chany_bottom_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:12] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_12_sram; +wire [0:1] mux_tree_tapbuf_size3_12_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_13_sram; +wire [0:1] mux_tree_tapbuf_size3_13_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_14_sram; +wire [0:1] mux_tree_tapbuf_size3_14_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_15_sram; +wire [0:1] mux_tree_tapbuf_size3_15_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_14_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size4 mux_bottom_track_1 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size4 mux_bottom_track_13 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size4 mux_left_track_1 ( + .in({chany_bottom_in[12], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size4 mux_left_track_13 ( + .in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_1 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_13 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_13 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_bottom_track_3 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size3 mux_bottom_track_5 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size3 mux_bottom_track_7 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size3 mux_bottom_track_9 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size3 mux_bottom_track_11 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size3 mux_bottom_track_15 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_bottom_out[7])); + + mux_tree_tapbuf_size3 mux_bottom_track_17 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size3 mux_bottom_track_25 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size3 mux_left_track_3 ( + .in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size3 mux_left_track_5 ( + .in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size3 mux_left_track_7 ( + .in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size3 mux_left_track_9 ( + .in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size3 mux_left_track_11 ( + .in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size3 mux_left_track_15 ( + .in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]), + .out(chanx_left_out[7])); + + mux_tree_tapbuf_size3 mux_left_track_17 ( + .in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size3_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_14_sram_inv[0:1]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size3 mux_left_track_25 ( + .in({chany_bottom_in[11], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_15_sram_inv[0:1]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_11 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_15 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_17 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_25 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_9 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_11 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_15 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_17 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_14_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_15_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_bottom_track_19 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_bottom_out[9])); + + mux_tree_tapbuf_size2 mux_bottom_track_21 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size2 mux_bottom_track_23 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_bottom_out[11])); + + mux_tree_tapbuf_size2 mux_left_track_19 ( + .in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_left_out[9])); + + mux_tree_tapbuf_size2 mux_left_track_21 ( + .in({chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size2 mux_left_track_23 ( + .in({chany_bottom_in[10], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_left_out[11])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_21 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_23 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_19 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_21 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_23 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + +endmodule +// ----- END Verilog module for sb_1__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__0_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__0_.sdc new file mode 100644 index 000000000..1eb6d3aae --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__0_.sdc @@ -0,0 +1,91 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_0__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__1_.sdc new file mode 100644 index 000000000..8f37af1eb --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__1_.sdc @@ -0,0 +1,89 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_0__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__0_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__0_.sdc new file mode 100644 index 000000000..b17c6e0c0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__0_.sdc @@ -0,0 +1,91 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_1__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/sb_1__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__1_.sdc new file mode 100644 index 000000000..d70811c44 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__1_.sdc @@ -0,0 +1,89 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_1__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/arch_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/arch_encoder.v new file mode 100644 index 000000000..3a42c112a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/arch_encoder.v @@ -0,0 +1,6 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Decoders for fabric configuration protocol +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v new file mode 100644 index 000000000..9c69ae47b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v @@ -0,0 +1,193 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Essential gates +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for const0 ----- +module const0(const0); +//----- OUTPUT PORTS ----- +output [0:0] const0; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + assign const0[0] = 1'b0; +endmodule +// ----- END Verilog module for const0 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for const1 ----- +module const1(const1); +//----- OUTPUT PORTS ----- +output [0:0] const1; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + assign const1[0] = 1'b1; +endmodule +// ----- END Verilog module for const1 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for INVTX1 ----- +module INVTX1(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + assign out = (in === 1'bz)? $random : ~in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in => out) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for INVTX1 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for buf4 ----- +module buf4(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + assign out = (in === 1'bz)? $random : in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in => out) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for buf4 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for tap_buf4 ----- +module tap_buf4(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + assign out = (in === 1'bz)? $random : ~in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in => out) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for tap_buf4 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for TGATE ----- +module TGATE(in, + sel, + selb, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- INPUT PORTS ----- +input [0:0] sel; +//----- INPUT PORTS ----- +input [0:0] selb; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + assign out = sel ? in : 1'bz; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in => out) = (0.01, 0.01); + (sel => out) = (0.005, 0.005); + (selb => out) = (0.005, 0.005); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for TGATE ----- + +//----- Default net type ----- +`default_nettype wire + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/local_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/local_encoder.v new file mode 100644 index 000000000..49e4ef736 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/local_encoder.v @@ -0,0 +1,6 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Local Decoders for Multiplexers +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/luts.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/luts.v new file mode 100644 index 000000000..8e2d5245f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/luts.v @@ -0,0 +1,93 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Look-Up Tables +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for lut4 ----- +module lut4(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:3] in; +//----- INPUT PORTS ----- +input [0:15] sram; +//----- INPUT PORTS ----- +input [0:15] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +wire [0:3] in; +wire [0:0] out; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] buf4_0_out; +wire [0:0] buf4_1_out; +wire [0:0] buf4_2_out; +wire [0:0] buf4_3_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + buf4 buf4_0_ ( + .in(in[0]), + .out(buf4_0_out)); + + buf4 buf4_1_ ( + .in(in[1]), + .out(buf4_1_out)); + + buf4 buf4_2_ ( + .in(in[2]), + .out(buf4_2_out)); + + buf4 buf4_3_ ( + .in(in[3]), + .out(buf4_3_out)); + + lut4_mux lut4_mux_0_ ( + .in(sram[0:15]), + .sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out}), + .sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out}), + .out(out)); + +endmodule +// ----- END Verilog module for lut4 ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/memories.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/memories.v new file mode 100644 index 000000000..6e40f5ac9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/memories.v @@ -0,0 +1,500 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Memories used in FPGA +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size6_mem ----- +module mux_tree_tapbuf_size6_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:2] mem_out; +//----- OUTPUT PORTS ----- +output [0:2] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[2]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + + DFF DFF_2_ ( + .CK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]), + .QN(mem_outb[2])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size6_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size4_mem ----- +module mux_tree_tapbuf_size4_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:2] mem_out; +//----- OUTPUT PORTS ----- +output [0:2] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[2]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + + DFF DFF_2_ ( + .CK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]), + .QN(mem_outb[2])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size4_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size3_mem ----- +module mux_tree_tapbuf_size3_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:1] mem_out; +//----- OUTPUT PORTS ----- +output [0:1] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[1]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size3_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size2_mem ----- +module mux_tree_tapbuf_size2_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:1] mem_out; +//----- OUTPUT PORTS ----- +output [0:1] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[1]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size2_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_size14_mem ----- +module mux_tree_size14_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:3] mem_out; +//----- OUTPUT PORTS ----- +output [0:3] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[3]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + + DFF DFF_2_ ( + .CK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]), + .QN(mem_outb[2])); + + DFF DFF_3_ ( + .CK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]), + .QN(mem_outb[3])); + +endmodule +// ----- END Verilog module for mux_tree_size14_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for lut4_DFF_mem ----- +module lut4_DFF_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:15] mem_out; +//----- OUTPUT PORTS ----- +output [0:15] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[15]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + + DFF DFF_2_ ( + .CK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]), + .QN(mem_outb[2])); + + DFF DFF_3_ ( + .CK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]), + .QN(mem_outb[3])); + + DFF DFF_4_ ( + .CK(prog_clk), + .D(mem_out[3]), + .Q(mem_out[4]), + .QN(mem_outb[4])); + + DFF DFF_5_ ( + .CK(prog_clk), + .D(mem_out[4]), + .Q(mem_out[5]), + .QN(mem_outb[5])); + + DFF DFF_6_ ( + .CK(prog_clk), + .D(mem_out[5]), + .Q(mem_out[6]), + .QN(mem_outb[6])); + + DFF DFF_7_ ( + .CK(prog_clk), + .D(mem_out[6]), + .Q(mem_out[7]), + .QN(mem_outb[7])); + + DFF DFF_8_ ( + .CK(prog_clk), + .D(mem_out[7]), + .Q(mem_out[8]), + .QN(mem_outb[8])); + + DFF DFF_9_ ( + .CK(prog_clk), + .D(mem_out[8]), + .Q(mem_out[9]), + .QN(mem_outb[9])); + + DFF DFF_10_ ( + .CK(prog_clk), + .D(mem_out[9]), + .Q(mem_out[10]), + .QN(mem_outb[10])); + + DFF DFF_11_ ( + .CK(prog_clk), + .D(mem_out[10]), + .Q(mem_out[11]), + .QN(mem_outb[11])); + + DFF DFF_12_ ( + .CK(prog_clk), + .D(mem_out[11]), + .Q(mem_out[12]), + .QN(mem_outb[12])); + + DFF DFF_13_ ( + .CK(prog_clk), + .D(mem_out[12]), + .Q(mem_out[13]), + .QN(mem_outb[13])); + + DFF DFF_14_ ( + .CK(prog_clk), + .D(mem_out[13]), + .Q(mem_out[14]), + .QN(mem_outb[14])); + + DFF DFF_15_ ( + .CK(prog_clk), + .D(mem_out[14]), + .Q(mem_out[15]), + .QN(mem_outb[15])); + +endmodule +// ----- END Verilog module for lut4_DFF_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for GPIO_DFF_mem ----- +module GPIO_DFF_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:0] mem_out; +//----- OUTPUT PORTS ----- +output [0:0] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[0]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out), + .QN(mem_outb)); + +endmodule +// ----- END Verilog module for GPIO_DFF_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/mux_primitives.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/mux_primitives.v new file mode 100644 index 000000000..afcf99cac --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/mux_primitives.v @@ -0,0 +1,162 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Multiplexer primitives +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_basis_input2_mem1 ----- +module mux_tree_tapbuf_basis_input2_mem1(in, + mem, + mem_inv, + out); +//----- INPUT PORTS ----- +input [0:1] in; +//----- INPUT PORTS ----- +input [0:0] mem; +//----- INPUT PORTS ----- +input [0:0] mem_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + TGATE TGATE_0_ ( + .in(in[0]), + .sel(mem), + .selb(mem_inv), + .out(out)); + + TGATE TGATE_1_ ( + .in(in[1]), + .sel(mem_inv), + .selb(mem), + .out(out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_basis_input2_mem1 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_basis_input2_mem1 ----- +module mux_tree_basis_input2_mem1(in, + mem, + mem_inv, + out); +//----- INPUT PORTS ----- +input [0:1] in; +//----- INPUT PORTS ----- +input [0:0] mem; +//----- INPUT PORTS ----- +input [0:0] mem_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + TGATE TGATE_0_ ( + .in(in[0]), + .sel(mem), + .selb(mem_inv), + .out(out)); + + TGATE TGATE_1_ ( + .in(in[1]), + .sel(mem_inv), + .selb(mem), + .out(out)); + +endmodule +// ----- END Verilog module for mux_tree_basis_input2_mem1 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for lut4_mux_basis_input2_mem1 ----- +module lut4_mux_basis_input2_mem1(in, + mem, + mem_inv, + out); +//----- INPUT PORTS ----- +input [0:1] in; +//----- INPUT PORTS ----- +input [0:0] mem; +//----- INPUT PORTS ----- +input [0:0] mem_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + TGATE TGATE_0_ ( + .in(in[0]), + .sel(mem), + .selb(mem_inv), + .out(out)); + + TGATE TGATE_1_ ( + .in(in[1]), + .sel(mem_inv), + .selb(mem), + .out(out)); + +endmodule +// ----- END Verilog module for lut4_mux_basis_input2_mem1 ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/muxes.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/muxes.v new file mode 100644 index 000000000..9676a06d6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/muxes.v @@ -0,0 +1,823 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Multiplexers +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size6 ----- +module mux_tree_tapbuf_size6(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:5] in; +//----- INPUT PORTS ----- +input [0:2] sram; +//----- INPUT PORTS ----- +input [0:2] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] INVTX1_4_out; +wire [0:0] INVTX1_5_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_3_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_4_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_5_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + INVTX1 INVTX1_4_ ( + .in(in[4]), + .out(INVTX1_4_out)); + + INVTX1 INVTX1_5_ ( + .in(in[5]), + .out(INVTX1_5_out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + tap_buf4 tap_buf4_0_ ( + .in(mux_tree_tapbuf_basis_input2_mem1_5_out), + .out(out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_0_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_1_ ( + .in({INVTX1_2_out, INVTX1_3_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_1_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_2_ ( + .in({INVTX1_4_out, INVTX1_5_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_2_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_0_out, mux_tree_tapbuf_basis_input2_mem1_1_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_3_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_1_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_2_out, const1_0_const1}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_4_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l3_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_3_out, mux_tree_tapbuf_basis_input2_mem1_4_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(mux_tree_tapbuf_basis_input2_mem1_5_out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size6 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size4 ----- +module mux_tree_tapbuf_size4(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:3] in; +//----- INPUT PORTS ----- +input [0:2] sram; +//----- INPUT PORTS ----- +input [0:2] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_3_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + tap_buf4 tap_buf4_0_ ( + .in(mux_tree_tapbuf_basis_input2_mem1_3_out), + .out(out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_0_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_0_out, INVTX1_2_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_1_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_1_ ( + .in({INVTX1_3_out, const1_0_const1}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_2_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l3_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_1_out, mux_tree_tapbuf_basis_input2_mem1_2_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(mux_tree_tapbuf_basis_input2_mem1_3_out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size4 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size3 ----- +module mux_tree_tapbuf_size3(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:2] in; +//----- INPUT PORTS ----- +input [0:1] sram; +//----- INPUT PORTS ----- +input [0:1] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + tap_buf4 tap_buf4_0_ ( + .in(mux_tree_tapbuf_basis_input2_mem1_2_out), + .out(out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_0_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_1_ ( + .in({INVTX1_2_out, const1_0_const1}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_1_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_0_out, mux_tree_tapbuf_basis_input2_mem1_1_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_2_out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size3 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size2 ----- +module mux_tree_tapbuf_size2(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:1] in; +//----- INPUT PORTS ----- +input [0:1] sram; +//----- INPUT PORTS ----- +input [0:1] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + tap_buf4 tap_buf4_0_ ( + .in(mux_tree_tapbuf_basis_input2_mem1_1_out), + .out(out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_0_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_0_out, const1_0_const1}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_1_out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size2 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_size14 ----- +module mux_tree_size14(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:13] in; +//----- INPUT PORTS ----- +input [0:3] sram; +//----- INPUT PORTS ----- +input [0:3] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_10_out; +wire [0:0] INVTX1_11_out; +wire [0:0] INVTX1_12_out; +wire [0:0] INVTX1_13_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] INVTX1_4_out; +wire [0:0] INVTX1_5_out; +wire [0:0] INVTX1_6_out; +wire [0:0] INVTX1_7_out; +wire [0:0] INVTX1_8_out; +wire [0:0] INVTX1_9_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_basis_input2_mem1_0_out; +wire [0:0] mux_tree_basis_input2_mem1_10_out; +wire [0:0] mux_tree_basis_input2_mem1_11_out; +wire [0:0] mux_tree_basis_input2_mem1_12_out; +wire [0:0] mux_tree_basis_input2_mem1_13_out; +wire [0:0] mux_tree_basis_input2_mem1_1_out; +wire [0:0] mux_tree_basis_input2_mem1_2_out; +wire [0:0] mux_tree_basis_input2_mem1_3_out; +wire [0:0] mux_tree_basis_input2_mem1_4_out; +wire [0:0] mux_tree_basis_input2_mem1_5_out; +wire [0:0] mux_tree_basis_input2_mem1_6_out; +wire [0:0] mux_tree_basis_input2_mem1_7_out; +wire [0:0] mux_tree_basis_input2_mem1_8_out; +wire [0:0] mux_tree_basis_input2_mem1_9_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + INVTX1 INVTX1_4_ ( + .in(in[4]), + .out(INVTX1_4_out)); + + INVTX1 INVTX1_5_ ( + .in(in[5]), + .out(INVTX1_5_out)); + + INVTX1 INVTX1_6_ ( + .in(in[6]), + .out(INVTX1_6_out)); + + INVTX1 INVTX1_7_ ( + .in(in[7]), + .out(INVTX1_7_out)); + + INVTX1 INVTX1_8_ ( + .in(in[8]), + .out(INVTX1_8_out)); + + INVTX1 INVTX1_9_ ( + .in(in[9]), + .out(INVTX1_9_out)); + + INVTX1 INVTX1_10_ ( + .in(in[10]), + .out(INVTX1_10_out)); + + INVTX1 INVTX1_11_ ( + .in(in[11]), + .out(INVTX1_11_out)); + + INVTX1 INVTX1_12_ ( + .in(in[12]), + .out(INVTX1_12_out)); + + INVTX1 INVTX1_13_ ( + .in(in[13]), + .out(INVTX1_13_out)); + + INVTX1 INVTX1_14_ ( + .in(mux_tree_basis_input2_mem1_13_out), + .out(out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + mux_tree_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_0_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_1_ ( + .in({INVTX1_2_out, INVTX1_3_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_1_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_2_ ( + .in({INVTX1_4_out, INVTX1_5_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_2_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_3_ ( + .in({INVTX1_6_out, INVTX1_7_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_3_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_4_ ( + .in({INVTX1_8_out, INVTX1_9_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_4_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_5_ ( + .in({INVTX1_10_out, INVTX1_11_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_5_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_6_ ( + .in({INVTX1_12_out, INVTX1_13_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_6_out)); + + mux_tree_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_basis_input2_mem1_0_out, mux_tree_basis_input2_mem1_1_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_basis_input2_mem1_7_out)); + + mux_tree_basis_input2_mem1 mux_l2_in_1_ ( + .in({mux_tree_basis_input2_mem1_2_out, mux_tree_basis_input2_mem1_3_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_basis_input2_mem1_8_out)); + + mux_tree_basis_input2_mem1 mux_l2_in_2_ ( + .in({mux_tree_basis_input2_mem1_4_out, mux_tree_basis_input2_mem1_5_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_basis_input2_mem1_9_out)); + + mux_tree_basis_input2_mem1 mux_l2_in_3_ ( + .in({mux_tree_basis_input2_mem1_6_out, const1_0_const1}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_basis_input2_mem1_10_out)); + + mux_tree_basis_input2_mem1 mux_l3_in_0_ ( + .in({mux_tree_basis_input2_mem1_7_out, mux_tree_basis_input2_mem1_8_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(mux_tree_basis_input2_mem1_11_out)); + + mux_tree_basis_input2_mem1 mux_l3_in_1_ ( + .in({mux_tree_basis_input2_mem1_9_out, mux_tree_basis_input2_mem1_10_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(mux_tree_basis_input2_mem1_12_out)); + + mux_tree_basis_input2_mem1 mux_l4_in_0_ ( + .in({mux_tree_basis_input2_mem1_11_out, mux_tree_basis_input2_mem1_12_out}), + .mem(sram[3]), + .mem_inv(sram_inv[3]), + .out(mux_tree_basis_input2_mem1_13_out)); + +endmodule +// ----- END Verilog module for mux_tree_size14 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for lut4_mux ----- +module lut4_mux(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:15] in; +//----- INPUT PORTS ----- +input [0:3] sram; +//----- INPUT PORTS ----- +input [0:3] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_10_out; +wire [0:0] INVTX1_11_out; +wire [0:0] INVTX1_12_out; +wire [0:0] INVTX1_13_out; +wire [0:0] INVTX1_14_out; +wire [0:0] INVTX1_15_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] INVTX1_4_out; +wire [0:0] INVTX1_5_out; +wire [0:0] INVTX1_6_out; +wire [0:0] INVTX1_7_out; +wire [0:0] INVTX1_8_out; +wire [0:0] INVTX1_9_out; +wire [0:0] lut4_mux_basis_input2_mem1_0_out; +wire [0:0] lut4_mux_basis_input2_mem1_10_out; +wire [0:0] lut4_mux_basis_input2_mem1_11_out; +wire [0:0] lut4_mux_basis_input2_mem1_12_out; +wire [0:0] lut4_mux_basis_input2_mem1_13_out; +wire [0:0] lut4_mux_basis_input2_mem1_14_out; +wire [0:0] lut4_mux_basis_input2_mem1_1_out; +wire [0:0] lut4_mux_basis_input2_mem1_2_out; +wire [0:0] lut4_mux_basis_input2_mem1_3_out; +wire [0:0] lut4_mux_basis_input2_mem1_4_out; +wire [0:0] lut4_mux_basis_input2_mem1_5_out; +wire [0:0] lut4_mux_basis_input2_mem1_6_out; +wire [0:0] lut4_mux_basis_input2_mem1_7_out; +wire [0:0] lut4_mux_basis_input2_mem1_8_out; +wire [0:0] lut4_mux_basis_input2_mem1_9_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + INVTX1 INVTX1_4_ ( + .in(in[4]), + .out(INVTX1_4_out)); + + INVTX1 INVTX1_5_ ( + .in(in[5]), + .out(INVTX1_5_out)); + + INVTX1 INVTX1_6_ ( + .in(in[6]), + .out(INVTX1_6_out)); + + INVTX1 INVTX1_7_ ( + .in(in[7]), + .out(INVTX1_7_out)); + + INVTX1 INVTX1_8_ ( + .in(in[8]), + .out(INVTX1_8_out)); + + INVTX1 INVTX1_9_ ( + .in(in[9]), + .out(INVTX1_9_out)); + + INVTX1 INVTX1_10_ ( + .in(in[10]), + .out(INVTX1_10_out)); + + INVTX1 INVTX1_11_ ( + .in(in[11]), + .out(INVTX1_11_out)); + + INVTX1 INVTX1_12_ ( + .in(in[12]), + .out(INVTX1_12_out)); + + INVTX1 INVTX1_13_ ( + .in(in[13]), + .out(INVTX1_13_out)); + + INVTX1 INVTX1_14_ ( + .in(in[14]), + .out(INVTX1_14_out)); + + INVTX1 INVTX1_15_ ( + .in(in[15]), + .out(INVTX1_15_out)); + + INVTX1 INVTX1_16_ ( + .in(lut4_mux_basis_input2_mem1_14_out), + .out(out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_0_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_1_ ( + .in({INVTX1_2_out, INVTX1_3_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_1_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_2_ ( + .in({INVTX1_4_out, INVTX1_5_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_2_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_3_ ( + .in({INVTX1_6_out, INVTX1_7_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_3_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_4_ ( + .in({INVTX1_8_out, INVTX1_9_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_4_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_5_ ( + .in({INVTX1_10_out, INVTX1_11_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_5_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_6_ ( + .in({INVTX1_12_out, INVTX1_13_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_6_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_7_ ( + .in({INVTX1_14_out, INVTX1_15_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_7_out)); + + lut4_mux_basis_input2_mem1 mux_l2_in_0_ ( + .in({lut4_mux_basis_input2_mem1_0_out, lut4_mux_basis_input2_mem1_1_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(lut4_mux_basis_input2_mem1_8_out)); + + lut4_mux_basis_input2_mem1 mux_l2_in_1_ ( + .in({lut4_mux_basis_input2_mem1_2_out, lut4_mux_basis_input2_mem1_3_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(lut4_mux_basis_input2_mem1_9_out)); + + lut4_mux_basis_input2_mem1 mux_l2_in_2_ ( + .in({lut4_mux_basis_input2_mem1_4_out, lut4_mux_basis_input2_mem1_5_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(lut4_mux_basis_input2_mem1_10_out)); + + lut4_mux_basis_input2_mem1 mux_l2_in_3_ ( + .in({lut4_mux_basis_input2_mem1_6_out, lut4_mux_basis_input2_mem1_7_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(lut4_mux_basis_input2_mem1_11_out)); + + lut4_mux_basis_input2_mem1 mux_l3_in_0_ ( + .in({lut4_mux_basis_input2_mem1_8_out, lut4_mux_basis_input2_mem1_9_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(lut4_mux_basis_input2_mem1_12_out)); + + lut4_mux_basis_input2_mem1 mux_l3_in_1_ ( + .in({lut4_mux_basis_input2_mem1_10_out, lut4_mux_basis_input2_mem1_11_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(lut4_mux_basis_input2_mem1_13_out)); + + lut4_mux_basis_input2_mem1 mux_l4_in_0_ ( + .in({lut4_mux_basis_input2_mem1_12_out, lut4_mux_basis_input2_mem1_13_out}), + .mem(sram[3]), + .mem_inv(sram_inv[3]), + .out(lut4_mux_basis_input2_mem1_14_out)); + +endmodule +// ----- END Verilog module for lut4_mux ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v new file mode 100644 index 000000000..59d6aa2b8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v @@ -0,0 +1,6 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Shift register banks used in FPGA +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v new file mode 100644 index 000000000..1d5542b75 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v @@ -0,0 +1,117 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Template for user-defined Verilog modules +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- Template Verilog module for DFFSRQ ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for DFFSRQ ----- +module DFFSRQ(SET, + RST, + CK, + D, + Q); +//----- GLOBAL PORTS ----- +input [0:0] SET; +//----- GLOBAL PORTS ----- +input [0:0] RST; +//----- GLOBAL PORTS ----- +input [0:0] CK; +//----- INPUT PORTS ----- +input [0:0] D; +//----- OUTPUT PORTS ----- +output [0:0] Q; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- + + +// ----- Internal logic should end here ----- +endmodule +// ----- END Verilog module for DFFSRQ ----- + +//----- Default net type ----- +`default_nettype wire + + +// ----- Template Verilog module for DFF ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for DFF ----- +module DFF(CK, + D, + Q, + QN); +//----- GLOBAL PORTS ----- +input [0:0] CK; +//----- INPUT PORTS ----- +input [0:0] D; +//----- OUTPUT PORTS ----- +output [0:0] Q; +//----- OUTPUT PORTS ----- +output [0:0] QN; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- + + +// ----- Internal logic should end here ----- +endmodule +// ----- END Verilog module for DFF ----- + +//----- Default net type ----- +`default_nettype wire + + +// ----- Template Verilog module for GPIO ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for GPIO ----- +module GPIO(PAD, + A, + DIR, + Y); +//----- GPIO PORTS ----- +inout [0:0] PAD; +//----- INPUT PORTS ----- +input [0:0] A; +//----- INPUT PORTS ----- +input [0:0] DIR; +//----- OUTPUT PORTS ----- +output [0:0] Y; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- + + +// ----- Internal logic should end here ----- +endmodule +// ----- END Verilog module for GPIO ----- + +//----- Default net type ----- +`default_nettype wire + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/wires.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/wires.v new file mode 100644 index 000000000..ab3ee5445 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/wires.v @@ -0,0 +1,36 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Wires +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Verilog modules for regular wires ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for direct_interc ----- +module direct_interc(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +wire [0:0] in; +wire [0:0] out; + assign out[0] = in[0]; +endmodule +// ----- END Verilog module for direct_interc ----- + +//----- Default net type ----- +`default_nettype wire + + +// ----- END Verilog modules for regular wires ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/config/task.conf b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/config/task.conf index 60c164b4d..7ea074a5f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/config/task.conf @@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_device_layout = 2x2 openfpga_vpr_route_chan_width = 20 openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp +openfpga_preconfig_fabric_wrapper_dump_waveform= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index e9c8f977d..8321cad47 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.4866067469 + #0.5400847197 clk[0] <= !clk[0]; end end @@ -106,7 +106,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #6.812494755 + #7.561185837 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 73d00c19f..e96165350 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,14 +9,14 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 9.732135098e-10 -waveform {0 4.866067549e-10} +create_clock clk[0] -period 1.080169398e-09 -waveform {0 5.400846992e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 9.732135098e-10 gfpga_pad_GPIO_PAD[22] -set_input_delay -clock clk[0] -max 9.732135098e-10 gfpga_pad_GPIO_PAD[26] -set_output_delay -clock clk[0] -max 9.732135098e-10 gfpga_pad_GPIO_PAD[9] +set_input_delay -clock clk[0] -max 1.080169398e-09 gfpga_pad_GPIO_PAD[22] +set_input_delay -clock clk[0] -max 1.080169398e-09 gfpga_pad_GPIO_PAD[26] +set_output_delay -clock clk[0] -max 1.080169398e-09 gfpga_pad_GPIO_PAD[9] ################################################## # Disable timing for unused I/Os @@ -90,58 +90,6 @@ set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing pReset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -168,6 +116,62 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q @@ -186,6 +190,10 @@ set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q @@ -194,24 +202,14 @@ set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -220,6 +218,8 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc index a07071979..ca7724279 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,822 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFFR_0_/D 5 @@ -897,132 +81,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFFR_1_/Q -to fpga_top/ set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFFR_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_2_/D 5 @@ -1285,8 +345,968 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_4_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_2_/D 5 @@ -1961,208 +1981,188 @@ set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 5 set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_2_/D 5 @@ -2921,188 +2921,176 @@ set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_7_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 5 set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_2_/D 5 @@ -3861,224 +3849,236 @@ set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_7_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 5 set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index b5e84a4e8..2a3f42473 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,58 +6,6 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -84,6 +32,62 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q @@ -102,6 +106,10 @@ set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q @@ -110,24 +118,14 @@ set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -136,6 +134,8 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit index 3575fa16e..5336e6ed6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -339,13 +339,13 @@ 0 0 0 +1 0 0 0 0 0 -0 -0 +1 0 0 0 @@ -357,11 +357,13 @@ 0 0 0 +1 +0 0 0 -1 0 0 +1 0 0 0 @@ -375,21 +377,21 @@ 0 1 0 -1 -0 0 0 0 0 +1 0 0 -1 0 0 0 +1 0 0 0 +1 0 1 0 @@ -397,7 +399,7 @@ 0 0 0 -1 +0 0 1 0 @@ -407,7 +409,7 @@ 0 0 0 -1 +0 0 0 0 @@ -421,7 +423,7 @@ 0 0 0 -1 +0 0 1 0 @@ -429,10 +431,14 @@ 0 0 0 +1 +0 0 0 1 0 +1 +0 0 0 0 @@ -445,7 +451,7 @@ 0 0 0 -1 +0 0 1 0 @@ -827,19 +833,19 @@ 0 0 0 +1 0 0 0 0 0 +1 0 0 0 0 0 -0 -0 -0 +1 0 0 0 @@ -863,11 +869,11 @@ 0 0 0 -1 -0 0 0 +1 0 +1 0 1 0 @@ -877,7 +883,6 @@ 0 0 0 -1 0 0 0 @@ -885,15 +890,15 @@ 0 0 0 -1 0 0 0 +1 +1 0 0 0 0 -1 0 0 0 @@ -904,16 +909,11 @@ 0 0 0 -1 -1 0 0 0 0 0 -1 -0 -1 0 0 0 @@ -1297,26 +1297,20 @@ 0 0 0 -1 -0 0 0 0 0 -1 0 0 0 0 0 -1 0 0 0 0 0 -1 -0 0 0 0 @@ -1345,6 +1339,7 @@ 0 0 0 +1 0 0 0 @@ -1352,6 +1347,7 @@ 0 0 0 +1 0 0 0 @@ -1359,6 +1355,7 @@ 0 0 0 +1 0 0 0 @@ -1366,13 +1363,7 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 +1 0 0 0 @@ -1390,10 +1381,9 @@ 0 0 0 +1 0 -0 -0 -0 +1 0 0 0 @@ -1735,25 +1725,21 @@ 0 0 0 -1 0 0 0 0 0 -1 0 0 0 0 0 -1 -0 0 0 +1 0 0 -1 0 0 0 @@ -1765,6 +1751,8 @@ 0 0 0 +0 +0 1 0 0 @@ -1773,15 +1761,15 @@ 0 1 0 +1 0 0 0 0 -1 -0 0 0 0 +1 0 0 0 @@ -1789,11 +1777,13 @@ 0 0 0 +1 0 0 0 0 0 +1 0 1 0 @@ -1811,13 +1801,13 @@ 0 0 0 -1 -0 0 0 +1 0 0 0 +1 0 1 0 @@ -1841,15 +1831,23 @@ 0 0 0 +1 0 +1 +1 +1 +1 +1 +1 +1 +1 +1 0 0 0 0 0 -0 -0 -0 +1 0 0 0 @@ -1868,14 +1866,6 @@ 0 0 1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 @@ -1909,7 +1899,7 @@ 0 0 0 -0 +1 0 1 0 @@ -1917,13 +1907,12 @@ 0 0 0 -1 0 0 +1 0 0 0 -1 0 0 0 @@ -1934,16 +1923,19 @@ 0 0 0 +1 0 0 0 0 0 +1 0 0 0 0 0 +1 0 0 0 @@ -1951,13 +1943,19 @@ 0 0 0 +1 0 0 +1 +0 0 +1 0 0 +1 0 0 +1 0 0 0 @@ -2027,13 +2025,10 @@ 0 0 0 -1 0 0 0 -1 0 -1 0 0 0 @@ -2041,7 +2036,6 @@ 0 0 0 -1 0 0 0 @@ -2055,12 +2049,54 @@ 0 0 0 -1 0 0 0 0 0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 1 0 0 @@ -2073,31 +2109,41 @@ 0 0 0 +1 +0 0 0 -1 0 0 1 0 0 -1 +0 0 0 1 0 0 +0 +0 +0 1 0 0 0 0 0 +1 0 0 0 0 0 +1 +0 +0 +0 +0 0 0 0 @@ -2127,38 +2173,38 @@ 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 0 -1 0 0 0 0 0 1 +1 0 0 0 0 0 -1 0 0 0 0 0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 1 0 0 @@ -2187,7 +2233,7 @@ 0 0 0 -1 +0 0 1 0 @@ -2195,6 +2241,10 @@ 0 0 0 +1 +0 +0 +0 0 0 1 @@ -2221,17 +2271,15 @@ 0 0 0 -1 0 0 +1 0 0 0 -1 0 0 0 -1 0 1 0 @@ -2250,38 +2298,28 @@ 0 0 1 -1 -1 -1 -1 -1 0 -1 -1 0 0 0 0 0 -1 0 +1 0 0 0 0 -1 0 0 0 0 0 -1 0 0 0 0 0 -1 0 0 0 @@ -2293,13 +2331,9 @@ 0 0 0 -0 -0 1 0 -1 0 -1 0 0 0 @@ -2317,8 +2351,6 @@ 0 0 0 -1 -1 0 0 0 @@ -2341,35 +2373,3 @@ 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml index a2bf18b06..09c3c7723 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -682,1161 +682,1161 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2598,2157 +2598,2157 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml new file mode 100644 index 000000000..124109017 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml @@ -0,0 +1,1105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v index 0ca441363..cf224f409 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v @@ -359,7 +359,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__2__0_ccff_tail), + .ccff_head(grid_io_top_1_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -382,7 +382,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__2__1_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -451,7 +451,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_1_ccff_tail), + .ccff_head(cbx_1__0__1_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -474,7 +474,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -684,7 +684,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_1_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:9]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:9]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -715,7 +715,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__2__0_ccff_tail), + .ccff_head(grid_io_left_1_ccff_tail), .chany_top_out(sb_0__1__0_chany_top_out[0:9]), .chanx_right_out(sb_0__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:9]), @@ -781,7 +781,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:9]), .chanx_right_out(sb_1__0__0_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:9]), @@ -810,7 +810,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_5_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_6_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_7_), - .ccff_head(grid_clb_3_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_top_out(sb_1__1__0_chany_top_out[0:9]), .chanx_right_out(sb_1__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:9]), @@ -843,7 +843,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_top_1_ccff_tail), + .ccff_head(grid_clb_3_ccff_tail), .chanx_right_out(sb_1__2__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:9]), .chanx_left_out(sb_1__2__0_chanx_left_out[0:9]), @@ -878,7 +878,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_0_ccff_tail), + .ccff_head(grid_io_bottom_1_ccff_tail), .chany_top_out(sb_2__0__0_chany_top_out[0:9]), .chanx_left_out(sb_2__0__0_chanx_left_out[0:9]), .ccff_tail(sb_2__0__0_ccff_tail)); @@ -917,7 +917,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_5_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_6_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_7_), - .ccff_head(grid_clb_2_ccff_tail), + .ccff_head(grid_clb_0_ccff_tail), .chany_top_out(sb_2__1__0_chany_top_out[0:9]), .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:9]), .chanx_left_out(sb_2__1__0_chanx_left_out[0:9]), @@ -948,7 +948,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_5__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_clb_2_ccff_tail), .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:9]), .chanx_left_out(sb_2__2__0_chanx_left_out[0:9]), .ccff_tail(sb_2__2__0_ccff_tail)); @@ -1074,7 +1074,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:9]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1093,7 +1093,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__0_chany_top_out[0:9]), .chany_top_in(sb_0__2__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(sb_0__2__0_ccff_tail), .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_0__1__1_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1112,7 +1112,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:9]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1129,7 +1129,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__0_chany_top_out[0:9]), .chany_top_in(sb_1__2__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(cbx_1__2__0_ccff_tail), .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_1__1__1_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1146,7 +1146,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_2__0__0_chany_top_out[0:9]), .chany_top_in(sb_2__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__1_ccff_tail), + .ccff_head(cbx_1__1__1_ccff_tail), .chany_bottom_out(cby_2__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_2__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_2__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -1170,7 +1170,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_2__1__0_chany_top_out[0:9]), .chany_top_in(sb_2__2__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__1_ccff_tail), + .ccff_head(cbx_1__2__1_ccff_tail), .chany_bottom_out(cby_2__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_2__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_2__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc index f0d0e3c9b..610adfd62 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 9.732135098e-10 -waveform {0 4.866067549e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 1.080169398e-09 -waveform {0 5.400846992e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index 8e3ce2cdb..58b265d13 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml index 598b91e22..15a476439 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index 4742a8f45..9fc5a8117 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml index d96c9a38d..405c9abaf 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml index 853598113..d3421c3bc 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml index a5aff3785..586a15615 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml index 6b76a5c9a..8cee42a6f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml @@ -1,34 +1,34 @@ - + - + - + - + - + - + - + - + @@ -39,44 +39,44 @@ - - + + - - + + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml index a44b3a915..b92fd2831 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -39,8 +39,8 @@ - - + + @@ -53,25 +53,25 @@ - + - + - + - + @@ -103,9 +103,9 @@ - - - + + + @@ -123,9 +123,9 @@ - - - + + + @@ -142,8 +142,8 @@ - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml index e9a236355..40001d7a5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml @@ -1,34 +1,34 @@ - + - + - + - + - + - + - + - + @@ -39,35 +39,35 @@ - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml index 5852252cc..20c1fff92 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml @@ -1,24 +1,24 @@ - + - + - + - + @@ -48,10 +48,10 @@ - - - - + + + + @@ -70,10 +70,10 @@ - - - - + + + + @@ -90,10 +90,10 @@ - - - - + + + + @@ -108,10 +108,10 @@ - - - - + + + + @@ -128,10 +128,10 @@ - - - - + + + + @@ -148,10 +148,10 @@ - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml index c8a81010f..5f6ce3d54 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml @@ -1,7 +1,7 @@ - - + + @@ -24,7 +24,7 @@ - + @@ -44,7 +44,7 @@ - + @@ -62,8 +62,8 @@ - - + + @@ -85,7 +85,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -123,8 +123,8 @@ - - + + @@ -145,7 +145,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -185,8 +185,8 @@ - - + + @@ -206,7 +206,7 @@ - + @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml index 6c03f3109..d5a883d4b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -40,8 +40,8 @@ - - + + @@ -53,24 +53,24 @@ - + - + - + - + @@ -102,9 +102,9 @@ - - - + + + @@ -122,9 +122,9 @@ - - - + + + @@ -141,8 +141,8 @@ - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml index 520bdb20f..0eb3629ba 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml @@ -1,86 +1,86 @@ - - + + - - + + - + - + - + - + - + - + - + - + - - + + - - + + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml index fa68d4ad3..07cd62c33 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml @@ -1,9 +1,9 @@ - - - - + + + + @@ -22,10 +22,10 @@ - - - - + + + + @@ -42,10 +42,10 @@ - - - - + + + + @@ -59,10 +59,10 @@ - - - - + + + + @@ -79,10 +79,10 @@ - - - - + + + + @@ -99,10 +99,10 @@ - - - - + + + + @@ -115,25 +115,25 @@ - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml index 4a8ca3efe..09fbf2ac6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml @@ -1,77 +1,77 @@ - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 3afea90e8..d09d7c254 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml index 3a9b8024d..6b47a0491 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index 2e584b8ab..6acef668f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml index f3b69185d..106e8f2bb 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml index 6561ddb64..c3c93bfa1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml index 5d742ce89..b99a0f7f3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/mux_modules.yaml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/mux_modules.yaml new file mode 100644 index 000000000..8ee171e0a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/mux_modules.yaml @@ -0,0 +1,54 @@ +sb_0__0_: + - mux_2level_tapbuf_size2 + - mux_2level_tapbuf_size3 +sb_0__1_: + - mux_2level_tapbuf_size9 + - mux_2level_tapbuf_size8 + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size4 + - mux_2level_tapbuf_size2 + - mux_2level_tapbuf_size7 +sb_0__2_: + - mux_2level_tapbuf_size2 +sb_1__0_: + - mux_2level_tapbuf_size5 + - mux_2level_tapbuf_size4 + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size2 + - mux_2level_tapbuf_size10 + - mux_2level_tapbuf_size9 + - mux_2level_tapbuf_size11 +sb_1__1_: + - mux_2level_tapbuf_size13 + - mux_2level_tapbuf_size9 +sb_1__2_: + - mux_2level_tapbuf_size9 + - mux_2level_tapbuf_size7 + - mux_2level_tapbuf_size4 + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size2 +sb_2__0_: + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size2 +sb_2__1_: + - mux_2level_tapbuf_size11 + - mux_2level_tapbuf_size9 + - mux_2level_tapbuf_size10 + - mux_2level_tapbuf_size4 + - mux_2level_tapbuf_size2 +sb_2__2_: + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size2 +cbx_1__0_: + - mux_2level_tapbuf_size2 + - mux_2level_tapbuf_size4 +cbx_1__1_: + - mux_2level_tapbuf_size2 +cbx_1__2_: + - mux_2level_tapbuf_size4 +cby_0__1_: + - mux_2level_tapbuf_size4 +cby_1__1_: + - mux_2level_tapbuf_size4 +cby_2__1_: + - mux_2level_tapbuf_size4 diff --git a/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_bin/config/task.conf new file mode 100644 index 000000000..99dc26c0c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_bin/config/task.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=60 +openfpga_vpr_rr_graph_file=rr_graph.bin + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_xml/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_xml/config/task.conf new file mode 100644 index 000000000..856d7a45c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_xml/config/task.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=60 +openfpga_vpr_rr_graph_file=rr_graph.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/task.conf new file mode 100644 index 000000000..ca93b9ec3 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/task.conf @@ -0,0 +1,45 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin +openfpga_unique_block_file_read=bin +openfpga_unique_block_file_write=xml +write_unique_blocks=write_unique_block.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/read_unique_block.bin b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/read_unique_block.bin new file mode 100644 index 000000000..30cf2a5c3 Binary files /dev/null and b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_bin_write_xml/read_unique_block.bin differ diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf new file mode 100644 index 000000000..53e0da4dd --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin +openfpga_unique_block_file=bin +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin new file mode 100644 index 000000000..30cf2a5c3 Binary files /dev/null and b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_bin/read_unique_block.bin differ diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf new file mode 100644 index 000000000..bd72c7d3e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml +openfpga_unique_block_file=xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml new file mode 100644 index 000000000..12570d65e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf new file mode 100644 index 000000000..4246bdcdc --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf @@ -0,0 +1,45 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml +openfpga_unique_block_file_read=xml +openfpga_unique_block_file_write=xml +write_unique_blocks=write_unique_block.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/read_unique_block.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/read_unique_block.xml new file mode 100644 index 000000000..12570d65e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/read_unique_block.xml @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf new file mode 100644 index 000000000..3a30ebb5f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/task.conf @@ -0,0 +1,45 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin +openfpga_unique_block_file_read=bin +openfpga_unique_block_file_write=bin +write_unique_blocks=write_unique_block.bin +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin new file mode 100644 index 000000000..30cf2a5c3 Binary files /dev/null and b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks_bin/read_unique_block.bin differ diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf new file mode 100644 index 000000000..82ad03f4b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +write_unique_blocks=write_unique_block.bin +openfpga_unique_block_file=bin +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_bin_unique_blocks_full_flow/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf new file mode 100644 index 000000000..f82062160 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +write_unique_blocks=write_unique_blocks.xml +openfpga_unique_block_file=xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf b/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf new file mode 100644 index 000000000..0fa9feefd --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_report_reference_module_options=--file reference_module.yaml --module fpga_top +openfpga_report_reference_verbose_options=--file reference_verbose.yaml --module fpga_top --verbose +openfpga_report_reference_no_time_stamp_options=--file reference_no_time_stamp.yaml --module grid_io_right --no_time_stamp + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml new file mode 100644 index 000000000..2b85f88cd --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf new file mode 100644 index 000000000..f9c6517ab --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/clk_arch_1clk_2layer.xml new file mode 100644 index 000000000..1daf67644 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/clk_arch_1clk_2layer.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/task.conf new file mode 100644 index 000000000..f9d70a261 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_IoSubtile_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf new file mode 100644 index 000000000..99a16d52e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup/config/task.conf new file mode 100644 index 000000000..7bc24a3c0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options=--skip_sync_clustering_and_routing_results on +openfpga_pb_pin_fixup_command=pb_pin_fixup --verbose +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf new file mode 100644 index 000000000..c07a08d33 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml new file mode 100644 index 000000000..026c140be --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml index 0570406fd..6f289dbf4 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml @@ -1,5 +1,5 @@ - - + + @@ -11,7 +11,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf new file mode 100644 index 000000000..08aca9064 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options=--skip_sync_clustering_and_routing_results on +openfpga_pb_pin_fixup_command=pb_pin_fixup +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml new file mode 100644 index 000000000..026c140be --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf new file mode 100644 index 000000000..4e6a514f3 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x3 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/task.conf b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/task.conf new file mode 100644 index 000000000..094b80b88 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=auto +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_fabric_pin_phy_loc_file=fabric_pin_phy_loc.xml +openfpga_fabric_pin_phy_loc_module= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf new file mode 100644 index 000000000..a8fcda0db --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=auto +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_fabric_pin_phy_loc_file=fabric_pin_phy_loc.xml +openfpga_fabric_pin_phy_loc_module=--module tile* + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/task.conf b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/task.conf new file mode 100644 index 000000000..a6abb1e92 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=auto +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_fabric_pin_phy_loc_file=fabric_pin_phy_loc.xml +openfpga_fabric_pin_phy_loc_module=--module tile* --show_invalid_side + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/task.conf b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/task.conf new file mode 100644 index 000000000..1382ad6f0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=auto +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_fabric_pin_phy_loc_file=fabric_pin_phy_loc.xml +openfpga_fabric_pin_phy_loc_module=--module * + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/fpga_bitstream/extract_dsp_mode_bit/config/bitstream_annotation.xml b/openfpga_flow/tasks/fpga_bitstream/extract_dsp_mode_bit/config/bitstream_annotation.xml new file mode 100644 index 000000000..7c835ad7e --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/extract_dsp_mode_bit/config/bitstream_annotation.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/extract_dsp_mode_bit/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/extract_dsp_mode_bit/config/task.conf new file mode 100644 index 000000000..908678571 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/extract_dsp_mode_bit/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_bitstream_setting_file=${PATH:TASK_DIR}/config/bitstream_annotation.xml +# VPR parameter +openfpga_vpr_circuit_format=eblif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v +bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v +bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys +bench0_top = mult8 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/task.conf new file mode 100644 index 000000000..67a1e028c --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/test.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_bitstream_setting_file=bitstream_annotation.xml +openfpga_vpr_device_layout=4x4 +openfpga_ext_exec_python_script=${PATH:TASK_DIR}/config/test.py + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/test.openfpga b/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/test.openfpga new file mode 100644 index 000000000..1e9e3f79c --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/test.openfpga @@ -0,0 +1,53 @@ +# Majority of the content refer to fix_device_example_script.openfpga + +ext_exec --command "python3 ${OPENFPGA_EXT_EXEC_PYTHON_SCRIPT} run_golden ${OPENFPGA_PATH}" + +ext_exec --command "python3 ${OPENFPGA_EXT_EXEC_PYTHON_SCRIPT} generate_testcase" + +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Read OpenFPGA bitstream settings +read_openfpga_bitstream_setting -f ${OPENFPGA_BITSTREAM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +ext_exec --command "python3 ${OPENFPGA_EXT_EXEC_PYTHON_SCRIPT} validate" + +# Finish and exit OpenFPGA +exit diff --git a/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/test.py b/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/test.py new file mode 100644 index 000000000..2997bb5d6 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/test.py @@ -0,0 +1,120 @@ +import xml.etree.ElementTree as ET +import sys +import shutil +import os +import random + +random.seed() +assert len(sys.argv) >= 2 +assert sys.argv[1] in ["run_golden", "generate_testcase", "validate"] +TEST_BIT_COUNT = 200 + +def read_fabric_bitstream_xml(file) : + + bit_count = 0 + tree = ET.parse(file) + root = tree.getroot() + assert root.tag == "fabric_bitstream", "Root tag is not 'fabric_bitstream', but '%s'" % root.tag + for region in root : + assert region.tag == "region", "fabric_bitstream child node tag is not 'region', but '%s'" % region.tag + for bit in region : + assert bit.tag == "bit", "region child node tag is not 'bit', but '%s'" % bit.tag + assert "path" in bit.attrib, "Attribute 'path' does not exist in bit node" + assert "value" in bit.attrib, "Attribute 'value' does not exist in bit node" + assert bit.attrib["value"] in ["0", "1"] + bit_count += 1 + return [tree, bit_count] + +def read_bitstream_annotation_xml(file) : + + xml = {} + tree = ET.parse(file) + root = tree.getroot() + assert root.tag == "openfpga_bitstream_setting", "Root tag is not 'openfpga_bitstream_setting', but '%s'" % root.tag + for overwrite_bitstream in root : + assert overwrite_bitstream.tag == "overwrite_bitstream", "openfpga_bitstream_setting child node tag is not 'overwrite_bitstream', but '%s'" % overwrite_bitstream.tag + for bit in overwrite_bitstream : + assert bit.tag == "bit", "overwrite_bitstream child node tag is not 'bit', but '%s'" % bit.tag + assert "path" in bit.attrib, "Attribute 'path' does not exist in bit node" + assert "value" in bit.attrib, "Attribute 'value' does not exist in bit node" + path = bit.attrib["path"] + assert path not in xml + index = path.rfind("[") + assert index != -1 + path = "%s.mem_out%s" % (path[:index], path[index:]) + assert path not in xml + assert bit.attrib["value"] in ["0", "1"] + xml[path] = bit.attrib["value"] + return xml + +if sys.argv[1] == "run_golden" : + + assert len(sys.argv) >= 3 + openfpga_exe = os.path.abspath("%s/build/openfpga/openfpga" % sys.argv[2]) + assert os.path.exists(openfpga_exe) + shutil.rmtree("golden", ignore_errors=True) + os.mkdir("golden") + original_openfpga = open("and2_run.openfpga") + golden_openfpga = open("golden/and2_run.openfpga", "w") + for line in original_openfpga : + if line.find("ext_exec") == 0 : + pass + else : + golden_openfpga.write(line) + golden_openfpga.close() + original_openfpga.close() + bitstream_annotation = open("golden/bitstream_annotation.xml", "w") + bitstream_annotation.write("\n") + bitstream_annotation.close() + shutil.copyfile("and2.blif", "golden/and2.blif") + shutil.copyfile("and2_ace_out.act", "golden/and2_ace_out.act") + cmd = "cd golden && %s -batch -f and2_run.openfpga > golden.log" % (openfpga_exe) + assert os.system(cmd) == 0 + +elif sys.argv[1] == "generate_testcase" : + + (tree, bit_count) = read_fabric_bitstream_xml("golden/fabric_bitstream.xml") + random_bits = [] + while len(random_bits) != TEST_BIT_COUNT : + bit = random.randint(0, bit_count - 1) + if bit not in random_bits : + random_bits.append(bit) + bitstream_annotation = open("bitstream_annotation.xml", "w") + bitstream_annotation.write("\n") + bitstream_annotation.write(" \n") + index = 0 + for region in tree.getroot() : + for bit in region : + if index in random_bits : + path = bit.attrib["path"] + value = bit.attrib["value"] + assert value in ["0", "1"] + path = path.replace(".mem_out[", "[") + bitstream_annotation.write(" \n" % ("1" if value == "0" else "0", path)) + index += 1 + bitstream_annotation.write(" \n") + bitstream_annotation.write("\n") + bitstream_annotation.close() + +else : + + gtree = ET.parse("golden/fabric_bitstream.xml") + tree = ET.parse("fabric_bitstream.xml") + bitstream_annotation = read_bitstream_annotation_xml("bitstream_annotation.xml") + checked_count = 0 + for gregion, region in zip(gtree.getroot(), tree.getroot()) : + for gbit, bit in zip(gregion, region) : + assert bit.attrib["path"] == gbit.attrib["path"] + path = bit.attrib["path"] + if path in bitstream_annotation : + # This is something we want to overwrite, hence the value should + # Same in the annotation file + # Not same in golden fabric + assert bit.attrib["value"] != gbit.attrib["value"] + assert bit.attrib["value"] == bitstream_annotation[path] + else : + # This is not what we want to overwrite + # Hence the value should same in golden fabric + assert bit.attrib["value"] == gbit.attrib["value"] + +exit(0) diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml index 71153e425..748e23269 100644 --- a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml @@ -2,7 +2,7 @@ - + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf index 63ffd257c..6076c364f 100644 --- a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf @@ -28,6 +28,8 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_lo [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/two_dff_inv_rst/two_dff_inv_rst.v bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_8bit/rst_on_lut_8bit.v [SYNTHESIS_PARAM] # Yosys script parameters @@ -45,6 +47,14 @@ bench1_top = rst_on_lut bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml bench1_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml +bench2_top = rst_on_lut_4bit +bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml +bench2_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml + +bench3_top = rst_on_lut_8bit +bench3_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml +bench3_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml + [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2_last_stage/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2_last_stage/config/task.conf new file mode 100644 index 000000000..d9b3a1757 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2_last_stage/config/task.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_laststage_mux_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit0/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit0/config/task.conf new file mode 100644 index 000000000..461859af6 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit0/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x3 +openfpga_verilog_undriven_input_type=bit0 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit1/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit1/config/task.conf new file mode 100644 index 000000000..ade3f8a34 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit1/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x3 +openfpga_verilog_undriven_input_type=bit1 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus0/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus0/config/task.conf new file mode 100644 index 000000000..078590872 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus0/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x3 +openfpga_verilog_undriven_input_type=bus0 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus1/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus1/config/task.conf new file mode 100644 index 000000000..310cf2adc --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus1/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x3 +openfpga_verilog_undriven_input_type=bus1 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none/config/task.conf new file mode 100644 index 000000000..b44946e4b --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x3 +openfpga_verilog_undriven_input_type=none + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none_force/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none_force/config/task.conf new file mode 100644 index 000000000..b0246bb33 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none_force/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x3 +openfpga_verilog_undriven_input_type=none + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 65f3c3d55..2c69935c6 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -23,6 +23,7 @@ Please reveal the following architecture features in the names to help quickly s - reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs - registerable\_io: If I/Os are registerable (can be either combinational or sequential) - IoSubtile: If I/O block contains sub tiles (more compact with a higher density of I/Os) +- PerimeterCb: If connection blocks can occur on perimeter I/Os (I/O tile has more routability) - CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax - rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture - localClkGen: The clock signal of CLB can be generated by internal programmable resources @@ -33,6 +34,7 @@ Please reveal the following architecture features in the names to help quickly s * Top-right (Tr): the pins of a tile are placed on the top side and right side only * Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only - GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks +- ecb: *Enhanced Connection Block* where connection blocks includes feedback connections Other features are used in naming should be listed here. diff --git a/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml new file mode 100644 index 000000000..c9899d852 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml @@ -0,0 +1,373 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + clb.clk + clb.I2[0:3] clb.I3[0:3] clb.O[2:3] + + clb.I0[0:3] clb.I1[0:3] clb.O[0:1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml new file mode 100644 index 000000000..142784a73 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -0,0 +1,345 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + fpga_input_center[1:0].inpad + fpga_input_center[3:2].inpad + fpga_input_center[4:4].inpad + fpga_input_center[5:5].inpad + + + + + + + + + + fpga_output_center[1:0].outpad + + fpga_output_center[3:2].outpad + + + + + + + + + + + + + + + + fpga_input[0:3].inpad + + + + + + + + + + + + fpga_output[0:0].outpad + fpga_output[1:1].outpad + + + + + + + + + + + + fpga_input[0:3].inpad + + + + + + + + + + + + + fpga_output[0:0].outpad + + fpga_output[1:1].outpad + + + + + + + + + + + + + + + fpga_input[0:3].inpad + + + + + + + + + + + + fpga_output[0:0].outpad + fpga_output[1:1].outpad + + + + + + + + + + + + + + fpga_input[0:3].inpad + + + + + + + + + + + + + fpga_output[0:0].outpad + + fpga_output[1:1].outpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml index f4e40b275..231aef08b 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml @@ -59,7 +59,7 @@ - + @@ -250,7 +250,7 @@ - + diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_IoSubtile_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_IoSubtile_40nm.xml new file mode 100644 index 000000000..1bc930519 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_IoSubtile_40nm.xml @@ -0,0 +1,506 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + fpga_input[0:5].clk[0:0] + fpga_input[0:5].inpad[0:0] + + + + + + + + + + + + + fpga_output[0:1].outpad[0:0] + + fpga_output[2:3].outpad fpga_output[0:5].clk[0:0] + fpga_output[4:5].outpad[0:0] + + + + + + + + + + + + + + + fpga_input[0:2].inpad[0:0] fpga_input[0:2].clk[0:0] + + + + + + + + + + + + + + + + fpga_output[0:0].outpad[0:0] fpga_output[0:2].clk[0:0] + + fpga_output[1:1].outpad[0:0] + fpga_output[2:2].outpad[0:0] + + + + + + + + + + + + + + + fpga_input[0:3].clk[0:0] + + fpga_input[0:3].inpad[0:0] + + + + + + + + + + + + + + fpga_output[0:1].outpad[0:0] fpga_output[0:3].clk[0:0] + + fpga_output[2:2].outpad[0:0] + fpga_output[3:3].outpad[0:0] + + + + + + + + + + + + + + + fpga_input[0:3].inpad[0:0] fpga_input[0:3].clk[0:0] + + + + + + + + + + + + + + + + fpga_output[0:1].outpad[0:0] fpga_output[0:3].clk[0:0] + + fpga_output[2:2].outpad[0:0] + fpga_output[3:3].outpad[0:0] + + + + + + + + + + + + + + + + clb.I[0:1] clb.O[0:0] + clb.I[2:3] clb.O[1:1] clb.clk + clb.I[4:6] clb.O[2:2] + clb.I[7:9] clb.O[3:3] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml new file mode 100644 index 000000000..fe403bd62 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -0,0 +1,407 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_top[0:1].outpad[0:0] + + io_top[2:3].outpad io_top[0:5].clk[0:0] + io_top[4:5].outpad[0:0] io_top[0:5].inpad[0:0] + + + + + + + + + + + + + + + + io_right[0:0].outpad[0:0] io_right[0:2].inpad[0:0] io_right[0:2].clk[0:0] + + io_right[1:1].outpad[0:0] + io_right[2:2].outpad[0:0] + + + + + + + + + + + + + + + + io_bottom[0:1].outpad[0:0] io_bottom[0:3].clk[0:0] + + io_bottom[2:2].outpad[0:0] io_bottom[0:3].inpad[0:0] + io_bottom[3:3].outpad[0:0] + + + + + + + + + + + + + + + + io_left[0:1].outpad[0:0] io_left[0:3].inpad[0:0] io_left[0:3].clk[0:0] + + io_left[2:2].outpad[0:0] + io_left[3:3].outpad[0:0] + + + + + + + + + + + + + + + + clb.I[0:1] clb.O[0:0] + clb.I[2:3] clb.O[1:1] clb.clk + clb.I[4:6] clb.O[2:2] + clb.I[7:9] clb.O[3:3] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_TileOrgzTr_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_TileOrgzTr_fracff_40nm.xml new file mode 100644 index 000000000..0d07fa612 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_TileOrgzTr_fracff_40nm.xml @@ -0,0 +1,642 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + clb.O[0:3] clb.I[0:5] + clb.reset clb.clk clb.O[4:7] clb.I[6:11] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml index 095a82096..038161627 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml @@ -136,7 +136,7 @@ - + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index cc4d5de0e..b105149b1 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -107,7 +107,13 @@ - + + + + + clb.reset clb.clk clb.O[0:3] clb.I[0:5] + clb.O[4:7] clb.I[6:11] + @@ -194,6 +200,11 @@ With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> + + + 1 1 + 1 + 1 1 1 1 1 diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml new file mode 100644 index 000000000..111b5709d --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml @@ -0,0 +1,642 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.reset clb.clk + + clb.O[0:3] clb.I[0:5] + clb.O[4:7] clb.I[6:11] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/requirements.txt b/requirements.txt index 889fe9159..502bfc8e0 100644 --- a/requirements.txt +++ b/requirements.txt @@ -5,5 +5,5 @@ pyverilog # Python linter and formatter click==8.0.2 # Our version of black needs an older version of click (https://stackoverflow.com/questions/71673404/importerror-cannot-import-name-unicodefun-from-click) -black==20.8b1 +black==24.3.0 pylint==2.7.4 diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index eb9722851..39c80f444 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit eb9722851bd3de03df7fb9ace5bdfb9cb078ca83 +Subproject commit 39c80f444fb37b81681294aadae6dc518f79ac8b diff --git a/yosys b/yosys index 8bd681acf..0200a7680 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 8bd681acfc3b0913e57f6312ed357b2334cf19cb +Subproject commit 0200a7680a2d012e7737b01f07ec354b1bddf602 diff --git a/yosys-plugins b/yosys-plugins index 7c89a55eb..dfe9b1a15 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit 7c89a55eb20efa4184fefa5c0bd1096d311a6ded +Subproject commit dfe9b1a15b494e7dd81a2b394dac30ea707ec5cc