remove input port requirements for SRAM circuit module

vpr7_x2p/libarchfpga/SRC/read_xml_spice.c

@@ -1300,18 +1300,15 @@ static void check_spice_models(int num_spice_model,
     /* Check sram has been defined and has input and output ports*/
     if (SPICE_MODEL_SRAM == spice_models[i].type) {
       has_sram = 1;
-      has_in_port = 0;
       has_out_port = 0;
       for (j = 0; j < spice_models[i].num_port; j++) {
-        if (SPICE_MODEL_PORT_INPUT == spice_models[i].ports[j].type) {
+        if (SPICE_MODEL_PORT_OUTPUT == spice_models[i].ports[j].type) {
-          has_in_port = 1;
-        } else if (SPICE_MODEL_PORT_OUTPUT == spice_models[i].ports[j].type) {
           has_out_port = 1;
         }
       }
       /* Check if we have two ports*/
-      if ((0 == has_in_port)||(0 == has_out_port)) {
+      if (0 == has_out_port) {
-        vpr_printf(TIO_MESSAGE_ERROR,"SRAM Spice model(%s) does not have input|output port\n",spice_models[i].name);
+        vpr_printf(TIO_MESSAGE_ERROR, "SRAM Spice model(%s) does not have output port\n", spice_models[i].name);
         exit(1);
       }
     }

vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c

@@ -2020,8 +2020,6 @@ void update_spice_models_routing_index_low(int x, int y, t_rr_type chan_type,
  */
 void check_sram_spice_model_ports(t_spice_model* cur_spice_model,
                                   boolean include_bl_wl) {
-  int num_input_ports;
-  t_spice_model_port** input_ports = NULL;
   int num_output_ports;
   t_spice_model_port** output_ports = NULL;
   int num_bl_ports;
@@ -2036,24 +2034,6 @@ void check_sram_spice_model_ports(t_spice_model* cur_spice_model,
   /* Check the type of SPICE model */
   assert(SPICE_MODEL_SRAM == cur_spice_model->type);
 
-  /* Check if we has 1 input other than global ports */
-  input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, TRUE);
-  num_global_ports = 0;
-  for (iport = 0; iport < num_input_ports; iport++) {
-    if (TRUE == input_ports[iport]->is_global) {
-      num_global_ports++;
-    }
-  }
-  if (1 != (num_input_ports - num_global_ports)) {
-    vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have only 1 non-global input port!\n",
-               __FILE__, __LINE__);
-    num_err++;
-    if (1 != input_ports[0]->size) {
-      vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have an input port with size 1!\n",
-                 __FILE__, __LINE__);
-      num_err++;
-    }
-  }
   /* Check if we has 1 output with size 2 */
   output_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_ports, TRUE);
   num_global_ports = 0;
@@ -2112,7 +2092,6 @@ void check_sram_spice_model_ports(t_spice_model* cur_spice_model,
   }
 
   /* Free */
-  my_free(input_ports);
   my_free(output_ports);
   my_free(bl_ports);
   my_free(wl_ports);

vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp

@@ -1346,11 +1346,11 @@ const char* RRGSB::gen_cb_verilog_routing_track_name(t_rr_type cb_type,
   std::string y_str = std::to_string(get_cb_y(cb_type));
   std::string track_id_str = std::to_string(track_id);
   
-  ret = (char*)my_malloc(cb_name.length()
+  ret = (char*)my_malloc(sizeof(char) * (cb_name.length()
                          + 1 + x_str.length()
                          + 2 + y_str.length()
                          + 9 + track_id_str.length()
-                         + 1 + 1);
+                         + 1 + 1));
 
   sprintf(ret, "%s_%s__%s__midout_%s_",
           cb_name.c_str(), x_str.c_str(), y_str.c_str(), track_id_str.c_str());
@@ -1389,7 +1389,7 @@ const char* RRGSB::gen_sb_verilog_side_module_name(enum e_side side, size_t seg_
   std::string prefix(gen_sb_verilog_module_name());
   char* ret = NULL;
 
-  ret = (char*) my_malloc (prefix.length() + 1 + side_str.length() + 5 + seg_id_str.length() + 1 + 1);
+  ret = (char*) my_malloc (sizeof(char) * (prefix.length() + 1 + side_str.length() + 5 + seg_id_str.length() + 1 + 1));
   sprintf(ret, "%s_%s_seg_%s_", prefix.c_str(), side_str.c_str(), seg_id_str.c_str());
 
   return ret;
@@ -1409,7 +1409,7 @@ const char* RRGSB::gen_sb_verilog_side_instance_name(enum e_side side, size_t se
 
   std::string prefix(gen_sb_verilog_side_module_name(side, seg_id));
   char* ret = NULL;
-  ret = (char*) my_malloc (prefix.length() + 3 + 1);
+  ret = (char*) my_malloc (sizeof(char)* (prefix.length() + 3 + 1));
   sprintf(ret, "%s_0_", prefix.c_str());
 
   return ret;
@@ -1426,9 +1426,17 @@ const char* RRGSB::gen_cb_verilog_module_name(t_rr_type cb_type) const {
   /* check */
   assert (validate_cb_type(cb_type));
 
+  std::string prefix_str = convert_cb_type_to_string(cb_type);
   std::string x_str = std::to_string(get_cb_x(cb_type));
   std::string y_str = std::to_string(get_cb_y(cb_type));
 
+  char* ret = NULL;
+  ret = (char*) my_malloc ( sizeof(char) * (prefix_str.length() + 1 + x_str.length() + 2 + y_str.length() + 1 + 1));
+  sprintf(ret, "%s_%s__%s_", 
+          prefix_str.c_str(), x_str.c_str(), y_str.c_str());
+
+  return ret;
+  /* FIXME Have no clue why the following c++ code is not working
   std::string ret;
   ret.append(convert_cb_type_to_string(cb_type));
   ret.append("_");
@@ -1438,6 +1446,7 @@ const char* RRGSB::gen_cb_verilog_module_name(t_rr_type cb_type) const {
   ret.append("_");
 
   return ret.c_str();
+  */
 }
 
 const char* RRGSB::gen_cb_verilog_instance_name(t_rr_type cb_type) const {

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c

@@ -2986,7 +2986,6 @@ void dump_verilog_submodule_one_mem(FILE* fp,
     return;
   }
 
-
   /* Currently, Only support one mem_model for each SPICE MODEL  */
   for (iport = 0; iport < num_sram_port; iport++) {
     if (NULL == mem_model) {

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c

@@ -3031,14 +3031,6 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
       fprintf(fp, "%s_size%d_%d_", 
               cur_verilog_model->name, mux_size, cur_verilog_model->cnt);
     }
-    dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, 
-                                      lsb, msb,
-                                      0, VERILOG_PORT_CONKT);
-    fprintf(fp, ",");
-    if (SPICE_MODEL_MUX == cur_verilog_model->type) {
-      fprintf(fp, "%s_size%d_%d_", 
-              cur_verilog_model->name, mux_size, cur_verilog_model->cnt);
-    }
     dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, 
                                       lsb, msb,
                                       1, VERILOG_PORT_CONKT);