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Merge pull request #542 from lnis-uofu/bus_support 

More tests on Bus support: Validate its correctness on Input buses
This commit is contained in:
tangxifan 2022-02-20 11:37:48 -08:00 committed by GitHub
parent cfd4b6f2bf e33ba667e4
commit f430427669
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GPG Key ID: 4AEE18F83AFDEB23
12 changed files with 148 additions and 4 deletions
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26
openfpga_flow/tasks/basic_tests/bus_group/full_testbench_explicit_mapping/config/mac4_bus_group.xml Normal file
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@ -0,0 +1,26 @@
<bus_group>
<bus name="a[3:0]" big_endian="false">
<pin id="0" name="a_0_"/>
<pin id="1" name="a_1_"/>
<pin id="2" name="a_2_"/>
<pin id="3" name="a_3_"/>
</bus>
<bus name="b[3:0]" big_endian="false">
<pin id="0" name="b_0_"/>
<pin id="1" name="b_1_"/>
<pin id="2" name="b_2_"/>
<pin id="3" name="b_3_"/>
</bus>
<bus name="c[3:0]" big_endian="false">
<pin id="0" name="c_0_"/>
<pin id="1" name="c_1_"/>
<pin id="2" name="c_2_"/>
<pin id="3" name="c_3_"/>
</bus>
<bus name="out[3:0]" big_endian="false">
<pin id="0" name="out_0_"/>
<pin id="1" name="out_1_"/>
<pin id="2" name="out_2_"/>
<pin id="3" name="out_3_"/>
</bus>
</bus_group>

5
openfpga_flow/tasks/basic_tests/bus_group/full_testbench_explicit_mapping/config/pin_constraints_dummy.xml Normal file
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@ -0,0 +1,5 @@
<pin_constraints>
<!-- A dummy pin constraints file
-->
</pin_constraints>

7
openfpga_flow/tasks/basic_tests/bus_group/full_testbench_explicit_mapping/config/task.conf
View File

@ -20,13 +20,13 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_verilog_port_mapping=--explicit_port_mapping openfpga_verilog_port_mapping=--explicit_port_mapping
openfpga_bus_group_file=${PATH:TASK_DIR}/config/counter8_bus_group.xml
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
# Yosys script parameters # Yosys script parameters
@ -42,6 +42,11 @@ bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosy
bench0_top = counter bench0_top = counter
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_bus_group_file=${PATH:TASK_DIR}/config/counter8_bus_group.xml
bench1_top = mac_4
bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_dummy.xml
bench1_openfpga_bus_group_file=${PATH:TASK_DIR}/config/mac4_bus_group.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test= end_flow_with_test=

26
openfpga_flow/tasks/basic_tests/bus_group/full_testbench_implicit_mapping/config/mac4_bus_group.xml Normal file
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@ -0,0 +1,26 @@
<bus_group>
<bus name="a[3:0]" big_endian="false">
<pin id="0" name="a_0_"/>
<pin id="1" name="a_1_"/>
<pin id="2" name="a_2_"/>
<pin id="3" name="a_3_"/>
</bus>
<bus name="b[3:0]" big_endian="false">
<pin id="0" name="b_0_"/>
<pin id="1" name="b_1_"/>
<pin id="2" name="b_2_"/>
<pin id="3" name="b_3_"/>
</bus>
<bus name="c[3:0]" big_endian="false">
<pin id="0" name="c_0_"/>
<pin id="1" name="c_1_"/>
<pin id="2" name="c_2_"/>
<pin id="3" name="c_3_"/>
</bus>
<bus name="out[3:0]" big_endian="false">
<pin id="0" name="out_0_"/>
<pin id="1" name="out_1_"/>
<pin id="2" name="out_2_"/>
<pin id="3" name="out_3_"/>
</bus>
</bus_group>

5
openfpga_flow/tasks/basic_tests/bus_group/full_testbench_implicit_mapping/config/pin_constraints_dummy.xml Normal file
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@ -0,0 +1,5 @@
<pin_constraints>
<!-- A dummy pin constraints file
-->
</pin_constraints>

7
openfpga_flow/tasks/basic_tests/bus_group/full_testbench_implicit_mapping/config/task.conf
View File

@ -20,13 +20,13 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_verilog_port_mapping= openfpga_verilog_port_mapping=
openfpga_bus_group_file=${PATH:TASK_DIR}/config/counter8_bus_group.xml
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
# Yosys script parameters # Yosys script parameters
@ -42,6 +42,11 @@ bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosy
bench0_top = counter bench0_top = counter
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_bus_group_file=${PATH:TASK_DIR}/config/counter8_bus_group.xml
bench1_top = mac_4
bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_dummy.xml
bench1_openfpga_bus_group_file=${PATH:TASK_DIR}/config/mac4_bus_group.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test= end_flow_with_test=

26
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/mac4_bus_group.xml Normal file
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@ -0,0 +1,26 @@
<bus_group>
<bus name="a[3:0]" big_endian="false">
<pin id="0" name="a_0_"/>
<pin id="1" name="a_1_"/>
<pin id="2" name="a_2_"/>
<pin id="3" name="a_3_"/>
</bus>
<bus name="b[3:0]" big_endian="false">
<pin id="0" name="b_0_"/>
<pin id="1" name="b_1_"/>
<pin id="2" name="b_2_"/>
<pin id="3" name="b_3_"/>
</bus>
<bus name="c[3:0]" big_endian="false">
<pin id="0" name="c_0_"/>
<pin id="1" name="c_1_"/>
<pin id="2" name="c_2_"/>
<pin id="3" name="c_3_"/>
</bus>
<bus name="out[3:0]" big_endian="false">
<pin id="0" name="out_0_"/>
<pin id="1" name="out_1_"/>
<pin id="2" name="out_2_"/>
<pin id="3" name="out_3_"/>
</bus>
</bus_group>

5
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/pin_constraints_dummy.xml Normal file
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@ -0,0 +1,5 @@
<pin_constraints>
<!-- A dummy pin constraints file
-->
</pin_constraints>

7
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/task.conf
View File

@ -20,13 +20,13 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_verilog_port_mapping=--explicit_port_mapping openfpga_verilog_port_mapping=--explicit_port_mapping
openfpga_bus_group_file=${PATH:TASK_DIR}/config/counter8_bus_group.xml
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
# Yosys script parameters # Yosys script parameters
@ -42,6 +42,11 @@ bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosy
bench0_top = counter bench0_top = counter
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_bus_group_file=${PATH:TASK_DIR}/config/counter8_bus_group.xml
bench1_top = mac_4
bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_dummy.xml
bench1_openfpga_bus_group_file=${PATH:TASK_DIR}/config/mac4_bus_group.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test= end_flow_with_test=

26
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_implicit_mapping/config/mac4_bus_group.xml Normal file
View File

@ -0,0 +1,26 @@
<bus_group>
<bus name="a[3:0]" big_endian="false">
<pin id="0" name="a_0_"/>
<pin id="1" name="a_1_"/>
<pin id="2" name="a_2_"/>
<pin id="3" name="a_3_"/>
</bus>
<bus name="b[3:0]" big_endian="false">
<pin id="0" name="b_0_"/>
<pin id="1" name="b_1_"/>
<pin id="2" name="b_2_"/>
<pin id="3" name="b_3_"/>
</bus>
<bus name="c[3:0]" big_endian="false">
<pin id="0" name="c_0_"/>
<pin id="1" name="c_1_"/>
<pin id="2" name="c_2_"/>
<pin id="3" name="c_3_"/>
</bus>
<bus name="out[3:0]" big_endian="false">
<pin id="0" name="out_0_"/>
<pin id="1" name="out_1_"/>
<pin id="2" name="out_2_"/>
<pin id="3" name="out_3_"/>
</bus>
</bus_group>

5
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_implicit_mapping/config/pin_constraints_dummy.xml Normal file
View File

@ -0,0 +1,5 @@
<pin_constraints>
<!-- A dummy pin constraints file
-->
</pin_constraints>

7
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_implicit_mapping/config/task.conf
View File

@ -20,13 +20,13 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_verilog_port_mapping= openfpga_verilog_port_mapping=
openfpga_bus_group_file=${PATH:TASK_DIR}/config/counter8_bus_group.xml
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
# Yosys script parameters # Yosys script parameters
@ -42,6 +42,11 @@ bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosy
bench0_top = counter bench0_top = counter
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_bus_group_file=${PATH:TASK_DIR}/config/counter8_bus_group.xml
bench1_top = mac_4
bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_dummy.xml
bench1_openfpga_bus_group_file=${PATH:TASK_DIR}/config/mac4_bus_group.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test= end_flow_with_test=