diff --git a/.travis/regression.sh b/.travis/regression.sh
old mode 100644
new mode 100755
index 138e39f74..c5f79053c
--- a/.travis/regression.sh
+++ b/.travis/regression.sh
@@ -2,39 +2,39 @@
 # Regression test version 1.0
 
 # Set variables
-set benchmark = test_modes
-set include_netlists = _include_netlists.v
-set compiled_file = compiled_$benchmark
-set tb_formal_postfix = _top_formal_verification_random_tb
-set verilog_output_dirname = ${benchmark}_Verilog
-set log_file = ${benchmark}_sim.log
+benchmark="test_modes"
+include_netlists="_include_netlists.v"
+compiled_file="compiled_$benchmark"
+tb_formal_postfix="_top_formal_verification_random_tb"
+verilog_output_dirname="${benchmark}_Verilog"
+log_file="${benchmark}_sim.log"
 
 # Move to vpr folder
 cd vpr7_x2p/vpr
 
 # Remove former log file
-rm $log_file
-rm $compiled_file
+rm -f $log_file
+rm -f $compiled_file
 
 # Start the script -> run the fpga generation -> run the simulation -> check the log file
 source .regression_verilog.sh
 iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
 vvp $compiled_file -j 16 >> $log_file
 
-set result = `grep "Succeed" $log_file`
-if ("$result" != "")then
-  echo "Verification succeed"
-  cd -
-  exit 0
-else
-  set result = `grep "Failed" $log_file`
-  if ("$result" != "")then
-    echo "Verification failed"
+result=`grep "Succeed" $log_file`
+if ["$result" = ""]; then
+  result=`grep "Failed" $log_file`
+  if ["$result" = ""]; then
+    echo "Unexpected error, Verification didn't run"
     cd -
     exit 1
   else
-    echo "Unexpected error, Verification didn't run"
+    echo "Verification failed"
     cd -
     exit 2
   fi
+else
+  echo "Verification succeed"
+  cd -
+  exit 0
 fi
diff --git a/.travis/script.sh b/.travis/script.sh
index fe6b8ba6e..de0120751 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -23,3 +23,5 @@ fi
 end_section "OpenFPGA.build"
 
 $SPACER
+
+source .travis/regression.sh
diff --git a/vpr7_x2p/vpr/.regression_verilog.sh b/vpr7_x2p/vpr/.regression_verilog.sh
old mode 100644
new mode 100755
index 7b350d86b..04ff72ad4
--- a/vpr7_x2p/vpr/.regression_verilog.sh
+++ b/vpr7_x2p/vpr/.regression_verilog.sh
@@ -1,32 +1,32 @@
-#! /bin/csh -f
+#!/bin/bash
 # Example of how to run vpr
 
 # Set variables
 # For FPGA-Verilog ONLY 
-set benchmark = test_modes
-set verilog_output_dirname = ${benchmark}_Verilog
-set verilog_output_dirpath = $PWD
-set modelsim_ini_file = /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
+benchmark="test_modes"
+verilog_output_dirname="${benchmark}_Verilog"
+verilog_output_dirpath="$PWD"
+modelsim_ini_file="/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini"
 # VPR critical inputs
-#set arch_xml_file = ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml 
-#set arch_xml_file = ARCH/k8_N10_SC_tsmc40nm_chain_TT_stratixIV_lookalike.xml
-set arch_xml_file = ARCH/.regression_k6_N10_sram_chain_HC.xml
-#set arch_xml_file = ARCH/ed_stdcell.xml
-#set arch_xml_file = ARCH/k6_N10_sram_chain_FC_tsmc40.xml
-#set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml 
-#set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT_yosys.xml 
-#set arch_xml_file = ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml
-#set verilog_reference = ${PWD}/Circuits/alu4_K6_N10_ace.v
-#set blif_file = Circuits/shiftReg.blif 
-#set act_file = Circuits/shiftReg.act 
-set blif_file = Circuits/$benchmark.blif 
-set act_file = Circuits/$benchmark.act 
-set verilog_reference = ${PWD}/Circuits/$benchmark.v
-#set blif_file = Circuits/frisc.blif 
-#set act_file = Circuits/frisc.act 
-#set blif_file = Circuits/elliptic.blif 
-#set act_file = Circuits/elliptic.act 
-set vpr_route_chan_width = 200
+#set arch_xml_file=ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml 
+#set arch_xml_file=ARCH/k8_N10_SC_tsmc40nm_chain_TT_stratixIV_lookalike.xml
+arch_xml_file="ARCH/.regression_k6_N10_sram_chain_HC.xml"
+#set arch_xml_file=ARCH/ed_stdcell.xml
+#set arch_xml_file=ARCH/k6_N10_sram_chain_FC_tsmc40.xml
+#set arch_xml_file=ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml 
+#set arch_xml_file=ARCH/k6_N10_SC_tsmc40nm_chain_TT_yosys.xml 
+#set arch_xml_file=ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml
+#set verilog_reference=${PWD}/Circuits/alu4_K6_N10_ace.v
+#set blif_file=Circuits/shiftReg.blif 
+#set act_file=Circuits/shiftReg.act 
+blif_file="Circuits/$benchmark.blif" 
+act_file="Circuits/$benchmark.act "
+verilog_reference="${PWD}/Circuits/$benchmark.v"
+#set blif_file=Circuits/frisc.blif 
+#set act_file=Circuits/frisc.act 
+#set blif_file=Circuits/elliptic.blif 
+#set act_file=Circuits/elliptic.act 
+vpr_route_chan_width="200"
 
 # Step A: Make sure a clean start 
 # Recompile if needed