From 4fe190fa7e6a9447955de6e5c69e15ee20d7d1ab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 4 Dec 2020 14:44:27 -0700 Subject: [PATCH 1/2] [Doc] Bug fix in LUT circuit model documentation --- .../arch_lang/circuit_model_examples.rst | 6 +++--- .../arch_lang/figures/native_frac_lut.svg | 18 ++++++++--------- .../manual/arch_lang/figures/std_frac_lut.svg | 20 +++++++++---------- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index b9af6be37..d60a51bd1 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -825,7 +825,7 @@ The code describing this LUT is: - + This example shows: @@ -833,9 +833,9 @@ This example shows: - There is a SRAM cell to switch the operating mode of this LUT, configured by a configuration-chain flip-flop ``ccff`` - The last input ``in[2]`` of LUT will be tri-stated in dual-LUT2 mode. - An 2-input OR gate will be wired to the last input ``in[2]`` to tri-state the input. The mode-select SRAM will be wired to an input of the OR gate. - It means that when the mode-selection bit is '1', the LUT will operate in dual-LUT5 mode. + It means that when the mode-selection bit is '0', the LUT will operate in dual-LUT2 mode. - There will be two outputs wired to the 5th stage of routing multiplexer (the outputs of dual 5-input LUTs) - - By default, the mode-selection configuration bit will be '1', indicating that by default the LUT will operate in dual-LUT2 mode. + - By default, the mode-selection configuration bit will be '0', indicating that by default the LUT will operate in dual-LUT2 mode. :numref:`fig_std_frac_lut` illustrates the detailed schematic of a standard fracturable 6-input LUT, where the 5th and 6th inputs can be pull up/down to a fixed logic value to enable LUT4 and LUT5 outputs. diff --git a/docs/source/manual/arch_lang/figures/native_frac_lut.svg b/docs/source/manual/arch_lang/figures/native_frac_lut.svg index a95fb106e..532ab978b 100644 --- a/docs/source/manual/arch_lang/figures/native_frac_lut.svg +++ b/docs/source/manual/arch_lang/figures/native_frac_lut.svg @@ -1,6 +1,6 @@ - + @@ -28,8 +28,8 @@ - Produced by OmniGraffle 7.18\n2020-11-26 19:31:38 +0000 - + Produced by OmniGraffle 7.18\n2020-12-04 21:35:09 +0000 + native_frac_lut Schematic @@ -210,32 +210,32 @@ - in0 + in5 - in1 + in4 - in2 + in3 - in3 + in2 - in4 + in1 - in5 + in0 diff --git a/docs/source/manual/arch_lang/figures/std_frac_lut.svg b/docs/source/manual/arch_lang/figures/std_frac_lut.svg index 38a2b3e7d..406492968 100644 --- a/docs/source/manual/arch_lang/figures/std_frac_lut.svg +++ b/docs/source/manual/arch_lang/figures/std_frac_lut.svg @@ -1,6 +1,6 @@ - + @@ -33,8 +33,8 @@ - Produced by OmniGraffle 7.18\n2020-11-26 19:31:38 +0000 - + Produced by OmniGraffle 7.18\n2020-12-04 21:35:09 +0000 + std_frac_lut Schematic @@ -203,33 +203,33 @@ - - in0 + + in5 - in1 + in4 - in2 + in3 - in3 + in2 - in4 + in1 - in5 + in0 From 406edeec89e23d09a109ac94bd9526afd403513c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 4 Dec 2020 15:07:02 -0700 Subject: [PATCH 2/2] [Doc] Typo fix --- docs/source/manual/arch_lang/circuit_model_examples.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index d60a51bd1..48b7fdf2f 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -833,8 +833,8 @@ This example shows: - There is a SRAM cell to switch the operating mode of this LUT, configured by a configuration-chain flip-flop ``ccff`` - The last input ``in[2]`` of LUT will be tri-stated in dual-LUT2 mode. - An 2-input OR gate will be wired to the last input ``in[2]`` to tri-state the input. The mode-select SRAM will be wired to an input of the OR gate. - It means that when the mode-selection bit is '0', the LUT will operate in dual-LUT2 mode. - - There will be two outputs wired to the 5th stage of routing multiplexer (the outputs of dual 5-input LUTs) + It means that when the mode-selection bit is '0', the LUT will operate in dual-LUT3 mode. + - There will be two outputs wired to the 2th stage of routing multiplexer (the outputs of dual 2-input LUTs) - By default, the mode-selection configuration bit will be '0', indicating that by default the LUT will operate in dual-LUT2 mode. :numref:`fig_std_frac_lut` illustrates the detailed schematic of a standard fracturable 6-input LUT, where the 5th and 6th inputs can be pull up/down to a fixed logic value to enable LUT4 and LUT5 outputs.