From f2aa31ddb1bc3ee646f257bbc20ce68861ebd3e6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 15 Sep 2021 13:45:30 -0700 Subject: [PATCH] [FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank --- .../build_fabric_bitstream_memory_bank.cpp | 29 ++++++++++++------- openfpga/src/utils/memory_bank_utils.cpp | 14 ++++----- openfpga/src/utils/memory_bank_utils.h | 10 +++++++ openfpga/src/utils/module_manager_utils.cpp | 20 ++++--------- 4 files changed, 40 insertions(+), 33 deletions(-) diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp index 82d9a7f0d..3e7f2e9cc 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp @@ -47,11 +47,13 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B const ModuleId& top_module, const ModuleId& parent_module, const ConfigRegionId& config_region, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, const size_t& bl_addr_size, const size_t& wl_addr_size, - const std::map& num_bls_per_tile, + size_t& num_bls_cur_tile, const std::map& bl_start_index_per_tile, - const std::map& num_wls_per_tile, + size_t& num_wls_cur_tile, const std::map& wl_start_index_per_tile, vtr::Point& tile_coord, std::map, size_t>& cur_mem_index, @@ -84,6 +86,8 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B size_t child_instance = module_manager.region_configurable_child_instances(parent_module, config_region)[child_id]; tile_coord = module_manager.region_configurable_child_coordinates(parent_module, config_region)[child_id]; + num_bls_cur_tile = find_module_ql_memory_bank_num_blwls(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK, CIRCUIT_MODEL_PORT_BL); + num_wls_cur_tile = find_module_ql_memory_bank_num_blwls(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK, CIRCUIT_MODEL_PORT_WL); /* Get the instance name and ensure it is not empty */ std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); @@ -97,9 +101,10 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(bitstream_manager, child_block, module_manager, top_module, child_module, config_region, + circuit_lib, sram_model, bl_addr_size, wl_addr_size, - num_bls_per_tile, bl_start_index_per_tile, - num_wls_per_tile, wl_start_index_per_tile, + num_bls_cur_tile, bl_start_index_per_tile, + num_wls_cur_tile, wl_start_index_per_tile, tile_coord, cur_mem_index, fabric_bitstream, @@ -138,9 +143,10 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(bitstream_manager, child_block, module_manager, top_module, child_module, config_region, + circuit_lib, sram_model, bl_addr_size, wl_addr_size, - num_bls_per_tile, bl_start_index_per_tile, - num_wls_per_tile, wl_start_index_per_tile, + num_bls_cur_tile, bl_start_index_per_tile, + num_wls_cur_tile, wl_start_index_per_tile, tile_coord, cur_mem_index, fabric_bitstream, @@ -161,11 +167,11 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B FabricBitId fabric_bit = fabric_bitstream.add_bit(config_bit); /* Find BL address */ - size_t cur_bl_index = bl_start_index_per_tile.at(tile_coord.x()) + cur_mem_index[tile_coord] % num_bls_per_tile.at(tile_coord.x()); + size_t cur_bl_index = bl_start_index_per_tile.at(tile_coord.x()) + cur_mem_index[tile_coord] % num_bls_cur_tile; std::vector bl_addr_bits_vec = itobin_charvec(cur_bl_index, bl_addr_size); /* Find WL address */ - size_t cur_wl_index = wl_start_index_per_tile.at(tile_coord.y()) + std::floor(cur_mem_index[tile_coord] / num_bls_per_tile.at(tile_coord.x())); + size_t cur_wl_index = wl_start_index_per_tile.at(tile_coord.y()) + std::floor(cur_mem_index[tile_coord] / num_bls_cur_tile); std::vector wl_addr_bits_vec = itobin_charvec(cur_wl_index, wl_addr_size); /* Set BL address */ @@ -250,14 +256,17 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol vtr::Point temp_coord; std::map, size_t> cur_mem_index; + size_t temp_num_bls_cur_tile = 0; + size_t temp_num_wls_cur_tile = 0; rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(bitstream_manager, top_block, module_manager, top_module, top_module, config_region, + circuit_lib, config_protocol.memory_model(), bl_addr_port_info.get_width(), wl_addr_port_info.get_width(), - num_bls_per_tile, bl_start_index_per_tile, - num_wls_per_tile, wl_start_index_per_tile, + temp_num_bls_cur_tile, bl_start_index_per_tile, + temp_num_wls_cur_tile, wl_start_index_per_tile, temp_coord, cur_mem_index, fabric_bitstream, diff --git a/openfpga/src/utils/memory_bank_utils.cpp b/openfpga/src/utils/memory_bank_utils.cpp index 14b3a6cf7..a441813ad 100644 --- a/openfpga/src/utils/memory_bank_utils.cpp +++ b/openfpga/src/utils/memory_bank_utils.cpp @@ -56,16 +56,12 @@ std::pair compute_memory_bank_regional_configurable_child_y_range(cons return child_y_range; } -/******************************************************************** - * Find the size of BL ports for module - *******************************************************************/ -static size_t find_module_ql_memory_bank_num_blwls(const ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_config_protocol_type& sram_orgz_type, - const e_circuit_model_port_type& circuit_port_type) { + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& sram_orgz_type, + const e_circuit_model_port_type& circuit_port_type) { std::vector config_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type); size_t num_blwls = 0; /* By default it has zero configuration bits*/ diff --git a/openfpga/src/utils/memory_bank_utils.h b/openfpga/src/utils/memory_bank_utils.h index 65d2ea49f..237098927 100644 --- a/openfpga/src/utils/memory_bank_utils.h +++ b/openfpga/src/utils/memory_bank_utils.h @@ -39,6 +39,16 @@ std::pair compute_memory_bank_regional_configurable_child_y_range(cons const ModuleId& top_module, const ConfigRegionId& config_region); +/** + * @brief Find the size of BL or WL ports for a given module + */ +size_t find_module_ql_memory_bank_num_blwls(const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& sram_orgz_type, + const e_circuit_model_port_type& circuit_port_type); + /** * @brief Precompute the number of bit lines required by each tile under a specific configuration region * @note diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index ce9edca12..12e2d0636 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -985,15 +985,11 @@ void add_module_nets_cmos_memory_bank_bl_config_bus(ModuleManager& module_manage BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) { - ModuleId net_sink_module_id; - size_t net_sink_instance_id; - ModulePortId net_sink_port_id; - /* Find the port name of next memory module */ std::string sink_port_name = generate_sram_port_name(sram_orgz_type, config_port_type); - net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; - net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; - net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + ModuleId net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; + size_t net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; + ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); /* Get the pin id for sink port */ BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); @@ -1064,15 +1060,11 @@ void add_module_nets_cmos_memory_bank_wl_config_bus(ModuleManager& module_manage BasicPort net_bl_port = module_manager.module_port(net_src_module_id, net_bl_port_id); for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) { - ModuleId net_sink_module_id; - size_t net_sink_instance_id; - ModulePortId net_sink_port_id; - /* Find the port name of next memory module */ std::string sink_port_name = generate_sram_port_name(sram_orgz_type, config_port_type); - net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; - net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; - net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + ModuleId net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; + size_t net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; + ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); /* Get the pin id for sink port */ BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id);