riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs

This commit is contained in:
tangxifan 2020-09-20 12:03:10 -06:00
parent 6801d260e9
commit f284f6f8d0
8 changed files with 19 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
libopenfpga/libarchopenfpga/src/circuit_library.cpp
View File

@ -79,11 +79,11 @@ std::string CircuitLibrary::model_verilog_netlist(const CircuitModelId& model_id
return model_verilog_netlists_[model_id]; return model_verilog_netlists_[model_id];
} }
/* Access the path + file of user-defined circuit netlist of a circuit model */ /* Access the path + file of user-defined spice netlist of a circuit model */
std::string CircuitLibrary::model_circuit_netlist(const CircuitModelId& model_id) const { std::string CircuitLibrary::model_spice_netlist(const CircuitModelId& model_id) const {
/* validate the model_id */ /* validate the model_id */
VTR_ASSERT(valid_model_id(model_id)); VTR_ASSERT(valid_model_id(model_id));
return model_circuit_netlists_[model_id]; return model_spice_netlists_[model_id];
} }
/* Access the is_default flag (check if this is the default circuit model in the type) of a circuit model */ /* Access the is_default flag (check if this is the default circuit model in the type) of a circuit model */
@ -1132,7 +1132,7 @@ CircuitModelId CircuitLibrary::add_model(const enum e_circuit_model_type& type)
model_names_.emplace_back(); model_names_.emplace_back();
model_prefix_.emplace_back(); model_prefix_.emplace_back();
model_verilog_netlists_.emplace_back(); model_verilog_netlists_.emplace_back();
model_circuit_netlists_.emplace_back(); model_spice_netlists_.emplace_back();
model_is_default_.push_back(false); model_is_default_.push_back(false);
sub_models_.emplace_back(); sub_models_.emplace_back();
@ -1226,11 +1226,11 @@ void CircuitLibrary::set_model_verilog_netlist(const CircuitModelId& model_id, c
return; return;
} }
/* Set the circuit_netlist of a Circuit Model */ /* Set the spice_netlist of a Circuit Model */
void CircuitLibrary::set_model_circuit_netlist(const CircuitModelId& model_id, const std::string& circuit_netlist) { void CircuitLibrary::set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist) {
/* validate the model_id */ /* validate the model_id */
VTR_ASSERT(valid_model_id(model_id)); VTR_ASSERT(valid_model_id(model_id));
model_circuit_netlists_[model_id] = circuit_netlist; model_spice_netlists_[model_id] = spice_netlist;
return; return;
} }

8
libopenfpga/libarchopenfpga/src/circuit_library.h
View File

@ -48,7 +48,7 @@
* It should be the same as user-defined Verilog modules, if it is not auto-generated * It should be the same as user-defined Verilog modules, if it is not auto-generated
* 4. model_prefix_: the prefix of a circuit model when it is instanciated * 4. model_prefix_: the prefix of a circuit model when it is instanciated
* 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated
* 6. circuit_netlist_: specified path and file name of CIRCUIT netlist if a circuit model is not auto-generated * 6. spice_netlist_: specified path and file name of CIRCUIT netlist if a circuit model is not auto-generated
* 7. is_default_: indicate if the circuit model is the default one among all those in the same type * 7. is_default_: indicate if the circuit model is the default one among all those in the same type
* 8. sub_models_: the sub circuit models included by a circuit model. It is a collection of unique circuit model ids * 8. sub_models_: the sub circuit models included by a circuit model. It is a collection of unique circuit model ids
* found in the CircuitModelId of pass-gate/buffers/port-related circuit models. * found in the CircuitModelId of pass-gate/buffers/port-related circuit models.
@ -190,7 +190,7 @@ class CircuitLibrary {
std::string model_name(const CircuitModelId& model_id) const; std::string model_name(const CircuitModelId& model_id) const;
std::string model_prefix(const CircuitModelId& model_id) const; std::string model_prefix(const CircuitModelId& model_id) const;
std::string model_verilog_netlist(const CircuitModelId& model_id) const; std::string model_verilog_netlist(const CircuitModelId& model_id) const;
std::string model_circuit_netlist(const CircuitModelId& model_id) const; std::string model_spice_netlist(const CircuitModelId& model_id) const;
bool model_is_default(const CircuitModelId& model_id) const; bool model_is_default(const CircuitModelId& model_id) const;
bool dump_structural_verilog(const CircuitModelId& model_id) const; bool dump_structural_verilog(const CircuitModelId& model_id) const;
bool dump_explicit_port_map(const CircuitModelId& model_id) const; bool dump_explicit_port_map(const CircuitModelId& model_id) const;
@ -314,7 +314,7 @@ class CircuitLibrary {
void set_model_name(const CircuitModelId& model_id, const std::string& name); void set_model_name(const CircuitModelId& model_id, const std::string& name);
void set_model_prefix(const CircuitModelId& model_id, const std::string& prefix); void set_model_prefix(const CircuitModelId& model_id, const std::string& prefix);
void set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist); void set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist);
void set_model_circuit_netlist(const CircuitModelId& model_id, const std::string& circuit_netlist); void set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist);
void set_model_is_default(const CircuitModelId& model_id, const bool& is_default); void set_model_is_default(const CircuitModelId& model_id, const bool& is_default);
/* Verilog generator options */ /* Verilog generator options */
void set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog); void set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog);
@ -499,7 +499,7 @@ class CircuitLibrary {
vtr::vector<CircuitModelId, std::string> model_names_; vtr::vector<CircuitModelId, std::string> model_names_;
vtr::vector<CircuitModelId, std::string> model_prefix_; vtr::vector<CircuitModelId, std::string> model_prefix_;
vtr::vector<CircuitModelId, std::string> model_verilog_netlists_; vtr::vector<CircuitModelId, std::string> model_verilog_netlists_;
vtr::vector<CircuitModelId, std::string> model_circuit_netlists_; vtr::vector<CircuitModelId, std::string> model_spice_netlists_;
vtr::vector<CircuitModelId, bool> model_is_default_; vtr::vector<CircuitModelId, bool> model_is_default_;
/* Submodules that a circuit model contains */ /* Submodules that a circuit model contains */

2
libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
View File

@ -674,7 +674,7 @@ void read_xml_circuit_model(pugi::xml_node& xml_model,
circuit_lib.set_model_prefix(model, std::string(prefix_attr)); circuit_lib.set_model_prefix(model, std::string(prefix_attr));
/* Find a SPICE netlist which is an optional attribute*/ /* Find a SPICE netlist which is an optional attribute*/
circuit_lib.set_model_circuit_netlist(model, get_attribute(xml_model, "spice_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string("")); circuit_lib.set_model_spice_netlist(model, get_attribute(xml_model, "spice_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(""));
/* Find a Verilog netlist which is an optional attribute*/ /* Find a Verilog netlist which is an optional attribute*/
circuit_lib.set_model_verilog_netlist(model, get_attribute(xml_model, "verilog_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string("")); circuit_lib.set_model_verilog_netlist(model, get_attribute(xml_model, "verilog_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(""));

4
libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
View File

@ -409,8 +409,8 @@ void write_xml_circuit_model(std::fstream& fp,
if (true == circuit_lib.dump_structural_verilog(model)) { if (true == circuit_lib.dump_structural_verilog(model)) {
write_xml_attribute(fp, "dump_structural_verilog", "true"); write_xml_attribute(fp, "dump_structural_verilog", "true");
} }
if (!circuit_lib.model_circuit_netlist(model).empty()) { if (!circuit_lib.model_spice_netlist(model).empty()) {
write_xml_attribute(fp, "circuit_netlist", circuit_lib.model_circuit_netlist(model).c_str()); write_xml_attribute(fp, "spice_netlist", circuit_lib.model_spice_netlist(model).c_str());
} }
if (!circuit_lib.model_verilog_netlist(model).empty()) { if (!circuit_lib.model_verilog_netlist(model).empty()) {
write_xml_attribute(fp, "verilog_netlist", circuit_lib.model_verilog_netlist(model).c_str()); write_xml_attribute(fp, "verilog_netlist", circuit_lib.model_verilog_netlist(model).c_str());

4
openfpga/src/fabric/build_essential_modules.cpp
View File

@ -187,7 +187,7 @@ void build_user_defined_modules(ModuleManager& module_manager,
for (const auto& model : circuit_lib.models()) { for (const auto& model : circuit_lib.models()) {
/* We only care about user-defined models */ /* We only care about user-defined models */
if ( (true == circuit_lib.model_verilog_netlist(model).empty()) if ( (true == circuit_lib.model_verilog_netlist(model).empty())
&& (true == circuit_lib.model_circuit_netlist(model).empty()) ) { && (true == circuit_lib.model_spice_netlist(model).empty()) ) {
continue; continue;
} }
/* Skip Routing channel wire models because they need a different name. Do it later */ /* Skip Routing channel wire models because they need a different name. Do it later */
@ -255,7 +255,7 @@ void rename_primitive_module_port_names(ModuleManager& module_manager,
for (const CircuitModelId& model : circuit_lib.models()) { for (const CircuitModelId& model : circuit_lib.models()) {
/* We only care about user-defined models */ /* We only care about user-defined models */
if ( (true == circuit_lib.model_verilog_netlist(model).empty()) if ( (true == circuit_lib.model_verilog_netlist(model).empty())
&& (true == circuit_lib.model_circuit_netlist(model).empty()) ) { && (true == circuit_lib.model_spice_netlist(model).empty()) ) {
continue; continue;
} }
/* Skip Routing channel wire models because they need a different name. Do it later */ /* Skip Routing channel wire models because they need a different name. Do it later */

2
openfpga/src/fabric/build_wire_modules.cpp
View File

@ -62,7 +62,7 @@ void build_wire_modules(ModuleManager& module_manager,
/* Print Verilog models for regular wires*/ /* Print Verilog models for regular wires*/
for (const auto& wire_model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) { for (const auto& wire_model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) {
/* Bypass user-defined circuit models */ /* Bypass user-defined circuit models */
if ( (!circuit_lib.model_circuit_netlist(wire_model).empty()) if ( (!circuit_lib.model_spice_netlist(wire_model).empty())
&& (!circuit_lib.model_verilog_netlist(wire_model).empty()) ) { && (!circuit_lib.model_verilog_netlist(wire_model).empty()) ) {
continue; continue;
} }

2
openfpga/src/fpga_spice/spice_essential_gates.cpp
View File

@ -136,7 +136,7 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
/* Iterate over the circuit models */ /* Iterate over the circuit models */
for (const CircuitModelId& circuit_model : circuit_lib.models()) { for (const CircuitModelId& circuit_model : circuit_lib.models()) {
/* Bypass models require extern netlists */ /* Bypass models require extern netlists */
if (!circuit_lib.model_circuit_netlist(circuit_model).empty()) { if (!circuit_lib.model_spice_netlist(circuit_model).empty()) {
continue; continue;
} }

2
openfpga/src/fpga_spice/spice_lut.cpp
View File

@ -56,7 +56,7 @@ int print_spice_submodule_luts(NetlistManager& netlist_manager,
/* Search for each LUT circuit model */ /* Search for each LUT circuit model */
for (const auto& lut_model : circuit_lib.models()) { for (const auto& lut_model : circuit_lib.models()) {
/* Bypass user-defined and non-LUT modules */ /* Bypass user-defined and non-LUT modules */
if ( (!circuit_lib.model_circuit_netlist(lut_model).empty()) if ( (!circuit_lib.model_spice_netlist(lut_model).empty())
|| (CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model)) ) { || (CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model)) ) {
continue; continue;
} }