[code] format

2023-01-31 12:52:59 -08:00 · 2023-01-31 12:52:59 -08:00 · f25dc461dc
parent f00acf1e62
commit f25dc461dc
1 changed files with 2 additions and 2 deletions
--- a/openfpga/src/utils/lut_utils.cpp
+++ b/openfpga/src/utils/lut_utils.cpp
@ -451,8 +451,8 @@ std::vector<bool> build_frac_lut_bitstream(
  std::vector<bool> lut_bitstream(lut_mux_graph.num_inputs(),
                                  default_sram_bit_value);

-  for (std::pair<const t_pb_graph_pin*, AtomNetlist::TruthTable>
-         element : truth_tables) {
+  for (std::pair<const t_pb_graph_pin*, AtomNetlist::TruthTable> element :
+       truth_tables) {
    /* Find the corresponding circuit model output port and assoicated
     * lut_output_mask */
    CircuitPortId lut_model_output_port =