From f23c25e1234b99ea88bf95a2b520a78bf207d77d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:25:17 -0600 Subject: [PATCH] [Regression Test] Add test case for configurable latch with active-low reset --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf new file mode 100644 index 000000000..755b9ec94 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test=