From f21d22f691fd01091a5b157ea0992b1903c9929c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 10 Jan 2021 10:54:59 -0700 Subject: [PATCH] [Doc] Update README for new architectures --- openfpga_flow/openfpga_arch/README.md | 1 + openfpga_flow/vpr_arch/README.md | 1 + 2 files changed, 2 insertions(+) diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index ba6e307ca..5d1e8cafa 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -21,6 +21,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f - behavioral: If behavioral Verilog modeling is specified - local\_encoder: If local encoders are used in routing multiplexer design - spyio/spypad: If spy I/Os are used +- registerable\_io: If I/Os are registerable (can be either combinational or sequential) - stdcell: If circuit designs are built with standard cells only - tree\_mux: If routing multiplexers are built with a tree-like structure - : The technology node which the delay numbers are extracted from. diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 4ab3a92e4..87723c7e3 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -15,6 +15,7 @@ Please reveal the following architecture features in the names to help quickly s - aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os. - multi\_io\_capacity: If I/O capacity is different on each side of FPGAs. - reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs +- registerable\_io: If I/Os are registerable (can be either combinational or sequential) - : The technology node which the delay numbers are extracted from. - TileOrgz: How tile is organized. * Top-left (Tl): the pins of a tile are placed on the top side and left side only