From 0da44ad1fc1303fd282f3c89cb20a645ae2f38b3 Mon Sep 17 00:00:00 2001 From: root Date: Tue, 2 Aug 2022 08:02:28 +0800 Subject: [PATCH 1/6] [script] now .act file is no longer required in openfpga_flow/task when power analysis option is off --- openfpga_flow/scripts/run_fpga_flow.py | 15 +++++++++------ openfpga_flow/scripts/run_fpga_task.py | 14 +++++++++----- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 0c36338a6..064defa19 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -411,8 +411,9 @@ def validate_command_line_arguments(): # Expand run directory to absolute path args.run_dir = os.path.abspath(args.run_dir) - if args.activity_file: - args.activity_file = os.path.abspath(args.activity_file) + if args.power: + if args.activity_file: + args.activity_file = os.path.abspath(args.activity_file) if args.base_verilog: args.base_verilog = os.path.abspath(args.base_verilog) @@ -717,10 +718,11 @@ def collect_files_for_vpr(): shutil.copy(args.benchmark_files[0], args.top_module+".blif") # Sanitize provided Activity file option - if not os.path.isfile(args.activity_file or ""): - logger.error("Activity File - %s" % args.activity_file) - clean_up_and_exit("Provided activity file not found") - shutil.copy(args.activity_file, args.top_module+"_ace_out.act") + if args.power: + if not os.path.isfile(args.activity_file or ""): + logger.error("Activity File - %s" % args.activity_file) + clean_up_and_exit("Provided activity file not found") + shutil.copy(args.activity_file, args.top_module+"_ace_out.act") # Sanitize provided Benchmark option if not os.path.isfile(args.base_verilog or ""): @@ -736,6 +738,7 @@ def run_openfpga_shell(): encoding='utf-8').read()) path_variables = script_env_vars["PATH"] + path_variables["TOP_MODULE"] = args.top_module path_variables["VPR_ARCH_FILE"] = args.arch_file path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif" diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 6b6e43294..2c73e98e8 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -317,11 +317,15 @@ def generate_each_task_actions(taskname): CurrBenchPara["benchVariable"] += [f"--{param}", value] if GeneralSection.get("fpga_flow") == "vpr_blif": - # Check if activity file exist - if not SynthSection.get(bech_name+"_act"): - clean_up_and_exit("Missing argument %s" % (bech_name+"_act") + - "for vpr_blif flow") - CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act") + # Check if activity file exist only when power analysis is required + if (GeneralSection.getboolean("power_analysis")): + if not SynthSection.get(bech_name+"_act"): + clean_up_and_exit("Missing argument %s" % (bech_name+"_act") + + "for vpr_blif flow") + CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act") + else: + # Send a dummy act + CurrBenchPara["activity_file"] = bech_name+"_act" # Check if base verilog file exists if not SynthSection.get(bech_name+"_verilog"): From 55c7b75ab6e1591b836d1456700298592e46bb25 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Aug 2022 18:13:57 -0700 Subject: [PATCH 2/6] [script] even when power analysis mode is turned off, if users define a act file, still use it --- openfpga_flow/scripts/run_fpga_flow.py | 4 +++- openfpga_flow/scripts/run_fpga_task.py | 7 +++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 064defa19..3cbd29f90 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -722,7 +722,9 @@ def collect_files_for_vpr(): if not os.path.isfile(args.activity_file or ""): logger.error("Activity File - %s" % args.activity_file) clean_up_and_exit("Provided activity file not found") - shutil.copy(args.activity_file, args.top_module+"_ace_out.act") + else: + if os.path.isfile(args.activity_file): + shutil.copy(args.activity_file, args.top_module+"_ace_out.act") # Sanitize provided Benchmark option if not os.path.isfile(args.base_verilog or ""): diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 2c73e98e8..dd21d6881 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -324,8 +324,11 @@ def generate_each_task_actions(taskname): "for vpr_blif flow") CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act") else: - # Send a dummy act - CurrBenchPara["activity_file"] = bech_name+"_act" + # If users defined an acitivity file, we use it otherwise create a dummy act + if not SynthSection.get(bech_name+"_act"): + CurrBenchPara["activity_file"] = bech_name+"_act" + else: + CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act") # Check if base verilog file exists if not SynthSection.get(bech_name+"_verilog"): From 8b17bf1b1cfc2e9bba20e83afb931c69bde27c2d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Aug 2022 18:44:47 -0700 Subject: [PATCH 3/6] [test] add a new test case to validate that .act file is not required when power analysis flow is off --- .../config/pin_constraints.xml | 4 +++ .../config/task.conf | 36 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace/config/pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace/config/pin_constraints.xml new file mode 100644 index 000000000..005dcb5f7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace/config/pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace/config/task.conf new file mode 100644 index 000000000..9567d9dce --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 9ea4a7c90f950d59206a29e2759c66cea7388e24 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Aug 2022 19:18:41 -0700 Subject: [PATCH 4/6] [script] fixed a bug --- openfpga_flow/scripts/run_fpga_flow.py | 1 + openfpga_flow/scripts/run_fpga_task.py | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 3cbd29f90..fb897cd31 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -722,6 +722,7 @@ def collect_files_for_vpr(): if not os.path.isfile(args.activity_file or ""): logger.error("Activity File - %s" % args.activity_file) clean_up_and_exit("Provided activity file not found") + shutil.copy(args.activity_file, args.top_module+"_ace_out.act") else: if os.path.isfile(args.activity_file): shutil.copy(args.activity_file, args.top_module+"_ace_out.act") diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index dd21d6881..7cf4aa83d 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -324,7 +324,7 @@ def generate_each_task_actions(taskname): "for vpr_blif flow") CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act") else: - # If users defined an acitivity file, we use it otherwise create a dummy act + # If users defined an activity file, we use it otherwise create a dummy act if not SynthSection.get(bech_name+"_act"): CurrBenchPara["activity_file"] = bech_name+"_act" else: From 6ce1d4804c13577afce6c3ce432afd295656ae20 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Aug 2022 21:05:05 -0700 Subject: [PATCH 5/6] [test] deploy new test case to basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 9806f5001..34f707eaf 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -88,6 +88,7 @@ run-task basic_tests/custom_fabric_netlist_location $@ echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq $@ +run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace $@ # TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank #run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq $@ From 77abb86dabe8db7a79f44dc7c174e62fe08fd33e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Aug 2022 21:37:22 -0700 Subject: [PATCH 6/6] [doc] update documentation about the activity file options --- docs/source/manual/openfpga_flow/run_fpga_task.rst | 2 ++ yosys-plugins | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/openfpga_flow/run_fpga_task.rst b/docs/source/manual/openfpga_flow/run_fpga_task.rst index ceba5fd56..366e9bd23 100644 --- a/docs/source/manual/openfpga_flow/run_fpga_task.rst +++ b/docs/source/manual/openfpga_flow/run_fpga_task.rst @@ -206,6 +206,8 @@ Synthesis Parameter Sections In case of running ``blif_vpr_flow`` this option provides the activity files to be used to generate testbench for ``bench_label`` benchmark +.. note:: This file is required only when the ``power_analysis`` option in the general section is enabled. Otherwise, it is optional + .. option:: bench_verilog= In case of running ``blif_vpr_flow`` with verification this option provides diff --git a/yosys-plugins b/yosys-plugins index 3b3dcc5cc..52cdcc42d 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit 3b3dcc5cc216f7a39d26a6d894c53b8aa3e10d71 +Subproject commit 52cdcc42db527087fb342b4dabdb1a79878266cb