[test] add new testcases for validate clock tree disable functions
This commit is contained in:
tangxifan
parent
ad5795bece
commit
f1a4304ee7
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<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
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<clock_network name="clk_tree_2lvl" width="1">
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<spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="clk_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="rst[0:0]" to_pin="clb[0:0].clk[0:0]"/>
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</taps>
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</clock_network>
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<clock_network name="rst_tree_2lvl" width="1">
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<spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/>
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<switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/>
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<switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="rst_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="rst[0:0]" to_pin="clb[0:0].reset[0:0]"/>
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</taps>
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</clock_network>
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</clock_networks>
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<pin_constraints>
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<!-- For a given .blif file, we want to assign
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- the reset signal to the op_reset[0] port of the FPGA fabric
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-->
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<set_io pin="op_reset[0]" net="reset"/>
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</pin_constraints>
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<pin_constraints>
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<!-- For a given .blif file, we want to assign
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- the reset signal to the op_reset[0] port of the FPGA fabric
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-->
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<set_io pin="op_reset[0]" net="resetb" default_value="1"/>
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</pin_constraints>
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<repack_design_constraints>
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<!-- Intended to be dummy -->
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</repack_design_constraints>
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = false
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spice_output=false
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verilog_output=true
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timeout_each_job = 3*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
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openfpga_vpr_device_layout=2x2
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openfpga_vpr_route_chan_width=40
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openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
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openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
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openfpga_route_clock_options=--disable_unused_spines
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
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[SYNTHESIS_PARAM]
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# Yosys script parameters
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bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
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bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
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bench_read_verilog_options_common = -nolatches
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bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
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bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
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bench0_top = counter
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bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml
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bench0_openfpga_verilog_testbench_port_mapping=
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bench1_top = counter
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bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml
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bench1_openfpga_verilog_testbench_port_mapping=
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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vpr_fpga_verilog_formal_verification_top_netlist=
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<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
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<clock_network name="clk_tree_2lvl" width="2">
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<spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/>
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<switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/>
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<switch_point tap="rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
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<all from_pin="clk[1:1]" to_pin="clb[0:0].clk[1:1]"/>
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</taps>
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</clock_network>
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</clock_networks>
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<pin_constraints>
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<set_io pin="clk[0]" net="clk"/>
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<set_io pin="clk[1]" net="OPEN"/>
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</pin_constraints>
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<repack_design_constraints>
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<pin_constraint pb_type="clb" pin="clk[0:0]" net="clk"/>
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<pin_constraint pb_type="clb" pin="clk[1:1]" net="OPEN"/>
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</repack_design_constraints>
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml
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openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_2clk_2layer.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=2x2
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openfpga_vpr_route_chan_width=24
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openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml
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openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml
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openfpga_route_clock_options=--disable_unused_trees --disable_unused_spines
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
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[SYNTHESIS_PARAM]
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bench_read_verilog_options_common = -nolatches
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bench0_top = and2_latch
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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vpr_fpga_verilog_formal_verification_top_netlist=
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<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
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<clock_network name="clk_tree_2lvl" width="2">
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<spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/>
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<switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/>
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<switch_point tap="rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
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<all from_pin="clk[1:1]" to_pin="clb[0:0].clk[1:1]"/>
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</taps>
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</clock_network>
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</clock_networks>
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<pin_constraints>
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<set_io pin="clk[0]" net="clk"/>
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<set_io pin="clk[1]" net="OPEN"/>
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</pin_constraints>
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<repack_design_constraints>
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<pin_constraint pb_type="clb" pin="clk[0:0]" net="clk"/>
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<pin_constraint pb_type="clb" pin="clk[1:1]" net="OPEN"/>
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</repack_design_constraints>
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml
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openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_2clk_2layer.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=2x2
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openfpga_vpr_route_chan_width=24
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openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml
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openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml
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openfpga_route_clock_options=--disable_unused_trees
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
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[SYNTHESIS_PARAM]
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bench_read_verilog_options_common = -nolatches
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bench0_top = and2_latch
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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vpr_fpga_verilog_formal_verification_top_netlist=
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