Merge pull request #659 from lnis-uofu/hotfix_reg
Hotfix on regression test scripts and documentation
This commit is contained in:
ganeshgore
GitHub
commit
f14e025ab7
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@ -264,7 +264,7 @@ jobs:
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chmod +x yosys/install/bin/yosys-smtbmc
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- name: ${{matrix.config.name}}_GCC-8_(Ubuntu 18.04)
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shell: bash
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run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh
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run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs
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- name: Upload artifact
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uses: actions/upload-artifact@v2
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if: ${{ failure() }}
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@ -310,7 +310,7 @@ jobs:
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${PYTHON_EXEC} -m pip install -r requirements.txt
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rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. .
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unset OPENFPGA_PATH
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source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh
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source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs
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- name: Upload artifact
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uses: actions/upload-artifact@v2
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if: ${{ failure() }}
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@ -22,6 +22,7 @@ RUN adduser --disabled-password \
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USER root
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RUN chown -R ${NB_UID} ${HOME}
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RUN chmod -R +r /opt/openfpga/
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git config --global --add safe.directory *
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USER ${NB_USER}
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WORKDIR ${HOME}
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@ -5,3 +5,5 @@
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ci_cd_setup/index
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version_number
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regression_tests
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@ -0,0 +1,48 @@
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.. dev_manual_regression_tests::
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Regression Tests
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================
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Regression tests are designed to cover various technical features of the OpenFPGA projects, including but not limited to
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- Netlist generation
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- Netlist verification
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- Bitstream generation
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Considering the large number of technical features, regression tests are categorized into several groups, which can be found at ``openfpga_flow/regression_test_scripts/``
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Run a Test
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----------
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.. note:: Make sure you have compiled OpenFPGA and set up your environment before reaching this step. See details in :ref:`getting_started_tutorials`.
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To run a regression test, users can execute a shell script (assume you are under the root directory of the project), for example,
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.. code-block:: shell
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./openfpga_flow/regression_test_scripts/basic_reg_test.sh [OPTIONS]
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.. note:: ``basic_reg_test`` can be replaced by other tests which are under ``openfpga_flow/regression_test_scripts/``
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Test Options
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------------
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There are a few options available when running the tests.
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.. option:: --debug
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This option can turn on debug mode when running regression tests. By default it is ``off``.
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.. option:: --show_thread_logs
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This option can enable verbose output when running regression tests. By default it is ``off``.
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.. note:: To avoid massive outputs, suggest to run the tests with default options. In CI, always recommend to turn on the debug and verbose options
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.. option:: --remove_run_dir all
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This option is to remove all the previous run results for a specific regression test. Suggest to use when there are limited disk space.
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.. note:: Be careful before using this option! It may cause permanent loss on test results.
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@ -65,6 +65,10 @@ clean-run () {
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rm -rf ./openfpga_flow/**/run???
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}
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clear-task-run () {
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$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all
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}
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run-modelsim () {
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$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_modelsim.py "$@"
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}
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@ -9,182 +9,191 @@ PYTHON_EXEC=python3.8
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echo -e "Basic regression tests";
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echo -e "Testing configuration chain of a K4N4 FPGA";
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run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs
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run-task basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain $@
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run-task basic_tests/full_testbench/configuration_chain_no_time_stamp $@
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run-task basic_tests/full_testbench/configuration_chain_use_reset $@
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run-task basic_tests/full_testbench/configuration_chain_use_resetb $@
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run-task basic_tests/full_testbench/configuration_chain_use_set $@
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run-task basic_tests/full_testbench/configuration_chain_use_setb $@
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run-task basic_tests/full_testbench/configuration_chain_use_set_reset $@
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run-task basic_tests/full_testbench/configuration_chain_config_enable_scff $@
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run-task basic_tests/full_testbench/multi_region_configuration_chain $@
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run-task basic_tests/full_testbench/fast_configuration_chain $@
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run-task basic_tests/full_testbench/fast_configuration_chain_use_set $@
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run-task basic_tests/full_testbench/smart_fast_configuration_chain $@
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run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain $@
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run-task basic_tests/preconfig_testbench/configuration_chain $@
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run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io $@
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run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp $@
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echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
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run-task basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame $@
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run-task basic_tests/full_testbench/smart_fast_configuration_frame $@
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run-task basic_tests/full_testbench/fast_configuration_frame $@
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run-task basic_tests/full_testbench/fast_configuration_frame_use_set $@
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run-task basic_tests/full_testbench/configuration_frame_ccff $@
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run-task basic_tests/full_testbench/configuration_frame_scff $@
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run-task basic_tests/full_testbench/configuration_frame_use_reset $@
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run-task basic_tests/full_testbench/configuration_frame_use_resetb $@
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run-task basic_tests/full_testbench/configuration_frame_use_set $@
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run-task basic_tests/full_testbench/configuration_frame_use_setb $@
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run-task basic_tests/full_testbench/configuration_frame_use_set_reset $@
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run-task basic_tests/full_testbench/multi_region_configuration_frame $@
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run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame $@
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run-task basic_tests/preconfig_testbench/configuration_frame $@
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echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
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run-task basic_tests/full_testbench/memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank $@
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run-task basic_tests/full_testbench/memory_bank_use_reset $@
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run-task basic_tests/full_testbench/memory_bank_use_resetb $@
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run-task basic_tests/full_testbench/memory_bank_use_set $@
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run-task basic_tests/full_testbench/memory_bank_use_setb $@
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run-task basic_tests/full_testbench/memory_bank_use_set_reset $@
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run-task basic_tests/full_testbench/multi_region_memory_bank $@
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run-task basic_tests/full_testbench/fast_memory_bank $@
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run-task basic_tests/full_testbench/fast_memory_bank_use_set $@
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run-task basic_tests/full_testbench/smart_fast_memory_bank $@
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run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank $@
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run-task basic_tests/preconfig_testbench/memory_bank $@
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echo -e "Testing physical design friendly memory bank configuration protocol of a K4N4 FPGA";
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run-task basic_tests/full_testbench/ql_memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank_use_wlr --debug --show_thread_logs
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run-task basic_tests/full_testbench/multi_region_ql_memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank_flatten --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank $@
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run-task basic_tests/full_testbench/ql_memory_bank_use_wlr $@
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run-task basic_tests/full_testbench/multi_region_ql_memory_bank $@
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run-task basic_tests/full_testbench/ql_memory_bank_flatten $@
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run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr $@
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain $@
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echo -e "Testing testbenches without self checking features";
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run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking --debug --show_thread_logs
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run-task basic_tests/full_testbench/full_testbench_without_self_checking $@
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run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking $@
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echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
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run-task basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
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run-task basic_tests/full_testbench/flatten_memory $@
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run-task basic_tests/preconfig_testbench/flatten_memory $@
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echo -e "Testing fixed device layout and routing channel width";
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run-task basic_tests/fixed_device_support --debug --show_thread_logs
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run-task basic_tests/fixed_device_support $@
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echo -e "Testing fabric Verilog generation only";
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run-task basic_tests/generate_fabric --debug --show_thread_logs
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run-task basic_tests/generate_fabric $@
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echo -e "Testing Verilog testbench generation only";
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run-task basic_tests/generate_testbench --debug --show_thread_logs
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run-task basic_tests/generate_testbench $@
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echo -e "Testing separated Verilog fabric netlists and testbench locations";
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run-task basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
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run-task basic_tests/custom_fabric_netlist_location $@
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echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
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run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq --debug --show_thread_logs
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run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq $@
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# TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank
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#run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq --debug --show_thread_logs
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#run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq $@
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echo -e "Testing Secured FPGA fabrics";
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run-task basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
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run-task basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
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run-task basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
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run-task basic_tests/fabric_key/generate_random_key_ql_memory_bank --debug --show_thread_logs
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run-task basic_tests/fabric_key/load_external_key --debug --show_thread_logs
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run-task basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
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run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
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run-task basic_tests/fabric_key/load_external_key_qlbank_fpga --debug --show_thread_logs
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run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga --debug --show_thread_logs
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run-task basic_tests/fabric_key/load_external_key_qlbanksr_multi_chain_fpga --debug --show_thread_logs
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run-task basic_tests/fabric_key/generate_vanilla_key $@
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run-task basic_tests/fabric_key/generate_multi_region_vanilla_key $@
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run-task basic_tests/fabric_key/generate_random_key $@
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run-task basic_tests/fabric_key/generate_random_key_ql_memory_bank $@
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run-task basic_tests/fabric_key/load_external_key $@
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run-task basic_tests/fabric_key/load_external_key_cc_fpga $@
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run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga $@
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run-task basic_tests/fabric_key/load_external_key_qlbank_fpga $@
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run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga $@
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run-task basic_tests/fabric_key/load_external_key_qlbanksr_multi_chain_fpga $@
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# TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank
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#run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga --debug --show_thread_logs
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#run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga $@
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echo -e "Testing K4 series FPGA";
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echo -e "Testing K4N4 with facturable LUTs";
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run-task basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_frac_lut $@
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echo -e "Testing K4N4 with asynchronous reset";
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run-task basic_tests/k4_series/k4n4_fracff --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_fracff $@
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echo -e "Testing K4N4 with negative edge clocks";
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run-task basic_tests/k4_series/k4n4_fracff2edge --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_fracff2edge $@
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echo -e "Testing K4N4 with hard adders";
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run-task basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_adder $@
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echo -e "Testing K4N4 without local routing architecture";
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run-task basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_no_local_routing $@
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echo -e "Testing K4N4 with block RAM";
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run-task basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_bram $@
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echo -e "Testing K4N4 with LUTRAM";
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run-task basic_tests/k4_series/k4n4_lutram --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_lutram $@
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echo -e "Testing K4N4 with multiple lengths of routing segments";
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run-task basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_L124 $@
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echo -e "Testing K4N4 with 32-bit fracturable multiplier";
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run-task basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_frac_mult $@
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echo -e "Testing K4N5 with pattern based local routing";
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run-task basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n5_pattern_local_routing $@
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||||
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echo -e "Testing different tile organizations";
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||||
echo -e "Testing tiles with pins only on top and left sides";
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||||
run-task basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs
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run-task basic_tests/tile_organization/top_left_custom_pins $@
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echo -e "Testing tiles with pins only on top and right sides";
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run-task basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs
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||||
run-task basic_tests/tile_organization/top_right_custom_pins $@
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||||
echo -e "Testing tiles with pins only on bottom and right sides";
|
||||
run-task basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/bottom_right_custom_pins $@
|
||||
echo -e "Testing tiles with I/O in center grid";
|
||||
run-task basic_tests/tile_organization/tileable_io --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/tileable_io $@
|
||||
|
||||
echo -e "Testing global port definition from tiles";
|
||||
run-task basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_4clock_pin --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_clock $@
|
||||
run-task basic_tests/global_tile_ports/global_tile_reset $@
|
||||
run-task basic_tests/global_tile_ports/global_tile_4clock $@
|
||||
run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@
|
||||
|
||||
echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific";
|
||||
run-task basic_tests/verific_test --debug --show_thread_logs
|
||||
run-task basic_tests/verific_test $@
|
||||
|
||||
echo -e "Testing explicit multi verilog files";
|
||||
run-task basic_tests/explicit_multi_verilog_files --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing output files without time stamp";
|
||||
run-task basic_tests/no_time_stamp --debug --show_thread_logs
|
||||
# Run git-diff to ensure no changes on the golden netlists
|
||||
if git diff --name-status -- ':openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/**'; then
|
||||
echo -e "Golden netlist remain unchanged"
|
||||
else
|
||||
echo -e "Detect changes in golden scripts"; exit 1;
|
||||
fi
|
||||
run-task basic_tests/explicit_multi_verilog_files $@
|
||||
|
||||
echo -e "Test the remove of runtime directories"
|
||||
run-task basic_tests/explicit_multi_verilog_files --debug --show_thread_logs --remove_run_dir all
|
||||
|
||||
# Repgression test to test multi-user enviroment
|
||||
cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/
|
||||
cd /tmp/ && run-task configuration_chain --debug --show_thread_logs
|
||||
clear-task-run basic_tests/explicit_multi_verilog_files $@
|
||||
|
||||
echo -e "Testing write GSB to files";
|
||||
run-task basic_tests/write_gsb/write_gsb_to_xml --debug --show_thread_logs
|
||||
run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing --debug --show_thread_logs
|
||||
run-task basic_tests/write_gsb/write_unique_gsb_to_xml --debug --show_thread_logs
|
||||
run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing --debug --show_thread_logs
|
||||
run-task basic_tests/write_gsb/write_gsb_to_xml $@
|
||||
run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@
|
||||
run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@
|
||||
run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@
|
||||
|
||||
echo -e "Testing bus group features";
|
||||
run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping --debug --show_thread_logs
|
||||
run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping --debug --show_thread_logs
|
||||
run-task basic_tests/bus_group/full_testbench_explicit_mapping --debug --show_thread_logs
|
||||
run-task basic_tests/bus_group/full_testbench_implicit_mapping --debug --show_thread_logs
|
||||
run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping $@
|
||||
run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping $@
|
||||
run-task basic_tests/bus_group/full_testbench_explicit_mapping $@
|
||||
run-task basic_tests/bus_group/full_testbench_implicit_mapping $@
|
||||
|
||||
echo -e "Testing fix pins features";
|
||||
run-task basic_tests/fix_pins --debug --show_thread_logs
|
||||
run-task basic_tests/fix_pins $@
|
||||
|
||||
echo -e "Testing project templates";
|
||||
run-task template_tasks/vpr_blif_template --debug --show_thread_logs
|
||||
run-task template_tasks/yosys_vpr_template --debug --show_thread_logs
|
||||
run-task template_tasks/vtr_benchmarks_template --debug --show_thread_logs
|
||||
run-task template_tasks/vpr_blif_template $@
|
||||
run-task template_tasks/yosys_vpr_template $@
|
||||
run-task template_tasks/vtr_benchmarks_template $@
|
||||
|
||||
echo -e "Testing create tsk from template and run task"
|
||||
create-task _task_copy basic_tests/generate_fabric
|
||||
run-task _task_copy
|
||||
|
||||
echo -e "Testing output files without time stamp";
|
||||
run-task basic_tests/no_time_stamp $@
|
||||
# Run git-diff to ensure no changes on the golden netlists
|
||||
# Switch to root path in case users are running the tests in another location
|
||||
cd ${OPENFPGA_PATH}
|
||||
pwd
|
||||
git config --global --add safe.directory ${OPENFPGA_PATH}
|
||||
git log
|
||||
git diff --name-status -- ':${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/**'
|
||||
if git diff --name-status --exit-code -- ':${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/**'; then
|
||||
echo -e "Golden netlist remain unchanged"
|
||||
else
|
||||
echo -e "Detect changes in golden netlists"; exit 1;
|
||||
fi
|
||||
cd -
|
||||
|
||||
# Repgression test to test multi-user enviroment
|
||||
# Note: Keep this task as the last one!!!
|
||||
cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/
|
||||
cd /tmp/ && run-task configuration_chain $@
|
||||
cd -
|
||||
|
|
|
|||
|
|
@ -9,8 +9,9 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "Basic regression tests for Yosys-only flow";
|
||||
|
||||
echo -e "Testing configuration chain of a K4N4 FPGA";
|
||||
run-task basic_tests/yosys_only --debug --show_thread_logs
|
||||
run-task basic_tests/yosys_only $@
|
||||
|
||||
# Repgression test to test multi-user enviroment
|
||||
cp -r */*/basic_tests/yosys_only /tmp/
|
||||
cd /tmp/ && run-task yosys_only --debug --show_thread_logs
|
||||
cd /tmp/ && run-task yosys_only $@
|
||||
cd -
|
||||
|
|
|
|||
|
|
@ -9,30 +9,30 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "FPGA-Bitstream regression tests";
|
||||
|
||||
echo -e "Testing bitstream generation for an auto-sized device";
|
||||
run-task fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
|
||||
run-task fpga_bitstream/generate_bitstream/device_auto $@
|
||||
|
||||
echo -e "Testing bitstream generation for an 48x48 FPGA device";
|
||||
run-task fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
|
||||
run-task fpga_bitstream/generate_bitstream/device_48x48 $@
|
||||
|
||||
echo -e "Testing bitstream generation for an 96x96 FPGA device";
|
||||
run-task fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
|
||||
run-task fpga_bitstream/generate_bitstream/device_96x96 $@
|
||||
|
||||
echo -e "Testing loading architecture bitstream from an external file";
|
||||
run-task fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
|
||||
run-task fpga_bitstream/load_external_architecture_bitstream $@
|
||||
|
||||
echo -e "Testing repacker capability in identifying wire LUTs";
|
||||
run-task fpga_bitstream/repack_wire_lut --debug --show_thread_logs
|
||||
run-task fpga_bitstream/repack_wire_lut $@
|
||||
|
||||
echo -e "Testing overloading default paths for programmable interconnect when generating bitstream";
|
||||
run-task fpga_bitstream/overload_mux_default_path --debug --show_thread_logs
|
||||
run-task fpga_bitstream/overload_mux_default_path $@
|
||||
|
||||
echo -e "Testing outputting I/O mapping result to file";
|
||||
run-task fpga_bitstream/write_io_mapping --debug --show_thread_logs
|
||||
run-task fpga_bitstream/write_io_mapping $@
|
||||
|
||||
echo -e "Testing report bitstream distribution to file";
|
||||
run-task fpga_bitstream/report_bitstream_distribution/default_depth --debug --show_thread_logs
|
||||
run-task fpga_bitstream/report_bitstream_distribution/custom_depth --debug --show_thread_logs
|
||||
run-task fpga_bitstream/report_bitstream_distribution/default_depth $@
|
||||
run-task fpga_bitstream/report_bitstream_distribution/custom_depth $@
|
||||
|
||||
echo -e "Testing bitstream file with don't care bits";
|
||||
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_flatten --debug --show_thread_logs
|
||||
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register --debug --show_thread_logs
|
||||
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_flatten $@
|
||||
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register $@
|
||||
|
|
|
|||
|
|
@ -9,12 +9,12 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "FPGA-SDC regression tests";
|
||||
|
||||
echo -e "Testing SDC generation with time units";
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_as --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_fs --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ps --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ns --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_us --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ms --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_default --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ks --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_Ms --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_as $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_fs $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ps $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ns $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_us $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ms $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_default $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ks $@
|
||||
run-task fpga_sdc/sdc_time_unit/sdc_time_unit_Ms $@
|
||||
|
|
|
|||
|
|
@ -9,4 +9,4 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "FPGA-SPICE regression tests";
|
||||
|
||||
echo -e "Testing FPGA-SPICE with netlist generation";
|
||||
run-task fpga_spice/generate_spice --debug --show_thread_logs
|
||||
run-task fpga_spice/generate_spice $@
|
||||
|
|
|
|||
|
|
@ -9,141 +9,141 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "FPGA-Verilog Feature Tests";
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
|
||||
run-task fpga_verilog/lut_design/single_mode --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/single_mode $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
|
||||
run-task fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4 $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: fracturable LUT4 with embedded carry logic";
|
||||
run-task fpga_verilog/lut_design/frac_lut4_arith --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4_arith $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 ";
|
||||
run-task fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_native_lut4 $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
|
||||
run-task fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4_and_switch $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
|
||||
run-task fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut6 $@
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
|
||||
run-task fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/intermediate_buffer $@
|
||||
|
||||
echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
|
||||
run-task fpga_verilog/untileable --debug --show_thread_logs
|
||||
run-task fpga_verilog/untileable $@
|
||||
|
||||
echo -e "Testing Verilog generation with hard adder chain in CLBs ";
|
||||
run-task fpga_verilog/adder/hard_adder --debug --show_thread_logs
|
||||
run-task fpga_verilog/adder/hard_adder $@
|
||||
|
||||
echo -e "Testing Verilog generation with soft adder chain in CLBs ";
|
||||
run-task fpga_verilog/adder/soft_adder --debug --show_thread_logs
|
||||
run-task fpga_verilog/adder/soft_adder $@
|
||||
|
||||
echo -e "Testing Verilog generation with 1k block RAMs ";
|
||||
run-task fpga_verilog/bram/dpram1k --debug --show_thread_logs
|
||||
run-task fpga_verilog/bram/dpram1k $@
|
||||
|
||||
echo -e "Testing Verilog generation with 1k block RAMs spanning two columns ";
|
||||
run-task fpga_verilog/bram/wide_dpram1k --debug --show_thread_logs
|
||||
run-task fpga_verilog/bram/wide_dpram1k $@
|
||||
|
||||
echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode multipliers ";
|
||||
run-task fpga_verilog/dsp/single_mode_mult_8x8 --debug --show_thread_logs
|
||||
run-task fpga_verilog/dsp/single_mode_mult_8x8 $@
|
||||
|
||||
echo -e "Testing Verilog generation with heterogeneous fabric using 16-bit multi-mode multipliers ";
|
||||
run-task fpga_verilog/dsp/multi_mode_mult_16x16 --debug --show_thread_logs
|
||||
run-task fpga_verilog/dsp/multi_mode_mult_16x16 $@
|
||||
|
||||
echo -e "Testing Verilog generation with heterogeneous fabric using multi-width 16-bit multi-mode multipliers ";
|
||||
run-task fpga_verilog/dsp/wide_multi_mode_mult_16x16 --debug --show_thread_logs
|
||||
run-task fpga_verilog/dsp/wide_multi_mode_mult_16x16 $@
|
||||
|
||||
echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode registerable multipliers ";
|
||||
run-task fpga_verilog/dsp/single_mode_mult_8x8_reg --debug --show_thread_logs
|
||||
run-task fpga_verilog/dsp/single_mode_mult_8x8_reg $@
|
||||
|
||||
echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
|
||||
run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/multi_io_capacity $@
|
||||
|
||||
echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
|
||||
run-task fpga_verilog/io/reduced_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/reduced_io $@
|
||||
|
||||
echo -e "Testing Verilog generation with embedded I/Os for an FPGA ";
|
||||
run-task fpga_verilog/io/embedded_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/embedded_io $@
|
||||
|
||||
echo -e "Testing Verilog generation with SoC I/Os for an FPGA ";
|
||||
run-task fpga_verilog/io/soc_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/soc_io $@
|
||||
|
||||
echo -e "Testing Verilog generation with registerable I/Os for an FPGA ";
|
||||
run-task fpga_verilog/io/registerable_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/registerable_io $@
|
||||
|
||||
echo -e "Testing Verilog generation with adder chain across an FPGA";
|
||||
run-task fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/adder_chain $@
|
||||
|
||||
echo -e "Testing Verilog generation with shift register chain across an FPGA";
|
||||
run-task fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/register_chain $@
|
||||
|
||||
echo -e "Testing Verilog generation with scan chain across an FPGA";
|
||||
run-task fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/scan_chain $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
|
||||
run-task fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/tree_structure $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
|
||||
run-task fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/stdcell_mux2 $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
|
||||
run-task fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/local_encoder $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers without buffers";
|
||||
run-task fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/debuf_mux $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
|
||||
run-task fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/inbuf_only_mux $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
|
||||
run-task fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/outbuf_only_mux $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with constant gnd input";
|
||||
run-task fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/const_input_gnd $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers without constant inputs";
|
||||
run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/no_const_input $@
|
||||
|
||||
echo -e "Testing Verilog generation with behavioral description";
|
||||
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog_default_nettype_wire --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog $@
|
||||
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog_default_nettype_wire $@
|
||||
|
||||
echo -e "Testing synthesizable Verilog generation with external standard cells";
|
||||
run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog $@
|
||||
|
||||
echo -e "Testing implicit Verilog generation";
|
||||
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog $@
|
||||
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire $@
|
||||
|
||||
echo -e "Testing explicit Verilog generation";
|
||||
run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire $@
|
||||
|
||||
echo -e "Testing Verilog generation with flatten routing modules";
|
||||
run-task fpga_verilog/flatten_routing --debug --show_thread_logs
|
||||
run-task fpga_verilog/flatten_routing $@
|
||||
|
||||
echo -e "Testing Verilog generation with duplicated grid output pins";
|
||||
run-task fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
|
||||
run-task fpga_verilog/duplicated_grid_pin $@
|
||||
|
||||
echo -e "Testing Verilog generation with spy output pads";
|
||||
run-task fpga_verilog/spypad --debug --show_thread_logs
|
||||
run-task fpga_verilog/spypad $@
|
||||
|
||||
echo -e "Testing Power-gating designs";
|
||||
run-task fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
|
||||
|
||||
echo -e "Testing Depopulated crossbar in local routing";
|
||||
run-task fpga_verilog/depopulate_crossbar --debug --show_thread_logs
|
||||
run-task fpga_verilog/depopulate_crossbar $@
|
||||
|
||||
echo -e "Testing Fully connected output crossbar in local routing";
|
||||
run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
|
||||
run-task fpga_verilog/fully_connected_output_crossbar $@
|
||||
|
||||
echo -e "Testing through channels in tileable routing";
|
||||
run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
|
||||
run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
|
||||
run-task fpga_verilog/thru_channel/thru_narrow_tile $@
|
||||
run-task fpga_verilog/thru_channel/thru_wide_tile $@
|
||||
|
||||
echo -e "Testing the generation of preconfigured fabric wrapper for different HDL simulators";
|
||||
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none $@
|
||||
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim $@
|
||||
|
||||
echo -e "Testing the netlist generation by forcing the use of relative paths";
|
||||
run-task fpga_verilog/verilog_netlist_formats/use_relative_path --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/preconfig_testbench_use_relative_path --debug --show_thread_logs
|
||||
run-task fpga_verilog/verilog_netlist_formats/use_relative_path $@
|
||||
run-task fpga_verilog/verilog_netlist_formats/preconfig_testbench_use_relative_path $@
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ PYTHON_EXEC=python3.8
|
|||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "IWLS'05 benchmark regression tests";
|
||||
run-task benchmark_sweep/iwls2005 --debug --show_thread_logs
|
||||
run-task benchmark_sweep/iwls2005 $@
|
||||
# Run a quick but relaxed QoR check for heterogeneous blocks
|
||||
#python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv --check_tolerance 0.2,100
|
||||
python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv --check_tolerance 0.2,100
|
||||
|
|
|
|||
|
|
@ -7,15 +7,15 @@ PYTHON_EXEC=python3.8
|
|||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "Micro benchmark regression tests";
|
||||
run-task benchmark_sweep/counter8 --debug --show_thread_logs
|
||||
run-task benchmark_sweep/counter8_full_testbench --debug --show_thread_logs
|
||||
run-task benchmark_sweep/counter128 --debug --show_thread_logs
|
||||
run-task benchmark_sweep/mac_units --debug --show_thread_logs
|
||||
run-task benchmark_sweep/counter8 $@
|
||||
run-task benchmark_sweep/counter8_full_testbench $@
|
||||
run-task benchmark_sweep/counter128 $@
|
||||
run-task benchmark_sweep/mac_units $@
|
||||
|
||||
# Verify MCNC big20 benchmark suite with ModelSim
|
||||
# Please make sure you have ModelSim installed in the environment
|
||||
# Otherwise, it will fail
|
||||
run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
|
||||
run-task benchmark_sweep/mcnc_big20 $@
|
||||
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
|
||||
|
||||
run-task benchmark_sweep/signal_gen --debug --show_thread_logs
|
||||
run-task benchmark_sweep/signal_gen $@
|
||||
|
|
|
|||
|
|
@ -9,11 +9,11 @@ PYTHON_EXEC=python3.8
|
|||
echo -e "QuickLogic regression tests";
|
||||
|
||||
echo -e "Testing yosys flow using custom ys script for running quicklogic device";
|
||||
run-task quicklogic_tests/flow_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/flow_test $@
|
||||
|
||||
echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
|
||||
run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/counter_5clock_test $@
|
||||
run-task quicklogic_tests/sdc_controller_test $@
|
||||
|
||||
echo -e "Testing yosys flow using custom ys script for adders in quicklogic device";
|
||||
run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/lut_adder_test $@
|
||||
|
|
|
|||
|
|
@ -7,6 +7,6 @@ PYTHON_EXEC=python3.8
|
|||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "VTR benchmark regression tests";
|
||||
run-task benchmark_sweep/vtr_benchmarks --debug --show_thread_logs
|
||||
run-task benchmark_sweep/vtr_benchmarks $@
|
||||
# Run a quick but relaxed QoR check for heterogeneous blocks
|
||||
python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv --check_tolerance 0.2,100
|
||||
|
|
|
|||
|
|
@ -19,29 +19,31 @@ module and2_top_formal_verification_random_tb;
|
|||
reg [0:0] b;
|
||||
|
||||
// ----- FPGA fabric outputs -------
|
||||
wire [0:0] out_c_gfpga;
|
||||
wire [0:0] c_gfpga;
|
||||
|
||||
// ----- Benchmark outputs -------
|
||||
wire [0:0] out_c_bench;
|
||||
wire [0:0] c_bench;
|
||||
|
||||
// ----- Output vectors checking flags -------
|
||||
reg [0:0] out_c_flag;
|
||||
reg [0:0] c_flag;
|
||||
|
||||
// ----- Error counter -------
|
||||
integer nb_error= 0;
|
||||
|
||||
// ----- FPGA fabric instanciation -------
|
||||
and2_top_formal_verification FPGA_DUT(
|
||||
.a_fm(a),
|
||||
.b_fm(b),
|
||||
.out_c_fm(out_c_gfpga) );
|
||||
.a(a),
|
||||
.b(b),
|
||||
.c(c_gfpga)
|
||||
);
|
||||
// ----- End FPGA Fabric Instanication -------
|
||||
|
||||
// ----- Reference Benchmark Instanication -------
|
||||
and2 REF_DUT(
|
||||
.a(a),
|
||||
.b(b),
|
||||
.c(out_c_bench) );
|
||||
.c(c_bench)
|
||||
);
|
||||
// ----- End reference Benchmark Instanication -------
|
||||
|
||||
// ----- Clock 'clk' Initialization -------
|
||||
|
|
@ -61,7 +63,7 @@ module and2_top_formal_verification_random_tb;
|
|||
a <= 1'b0;
|
||||
b <= 1'b0;
|
||||
|
||||
out_c_flag[0] <= 1'b0;
|
||||
c_flag[0] <= 1'b0;
|
||||
end
|
||||
|
||||
// ----- Input Stimulus -------
|
||||
|
|
@ -77,19 +79,20 @@ module and2_top_formal_verification_random_tb;
|
|||
always@(negedge clk[0]) begin
|
||||
if (1'b1 == sim_start[0]) begin
|
||||
sim_start[0] <= ~sim_start[0];
|
||||
end else begin
|
||||
if(!(out_c_gfpga === out_c_bench) && !(out_c_bench === 1'bx)) begin
|
||||
out_c_flag <= 1'b1;
|
||||
end else
|
||||
begin
|
||||
if(!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin
|
||||
c_flag <= 1'b1;
|
||||
end else begin
|
||||
out_c_flag<= 1'b0;
|
||||
c_flag<= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge out_c_flag) begin
|
||||
if(out_c_flag) begin
|
||||
always@(posedge c_flag) begin
|
||||
if(c_flag) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on out_c_gfpga at time = %t", $realtime);
|
||||
$display("Mismatch on c_gfpga at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -11,76 +11,76 @@
|
|||
`default_nettype none
|
||||
|
||||
module and2_top_formal_verification (
|
||||
input [0:0] a_fm,
|
||||
input [0:0] b_fm,
|
||||
output [0:0] out_c_fm);
|
||||
input [0:0] a,
|
||||
input [0:0] b,
|
||||
output [0:0] c);
|
||||
|
||||
// ----- Local wires for FPGA fabric -----
|
||||
wire [0:31] gfpga_pad_GPIO_PAD;
|
||||
wire [0:0] ccff_head;
|
||||
wire [0:0] ccff_tail;
|
||||
wire [0:0] prog_clk;
|
||||
wire [0:0] set;
|
||||
wire [0:0] reset;
|
||||
wire [0:0] clk;
|
||||
wire [0:31] gfpga_pad_GPIO_PAD_fm;
|
||||
wire [0:0] ccff_head_fm;
|
||||
wire [0:0] ccff_tail_fm;
|
||||
wire [0:0] prog_clk_fm;
|
||||
wire [0:0] set_fm;
|
||||
wire [0:0] reset_fm;
|
||||
wire [0:0] clk_fm;
|
||||
|
||||
// ----- FPGA top-level module to be capsulated -----
|
||||
fpga_top U0_formal_verification (
|
||||
.prog_clk(prog_clk[0]),
|
||||
.set(set[0]),
|
||||
.reset(reset[0]),
|
||||
.clk(clk[0]),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0:31]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(ccff_tail[0]));
|
||||
.prog_clk(prog_clk_fm[0]),
|
||||
.set(set_fm[0]),
|
||||
.reset(reset_fm[0]),
|
||||
.clk(clk_fm[0]),
|
||||
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD_fm[0:31]),
|
||||
.ccff_head(ccff_head_fm[0]),
|
||||
.ccff_tail(ccff_tail_fm[0]));
|
||||
|
||||
// ----- Begin Connect Global ports of FPGA top module -----
|
||||
assign set[0] = 1'b0;
|
||||
assign reset[0] = 1'b0;
|
||||
assign clk[0] = 1'b0;
|
||||
assign prog_clk[0] = 1'b0;
|
||||
assign set_fm[0] = 1'b0;
|
||||
assign reset_fm[0] = 1'b0;
|
||||
assign clk_fm[0] = 1'b0;
|
||||
assign prog_clk_fm[0] = 1'b0;
|
||||
// ----- End Connect Global ports of FPGA top module -----
|
||||
|
||||
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[6] -----
|
||||
assign gfpga_pad_GPIO_PAD[6] = a_fm[0];
|
||||
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[6] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[6] = a[0];
|
||||
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[1] -----
|
||||
assign gfpga_pad_GPIO_PAD[1] = b_fm[0];
|
||||
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] -----
|
||||
assign gfpga_pad_GPIO_PAD_fm[1] = b[0];
|
||||
|
||||
// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[9] -----
|
||||
assign out_c_fm[0] = gfpga_pad_GPIO_PAD[9];
|
||||
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[9] -----
|
||||
assign c[0] = gfpga_pad_GPIO_PAD_fm[9];
|
||||
|
||||
// ----- Wire unused FPGA I/Os to constants -----
|
||||
assign gfpga_pad_GPIO_PAD[0] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[2] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[3] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[4] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[5] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[7] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[8] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[10] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[11] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[12] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[13] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[14] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[15] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[16] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[17] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[18] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[19] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[20] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[21] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[22] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[23] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[24] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[25] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[26] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[27] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[28] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[29] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[30] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD[31] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[5] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[19] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[20] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[21] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[30] = 1'b0;
|
||||
assign gfpga_pad_GPIO_PAD_fm[31] = 1'b0;
|
||||
|
||||
// ----- Begin load bitstream to configuration memories -----
|
||||
// ----- Begin assign bitstream to configuration memories -----
|
||||
|
|
|
|||
|
|
@ -1,32 +1,40 @@
|
|||
<!--
|
||||
- Report Architecture Bitstream Distribution
|
||||
- Report Bitstream Distribution
|
||||
-->
|
||||
|
||||
<block name="fpga_top" number_of_bits="527">
|
||||
<block name="grid_clb_1__1_" number_of_bits="136">
|
||||
</block>
|
||||
<block name="grid_io_top_1__2_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_right_2__1_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_bottom_1__0_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_left_0__1_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="sb_0__0_" number_of_bits="58">
|
||||
</block>
|
||||
<block name="sb_0__1_" number_of_bits="57">
|
||||
</block>
|
||||
<block name="sb_1__0_" number_of_bits="59">
|
||||
</block>
|
||||
<block name="sb_1__1_" number_of_bits="56">
|
||||
</block>
|
||||
<block name="cbx_1__0_" number_of_bits="33">
|
||||
</block>
|
||||
<block name="cbx_1__1_" number_of_bits="33">
|
||||
</block>
|
||||
<block name="cby_0__1_" number_of_bits="30">
|
||||
</block>
|
||||
<block name="cby_1__1_" number_of_bits="33">
|
||||
</block>
|
||||
</block>
|
||||
<bitstream_distribution>
|
||||
<regions>
|
||||
<region id="0" number_of_bits="527">
|
||||
</region>
|
||||
</regions>
|
||||
<blocks>
|
||||
<block name="fpga_top" number_of_bits="527">
|
||||
<block name="grid_clb_1__1_" number_of_bits="136">
|
||||
</block>
|
||||
<block name="grid_io_top_1__2_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_right_2__1_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_bottom_1__0_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="grid_io_left_0__1_" number_of_bits="8">
|
||||
</block>
|
||||
<block name="sb_0__0_" number_of_bits="58">
|
||||
</block>
|
||||
<block name="sb_0__1_" number_of_bits="57">
|
||||
</block>
|
||||
<block name="sb_1__0_" number_of_bits="59">
|
||||
</block>
|
||||
<block name="sb_1__1_" number_of_bits="56">
|
||||
</block>
|
||||
<block name="cbx_1__0_" number_of_bits="33">
|
||||
</block>
|
||||
<block name="cbx_1__1_" number_of_bits="33">
|
||||
</block>
|
||||
<block name="cby_0__1_" number_of_bits="30">
|
||||
</block>
|
||||
<block name="cby_1__1_" number_of_bits="33">
|
||||
</block>
|
||||
</block>
|
||||
</blocks>
|
||||
</bitstream_distribution>
|
||||
|
|
|
|||
Loading…
Reference in New Issue