From f149c88548eaf92961ca7bb14af0c6a00546aadd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Sep 2020 16:11:48 -0600 Subject: [PATCH] [Regression Test] Deploy input buffer only multiplexer testcase to CI --- .travis/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index f4f0d82d0..0a46dd5de 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -58,6 +58,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_enc echo -e "Testing Verilog generation with routing multiplexers without buffers"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs +echo -e "Testing Verilog generation with routing multiplexers with input buffers only"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs + echo -e "Testing Verilog generation with behavioral description"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs