From 6ae96d9717c998de1496f3f8de97e7c91b4b749e Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Wed, 19 Jun 2024 06:23:30 +0000 Subject: [PATCH 001/230] Bump vtr-verilog-to-routing from `e099206` to `2ff460a` Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `e099206` to `2ff460a`. - [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases) - [Commits](https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/e099206db3b2d1b0eb55c63edd90c85c4937fb95...2ff460a2459fcb8b225cd18ab23c4f6fdc528a75) --- updated-dependencies: - dependency-name: vtr-verilog-to-routing dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index e099206db..2ff460a24 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit e099206db3b2d1b0eb55c63edd90c85c4937fb95 +Subproject commit 2ff460a2459fcb8b225cd18ab23c4f6fdc528a75 From 2d6c9c3428de74f8a6c06732dba2c1c97b986cb0 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 20 Jun 2024 06:48:40 +0000 Subject: [PATCH 002/230] Bump yosys from `74a1dd9` to `6c8ae44` Bumps [yosys](https://github.com/YosysHQ/yosys) from `74a1dd9` to `6c8ae44`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/74a1dd99ac0bc7355b5d8913bc4b7bb0160ddb1d...6c8ae44ae7ebe5cbad7cfaf2d0934701e29c9527) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 74a1dd99a..6c8ae44ae 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 74a1dd99ac0bc7355b5d8913bc4b7bb0160ddb1d +Subproject commit 6c8ae44ae7ebe5cbad7cfaf2d0934701e29c9527 From 1edbdf9f221eba78277e7805362c99b48af233f1 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 20 Jun 2024 17:26:30 +0000 Subject: [PATCH 003/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 5506f25d8..4c6029b42 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2262 +1.2.2268 From 9ccd14bf4d674c3fdffc5b7fd1d03367398e40ca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 16:45:05 -0700 Subject: [PATCH 004/230] [lib] now default switch of clk ntwk is split to default_tap_switch and default_driver_switch --- libs/libclkarchopenfpga/arch/example.xml | 2 +- .../src/base/clock_network.cpp | 30 ++++++++++++++----- .../src/base/clock_network.h | 13 +++++--- .../src/io/clock_network_xml_constants.h | 6 ++-- .../src/io/read_xml_clock_network.cpp | 12 ++++++-- .../src/io/write_xml_clock_network.cpp | 6 ++-- 6 files changed, 49 insertions(+), 20 deletions(-) diff --git a/libs/libclkarchopenfpga/arch/example.xml b/libs/libclkarchopenfpga/arch/example.xml index ac6e722dd..ac251bd3c 100644 --- a/libs/libclkarchopenfpga/arch/example.xml +++ b/libs/libclkarchopenfpga/arch/example.xml @@ -1,4 +1,4 @@ - + diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index ee562bfd5..7ae5b9a4f 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -18,7 +18,8 @@ namespace openfpga { // Begin namespace openfpga ***********************************************************************/ ClockNetwork::ClockNetwork() { default_segment_id_ = RRSegmentId::INVALID(); - default_switch_id_ = RRSwitchId::INVALID(); + default_tap_switch_id_ = RRSwitchId::INVALID(); + default_driver_switch_id_ = RRSwitchId::INVALID(); is_dirty_ = true; } @@ -172,11 +173,16 @@ RRSegmentId ClockNetwork::default_segment() const { return default_segment_id_; } -std::string ClockNetwork::default_switch_name() const { - return default_switch_name_; +std::string ClockNetwork::default_tap_switch_name() const { + return default_tap_switch_name_; } -RRSwitchId ClockNetwork::default_switch() const { return default_switch_id_; } +std::string ClockNetwork::default_driver_switch_name() const { + return default_driver_switch_name_; +} + +RRSwitchId ClockNetwork::default_tap_switch() const { return default_tap_switch_id_; } +RRSwitchId ClockNetwork::default_driver_switch() const { return default_driver_switch_id_; } std::string ClockNetwork::tree_name(const ClockTreeId& tree_id) const { VTR_ASSERT(valid_tree_id(tree_id)); @@ -417,16 +423,24 @@ void ClockNetwork::set_default_segment(const RRSegmentId& seg_id) { default_segment_id_ = seg_id; } -void ClockNetwork::set_default_switch(const RRSwitchId& switch_id) { - default_switch_id_ = switch_id; +void ClockNetwork::set_default_tap_switch(const RRSwitchId& switch_id) { + default_tap_switch_id_ = switch_id; +} + +void ClockNetwork::set_default_driver_switch(const RRSwitchId& switch_id) { + default_driver_switch_id_ = switch_id; } void ClockNetwork::set_default_segment_name(const std::string& name) { default_segment_name_ = name; } -void ClockNetwork::set_default_switch_name(const std::string& name) { - default_switch_name_ = name; +void ClockNetwork::set_default_tap_switch_name(const std::string& name) { + default_tap_switch_name_ = name; +} + +void ClockNetwork::set_default_driver_switch_name(const std::string& name) { + default_driver_switch_name_ = name; } ClockTreeId ClockNetwork::create_tree(const std::string& name, size_t width) { diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 0b9b8a42b..ad8d5e61f 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -145,9 +145,11 @@ class ClockNetwork { /* Reserve a number of trees to be memory efficent */ void reserve_trees(const size_t& num_trees); void set_default_segment(const RRSegmentId& seg_id); - void set_default_switch(const RRSwitchId& switch_id); + void set_default_tap_switch(const RRSwitchId& switch_id); + void set_default_driver_switch(const RRSwitchId& switch_id); void set_default_segment_name(const std::string& name); - void set_default_switch_name(const std::string& name); + void set_default_tap_switch_name(const std::string& name); + void set_default_driver_switch_name(const std::string& name); /* Create a new tree, by default the tree can accomodate only 1 clock signal; * use width to adjust the size */ ClockTreeId create_tree(const std::string& name, size_t width = 1); @@ -250,8 +252,11 @@ class ClockNetwork { clock wires */ RRSegmentId default_segment_id_; std::string - default_switch_name_; /* The routing switch interconnecting clock wire */ - RRSwitchId default_switch_id_; + default_tap_switch_name_; /* The routing switch interconnecting clock wire */ + RRSwitchId default_tap_switch_id_; + std::string + default_driver_switch_name_; /* The routing switch interconnecting clock wire */ + RRSwitchId default_driver_switch_id_; /* Fast lookup */ std::map tree_name2id_map_; diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index db7216f2d..a172b88ec 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -6,8 +6,10 @@ constexpr const char* XML_CLOCK_NETWORK_ROOT_NAME = "clock_networks"; constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SEGMENT = "default_segment"; -constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SWITCH = - "default_switch"; +constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_TAP_SWITCH = + "default_tap_switch"; +constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_DRIVER_SWITCH = + "default_driver_switch"; constexpr const char* XML_CLOCK_TREE_NODE_NAME = "clock_network"; constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_NAME = "name"; constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_WIDTH = "width"; diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index ed083f483..372ec0c81 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -263,11 +263,17 @@ ClockNetwork read_xml_clock_network(const char* fname) { .as_string(); clk_ntwk.set_default_segment_name(default_segment_name); - std::string default_switch_name = - get_attribute(xml_root, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SWITCH, + std::string default_tap_switch_name = + get_attribute(xml_root, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_TAP_SWITCH, loc_data) .as_string(); - clk_ntwk.set_default_switch_name(default_switch_name); + clk_ntwk.set_default_tap_switch_name(default_tap_switch_name); + + std::string default_driver_switch_name = + get_attribute(xml_root, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_DRIVER_SWITCH, + loc_data) + .as_string(); + clk_ntwk.set_default_driver_switch_name(default_driver_switch_name); size_t num_trees = std::distance(xml_root.children().begin(), xml_root.children().end()); diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 720335aa4..a71051fe1 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -168,8 +168,10 @@ int write_xml_clock_network(const char* fname, const ClockNetwork& clk_ntwk) { fp << "<" << XML_CLOCK_NETWORK_ROOT_NAME; write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SEGMENT, clk_ntwk.default_segment_name().c_str()); - write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SWITCH, - clk_ntwk.default_switch_name().c_str()); + write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_TAP_SWITCH, + clk_ntwk.default_tap_switch_name().c_str()); + write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_DRIVER_SWITCH, + clk_ntwk.default_driver_switch_name().c_str()); fp << ">" << "\n"; From 1ab75cf76c4920eab9e1b7cfb61a1683cf2a7d8a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 16:52:22 -0700 Subject: [PATCH 005/230] [lib] now link clock arch supports tap and driver default switches --- .../src/utils/clock_network_utils.cpp | 34 +++++++++++++++---- 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp index 79737b46c..45b367809 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp @@ -32,18 +32,40 @@ static int link_clock_network_rr_segments(ClockNetwork& clk_ntwk, *******************************************************************/ static int link_clock_network_rr_switches(ClockNetwork& clk_ntwk, const RRGraphView& rr_graph) { - /* default switch id */ - std::string default_switch_name = clk_ntwk.default_switch_name(); + /* default tap switch id */ + int status = CMD_EXEC_FATAL_ERROR; + std::string default_tap_switch_name = clk_ntwk.default_tap_switch_name(); for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches(); ++rr_switch_id) { if (std::string(rr_graph.rr_switch_inf(RRSwitchId(rr_switch_id)).name) == - default_switch_name) { - clk_ntwk.set_default_switch(RRSwitchId(rr_switch_id)); - return CMD_EXEC_SUCCESS; + default_tap_switch_name) { + clk_ntwk.set_default_tap_switch(RRSwitchId(rr_switch_id)); + status = CMD_EXEC_SUCCESS; + break; } } + if (status != CMD_EXEC_SUCCESS) { + VTR_LOG("Unable to find the default tap switch '%s' in VPR architecture description!\n", default_tap_switch_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + /* default driver switch id */ + status = CMD_EXEC_FATAL_ERROR; + std::string default_driver_switch_name = clk_ntwk.default_driver_switch_name(); + for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches(); + ++rr_switch_id) { + if (std::string(rr_graph.rr_switch_inf(RRSwitchId(rr_switch_id)).name) == + default_driver_switch_name) { + clk_ntwk.set_default_driver_switch(RRSwitchId(rr_switch_id)); + status = CMD_EXEC_SUCCESS; + break; + } + } + if (status != CMD_EXEC_SUCCESS) { + VTR_LOG("Unable to find the default driver switch '%s' in VPR architecture description!\n", default_driver_switch_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } - return CMD_EXEC_FATAL_ERROR; + return status; } int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, From 486cd01c1505823c5696e9dd4078ba9503de54a8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 16:54:22 -0700 Subject: [PATCH 006/230] [core] now clock graph builder supports two types of switches --- openfpga/src/annotation/append_clock_rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index a52a86ed2..d6d6fe1b7 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -526,7 +526,7 @@ static void add_rr_graph_block_clock_edges( /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_switch(), false); + clk_ntwk.default_driver_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n", @@ -542,7 +542,7 @@ static void add_rr_graph_block_clock_edges( /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_switch(), false); + clk_ntwk.default_tap_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n", From 6c5988575cae36962e0ca976ca66fff6947de26b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 16:59:21 -0700 Subject: [PATCH 007/230] [test] update clock network testcase --- .../homo_1clock_2layer/config/clk_arch_1clk_2layer.xml | 2 +- .../homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml | 2 +- .../homo_2clock_2layer/config/clk_arch_2clk_2layer.xml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml index 0570406fd..6aaf1b9b4 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml @@ -1,4 +1,4 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml index 0570406fd..6aaf1b9b4 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml @@ -1,4 +1,4 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml index 46fec8fd5..fdf1dc149 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml @@ -1,4 +1,4 @@ - + From 3ddaefc2a2af2f5460b65df3ae592d3b7e9d27e0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 17:02:37 -0700 Subject: [PATCH 008/230] [lib] syntax --- libs/libclkarchopenfpga/src/base/clock_network.cpp | 2 +- libs/libclkarchopenfpga/src/base/clock_network.h | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 7ae5b9a4f..eea5c8dbf 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -636,7 +636,7 @@ bool ClockNetwork::validate_tree() const { bool ClockNetwork::validate() const { is_dirty_ = true; - if (default_segment_id_ && default_switch_id_ && validate_tree()) { + if (default_segment_id_ && default_tap_switch_id_ && default_driver_switch_id_ && validate_tree()) { is_dirty_ = false; } return true; diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index ad8d5e61f..3873eae50 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -73,8 +73,10 @@ class ClockNetwork { * information from RRGraph */ RRSegmentId default_segment() const; std::string default_segment_name() const; - RRSwitchId default_switch() const; - std::string default_switch_name() const; + RRSwitchId default_tap_switch() const; + std::string default_tap_switch_name() const; + RRSwitchId default_driver_switch() const; + std::string default_driver_switch_name() const; std::string tree_name(const ClockTreeId& tree_id) const; size_t tree_width(const ClockTreeId& tree_id) const; size_t tree_depth(const ClockTreeId& tree_id) const; From ecd31955b1e7d9e11fbffa4807403a8bd9c6af4b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 17:11:32 -0700 Subject: [PATCH 009/230] [core] code format --- libs/libclkarchopenfpga/src/base/clock_network.cpp | 11 ++++++++--- libs/libclkarchopenfpga/src/base/clock_network.h | 8 ++++---- .../src/utils/clock_network_utils.cpp | 13 ++++++++++--- openfpga/src/annotation/append_clock_rr_graph.cpp | 8 ++++---- 4 files changed, 26 insertions(+), 14 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index eea5c8dbf..c235bab7a 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -181,8 +181,12 @@ std::string ClockNetwork::default_driver_switch_name() const { return default_driver_switch_name_; } -RRSwitchId ClockNetwork::default_tap_switch() const { return default_tap_switch_id_; } -RRSwitchId ClockNetwork::default_driver_switch() const { return default_driver_switch_id_; } +RRSwitchId ClockNetwork::default_tap_switch() const { + return default_tap_switch_id_; +} +RRSwitchId ClockNetwork::default_driver_switch() const { + return default_driver_switch_id_; +} std::string ClockNetwork::tree_name(const ClockTreeId& tree_id) const { VTR_ASSERT(valid_tree_id(tree_id)); @@ -636,7 +640,8 @@ bool ClockNetwork::validate_tree() const { bool ClockNetwork::validate() const { is_dirty_ = true; - if (default_segment_id_ && default_tap_switch_id_ && default_driver_switch_id_ && validate_tree()) { + if (default_segment_id_ && default_tap_switch_id_ && + default_driver_switch_id_ && validate_tree()) { is_dirty_ = false; } return true; diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 3873eae50..3cf37a79a 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -253,11 +253,11 @@ class ClockNetwork { std::string default_segment_name_; /* The routing segment representing the clock wires */ RRSegmentId default_segment_id_; - std::string - default_tap_switch_name_; /* The routing switch interconnecting clock wire */ + std::string default_tap_switch_name_; /* The routing switch interconnecting + clock wire */ RRSwitchId default_tap_switch_id_; - std::string - default_driver_switch_name_; /* The routing switch interconnecting clock wire */ + std::string default_driver_switch_name_; /* The routing switch interconnecting + clock wire */ RRSwitchId default_driver_switch_id_; /* Fast lookup */ diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp index 45b367809..723fc51ea 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp @@ -45,12 +45,16 @@ static int link_clock_network_rr_switches(ClockNetwork& clk_ntwk, } } if (status != CMD_EXEC_SUCCESS) { - VTR_LOG("Unable to find the default tap switch '%s' in VPR architecture description!\n", default_tap_switch_name.c_str()); + VTR_LOG( + "Unable to find the default tap switch '%s' in VPR architecture " + "description!\n", + default_tap_switch_name.c_str()); return CMD_EXEC_FATAL_ERROR; } /* default driver switch id */ status = CMD_EXEC_FATAL_ERROR; - std::string default_driver_switch_name = clk_ntwk.default_driver_switch_name(); + std::string default_driver_switch_name = + clk_ntwk.default_driver_switch_name(); for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches(); ++rr_switch_id) { if (std::string(rr_graph.rr_switch_inf(RRSwitchId(rr_switch_id)).name) == @@ -61,7 +65,10 @@ static int link_clock_network_rr_switches(ClockNetwork& clk_ntwk, } } if (status != CMD_EXEC_SUCCESS) { - VTR_LOG("Unable to find the default driver switch '%s' in VPR architecture description!\n", default_driver_switch_name.c_str()); + VTR_LOG( + "Unable to find the default driver switch '%s' in VPR architecture " + "description!\n", + default_driver_switch_name.c_str()); return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index d6d6fe1b7..dee65e605 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -525,8 +525,8 @@ static void add_rr_graph_block_clock_edges( chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_driver_switch(), false); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_driver_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n", @@ -541,8 +541,8 @@ static void add_rr_graph_block_clock_edges( itree, ClockTreePinId(ipin))) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_tap_switch(), false); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_tap_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n", From 3f08b83b3a9b1fd692b08c6a1986f76b1ec7d0e0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 17:12:10 -0700 Subject: [PATCH 010/230] [core] remove restrictions on 1 clock tree definition --- .../src/annotation/append_clock_rr_graph.cpp | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index dee65e605..ac48b5cef 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -525,8 +525,8 @@ static void add_rr_graph_block_clock_edges( chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge( - src_node, des_node, clk_ntwk.default_driver_switch(), false); + rr_graph_builder.create_edge(src_node, des_node, + clk_ntwk.default_driver_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n", @@ -541,8 +541,8 @@ static void add_rr_graph_block_clock_edges( itree, ClockTreePinId(ipin))) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge( - src_node, des_node, clk_ntwk.default_tap_switch(), false); + rr_graph_builder.create_edge(src_node, des_node, + clk_ntwk.default_tap_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n", @@ -638,14 +638,6 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, return CMD_EXEC_SUCCESS; } - /* Report any clock structure we do not support yet! */ - if (clk_ntwk.num_trees() > 1) { - VTR_LOG( - "Currently only support 1 clock tree in programmable clock " - "architecture\nPlease update your clock architecture definition\n"); - return CMD_EXEC_FATAL_ERROR; - } - /* Estimate the number of nodes and pre-allocate */ size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes(); size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes( From 8d7dba2d57ab136c95b45d0e781efe270de7264c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 18:13:37 -0700 Subject: [PATCH 011/230] [test] add a new testcase to programmable clock network on supporting reset signals --- ...acff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml | 255 ++++++++++++++++++ .../example_clkntwk_no_ace_script.openfpga | 75 ++++++ .../config/clk_arch_1clk_1rst_2layer.xml | 32 +++ .../config/pin_constraints_reset.xml | 7 + .../config/pin_constraints_resetb.xml | 7 + .../config/task.conf | 49 ++++ 6 files changed, 425 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml create mode 100644 openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml new file mode 100644 index 000000000..e8b0e755f --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml @@ -0,0 +1,255 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga new file mode 100644 index 000000000..83cc44860 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga @@ -0,0 +1,75 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \ + --clock_modeling ideal \ + --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \ + --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Read OpenFPGA clock architecture +read_openfpga_clock_arch -f ${OPENFPGA_CLOCK_ARCH_FILE} + +# Append clock network to vpr's routing resource graph +append_clock_rr_graph + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Route clock based on clock network definition +route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack --design_constraints ${OPENFPGA_REPACK_CONSTRAINTS_FILE} #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..fde2c515a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml new file mode 100644 index 000000000..abcf209f6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..cdef2ad86 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf new file mode 100644 index 000000000..9b038d744 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf @@ -0,0 +1,49 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 7d67b9d5b92d4c39143e71cd715b2ebdd00fe3af Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 18:14:54 -0700 Subject: [PATCH 012/230] [test] deploy new tests to basic reg tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index c4b3ebcb8..0f2e1514e 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -232,6 +232,7 @@ echo -e "Testing programmable clock architecture"; run-task basic_tests/clock_network/homo_1clock_2layer $@ run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ run-task basic_tests/clock_network/homo_2clock_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1_reset_2layer $@ echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; run-task basic_tests/verific_test $@ From c2e759fa70418c408b08cb8bc49fdcf84c452c90 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 18:42:29 -0700 Subject: [PATCH 013/230] [arch] fixed some bugs --- .../k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml | 1 + openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml index e8b0e755f..36d5dce05 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml @@ -197,6 +197,7 @@ + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index cc4d5de0e..19447dd7e 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -194,6 +194,11 @@ With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> + + + 1 1 + 1 + 1 1 1 1 1 From 2193f108ee77fa88d95f125b14711d859f05e3d9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 18:42:35 -0700 Subject: [PATCH 014/230] [core] add debugging messages --- .../src/utils/clock_network_utils.cpp | 55 ++++++++++--------- .../src/base/openfpga_read_arch_template.h | 12 +++- 2 files changed, 39 insertions(+), 28 deletions(-) diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp index 723fc51ea..138ac4087 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp @@ -22,7 +22,10 @@ static int link_clock_network_rr_segments(ClockNetwork& clk_ntwk, return CMD_EXEC_SUCCESS; } } - + VTR_LOG_ERROR( + "Unable to find the default segement '%s' in VPR architecture " + "description!\n", + default_segment_name.c_str()); return CMD_EXEC_FATAL_ERROR; } @@ -30,29 +33,32 @@ static int link_clock_network_rr_segments(ClockNetwork& clk_ntwk, * Link all the switches that are defined in a routing resource graph to a given *clock network *******************************************************************/ -static int link_clock_network_rr_switches(ClockNetwork& clk_ntwk, +static int link_clock_network_tap_rr_switches(ClockNetwork& clk_ntwk, const RRGraphView& rr_graph) { /* default tap switch id */ - int status = CMD_EXEC_FATAL_ERROR; std::string default_tap_switch_name = clk_ntwk.default_tap_switch_name(); for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches(); ++rr_switch_id) { if (std::string(rr_graph.rr_switch_inf(RRSwitchId(rr_switch_id)).name) == default_tap_switch_name) { clk_ntwk.set_default_tap_switch(RRSwitchId(rr_switch_id)); - status = CMD_EXEC_SUCCESS; - break; + return CMD_EXEC_SUCCESS; } } - if (status != CMD_EXEC_SUCCESS) { - VTR_LOG( - "Unable to find the default tap switch '%s' in VPR architecture " - "description!\n", - default_tap_switch_name.c_str()); - return CMD_EXEC_FATAL_ERROR; - } + VTR_LOG_ERROR( + "Unable to find the default tap switch '%s' in VPR architecture " + "description!\n", + default_tap_switch_name.c_str()); + return CMD_EXEC_FATAL_ERROR; +} + +/******************************************************************** + * Link all the switches that are defined in a routing resource graph to a given + *clock network + *******************************************************************/ +static int link_clock_network_driver_rr_switches(ClockNetwork& clk_ntwk, + const RRGraphView& rr_graph) { /* default driver switch id */ - status = CMD_EXEC_FATAL_ERROR; std::string default_driver_switch_name = clk_ntwk.default_driver_switch_name(); for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches(); @@ -60,19 +66,14 @@ static int link_clock_network_rr_switches(ClockNetwork& clk_ntwk, if (std::string(rr_graph.rr_switch_inf(RRSwitchId(rr_switch_id)).name) == default_driver_switch_name) { clk_ntwk.set_default_driver_switch(RRSwitchId(rr_switch_id)); - status = CMD_EXEC_SUCCESS; - break; + return CMD_EXEC_SUCCESS; } } - if (status != CMD_EXEC_SUCCESS) { - VTR_LOG( - "Unable to find the default driver switch '%s' in VPR architecture " - "description!\n", - default_driver_switch_name.c_str()); - return CMD_EXEC_FATAL_ERROR; - } - - return status; + VTR_LOG_ERROR( + "Unable to find the default driver switch '%s' in VPR architecture " + "description!\n", + default_driver_switch_name.c_str()); + return CMD_EXEC_FATAL_ERROR; } int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, @@ -83,7 +84,11 @@ int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, if (CMD_EXEC_FATAL_ERROR == status) { return status; } - status = link_clock_network_rr_switches(clk_ntwk, rr_graph); + status = link_clock_network_tap_rr_switches(clk_ntwk, rr_graph); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + status = link_clock_network_driver_rr_switches(clk_ntwk, rr_graph); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/base/openfpga_read_arch_template.h b/openfpga/src/base/openfpga_read_arch_template.h index 829499c45..91e25a607 100644 --- a/openfpga/src/base/openfpga_read_arch_template.h +++ b/openfpga/src/base/openfpga_read_arch_template.h @@ -236,9 +236,15 @@ int read_openfpga_clock_arch_template(T& openfpga_context, const Command& cmd, openfpga_context.mutable_clock_arch() = read_xml_clock_network(arch_file_name.c_str()); /* Build internal links */ - openfpga_context.mutable_clock_arch().link(); - link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(), - g_vpr_ctx.device().rr_graph); + if (!openfpga_context.mutable_clock_arch().link()) { + VTR_LOG_ERROR("Link clock network failed!"); + return CMD_EXEC_FATAL_ERROR; + } + if (CMD_EXEC_SUCCESS != link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(), + g_vpr_ctx.device().rr_graph)) { + VTR_LOG_ERROR("Link clock network to routing architecture failed!"); + return CMD_EXEC_FATAL_ERROR; + } /* Ensure clean data */ openfpga_context.clock_arch().validate(); if (!openfpga_context.clock_arch().is_valid()) { From 292f4a9273b83c7f87b58cfb1514e61a4ef2f298 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 18:43:25 -0700 Subject: [PATCH 015/230] [test] fixed a bug where ace is no required --- .../example_clkntwk_no_ace_script.openfpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga index 83cc44860..1cdaa1932 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga @@ -19,7 +19,7 @@ append_clock_rr_graph # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Route clock based on clock network definition route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} From d2053db21c434c83e9606e0f76a8ba68acd014a1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 19:00:01 -0700 Subject: [PATCH 016/230] [core] removing the restrictions on only 1 clock tree is supported in programmable clock network --- openfpga/src/annotation/route_clock_rr_graph.cpp | 8 -------- 1 file changed, 8 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index bafc8215f..d669304c0 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -210,14 +210,6 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, return CMD_EXEC_SUCCESS; } - /* Report any clock structure we do not support yet! */ - if (clk_ntwk.num_trees() > 1) { - VTR_LOG( - "Currently only support 1 clock tree in programmable clock " - "architecture\nPlease update your clock architecture definition\n"); - return CMD_EXEC_FATAL_ERROR; - } - /* If there are multiple clock signals from the netlist, require pin * constraints */ std::vector clock_net_names = From 9bb076d89296508c5795b6647897b4973cd71192 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 20:29:21 -0700 Subject: [PATCH 017/230] [test] fixed a bug on pin mapping of tetbenche --- .../example_clkntwk_no_ace_script.openfpga | 6 +++--- .../homo_1clock_1reset_2layer/config/task.conf | 4 ++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga index 1cdaa1932..f62d62ecc 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga @@ -64,9 +64,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf index 9b038d744..d47ef31c7 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf @@ -19,9 +19,11 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -40,9 +42,11 @@ bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosy bench0_top = counter bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= bench1_top = counter bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From 253e3e0cbac13a06f0483670d8bc19343808c21f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 23 Jun 2024 17:43:38 -0700 Subject: [PATCH 018/230] [doc] add new syntax for clock network --- .../manual/file_formats/clock_network.rst | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index 9d6baad98..fe6d89b79 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -22,7 +22,7 @@ Using the clock network description language, users can define multiple clock ne .. code-block:: xml - + @@ -56,23 +56,28 @@ where the segment is defined in the VPR architecture file: .. note:: Currently, clock network requires only length-1 wire segment to be used! -.. option:: default_switch="" +.. option:: default_tap_switch="" + + Define the default routing switch to be used when interconnects the routing tracks to the input pins of programmable blocks in the clock network. Must be a valid routing switch defined in the VPR architecture file. See the example in the ``default_driver_switch``. + +.. option:: default_driver_switch="" Define the default routing switch to be used when interconnects the routing tracks in the clock network. Must be a valid routing switch defined in the VPR architecture file. For example, .. code-block:: xml - default_switch="clk_mux" + default_tap_switch="cb_mux" default_driver_switch="sb_clk_mux" where the switch is defined in the VPR architecture file: .. code-block:: xml - + + -.. note:: Currently, clock network only supports one type of routing switch, which means all the programmable routing switch in the clock network will be in the same type and circuit design topology. +.. note:: Currently, clock network only supports the default types of routing switch, which means all the programmable routing switch in the clock network will be in the same type and circuit design topology. Clock Network Settings ^^^^^^^^^^^^^^^^^^^^^^ @@ -94,7 +99,7 @@ where the clock network is used to drive the global clock pin ``clk0`` in OpenFP - From 9bdcc27913b28598cb4c9f51956c1f6a662e1c47 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 24 Jun 2024 06:55:52 +0000 Subject: [PATCH 019/230] Bump vtr-verilog-to-routing from `2ff460a` to `6a4f0ca` Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `2ff460a` to `6a4f0ca`. - [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases) - [Commits](https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/2ff460a2459fcb8b225cd18ab23c4f6fdc528a75...6a4f0cac3b180bdb78f53f58c9f3f23912858173) --- updated-dependencies: - dependency-name: vtr-verilog-to-routing dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 2ff460a24..6a4f0cac3 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 2ff460a2459fcb8b225cd18ab23c4f6fdc528a75 +Subproject commit 6a4f0cac3b180bdb78f53f58c9f3f23912858173 From a436afcc4fb979b848c6e4ddd467e371a70e432b Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 24 Jun 2024 17:21:57 +0000 Subject: [PATCH 020/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 4c6029b42..2a9a5e2f0 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2268 +1.2.2272 From dd5c3dc769b542ca27c246444154d632d3d6eb69 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 24 Jun 2024 15:17:57 -0700 Subject: [PATCH 021/230] [ci] use a new version of cancel-previous-flow due to node16 deprecation --- .github/workflows/build.yml | 18 +++++++++--------- .github/workflows/cell_lib_test.yml | 2 +- .github/workflows/format.yaml | 2 +- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 8b04312d5..c2ce66fcc 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -37,7 +37,7 @@ jobs: docker_repo: ${{ steps.changes.outputs.docker_repo }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} @@ -120,7 +120,7 @@ jobs: CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} @@ -216,7 +216,7 @@ jobs: CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} @@ -262,7 +262,7 @@ jobs: CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} @@ -308,7 +308,7 @@ jobs: CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} @@ -360,7 +360,7 @@ jobs: CXX: ${{ matrix.config.cxx }} steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} @@ -397,7 +397,7 @@ jobs: needs: [linux_build, change_detect] steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} @@ -450,7 +450,7 @@ jobs: - name: tcl_reg_test steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} @@ -508,7 +508,7 @@ jobs: - name: tcl_reg_test steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 5d590dc90..feaa28a3e 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -22,7 +22,7 @@ jobs: runs-on: ubuntu-22.04 steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} diff --git a/.github/workflows/format.yaml b/.github/workflows/format.yaml index 2631f135b..2a4fd8bbb 100644 --- a/.github/workflows/format.yaml +++ b/.github/workflows/format.yaml @@ -35,7 +35,7 @@ jobs: dependency_version: "ubuntu22p04" steps: - name: Cancel previous - uses: styfle/cancel-workflow-action@0.9.1 + uses: styfle/cancel-workflow-action@0.12.1 with: access_token: ${{ github.token }} From 428f5b480377640f6c5881bc1fd8d76946629497 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 24 Jun 2024 15:23:55 -0700 Subject: [PATCH 022/230] [ci] now use upload-artifact v4 due to deprecation --- .github/workflows/build.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index c2ce66fcc..b324c8c89 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -153,7 +153,7 @@ jobs: - name: Check ccache size run: ccache -s - name: Upload artifact - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 if: ${{ matrix.config.cc == 'gcc-11'}} with: name: openfpga @@ -475,7 +475,7 @@ jobs: shell: bash run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs - name: Upload artifact - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 if: ${{ failure() }} with: name: failed_${{matrix.config.name}}_regression_log @@ -524,7 +524,7 @@ jobs: unset OPENFPGA_PATH source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs - name: Upload artifact - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 if: ${{ failure() }} with: name: failed_${{matrix.config.name}}_regression_log From 0c442f6238abf3e5df96693ac3ffd4ed4e0f04bf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 24 Jun 2024 17:54:58 -0700 Subject: [PATCH 023/230] [lib] add syntax to support internal drivers in clock network parsers --- .../src/base/clock_network.cpp | 46 ++++++++++++++++++- .../src/base/clock_network.h | 21 ++++++++- .../src/base/clock_network_fwd.h | 2 + .../src/io/clock_network_xml_constants.h | 2 + .../src/io/read_xml_clock_network.cpp | 35 +++++++++++++- .../src/io/write_xml_clock_network.cpp | 20 ++++++-- 6 files changed, 119 insertions(+), 7 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index c235bab7a..4972e303b 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -32,6 +32,10 @@ ClockNetwork::clock_tree_range ClockNetwork::trees() const { return vtr::make_range(tree_ids_.begin(), tree_ids_.end()); } +ClockNetwork::clock_internal_driver_range ClockNetwork::internal_drivers() const { + return vtr::make_range(internal_driver_ids_.begin(), internal_driver_ids_.end()); +} + std::vector ClockNetwork::levels( const ClockTreeId& tree_id) const { std::vector ret; @@ -325,6 +329,18 @@ vtr::Point ClockNetwork::spine_switch_point( return spine_switch_coords_[spine_id][size_t(switch_point_id)]; } +std::vector ClockNetwork::spine_switch_point_internal_drivers( + const ClockSpineId& spine_id, + const ClockSwitchPointId& switch_point_id) const { + VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id)); + return spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)]; +} + +std::string ClockNetwork::internal_driver_port(const ClockInternalDriverId& int_driver_id) const { + VTR_ASSERT(valid_internal_driver_id(int_driver_id)); + return internal_driver_ports_[int_driver_id]; +} + std::vector ClockNetwork::tree_taps( const ClockTreeId& tree_id) const { VTR_ASSERT(valid_tree_id(tree_id)); @@ -410,6 +426,7 @@ void ClockNetwork::reserve_spines(const size_t& num_spines) { spine_track_types_.reserve(num_spines); spine_switch_points_.reserve(num_spines); spine_switch_coords_.reserve(num_spines); + spine_switch_internal_drivers_.reserve(num_spines); spine_parents_.reserve(num_spines); spine_children_.reserve(num_spines); spine_parent_trees_.reserve(num_spines); @@ -494,6 +511,7 @@ ClockSpineId ClockNetwork::create_spine(const std::string& name) { spine_track_types_.emplace_back(NUM_RR_TYPES); spine_switch_points_.emplace_back(); spine_switch_coords_.emplace_back(); + spine_switch_internal_drivers_.emplace_back(); spine_parents_.emplace_back(); spine_children_.emplace_back(); spine_parent_trees_.emplace_back(); @@ -544,7 +562,7 @@ void ClockNetwork::set_spine_track_type(const ClockSpineId& spine_id, spine_track_types_[spine_id] = type; } -void ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id, +ClockSwitchPointId ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id, const ClockSpineId& drive_spine_id, const vtr::Point& coord) { VTR_ASSERT(valid_spine_id(spine_id)); @@ -563,6 +581,27 @@ void ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id, } spine_parents_[drive_spine_id] = spine_id; spine_children_[spine_id].push_back(drive_spine_id); + return ClockSwitchPointId(spine_switch_points_[spine_id].size() - 1); +} + +ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver(const ClockSpineId& spine_id, + const ClockSwitchPointId& switch_point_id, + const std::string& int_driver_port) { + VTR_ASSERT(valid_spine_id(spine_id)); + VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id)); + /* Find any existing id for the driver port */ + for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { + if (internal_driver_ports_[int_driver_id] == int_driver_port) { + spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back(int_driver_id); + return int_driver_id; + } + } + /* Reaching here, no existing id can be reused, create a new one */ + ClockInternalDriverId int_driver_id = ClockInternalDriverId(internal_driver_ids_.size()); + internal_driver_ids_.push_back(int_driver_id); + internal_driver_ports_.push_back(int_driver_port); + spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back(int_driver_id); + return int_driver_id; } void ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, @@ -717,6 +756,11 @@ bool ClockNetwork::valid_tree_id(const ClockTreeId& tree_id) const { (tree_id == tree_ids_[tree_id]); } +bool ClockNetwork::valid_internal_driver_id(const ClockInternalDriverId& int_driver_id) const { + return (size_t(int_driver_id) < internal_driver_ids_.size()) && + (int_driver_id == internal_driver_ids_[int_driver_id]); +} + bool ClockNetwork::valid_level_id(const ClockTreeId& tree_id, const ClockLevelId& lvl_id) const { return valid_tree_id(tree_id) && (size_t(lvl_id) < tree_depth(tree_id)); diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 3cf37a79a..836781ee6 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -42,6 +42,10 @@ class ClockNetwork { clock_tree_iterator; /* Create range */ typedef vtr::Range clock_tree_range; + typedef vtr::vector::const_iterator + clock_internal_driver_iterator; + /* Create range */ + typedef vtr::Range clock_internal_driver_range; public: /* Constructors */ ClockNetwork(); @@ -49,6 +53,7 @@ class ClockNetwork { public: /* Accessors: aggregates */ size_t num_trees() const; clock_tree_range trees() const; + clock_internal_driver_range internal_drivers() const; /* Return the range of clock levels */ std::vector levels(const ClockTreeId& tree_id) const; /* Return a list of spine id under a clock tree */ @@ -116,6 +121,11 @@ class ClockNetwork { vtr::Point spine_switch_point( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const; + std::vector spine_switch_point_internal_drivers( + const ClockSpineId& spine_id, + const ClockSwitchPointId& switch_point_id) const; + std::string internal_driver_port(const ClockInternalDriverId& int_driver_id) const; + /* Return the original list of tap pins that is in storage; useful for parsers */ std::vector tree_taps(const ClockTreeId& tree_id) const; @@ -172,9 +182,12 @@ class ClockNetwork { void set_spine_direction(const ClockSpineId& spine_id, const Direction& dir); void set_spine_track_type(const ClockSpineId& spine_id, const t_rr_type& type); - void add_spine_switch_point(const ClockSpineId& spine_id, + ClockSwitchPointId add_spine_switch_point(const ClockSpineId& spine_id, const ClockSpineId& drive_spine_id, const vtr::Point& coord); + ClockInternalDriverId add_spine_switch_point_internal_driver(const ClockSpineId& spine_id, + const ClockSwitchPointId& switch_point_id, + const std::string& internal_driver_port); void add_tree_tap(const ClockTreeId& tree_id, const std::string& pin_name); /* Build internal links between clock tree, spines etc. This is also an * validator to verify the correctness of the clock network. Must run before @@ -184,6 +197,7 @@ class ClockNetwork { public: /* Public invalidators/validators */ /* Show if the tree id is a valid for data queries */ bool valid_tree_id(const ClockTreeId& tree_id) const; + bool valid_internal_driver_id(const ClockInternalDriverId& int_driver_id) const; /* Show if the level id is a valid for a given tree */ bool valid_level_id(const ClockTreeId& tree_id, const ClockLevelId& lvl_id) const; @@ -245,10 +259,15 @@ class ClockNetwork { vtr::vector spine_track_types_; vtr::vector> spine_switch_points_; vtr::vector>> spine_switch_coords_; + vtr::vector>> spine_switch_internal_drivers_; vtr::vector spine_parents_; vtr::vector> spine_children_; vtr::vector spine_parent_trees_; + /* Basic Information about internal drivers */ + vtr::vector internal_driver_ids_; + vtr::vector internal_driver_ports_; + /* Default routing resource */ std::string default_segment_name_; /* The routing segment representing the clock wires */ diff --git a/libs/libclkarchopenfpga/src/base/clock_network_fwd.h b/libs/libclkarchopenfpga/src/base/clock_network_fwd.h index 1285f069c..e9602d384 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network_fwd.h +++ b/libs/libclkarchopenfpga/src/base/clock_network_fwd.h @@ -19,12 +19,14 @@ struct clock_tree_id_tag; struct clock_tree_pin_id_tag; struct clock_spine_id_tag; struct clock_switch_point_id_tag; +struct clock_internal_driver_id_tag; typedef vtr::StrongId ClockLevelId; typedef vtr::StrongId ClockTreeId; typedef vtr::StrongId ClockTreePinId; typedef vtr::StrongId ClockSpineId; typedef vtr::StrongId ClockSwitchPointId; +typedef vtr::StrongId ClockInternalDriverId; /* Short declaration of class */ class ClockNetwork; diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index a172b88ec..6856a49f2 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -22,6 +22,8 @@ constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_Y = "end_y"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_TYPE = "type"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_DIRECTION = "direction"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point"; +constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = "internal_driver"; +constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ARRIBUTER_TILE_PIN = "tile_pin"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_TAP = "tap"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X = "x"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y = "y"; diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 372ec0c81..bdd3c6ab1 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -56,6 +56,24 @@ static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps, } } +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_spine_switch_point_internal_driver( + pugi::xml_node& xml_int_driver, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) { + if (!clk_ntwk.valid_spine_id(spine_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_switch_point), + "Invalid id of a clock spine!\n"); + } + + std::string int_driver_port_name = + get_attribute(xml_int_driver, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, + loc_data) + .as_string(); + clk_ntwk.add_spine_switch_point(spine_id, switch_point_id, int_driver_port_name); +} + /******************************************************************** * Parse XML codes of a to an object of ClockNetwork *******************************************************************/ @@ -90,8 +108,21 @@ static void read_xml_clock_spine_switch_point( XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y, loc_data) .as_int(); - clk_ntwk.add_spine_switch_point(spine_id, tap_spine_id, - vtr::Point(tap_x, tap_y)); + ClockSwitchPointId switch_point_id = clk_ntwk.add_spine_switch_point(spine_id, tap_spine_id, + vtr::Point(tap_x, tap_y)); + + /* Add internal drivers if possible */ + for (pugi::xml_node xml_int_driver : xml_switch_point.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_int_driver.name() == + std::string(XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME)) { + read_xml_clock_spine_switch_point_internal_driver(xml_int_driver, loc_data, clk_ntwk, + spine_id, switch_point_id); + } else { + bad_tag(xml_int_driver, loc_data, xml_switch_point, + {XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME}); + } + } } /******************************************************************** diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index a71051fe1..ce8380c77 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -59,9 +59,23 @@ static int write_xml_clock_spine_switch_point( clk_ntwk.spine_switch_point(spine_id, switch_point_id); write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X, coord.x()); write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y, coord.y()); - - fp << "/>" - << "\n"; + + /* Optional: internal drivers */ + if (clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id).empty()) { + fp << "/>" + << "\n"; + } else { + fp << ">" + << "\n"; + for (ClockInternalDriverId int_driver_id : clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id)) { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME; + write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ARRIBUTER_TILE_PIN, clk_ntwk.internal_driver_port(int_driver_id).c_str()); + fp << "/>" + << "\n"; + } + fp << "\n"; + } return 0; } From 2eda2825b7417501a8bc6ff6e92b3c47f041f6df Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 24 Jun 2024 18:28:42 -0700 Subject: [PATCH 024/230] [lib] syntax --- libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h | 2 +- libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp | 4 ++-- libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index 6856a49f2..9eab6bd8f 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -23,7 +23,7 @@ constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_TYPE = "type"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_DIRECTION = "direction"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = "internal_driver"; -constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ARRIBUTER_TILE_PIN = "tile_pin"; +constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN = "tile_pin"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_TAP = "tap"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X = "x"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y = "y"; diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index bdd3c6ab1..be73eb689 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -63,7 +63,7 @@ static void read_xml_clock_spine_switch_point_internal_driver( pugi::xml_node& xml_int_driver, const pugiutil::loc_data& loc_data, ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) { if (!clk_ntwk.valid_spine_id(spine_id)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_switch_point), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_int_driver), "Invalid id of a clock spine!\n"); } @@ -71,7 +71,7 @@ static void read_xml_clock_spine_switch_point_internal_driver( get_attribute(xml_int_driver, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, loc_data) .as_string(); - clk_ntwk.add_spine_switch_point(spine_id, switch_point_id, int_driver_port_name); + clk_ntwk.add_spine_switch_point_internal_driver(spine_id, switch_point_id, int_driver_port_name); } /******************************************************************** diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index ce8380c77..e107a4606 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -70,7 +70,7 @@ static int write_xml_clock_spine_switch_point( for (ClockInternalDriverId int_driver_id : clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id)) { openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME; - write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ARRIBUTER_TILE_PIN, clk_ntwk.internal_driver_port(int_driver_id).c_str()); + write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, clk_ntwk.internal_driver_port(int_driver_id).c_str()); fp << "/>" << "\n"; } From 36ef555dda41a9fb63c2be06b34ed21d778b0581 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 24 Jun 2024 18:33:47 -0700 Subject: [PATCH 025/230] [lib] add example arch for clock arch with internal drivers --- .../arch/example_internal_drivers.xml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 libs/libclkarchopenfpga/arch/example_internal_drivers.xml diff --git a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml new file mode 100644 index 000000000..2b8a5fe0d --- /dev/null +++ b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 22bee35fd178a8b7bc5dedb8e2401949634d7bbf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 24 Jun 2024 18:47:56 -0700 Subject: [PATCH 026/230] [lib] mem allocate --- libs/libclkarchopenfpga/src/base/clock_network.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 4972e303b..ecfdd48c6 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -569,6 +569,7 @@ ClockSwitchPointId ClockNetwork::add_spine_switch_point(const ClockSpineId& spin VTR_ASSERT(valid_spine_id(drive_spine_id)); spine_switch_points_[spine_id].push_back(drive_spine_id); spine_switch_coords_[spine_id].push_back(coord); + spine_switch_internal_drivers_[spine_id].emplace_back(); /* Do not allow any spine has different parents */ if (spine_parents_[drive_spine_id]) { VTR_LOG_ERROR( From 272d78eb43fa56d2d793f943b2fb7ff9d6399809 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 24 Jun 2024 19:13:36 -0700 Subject: [PATCH 027/230] [test] add a new unit test --- libs/libclkarchopenfpga/test/xml_io_clock_network.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libs/libclkarchopenfpga/test/xml_io_clock_network.cpp b/libs/libclkarchopenfpga/test/xml_io_clock_network.cpp index 7a3708c67..fbabf50c5 100644 --- a/libs/libclkarchopenfpga/test/xml_io_clock_network.cpp +++ b/libs/libclkarchopenfpga/test/xml_io_clock_network.cpp @@ -22,6 +22,10 @@ int main(int argc, const char** argv) { /* Validate before write out */ if (!clk_ntwk.link()) { + VTR_LOG_ERROR("Invalid clock network when linking.\n"); + exit(1); + } + if (!clk_ntwk.validate()) { VTR_LOG_ERROR("Invalid clock network.\n"); exit(1); } From 4619e3ea53966b36e78e479e8f4b26559a301f7b Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Tue, 25 Jun 2024 06:59:40 +0000 Subject: [PATCH 028/230] Bump yosys from `6c8ae44` to `1288166` Bumps [yosys](https://github.com/YosysHQ/yosys) from `6c8ae44` to `1288166`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/6c8ae44ae7ebe5cbad7cfaf2d0934701e29c9527...1288166f7ac03456b6beb0acff5d4fc84f63f57c) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 6c8ae44ae..1288166f7 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 6c8ae44ae7ebe5cbad7cfaf2d0934701e29c9527 +Subproject commit 1288166f7ac03456b6beb0acff5d4fc84f63f57c From ea5ab5117c423eefb4ca771b6605365e0f0312eb Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 25 Jun 2024 16:36:44 +0000 Subject: [PATCH 029/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 2a9a5e2f0..91f6656fa 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2272 +1.2.2276 From 31d4b4c40258e65f207f87cebe749f6285d0ddd0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 11:27:22 -0700 Subject: [PATCH 030/230] [core] now support add internal drivers to clock tree --- .../src/base/clock_network.cpp | 40 +++++ .../src/base/clock_network.h | 1 + .../src/annotation/append_clock_rr_graph.cpp | 145 +++++++++++++++++- 3 files changed, 185 insertions(+), 1 deletion(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index ecfdd48c6..9c493c9f7 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -389,6 +389,46 @@ std::vector ClockNetwork::tree_flatten_taps( return flatten_taps; } +std::vector ClockNetwork::flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const { + std::vector flatten_taps; + for (const std::string& tap_name : internal_driver_port(int_driver_id)) { + StringToken tokenizer(tap_name); + std::vector pin_tokens = tokenizer.split("."); + if (pin_tokens.size() != 2) { + VTR_LOG_ERROR("Invalid pin name '%s'. Expect .\n", + tap_name.c_str()); + exit(1); + } + PortParser tile_parser(pin_tokens[0]); + BasicPort tile_info = tile_parser.port(); + PortParser pin_parser(pin_tokens[1]); + BasicPort pin_info = pin_parser.port(); + if (!tile_info.is_valid()) { + VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n", + tap_name.c_str()); + exit(1); + } + if (!pin_info.is_valid()) { + VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n", + tap_name.c_str()); + exit(1); + } + for (size_t& tile_idx : tile_info.pins()) { + std::string flatten_tile_str = + tile_info.get_name() + "[" + std::to_string(tile_idx) + "]"; + for (size_t& pin_idx : pin_info.pins()) { + if (pin_idx != size_t(clk_pin_id)) { + continue; + } + std::string flatten_pin_str = + pin_info.get_name() + "[" + std::to_string(pin_idx) + "]"; + flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str); + } + } + } + return flatten_taps; +} + ClockTreeId ClockNetwork::find_tree(const std::string& name) const { auto result = tree_name2id_map_.find(name); if (result == tree_name2id_map_.end()) { diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 836781ee6..6a972cb46 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -125,6 +125,7 @@ class ClockNetwork { const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const; std::string internal_driver_port(const ClockInternalDriverId& int_driver_id) const; + std::vector flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const; /* Return the original list of tap pins that is in storage; useful for parsers */ diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index ac48b5cef..3263c838b 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -545,7 +545,7 @@ static void add_rr_graph_block_clock_edges( clk_ntwk.default_tap_switch(), false); edge_count++; } - VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n", + VTR_LOGV(verbose, "\tWill add %lu edges to IPINs\n", edge_count - curr_edge_count); } } @@ -557,6 +557,147 @@ static void add_rr_graph_block_clock_edges( num_edges_to_create += edge_count; } +/******************************************************************** + * Try to find an OPIN of a grid which satisfy the requirement of clock pins + * that has been defined in clock network. If the OPIN does exist in a + * routing resource graph, add it to the node list + *******************************************************************/ +static void try_find_and_add_clock_opin2track_node( + std::vector& opin_nodes, const DeviceGrid& grids, + const RRGraphView& rr_graph_view, const size_t& layer, + const vtr::Point& grid_coord, const e_side& pin_side, + const ClockNetwork& clk_ntwk, + const ClockInternalDriverId& int_driver_id) { + t_physical_tile_type_ptr grid_type = grids.get_physical_type( + t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); + for (std::string tap_pin_name : + clk_ntwk.flatten_internal_driver_port(int_driver_id)) { + /* tap pin name could be 'io[5:5].a2f[0]' */ + int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name); + if (grid_pin_idx == grid_type->num_pins) { + continue; + } + RRNodeId opin_node = rr_graph_view.node_lookup().find_node( + layer, grid_coord.x(), grid_coord.y(), OPIN, grid_pin_idx, pin_side); + if (rr_graph_view.valid_node(opin_node)) { + opin_nodes.push_back(opin_node); + } + } +} + +/******************************************************************** + * Find the source OPIN nodes as internal drivers for a clock node + * For example + * clk0_lvl1_chany[1][1] + * ^ + * | + * internal_driver OPIN[0] -->-------+ + * ^ + * | + * internal_driver OPIN[1] + * + * Coordinate system: + * + * +----------+----------+------------+ + * | Grid | CBy | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * +----------+----------+------------+ + * | CBx | SB | CBx | + * | [x][y] | [x][y] | [x+1][y] | + * +----------+----------+------------+ + * | Grid | CBy | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * +----------+----------+------------+ + *******************************************************************/ +static std::vector find_clock_opin2track_node( + const DeviceGrid& grids, const RRGraphView& rr_graph_view, + const size_t& layer, + const vtr::Point& sb_coord, + const ClockNetwork& clk_ntwk, + const std::vector& int_driver_ids +) { + std::vector opin_nodes; + /* Find opins from + * - Grid[x][y+1] on right and bottom sides + * - Grid[x+1][y+1] on left and bottom sides + * - Grid[x][y] on right and top sides + * - Grid[x+1][y] on left and top sides + */ + std::array, 4> grid_coords; + std::array, 2>, 4> grid_sides; + grid_coords[0] = grid_coord(sb_coord.x(), sb_coord.y() + 1); + grid_sides[0] = {RIGHT, BOTTOM}; + grid_coords[1] = grid_coord(sb_coord.x() + 1, sb_coord.y() + 1); + grid_sides[1] = {LEFT, BOTTOM}; + grid_coords[2] = grid_coord(sb_coord.x() + 1, sb_coord.y()); + grid_sides[2] = {RIGHT, TOP}; + grid_coords[3] = grid_coord(sb_coord.x(), sb_coord.y()); + grid_sides[3] = {LEFT, TOP}; + for (size_t igrid = 0; igrid < 4; igrid++) { + vtr::Point grid_coord = grid_coords[igrid]; + for (e_side grid_side : grid_sides[igrid]) { + for (ClockInternalDriverId int_driver_id : int_driver_ids) { + try_find_and_add_clock_opin2track_node(opin_nodes, grids, rr_graph_view, + layer, grid_coord, grid_side, + clk_ntwk, int_driver_id); + } + } + } + return opin_nodes; +} + +/******************************************************************** + * Add edges between OPIN of programmable blocks and clock routing tracks + * Note that such edges only occur at the switching points of spines + * Different from add_rr_graph_block_clock_edges(), we follow the clock spines here + * By expanding on switching points, internal drivers will be added + *******************************************************************/ +static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, + const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, + const DeviceGrid& grids, const size_t& layer, + const ClockNetwork& clk_ntwk, const bool& verbose) { + size_t edge_count = 0; + for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) { + VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); + for (auto ipin : clk_ntwk.pins(clk_tree)) { + for (ClockSwitchPointId switch_point_id : + clk_ntwk.spine_switch_points(ispine)) { + if (clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty()) { + continue; /* We only focus on switching points containing internal drivers */ + } + size_t curr_edge_count = edge_count; + /* Get the rr node of destination spine */ + ClockSpineId des_spine = + clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); + vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); + Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); + RRNodeId des_node = + clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, + des_spine_level, ipin, des_spine_direction); + /* Walk through each qualified OPIN, build edges */ + vtr::Point src_coord = + clk_ntwk.spine_switch_point(ispine, switch_point_id); + std::vector int_driver_ids = clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id); + for (RRNodId src_node : find_clock_opin2track_node(grids, rr_graph_view, layer, src_coord, clk_ntwk, int_driver_ids)) { + /* Create edges */ + VTR_ASSERT(rr_graph_view.valid_node(des_node)); + rr_graph_builder.create_edge(src_node, des_node, + clk_ntwk.default_driver_switch(), false); + edge_count++; + } + VTR_LOGV(verbose, "\tWill add %lu edges to OPINs at (x=%lu, y=%lu)\n", + edge_count - curr_edge_count, des_coord.x(), des_coord.y()); + } + } + } + /* Allocate edges */ + rr_graph_builder.build_edges(true); + num_edges_to_create += edge_count; + return CMD_EXEC_SUCCESS; +} + /******************************************************************** * Add edges to interconnect clock nodes * Walk through the routing tracks in each connection block (driver nodes) @@ -614,6 +755,8 @@ static void add_rr_graph_clock_edges( clk_ntwk, chany_coord, CHANY, verbose); } } + /* Add edges between OPIN (internal driver) and clock routing tracks */ + add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, rr_graph_view, grids, layer, clk_ntwk, verbose); } /******************************************************************** From 3b2c13402a3cfa2ea35160ba9f6bfa23500288c8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 11:44:25 -0700 Subject: [PATCH 031/230] [core] syntax --- .../src/base/clock_network.cpp | 62 +++++++-------- .../src/annotation/append_clock_rr_graph.cpp | 78 ++++++++++--------- 2 files changed, 69 insertions(+), 71 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 9c493c9f7..b76631c5c 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -391,39 +391,35 @@ std::vector ClockNetwork::tree_flatten_taps( std::vector ClockNetwork::flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const { std::vector flatten_taps; - for (const std::string& tap_name : internal_driver_port(int_driver_id)) { - StringToken tokenizer(tap_name); - std::vector pin_tokens = tokenizer.split("."); - if (pin_tokens.size() != 2) { - VTR_LOG_ERROR("Invalid pin name '%s'. Expect .\n", - tap_name.c_str()); - exit(1); - } - PortParser tile_parser(pin_tokens[0]); - BasicPort tile_info = tile_parser.port(); - PortParser pin_parser(pin_tokens[1]); - BasicPort pin_info = pin_parser.port(); - if (!tile_info.is_valid()) { - VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n", - tap_name.c_str()); - exit(1); - } - if (!pin_info.is_valid()) { - VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n", - tap_name.c_str()); - exit(1); - } - for (size_t& tile_idx : tile_info.pins()) { - std::string flatten_tile_str = - tile_info.get_name() + "[" + std::to_string(tile_idx) + "]"; - for (size_t& pin_idx : pin_info.pins()) { - if (pin_idx != size_t(clk_pin_id)) { - continue; - } - std::string flatten_pin_str = - pin_info.get_name() + "[" + std::to_string(pin_idx) + "]"; - flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str); - } + std::string tap_name = internal_driver_port(int_driver_id); + StringToken tokenizer(tap_name); + std::vector pin_tokens = tokenizer.split("."); + if (pin_tokens.size() != 2) { + VTR_LOG_ERROR("Invalid pin name '%s'. Expect .\n", + tap_name.c_str()); + exit(1); + } + PortParser tile_parser(pin_tokens[0]); + BasicPort tile_info = tile_parser.port(); + PortParser pin_parser(pin_tokens[1]); + BasicPort pin_info = pin_parser.port(); + if (!tile_info.is_valid()) { + VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n", + tap_name.c_str()); + exit(1); + } + if (!pin_info.is_valid()) { + VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n", + tap_name.c_str()); + exit(1); + } + for (size_t& tile_idx : tile_info.pins()) { + std::string flatten_tile_str = + tile_info.get_name() + "[" + std::to_string(tile_idx) + "]"; + for (size_t& pin_idx : pin_info.pins()) { + std::string flatten_pin_str = + pin_info.get_name() + "[" + std::to_string(pin_idx) + "]"; + flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str); } } return flatten_taps; diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 3263c838b..ecfe5e874 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -565,7 +565,7 @@ static void add_rr_graph_block_clock_edges( static void try_find_and_add_clock_opin2track_node( std::vector& opin_nodes, const DeviceGrid& grids, const RRGraphView& rr_graph_view, const size_t& layer, - const vtr::Point& grid_coord, const e_side& pin_side, + const vtr::Point& grid_coord, const e_side& pin_side, const ClockNetwork& clk_ntwk, const ClockInternalDriverId& int_driver_id) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( @@ -624,14 +624,14 @@ static std::vector find_clock_opin2track_node( * - Grid[x+1][y] on left and top sides */ std::array, 4> grid_coords; - std::array, 2>, 4> grid_sides; - grid_coords[0] = grid_coord(sb_coord.x(), sb_coord.y() + 1); + std::array, 4> grid_sides; + grid_coords[0] = vtr::Point(sb_coord.x(), sb_coord.y() + 1); grid_sides[0] = {RIGHT, BOTTOM}; - grid_coords[1] = grid_coord(sb_coord.x() + 1, sb_coord.y() + 1); + grid_coords[1] = vtr::Point(sb_coord.x() + 1, sb_coord.y() + 1); grid_sides[1] = {LEFT, BOTTOM}; - grid_coords[2] = grid_coord(sb_coord.x() + 1, sb_coord.y()); + grid_coords[2] = vtr::Point(sb_coord.x() + 1, sb_coord.y()); grid_sides[2] = {RIGHT, TOP}; - grid_coords[3] = grid_coord(sb_coord.x(), sb_coord.y()); + grid_coords[3] = vtr::Point(sb_coord.x(), sb_coord.y()); grid_sides[3] = {LEFT, TOP}; for (size_t igrid = 0; igrid < 4; igrid++) { vtr::Point grid_coord = grid_coords[igrid]; @@ -657,38 +657,40 @@ static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t& const DeviceGrid& grids, const size_t& layer, const ClockNetwork& clk_ntwk, const bool& verbose) { size_t edge_count = 0; - for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) { - VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - for (auto ipin : clk_ntwk.pins(clk_tree)) { - for (ClockSwitchPointId switch_point_id : - clk_ntwk.spine_switch_points(ispine)) { - if (clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty()) { - continue; /* We only focus on switching points containing internal drivers */ + for (ClockTreeId clk_tree : clk_ntwk.trees()) { + for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) { + VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); + for (auto ipin : clk_ntwk.pins(clk_tree)) { + for (ClockSwitchPointId switch_point_id : + clk_ntwk.spine_switch_points(ispine)) { + if (clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty()) { + continue; /* We only focus on switching points containing internal drivers */ + } + size_t curr_edge_count = edge_count; + /* Get the rr node of destination spine */ + ClockSpineId des_spine = + clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); + vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); + Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); + RRNodeId des_node = + clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, + des_spine_level, ipin, des_spine_direction); + /* Walk through each qualified OPIN, build edges */ + vtr::Point src_coord = + clk_ntwk.spine_switch_point(ispine, switch_point_id); + std::vector int_driver_ids = clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id); + for (RRNodeId src_node : find_clock_opin2track_node(grids, rr_graph_view, layer, src_coord, clk_ntwk, int_driver_ids)) { + /* Create edges */ + VTR_ASSERT(rr_graph_view.valid_node(des_node)); + rr_graph_builder.create_edge(src_node, des_node, + clk_ntwk.default_driver_switch(), false); + edge_count++; + } + VTR_LOGV(verbose, "\tWill add %lu edges to OPINs at (x=%lu, y=%lu)\n", + edge_count - curr_edge_count, des_coord.x(), des_coord.y()); } - size_t curr_edge_count = edge_count; - /* Get the rr node of destination spine */ - ClockSpineId des_spine = - clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); - vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); - Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); - RRNodeId des_node = - clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); - /* Walk through each qualified OPIN, build edges */ - vtr::Point src_coord = - clk_ntwk.spine_switch_point(ispine, switch_point_id); - std::vector int_driver_ids = clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id); - for (RRNodId src_node : find_clock_opin2track_node(grids, rr_graph_view, layer, src_coord, clk_ntwk, int_driver_ids)) { - /* Create edges */ - VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_driver_switch(), false); - edge_count++; - } - VTR_LOGV(verbose, "\tWill add %lu edges to OPINs at (x=%lu, y=%lu)\n", - edge_count - curr_edge_count, des_coord.x(), des_coord.y()); } } } @@ -756,7 +758,7 @@ static void add_rr_graph_clock_edges( } } /* Add edges between OPIN (internal driver) and clock routing tracks */ - add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, rr_graph_view, grids, layer, clk_ntwk, verbose); + add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, clk_rr_lookup, rr_graph_view, grids, layer, clk_ntwk, verbose); } /******************************************************************** From 7bcbd8a88be36b1fef8186465d74c1b8a3c5efad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 11:44:50 -0700 Subject: [PATCH 032/230] [core] code format --- .../src/base/clock_network.cpp | 43 +++++++++------- .../src/base/clock_network.h | 31 ++++++----- .../src/io/clock_network_xml_constants.h | 6 ++- .../src/io/read_xml_clock_network.cpp | 21 ++++---- .../src/io/write_xml_clock_network.cpp | 13 +++-- .../src/utils/clock_network_utils.cpp | 4 +- .../src/annotation/append_clock_rr_graph.cpp | 51 +++++++++++-------- .../src/base/openfpga_read_arch_template.h | 5 +- 8 files changed, 104 insertions(+), 70 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index b76631c5c..20e1f116c 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -32,8 +32,10 @@ ClockNetwork::clock_tree_range ClockNetwork::trees() const { return vtr::make_range(tree_ids_.begin(), tree_ids_.end()); } -ClockNetwork::clock_internal_driver_range ClockNetwork::internal_drivers() const { - return vtr::make_range(internal_driver_ids_.begin(), internal_driver_ids_.end()); +ClockNetwork::clock_internal_driver_range ClockNetwork::internal_drivers() + const { + return vtr::make_range(internal_driver_ids_.begin(), + internal_driver_ids_.end()); } std::vector ClockNetwork::levels( @@ -329,14 +331,16 @@ vtr::Point ClockNetwork::spine_switch_point( return spine_switch_coords_[spine_id][size_t(switch_point_id)]; } -std::vector ClockNetwork::spine_switch_point_internal_drivers( +std::vector +ClockNetwork::spine_switch_point_internal_drivers( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const { VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id)); return spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)]; } -std::string ClockNetwork::internal_driver_port(const ClockInternalDriverId& int_driver_id) const { +std::string ClockNetwork::internal_driver_port( + const ClockInternalDriverId& int_driver_id) const { VTR_ASSERT(valid_internal_driver_id(int_driver_id)); return internal_driver_ports_[int_driver_id]; } @@ -389,7 +393,8 @@ std::vector ClockNetwork::tree_flatten_taps( return flatten_taps; } -std::vector ClockNetwork::flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const { +std::vector ClockNetwork::flatten_internal_driver_port( + const ClockInternalDriverId& int_driver_id) const { std::vector flatten_taps; std::string tap_name = internal_driver_port(int_driver_id); StringToken tokenizer(tap_name); @@ -598,9 +603,9 @@ void ClockNetwork::set_spine_track_type(const ClockSpineId& spine_id, spine_track_types_[spine_id] = type; } -ClockSwitchPointId ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id, - const ClockSpineId& drive_spine_id, - const vtr::Point& coord) { +ClockSwitchPointId ClockNetwork::add_spine_switch_point( + const ClockSpineId& spine_id, const ClockSpineId& drive_spine_id, + const vtr::Point& coord) { VTR_ASSERT(valid_spine_id(spine_id)); VTR_ASSERT(valid_spine_id(drive_spine_id)); spine_switch_points_[spine_id].push_back(drive_spine_id); @@ -621,24 +626,27 @@ ClockSwitchPointId ClockNetwork::add_spine_switch_point(const ClockSpineId& spin return ClockSwitchPointId(spine_switch_points_[spine_id].size() - 1); } -ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver(const ClockSpineId& spine_id, - const ClockSwitchPointId& switch_point_id, - const std::string& int_driver_port) { +ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( + const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, + const std::string& int_driver_port) { VTR_ASSERT(valid_spine_id(spine_id)); VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id)); /* Find any existing id for the driver port */ for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { if (internal_driver_ports_[int_driver_id] == int_driver_port) { - spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back(int_driver_id); - return int_driver_id; + spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)] + .push_back(int_driver_id); + return int_driver_id; } } /* Reaching here, no existing id can be reused, create a new one */ - ClockInternalDriverId int_driver_id = ClockInternalDriverId(internal_driver_ids_.size()); + ClockInternalDriverId int_driver_id = + ClockInternalDriverId(internal_driver_ids_.size()); internal_driver_ids_.push_back(int_driver_id); internal_driver_ports_.push_back(int_driver_port); - spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back(int_driver_id); - return int_driver_id; + spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back( + int_driver_id); + return int_driver_id; } void ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, @@ -793,7 +801,8 @@ bool ClockNetwork::valid_tree_id(const ClockTreeId& tree_id) const { (tree_id == tree_ids_[tree_id]); } -bool ClockNetwork::valid_internal_driver_id(const ClockInternalDriverId& int_driver_id) const { +bool ClockNetwork::valid_internal_driver_id( + const ClockInternalDriverId& int_driver_id) const { return (size_t(int_driver_id) < internal_driver_ids_.size()) && (int_driver_id == internal_driver_ids_[int_driver_id]); } diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 6a972cb46..8884f5c55 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -42,10 +42,12 @@ class ClockNetwork { clock_tree_iterator; /* Create range */ typedef vtr::Range clock_tree_range; - typedef vtr::vector::const_iterator + typedef vtr::vector::const_iterator clock_internal_driver_iterator; /* Create range */ - typedef vtr::Range clock_internal_driver_range; + typedef vtr::Range + clock_internal_driver_range; public: /* Constructors */ ClockNetwork(); @@ -124,8 +126,10 @@ class ClockNetwork { std::vector spine_switch_point_internal_drivers( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const; - std::string internal_driver_port(const ClockInternalDriverId& int_driver_id) const; - std::vector flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const; + std::string internal_driver_port( + const ClockInternalDriverId& int_driver_id) const; + std::vector flatten_internal_driver_port( + const ClockInternalDriverId& int_driver_id) const; /* Return the original list of tap pins that is in storage; useful for parsers */ @@ -184,11 +188,11 @@ class ClockNetwork { void set_spine_track_type(const ClockSpineId& spine_id, const t_rr_type& type); ClockSwitchPointId add_spine_switch_point(const ClockSpineId& spine_id, - const ClockSpineId& drive_spine_id, - const vtr::Point& coord); - ClockInternalDriverId add_spine_switch_point_internal_driver(const ClockSpineId& spine_id, - const ClockSwitchPointId& switch_point_id, - const std::string& internal_driver_port); + const ClockSpineId& drive_spine_id, + const vtr::Point& coord); + ClockInternalDriverId add_spine_switch_point_internal_driver( + const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, + const std::string& internal_driver_port); void add_tree_tap(const ClockTreeId& tree_id, const std::string& pin_name); /* Build internal links between clock tree, spines etc. This is also an * validator to verify the correctness of the clock network. Must run before @@ -198,7 +202,8 @@ class ClockNetwork { public: /* Public invalidators/validators */ /* Show if the tree id is a valid for data queries */ bool valid_tree_id(const ClockTreeId& tree_id) const; - bool valid_internal_driver_id(const ClockInternalDriverId& int_driver_id) const; + bool valid_internal_driver_id( + const ClockInternalDriverId& int_driver_id) const; /* Show if the level id is a valid for a given tree */ bool valid_level_id(const ClockTreeId& tree_id, const ClockLevelId& lvl_id) const; @@ -260,13 +265,15 @@ class ClockNetwork { vtr::vector spine_track_types_; vtr::vector> spine_switch_points_; vtr::vector>> spine_switch_coords_; - vtr::vector>> spine_switch_internal_drivers_; + vtr::vector>> + spine_switch_internal_drivers_; vtr::vector spine_parents_; vtr::vector> spine_children_; vtr::vector spine_parent_trees_; /* Basic Information about internal drivers */ - vtr::vector internal_driver_ids_; + vtr::vector + internal_driver_ids_; vtr::vector internal_driver_ports_; /* Default routing resource */ diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index 9eab6bd8f..14b2f1204 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -22,8 +22,10 @@ constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_Y = "end_y"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_TYPE = "type"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_DIRECTION = "direction"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point"; -constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = "internal_driver"; -constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN = "tile_pin"; +constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = + "internal_driver"; +constexpr const char* + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN = "tile_pin"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_TAP = "tap"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X = "x"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y = "y"; diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index be73eb689..152b4ae35 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -61,17 +61,20 @@ static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps, *******************************************************************/ static void read_xml_clock_spine_switch_point_internal_driver( pugi::xml_node& xml_int_driver, const pugiutil::loc_data& loc_data, - ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) { + ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, + const ClockSwitchPointId& switch_point_id) { if (!clk_ntwk.valid_spine_id(spine_id)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_int_driver), "Invalid id of a clock spine!\n"); } std::string int_driver_port_name = - get_attribute(xml_int_driver, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, - loc_data) + get_attribute( + xml_int_driver, + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, loc_data) .as_string(); - clk_ntwk.add_spine_switch_point_internal_driver(spine_id, switch_point_id, int_driver_port_name); + clk_ntwk.add_spine_switch_point_internal_driver(spine_id, switch_point_id, + int_driver_port_name); } /******************************************************************** @@ -108,16 +111,16 @@ static void read_xml_clock_spine_switch_point( XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y, loc_data) .as_int(); - ClockSwitchPointId switch_point_id = clk_ntwk.add_spine_switch_point(spine_id, tap_spine_id, - vtr::Point(tap_x, tap_y)); + ClockSwitchPointId switch_point_id = clk_ntwk.add_spine_switch_point( + spine_id, tap_spine_id, vtr::Point(tap_x, tap_y)); - /* Add internal drivers if possible */ + /* Add internal drivers if possible */ for (pugi::xml_node xml_int_driver : xml_switch_point.children()) { /* Error out if the XML child has an invalid name! */ if (xml_int_driver.name() == std::string(XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME)) { - read_xml_clock_spine_switch_point_internal_driver(xml_int_driver, loc_data, clk_ntwk, - spine_id, switch_point_id); + read_xml_clock_spine_switch_point_internal_driver( + xml_int_driver, loc_data, clk_ntwk, spine_id, switch_point_id); } else { bad_tag(xml_int_driver, loc_data, xml_switch_point, {XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME}); diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index e107a4606..76d10fbe8 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -59,18 +59,23 @@ static int write_xml_clock_spine_switch_point( clk_ntwk.spine_switch_point(spine_id, switch_point_id); write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X, coord.x()); write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y, coord.y()); - + /* Optional: internal drivers */ - if (clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id).empty()) { + if (clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id) + .empty()) { fp << "/>" << "\n"; } else { fp << ">" << "\n"; - for (ClockInternalDriverId int_driver_id : clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id)) { + for (ClockInternalDriverId int_driver_id : + clk_ntwk.spine_switch_point_internal_drivers(spine_id, + switch_point_id)) { openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME; - write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, clk_ntwk.internal_driver_port(int_driver_id).c_str()); + write_xml_attribute( + fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, + clk_ntwk.internal_driver_port(int_driver_id).c_str()); fp << "/>" << "\n"; } diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp index 138ac4087..3d82f9c23 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp @@ -34,7 +34,7 @@ static int link_clock_network_rr_segments(ClockNetwork& clk_ntwk, *clock network *******************************************************************/ static int link_clock_network_tap_rr_switches(ClockNetwork& clk_ntwk, - const RRGraphView& rr_graph) { + const RRGraphView& rr_graph) { /* default tap switch id */ std::string default_tap_switch_name = clk_ntwk.default_tap_switch_name(); for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches(); @@ -57,7 +57,7 @@ static int link_clock_network_tap_rr_switches(ClockNetwork& clk_ntwk, *clock network *******************************************************************/ static int link_clock_network_driver_rr_switches(ClockNetwork& clk_ntwk, - const RRGraphView& rr_graph) { + const RRGraphView& rr_graph) { /* default driver switch id */ std::string default_driver_switch_name = clk_ntwk.default_driver_switch_name(); diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index ecfe5e874..38d06efc6 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -525,8 +525,8 @@ static void add_rr_graph_block_clock_edges( chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_driver_switch(), false); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_driver_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n", @@ -541,8 +541,8 @@ static void add_rr_graph_block_clock_edges( itree, ClockTreePinId(ipin))) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_tap_switch(), false); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_tap_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to IPINs\n", @@ -566,8 +566,7 @@ static void try_find_and_add_clock_opin2track_node( std::vector& opin_nodes, const DeviceGrid& grids, const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& grid_coord, const e_side& pin_side, - const ClockNetwork& clk_ntwk, - const ClockInternalDriverId& int_driver_id) { + const ClockNetwork& clk_ntwk, const ClockInternalDriverId& int_driver_id) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : @@ -611,11 +610,9 @@ static void try_find_and_add_clock_opin2track_node( *******************************************************************/ static std::vector find_clock_opin2track_node( const DeviceGrid& grids, const RRGraphView& rr_graph_view, - const size_t& layer, - const vtr::Point& sb_coord, + const size_t& layer, const vtr::Point& sb_coord, const ClockNetwork& clk_ntwk, - const std::vector& int_driver_ids -) { + const std::vector& int_driver_ids) { std::vector opin_nodes; /* Find opins from * - Grid[x][y+1] on right and bottom sides @@ -649,13 +646,14 @@ static std::vector find_clock_opin2track_node( /******************************************************************** * Add edges between OPIN of programmable blocks and clock routing tracks * Note that such edges only occur at the switching points of spines - * Different from add_rr_graph_block_clock_edges(), we follow the clock spines here - * By expanding on switching points, internal drivers will be added + * Different from add_rr_graph_block_clock_edges(), we follow the clock spines + *here By expanding on switching points, internal drivers will be added *******************************************************************/ -static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, +static int add_rr_graph_opin2clk_edges( + RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, - const DeviceGrid& grids, const size_t& layer, - const ClockNetwork& clk_ntwk, const bool& verbose) { + const DeviceGrid& grids, const size_t& layer, const ClockNetwork& clk_ntwk, + const bool& verbose) { size_t edge_count = 0; for (ClockTreeId clk_tree : clk_ntwk.trees()) { for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) { @@ -664,8 +662,11 @@ static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t& for (auto ipin : clk_ntwk.pins(clk_tree)) { for (ClockSwitchPointId switch_point_id : clk_ntwk.spine_switch_points(ispine)) { - if (clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty()) { - continue; /* We only focus on switching points containing internal drivers */ + if (clk_ntwk + .spine_switch_point_internal_drivers(ispine, switch_point_id) + .empty()) { + continue; /* We only focus on switching points containing internal + drivers */ } size_t curr_edge_count = edge_count; /* Get the rr node of destination spine */ @@ -680,12 +681,16 @@ static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t& /* Walk through each qualified OPIN, build edges */ vtr::Point src_coord = clk_ntwk.spine_switch_point(ispine, switch_point_id); - std::vector int_driver_ids = clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id); - for (RRNodeId src_node : find_clock_opin2track_node(grids, rr_graph_view, layer, src_coord, clk_ntwk, int_driver_ids)) { + std::vector int_driver_ids = + clk_ntwk.spine_switch_point_internal_drivers(ispine, + switch_point_id); + for (RRNodeId src_node : find_clock_opin2track_node( + grids, rr_graph_view, layer, src_coord, clk_ntwk, + int_driver_ids)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_driver_switch(), false); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_driver_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to OPINs at (x=%lu, y=%lu)\n", @@ -758,7 +763,9 @@ static void add_rr_graph_clock_edges( } } /* Add edges between OPIN (internal driver) and clock routing tracks */ - add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, clk_rr_lookup, rr_graph_view, grids, layer, clk_ntwk, verbose); + add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, + clk_rr_lookup, rr_graph_view, grids, layer, + clk_ntwk, verbose); } /******************************************************************** diff --git a/openfpga/src/base/openfpga_read_arch_template.h b/openfpga/src/base/openfpga_read_arch_template.h index 91e25a607..4ee895977 100644 --- a/openfpga/src/base/openfpga_read_arch_template.h +++ b/openfpga/src/base/openfpga_read_arch_template.h @@ -240,8 +240,9 @@ int read_openfpga_clock_arch_template(T& openfpga_context, const Command& cmd, VTR_LOG_ERROR("Link clock network failed!"); return CMD_EXEC_FATAL_ERROR; } - if (CMD_EXEC_SUCCESS != link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(), - g_vpr_ctx.device().rr_graph)) { + if (CMD_EXEC_SUCCESS != + link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(), + g_vpr_ctx.device().rr_graph)) { VTR_LOG_ERROR("Link clock network to routing architecture failed!"); return CMD_EXEC_FATAL_ERROR; } From 2cbb04b90d4e0be272cda002e79130acf0742b4b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 11:58:05 -0700 Subject: [PATCH 033/230] [test] add a new testcase to validate programmable clock network with internal drivers --- .../regression_test_scripts/basic_reg_test.sh | 1 + .../clk_arch_1clk_1rst_2layer_int_driver.xml | 40 ++++++++++++++ .../config/pin_constraints_reset.xml | 7 +++ .../config/pin_constraints_resetb.xml | 7 +++ .../config/repack_pin_constraints.xml | 4 ++ .../config/task.conf | 53 +++++++++++++++++++ 6 files changed, 112 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 0f2e1514e..20b2e3bf0 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -233,6 +233,7 @@ run-task basic_tests/clock_network/homo_1clock_2layer $@ run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ run-task basic_tests/clock_network/homo_2clock_2layer $@ run-task basic_tests/clock_network/homo_1clock_1_reset_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_internal_driver $@ echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; run-task basic_tests/verific_test $@ diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml new file mode 100644 index 000000000..78f156469 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml new file mode 100644 index 000000000..abcf209f6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..cdef2ad86 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf new file mode 100644 index 000000000..6bc568fb0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -0,0 +1,53 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From fbece49047c88a2ca0f64e71b626c8982c6e67b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 12:07:19 -0700 Subject: [PATCH 034/230] [core] fixed a bug where unexpected OPINs are added as internal drivers --- openfpga/src/annotation/append_clock_rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 38d06efc6..53cad0453 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -626,9 +626,9 @@ static std::vector find_clock_opin2track_node( grid_sides[0] = {RIGHT, BOTTOM}; grid_coords[1] = vtr::Point(sb_coord.x() + 1, sb_coord.y() + 1); grid_sides[1] = {LEFT, BOTTOM}; - grid_coords[2] = vtr::Point(sb_coord.x() + 1, sb_coord.y()); + grid_coords[2] = vtr::Point(sb_coord.x(), sb_coord.y()); grid_sides[2] = {RIGHT, TOP}; - grid_coords[3] = vtr::Point(sb_coord.x(), sb_coord.y()); + grid_coords[3] = vtr::Point(sb_coord.x() + 1, sb_coord.y()); grid_sides[3] = {LEFT, TOP}; for (size_t igrid = 0; igrid < 4; igrid++) { vtr::Point grid_coord = grid_coords[igrid]; From 66af73e91e837f83956d5240d29e57e763fb49b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 12:24:46 -0700 Subject: [PATCH 035/230] [lib] now accept reset and set in programmable clock network --- .../src/read_xml_tile_annotation.cpp | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp index 135e38361..c6ca09012 100644 --- a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp +++ b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp @@ -89,14 +89,6 @@ static void read_xml_tile_global_port_annotation( get_attribute(xml_tile, "is_clock", loc_data, pugiutil::ReqOpt::OPTIONAL) .as_bool(false)); - /* Get clock tree attributes if this is a clock */ - if (tile_annotation.global_port_is_clock(tile_global_port_id)) { - tile_annotation.set_global_port_clock_arch_tree_name( - tile_global_port_id, get_attribute(xml_tile, "clock_arch_tree_name", - loc_data, pugiutil::ReqOpt::OPTIONAL) - .as_string()); - } - /* Get is_set attributes */ tile_annotation.set_global_port_is_set( tile_global_port_id, @@ -109,6 +101,16 @@ static void read_xml_tile_global_port_annotation( get_attribute(xml_tile, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL) .as_bool(false)); + /* Get clock tree attributes if this is a clock, reset or set */ + if (tile_annotation.global_port_is_clock(tile_global_port_id) + || tile_annotation.global_port_is_reset(tile_global_port_id) + || tile_annotation.global_port_is_set(tile_global_port_id)) { + tile_annotation.set_global_port_clock_arch_tree_name( + tile_global_port_id, get_attribute(xml_tile, "clock_arch_tree_name", + loc_data, pugiutil::ReqOpt::OPTIONAL) + .as_string()); + } + /* Get default_value attributes */ tile_annotation.set_global_port_default_value( tile_global_port_id, From 4640e74e7e6e047d3f3f4eae7117d9ed8447a0ad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 12:25:16 -0700 Subject: [PATCH 036/230] [core] code format --- libs/libarchopenfpga/src/read_xml_tile_annotation.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp index c6ca09012..960f9352d 100644 --- a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp +++ b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp @@ -102,9 +102,9 @@ static void read_xml_tile_global_port_annotation( .as_bool(false)); /* Get clock tree attributes if this is a clock, reset or set */ - if (tile_annotation.global_port_is_clock(tile_global_port_id) - || tile_annotation.global_port_is_reset(tile_global_port_id) - || tile_annotation.global_port_is_set(tile_global_port_id)) { + if (tile_annotation.global_port_is_clock(tile_global_port_id) || + tile_annotation.global_port_is_reset(tile_global_port_id) || + tile_annotation.global_port_is_set(tile_global_port_id)) { tile_annotation.set_global_port_clock_arch_tree_name( tile_global_port_id, get_attribute(xml_tile, "clock_arch_tree_name", loc_data, pugiutil::ReqOpt::OPTIONAL) From c99178f350b94e931c6883e3e0dc395d23132b54 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 12:34:52 -0700 Subject: [PATCH 037/230] [test] fixed a bug on pin locations --- openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index 19447dd7e..ad21e6f59 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -107,7 +107,12 @@ - + + + + clb.reset clb.clk clb.O[4:7] clb.I[6:11] + clb.O[0:3] clb.I[0:5] + From ec1ad94d4aeee285380ef32fc5f0c149f0ac9b51 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 13:06:47 -0700 Subject: [PATCH 038/230] [doc] add syntax about internal drivers --- .../manual/file_formats/clock_network.rst | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index fe6d89b79..d998c63a9 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -25,7 +25,9 @@ Using the clock network description language, users can define multiple clock ne - + + + @@ -175,6 +177,33 @@ For example, where clock spine ``spine0`` will drive another clock spine ``spine1`` at (1, 1). +For each switch point, outputs of neighbouring programmable blocks are allowed to drive the spine at next level, through syntax ``internal_driver``. + +.. option:: tile_pin="" + + Define the pin of a programmable block as an internal driver to a clock network. The pin must be a valid pin defined in the VPR architecture description file. + +For example, + +.. code-block:: xml + + + + + + + +where the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file: + +.. code-block:: xml + + + + + + + + .. _file_formats_clock_network_tap_point: Tap Point Settings From c07e35136b67c7d09feddd4f965c6271e96e3e52 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 25 Jun 2024 16:46:33 -0700 Subject: [PATCH 039/230] [ci] now use download-artifact v4 --- .github/workflows/build.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index b324c8c89..e97ead79f 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -404,7 +404,7 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v4 - name: Download a built artifacts - uses: actions/download-artifact@v2 + uses: actions/download-artifact@v4 with: name: openfpga - name: Set up QEMU @@ -457,7 +457,7 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v4 - name: Download a built artifacts - uses: actions/download-artifact@v2 + uses: actions/download-artifact@v4 with: name: openfpga - name: chmod From 3ebaaa700e7a99a4d51894f2bc7ece5b64ca35b9 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 26 Jun 2024 01:31:49 +0000 Subject: [PATCH 040/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 91f6656fa..c4ceed717 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2276 +1.2.2282 From 381a8cb53548e5c1402d46606d6cf3c22aa1050d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 15:41:56 -0700 Subject: [PATCH 041/230] [lib] clock tap syntax are reworked. Support region, single, all and from/to ports --- .../src/base/clock_network.cpp | 113 +++++++++++++++++- .../src/base/clock_network.h | 52 +++++++- .../src/base/clock_network_fwd.h | 2 + .../src/io/clock_network_xml_constants.h | 15 ++- .../src/io/read_xml_clock_network.cpp | 101 ++++++++++++++-- .../src/io/write_xml_clock_network.cpp | 63 ++++++++-- 6 files changed, 314 insertions(+), 32 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 20e1f116c..69fbed21b 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -20,6 +20,8 @@ ClockNetwork::ClockNetwork() { default_segment_id_ = RRSegmentId::INVALID(); default_tap_switch_id_ = RRSwitchId::INVALID(); default_driver_switch_id_ = RRSwitchId::INVALID(); + /* Set a default invalid bounding box */ + empty_tap_bb_ = vtr::Rect(1, 0, 1, 0); is_dirty_ = true; } @@ -345,17 +347,67 @@ std::string ClockNetwork::internal_driver_port( return internal_driver_ports_[int_driver_id]; } -std::vector ClockNetwork::tree_taps( +std::vector ClockNetwork::tree_taps( const ClockTreeId& tree_id) const { VTR_ASSERT(valid_tree_id(tree_id)); return tree_taps_[tree_id]; } -std::vector ClockNetwork::tree_flatten_taps( +std::string ClockNetwork::tap_from_port(const ClockTapId& tap_id) const { + VTR_ASSERT(valid_tap_id(tap_id)); + return tap_from_ports_[tap_id]; +} + +std::string ClockNetwork::tap_to_port(const ClockTapId& tap_id) const { + VTR_ASSERT(valid_tap_id(tap_id)); + return tap_to_ports_[tap_id]; +} + +ClockNetwork::e_tap_type ClockNetwork::tap_type(const ClockTapId& tap_id) const { + VTR_ASSERT(valid_tap_id(tap_id)); + /* If not a region, it is a default type covering all the coordinates*/ + if (tap_bbs_[tap_id] == empty_tap_bb_) { + return ClockNetwork::e_tap_type::ALL; + } + /* Now check if this a single point */ + if (tap_bbs_[tap_id].height() == 0 && tap_bbs_[tap_id].width() == 0) { + return ClockNetwork::e_tap_type::SINGLE; + } + return ClockNetwork::e_tap_type::REGION; +} + +size_t ClockNetwork::tap_x(const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE); + return tap_bbs_[tap_id].xmin(); +} + +size_t ClockNetwork::tap_y(const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE); + return tap_bbs_[tap_id].ymin(); +} + +vtr::Rect ClockNetwork::tap_bounding_box(const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION); + return tap_bbs_[tap_id]; +} + +size_t ClockNetwork::tap_step_x(const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION); + return tap_bb_steps_[tap_id].x(); +} + +size_t ClockNetwork::tap_step_y(const ClockTapId& tap_id) const { + VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION); + return tap_bb_steps_[tap_id].y(); +} + +std::vector ClockNetwork::tree_flatten_tap_to_ports( const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const { VTR_ASSERT(valid_tree_id(tree_id)); std::vector flatten_taps; - for (const std::string& tap_name : tree_taps_[tree_id]) { + for (ClockTapId tap_id : tree_taps_[tree_id]) { + VTR_ASSERT(valid_tap_id(tap_id)); + std::string tap_name = tap_to_ports_[tap_id]; StringToken tokenizer(tap_name); std::vector pin_tokens = tokenizer.split("."); if (pin_tokens.size() != 2) { @@ -649,10 +701,53 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( return int_driver_id; } -void ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, - const std::string& pin_name) { +ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, + const std::string& from_port, + const std::string& to_port, + const ) { VTR_ASSERT(valid_tree_id(tree_id)); - tree_taps_[tree_id].push_back(pin_name); + /* TODO: Consider find existing tap template and avoid duplication in storage */ + ClockTapId tap_id = ClockTapId(tap_ids_.size()); + tap_ids_.push_back(tap_id); + tap_from_ports_.push_back(from_port); + tap_to_ports_.push_back(to_port); + tap_bbs_.emplace_back(empty_tap_bb_); + tap_bb_steps_.emplace_back(vtr::Point(1, 1)); + tree_taps_[tree_id].push_back(tap_id); + return tap_id; +} + +bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect& bb) { + VTR_ASSERT(valid_tap_id(tap_id)); + /* Check the bounding box, ensure it must be valid */ + if (bb.height() < 0 || bb.width() < 0) { + VTR_LOG_ERROR("Invalid bounding box (xlow=%lu, ylow=%lu) -> (xhigh=%lu, yhigh=%lu)! Must follow: xlow <= xhigh, ylow <= yhigh!\n", bb.xmin(), bb.ymin(), bb.xmax(), bb.ymax()); + return false; + } + tap_bbs_[tap_id] = bb; + return true; +} + +bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id, const size_t step) { + VTR_ASSERT(valid_tap_id(tap_id)); + /* Must be a valid step >= 1 */ + if (step == 0) { + VTR_LOG_ERROR("Invalid x-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step); + return false; + } + tap_bbs_[tap_id].set_x(step); + return true; +} + +bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id, const size_t step) { + VTR_ASSERT(valid_tap_id(tap_id)); + /* Must be a valid step >= 1 */ + if (step == 0) { + VTR_LOG_ERROR("Invalid y-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step); + return false; + } + tap_bbs_[tap_id].set_y(step); + return true; } bool ClockNetwork::link() { @@ -807,6 +902,12 @@ bool ClockNetwork::valid_internal_driver_id( (int_driver_id == internal_driver_ids_[int_driver_id]); } +bool ClockNetwork::valid_tap_id( + const ClockTapId& tap_id) const { + return (size_t(tap_id) < tap_ids_.size()) && + (tap_id == tap_ids_[tap_id]); +} + bool ClockNetwork::valid_level_id(const ClockTreeId& tree_id, const ClockLevelId& lvl_id) const { return valid_tree_id(tree_id) && (size_t(lvl_id) < tree_depth(tree_id)); diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 8884f5c55..f440c397c 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -48,6 +48,13 @@ class ClockNetwork { /* Create range */ typedef vtr::Range clock_internal_driver_range; + /* Type of tap points */ + enum class : unsigned char { + ALL = 0, + SINGLE, + REGION, + NUM_TYPES + }; public: /* Constructors */ ClockNetwork(); @@ -133,12 +140,30 @@ class ClockNetwork { /* Return the original list of tap pins that is in storage; useful for parsers */ - std::vector tree_taps(const ClockTreeId& tree_id) const; + std::vector tree_taps(const ClockTreeId& tree_id) const; + /* Return the source ports for a given tap */ + std::string tap_from_port(const ClockTapId& tap_id) const; + /* Return the destination ports for a given tap */ + std::string tap_to_port(const ClockTapId& tap_id) const; + /* Find the type of tap point: + * all -> all coordinates in efpga are required to tap + * single -> only 1 coordinate is required to tap + * region -> coordinates in a region required to tap. Steps in region may be required + */ + e_tap_type tap_type(const ClockTapId& tap_id) const; + /* Require the type of single */ + size_t tap_x(const ClockTapId& tap_id) const; + size_t tap_y(const ClockTapId& tap_id) const; + /* Require the type of region */ + vtr::Rect tap_bounding_box(const ClockTapId& tap_id) const; + /* Steps are only available when type is region */ + size_t tap_step_x(const ClockTapId& tap_id) const; + size_t tap_step_y(const ClockTapId& tap_id) const; /* Return the list of flatten tap pins. For example: clb[0:1].clk[2:2] is * flatten to { clb[0].clk[2], clb[1].clk[2] } Useful to build clock routing * resource graph Note that the clk_pin_id limits only 1 clock to be accessed */ - std::vector tree_flatten_taps( + std::vector tree_flatten_tap_to_ports( const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const; /* Find a spine with a given name, if not found, return an valid id, otherwise * return an invalid one */ @@ -193,7 +218,10 @@ class ClockNetwork { ClockInternalDriverId add_spine_switch_point_internal_driver( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, const std::string& internal_driver_port); - void add_tree_tap(const ClockTreeId& tree_id, const std::string& pin_name); + ClockTapId add_tree_tap(const ClockTreeId& tree_id, const std::string& from_port, const std::string& to_port); + bool set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect& bb); + bool set_tap_step_x(const ClockTapId& tap_id, const size_t& step); + bool set_tap_step_y(const ClockTapId& tap_id, const size_t& step); /* Build internal links between clock tree, spines etc. This is also an * validator to verify the correctness of the clock network. Must run before * using the data! */ @@ -202,8 +230,6 @@ class ClockNetwork { public: /* Public invalidators/validators */ /* Show if the tree id is a valid for data queries */ bool valid_tree_id(const ClockTreeId& tree_id) const; - bool valid_internal_driver_id( - const ClockInternalDriverId& int_driver_id) const; /* Show if the level id is a valid for a given tree */ bool valid_level_id(const ClockTreeId& tree_id, const ClockLevelId& lvl_id) const; @@ -233,6 +259,11 @@ class ClockNetwork { /* Ensure tree data is clean. All the spines are valid, and switch points are * valid */ bool validate_tree() const; + /* Show if the internal driver id is a valid for data queries */ + bool valid_internal_driver_id( + const ClockInternalDriverId& int_driver_id) const; + /* Show if the tap id is a valid for data queries */ + bool valid_tap_id(const ClockTapId& tap_id) const; private: /* Private mutators */ /* Build internal links between spines under a given tree */ @@ -253,7 +284,7 @@ class ClockNetwork { vtr::vector tree_widths_; vtr::vector tree_depths_; vtr::vector> tree_top_spines_; - vtr::vector> tree_taps_; + vtr::vector tree_taps_; /* Basic information of each spine */ vtr::vector spine_ids_; @@ -275,6 +306,12 @@ class ClockNetwork { vtr::vector internal_driver_ids_; vtr::vector internal_driver_ports_; + /* Basic information about tap */ + vtr::vector tap_ids_; + vtr::vector tap_from_ports_; + vtr::vector tap_to_ports_; + vtr::vector> tap_bbs_; /* Bounding box for tap points, (xlow, ylow) -> (xhigh, yhigh) */ + vtr::vector> tap_bb_steps_; /* x() -> x-direction step, y() -> y-direction step */ /* Default routing resource */ std::string default_segment_name_; /* The routing segment representing the @@ -291,6 +328,9 @@ class ClockNetwork { std::map tree_name2id_map_; std::map spine_name2id_map_; + /* Constants */ + vtr::Rect empty_tap_bb_; + /* Flags */ mutable bool is_dirty_; }; diff --git a/libs/libclkarchopenfpga/src/base/clock_network_fwd.h b/libs/libclkarchopenfpga/src/base/clock_network_fwd.h index e9602d384..dc329d04b 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network_fwd.h +++ b/libs/libclkarchopenfpga/src/base/clock_network_fwd.h @@ -20,6 +20,7 @@ struct clock_tree_pin_id_tag; struct clock_spine_id_tag; struct clock_switch_point_id_tag; struct clock_internal_driver_id_tag; +struct clock_tap_id_tag; typedef vtr::StrongId ClockLevelId; typedef vtr::StrongId ClockTreeId; @@ -27,6 +28,7 @@ typedef vtr::StrongId ClockTreePinId; typedef vtr::StrongId ClockSpineId; typedef vtr::StrongId ClockSwitchPointId; typedef vtr::StrongId ClockInternalDriverId; +typedef vtr::StrongId ClockTapId; /* Short declaration of class */ class ClockNetwork; diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index 14b2f1204..cfa5c306d 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -30,7 +30,18 @@ constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_TAP = "tap"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X = "x"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y = "y"; constexpr const char* XML_CLOCK_TREE_TAPS_NODE_NAME = "taps"; -constexpr const char* XML_CLOCK_TREE_TAP_NODE_NAME = "tap"; -constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN = "tile_pin"; +constexpr const char* XML_CLOCK_TREE_TAP_ALL_NODE_NAME = "all"; +constexpr const char* XML_CLOCK_TREE_TAP_REGION_NODE_NAME = "region"; +constexpr const char* XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME = "single"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN = "from_pin"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN = "to_pin"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_X = "x"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_Y = "y"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX = "start_x"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY = "start_y"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX = "end_x"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY = "end_y"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATX = "repeat_x"; +constexpr const char* XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATY = "repeat_y"; #endif diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 152b4ae35..2c8e8fdfe 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -25,10 +25,10 @@ namespace openfpga { // Begin namespace openfpga /******************************************************************** - * Parse XML codes of a to an object of ClockNetwork + * Parse XML codes of a to an object of ClockNetwork *******************************************************************/ -static void read_xml_clock_tree_tap(pugi::xml_node& xml_tap, - const pugiutil::loc_data& loc_data, +static void read_xml_clock_tree_tap_type_all(pugi::xml_node& xml_tap, + const pugiutil::loc_data& loc_data, ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) { if (!clk_ntwk.valid_tree_id(tree_id)) { @@ -36,10 +36,89 @@ static void read_xml_clock_tree_tap(pugi::xml_node& xml_tap, "Invalid id of a clock tree!\n"); } - std::string tile_pin_name = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN, loc_data) + std::string from_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, loc_data) .as_string(); - clk_ntwk.add_tree_tap(tree_id, tile_pin_name); + std::string to_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) + .as_string(); + clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); +} + +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_tree_tap_type_single(pugi::xml_node& xml_tap, + const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, + const ClockTreeId& tree_id) { + if (!clk_ntwk.valid_tree_id(tree_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap), + "Invalid id of a clock tree!\n"); + } + + std::string from_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, loc_data) + .as_string(); + std::string to_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) + .as_string(); + ClockTapId tap_id = clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + + /* Single tap only require a coordinate */ + size_t tap_x = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, loc_data, pugi::ReqOpt::REQUIRED) + .as_int(); + size_t tap_y = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, loc_data, pugi::ReqOpt::REQUIRED) + .as_int(); + clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect(tap_x, tap_y, tap_x, tap_y)); +} + +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_tree_tap_type_region(pugi::xml_node& xml_tap, + const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, + const ClockTreeId& tree_id) { + if (!clk_ntwk.valid_tree_id(tree_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap), + "Invalid id of a clock tree!\n"); + } + + std::string from_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, loc_data) + .as_string(); + std::string to_pin_name = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) + .as_string(); + ClockTapId tap_id = clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + + /* Region require a bounding box */ + size_t tap_start_x = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data, pugi::ReqOpt::REQUIRED) + .as_int(); + size_t tap_start_y = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data, pugi::ReqOpt::REQUIRED) + .as_int(); + size_t tap_end_x = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, loc_data, pugi::ReqOpt::REQUIRED) + .as_int(); + size_t tap_end_y = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, loc_data, pugi::ReqOpt::REQUIRED) + .as_int(); + clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect(tap_start_x, tap_start_y, tap_end_x, tap_end_y)); + + /* Default step is all 1 */ + size_t tap_step_x = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATX, loc_data) + .as_int(1); + size_t tap_step_y = + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATY, loc_data) + .as_int(1); + clk_ntwk.set_tap_step_x(tap_id, tap_step_x); + clk_ntwk.set_tap_step_y(tap_id, tap_step_y); } static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps, @@ -48,10 +127,14 @@ static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps, const ClockTreeId& tree_id) { for (pugi::xml_node xml_tap : xml_taps.children()) { /* Error out if the XML child has an invalid name! */ - if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_NODE_NAME)) { - read_xml_clock_tree_tap(xml_tap, loc_data, clk_ntwk, tree_id); + if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_ALL_NODE_NAME)) { + read_xml_clock_tree_tap_type_all(xml_tap, loc_data, clk_ntwk, tree_id); + } else if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_REGION_NODE_NAME)) { + read_xml_clock_tree_tap_type_region(xml_tap, loc_data, clk_ntwk, tree_id); + } else if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME)) { + read_xml_clock_tree_tap_type_single(xml_tap, loc_data, clk_ntwk, tree_id); } else { - bad_tag(xml_taps, loc_data, xml_tap, {XML_CLOCK_TREE_TAP_NODE_NAME}); + bad_tag(xml_taps, loc_data, xml_tap, {XML_CLOCK_TREE_TAP_ALL_NODE_NAME, XML_CLOCK_TREE_TAP_REGION_NODE_NAME, XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME}); } } } diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 76d10fbe8..addb745ed 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -28,15 +28,60 @@ static int write_xml_clock_tree_taps(std::fstream& fp, const ClockTreeId& tree_id) { openfpga::write_tab_to_file(fp, 3); fp << "<" << XML_CLOCK_TREE_TAPS_NODE_NAME << ">\n"; - for (const std::string& tile_pin_name : clk_ntwk.tree_taps(tree_id)) { - openfpga::write_tab_to_file(fp, 4); - fp << "<" << XML_CLOCK_TREE_TAP_NODE_NAME << ""; - - write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN, - tile_pin_name.c_str()); - fp << "/>" - << "\n"; - } + /* Depends on the type */ + for (ClockTapId tap_id : clk_ntwk.tree_taps(tree_id)) { + switch clk_ntwk.tap_type(tap_id): { + case ClockNetwork::e_tap_type::ALL: { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_TREE_TAP_ALL_NODE_NAME << ""; + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, + clk_ntwk.tap_to_port(tap_id).c_str()); + fp << "/>" + << "\n"; + } + case ClockNetwork::e_tap_type::SINGLE: { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, + clk_ntwk.tap_to_port(tap_id).c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, + clk_ntwk.tap_x(tap_id)); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, + clk_ntwk.tap_y(tap_id)); + fp << "/>" + << "\n"; + } + case ClockNetwork::e_tap_type::REGION: { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, + clk_ntwk.tap_to_port(tap_id).c_str()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, + clk_ntwk.tap_bounding_box(tap_id).xmin()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, + clk_ntwk.tap_bounding_box(tap_id).ymin()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, + clk_ntwk.tap_bounding_box(tap_id).xmax()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, + clk_ntwk.tap_bounding_box(tap_id).ymax()); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATX, + clk_ntwk.tap_step_x(tap_id)); + write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_REPEATY, + clk_ntwk.tap_step_y(tap_id)); + fp << "/>" + << "\n"; + } + default: { + VTR_LOG_ERROR("Invalid type of tap point!\n"); + return 1; + } + } openfpga::write_tab_to_file(fp, 3); fp << "\n"; From 3b25e427205d741dc4e3927555d945b5f5c00014 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 15:51:00 -0700 Subject: [PATCH 042/230] [lib] syntax --- .../libclkarchopenfpga/src/base/clock_network.cpp | 15 +++++++-------- libs/libclkarchopenfpga/src/base/clock_network.h | 4 ++-- .../src/io/read_xml_clock_network.cpp | 12 ++++++------ .../src/io/write_xml_clock_network.cpp | 6 +++++- 4 files changed, 20 insertions(+), 17 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 69fbed21b..6abb021d8 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -703,8 +703,7 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, const std::string& from_port, - const std::string& to_port, - const ) { + const std::string& to_port) { VTR_ASSERT(valid_tree_id(tree_id)); /* TODO: Consider find existing tap template and avoid duplication in storage */ ClockTapId tap_id = ClockTapId(tap_ids_.size()); @@ -712,7 +711,7 @@ ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, tap_from_ports_.push_back(from_port); tap_to_ports_.push_back(to_port); tap_bbs_.emplace_back(empty_tap_bb_); - tap_bb_steps_.emplace_back(vtr::Point(1, 1)); + tap_bb_steps_.emplace_back(vtr::Point(0, 0)); tree_taps_[tree_id].push_back(tap_id); return tap_id; } @@ -720,7 +719,7 @@ ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect& bb) { VTR_ASSERT(valid_tap_id(tap_id)); /* Check the bounding box, ensure it must be valid */ - if (bb.height() < 0 || bb.width() < 0) { + if (bb.xmax() < bb.xmin() || bb.ymax() < bb.ymin()) { VTR_LOG_ERROR("Invalid bounding box (xlow=%lu, ylow=%lu) -> (xhigh=%lu, yhigh=%lu)! Must follow: xlow <= xhigh, ylow <= yhigh!\n", bb.xmin(), bb.ymin(), bb.xmax(), bb.ymax()); return false; } @@ -728,25 +727,25 @@ bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rec return true; } -bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id, const size_t step) { +bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id, const size_t& step) { VTR_ASSERT(valid_tap_id(tap_id)); /* Must be a valid step >= 1 */ if (step == 0) { VTR_LOG_ERROR("Invalid x-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step); return false; } - tap_bbs_[tap_id].set_x(step); + tap_bb_steps_[tap_id].set_x(step); return true; } -bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id, const size_t step) { +bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id, const size_t& step) { VTR_ASSERT(valid_tap_id(tap_id)); /* Must be a valid step >= 1 */ if (step == 0) { VTR_LOG_ERROR("Invalid y-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step); return false; } - tap_bbs_[tap_id].set_y(step); + tap_bb_steps_[tap_id].set_y(step); return true; } diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index f440c397c..e5236ab10 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -49,7 +49,7 @@ class ClockNetwork { typedef vtr::Range clock_internal_driver_range; /* Type of tap points */ - enum class : unsigned char { + enum class e_tap_type : unsigned char { ALL = 0, SINGLE, REGION, @@ -284,7 +284,7 @@ class ClockNetwork { vtr::vector tree_widths_; vtr::vector tree_depths_; vtr::vector> tree_top_spines_; - vtr::vector tree_taps_; + vtr::vector> tree_taps_; /* Basic information of each spine */ vtr::vector spine_ids_; diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 2c8e8fdfe..fe90cd7f0 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -67,10 +67,10 @@ static void read_xml_clock_tree_tap_type_single(pugi::xml_node& xml_tap, /* Single tap only require a coordinate */ size_t tap_x = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, loc_data, pugi::ReqOpt::REQUIRED) + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, loc_data, pugiutil::ReqOpt::REQUIRED) .as_int(); size_t tap_y = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, loc_data, pugi::ReqOpt::REQUIRED) + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, loc_data, pugiutil::ReqOpt::REQUIRED) .as_int(); clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect(tap_x, tap_y, tap_x, tap_y)); } @@ -97,16 +97,16 @@ static void read_xml_clock_tree_tap_type_region(pugi::xml_node& xml_tap, /* Region require a bounding box */ size_t tap_start_x = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data, pugi::ReqOpt::REQUIRED) + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data, pugiutil::ReqOpt::REQUIRED) .as_int(); size_t tap_start_y = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data, pugi::ReqOpt::REQUIRED) + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data, pugiutil::ReqOpt::REQUIRED) .as_int(); size_t tap_end_x = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, loc_data, pugi::ReqOpt::REQUIRED) + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, loc_data, pugiutil::ReqOpt::REQUIRED) .as_int(); size_t tap_end_y = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, loc_data, pugi::ReqOpt::REQUIRED) + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, loc_data, pugiutil::ReqOpt::REQUIRED) .as_int(); clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect(tap_start_x, tap_start_y, tap_end_x, tap_end_y)); diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index addb745ed..cdcc12ecf 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -30,7 +30,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, fp << "<" << XML_CLOCK_TREE_TAPS_NODE_NAME << ">\n"; /* Depends on the type */ for (ClockTapId tap_id : clk_ntwk.tree_taps(tree_id)) { - switch clk_ntwk.tap_type(tap_id): { + switch (clk_ntwk.tap_type(tap_id)) { case ClockNetwork::e_tap_type::ALL: { openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_ALL_NODE_NAME << ""; @@ -40,6 +40,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, clk_ntwk.tap_to_port(tap_id).c_str()); fp << "/>" << "\n"; + break; } case ClockNetwork::e_tap_type::SINGLE: { openfpga::write_tab_to_file(fp, 4); @@ -54,6 +55,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, clk_ntwk.tap_y(tap_id)); fp << "/>" << "\n"; + break; } case ClockNetwork::e_tap_type::REGION: { openfpga::write_tab_to_file(fp, 4); @@ -76,12 +78,14 @@ static int write_xml_clock_tree_taps(std::fstream& fp, clk_ntwk.tap_step_y(tap_id)); fp << "/>" << "\n"; + break; } default: { VTR_LOG_ERROR("Invalid type of tap point!\n"); return 1; } } + } openfpga::write_tab_to_file(fp, 3); fp << "\n"; From 3efa97b84e34d3de6d979f65df9a953f6dd3a59d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 17:40:11 -0700 Subject: [PATCH 043/230] [core] support coordinate on clock taps --- .../src/base/clock_network.cpp | 58 ++++++++++++++++++- .../src/base/clock_network.h | 4 +- .../src/annotation/append_clock_rr_graph.cpp | 2 +- 3 files changed, 61 insertions(+), 3 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 6abb021d8..488deab6e 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -401,12 +401,68 @@ size_t ClockNetwork::tap_step_y(const ClockTapId& tap_id) const { return tap_bb_steps_[tap_id].y(); } +bool ClockNetwork::valid_tap_coord_in_bb(const ClockTapId& tap_id, const vtr::Point& tap_coord) const { + VTR_ASSERT(valid_tap_id(tap_id)); + if (tap_type(tap_id) == ClockNetwork::e_tap_type::ALL) { + return true; + } + if (tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE && tap_bbs_[tap_id].strictly_contains(tap_coord)) { + return true; + } + if (tap_type(tap_id) == ClockNetwork::e_tap_type::REGION && tap_bbs_[tap_id].strictly_contains(tap_coord)) { + /* Check if steps are considered, coords still matches */ + bool x_in_bb = false; + for (size_t ix = tap_bbs_[tap_id].xmin(); ix < tap_bbs_[tap_id].xmax(); ix = ix + tap_bb_steps_[tap_id].x()) { + if (tap_coord.x() == ix) { + x_in_bb = true; + break; + } + } + /* Early exit */ + if (!x_in_bb) { + return false; + } + bool y_in_bb = false; + for (size_t iy = tap_bbs_[tap_id].ymin(); iy < tap_bbs_[tap_id].ymax(); iy = iy + tap_bb_steps_[tap_id].y()) { + if (tap_coord.y() == iy) { + y_in_bb = true; + break; + } + } + if (y_in_bb && x_in_bb) { + return true; + } + } + return false; +} + std::vector ClockNetwork::tree_flatten_tap_to_ports( - const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const { + const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, const vtr::Point& tap_coord) const { VTR_ASSERT(valid_tree_id(tree_id)); std::vector flatten_taps; for (ClockTapId tap_id : tree_taps_[tree_id]) { VTR_ASSERT(valid_tap_id(tap_id)); + /* Filter out unmatched from ports. Expect [clk_pin_id:clk_pin_id] */ + std::string tap_from_port_name = tap_from_ports_[tap_id]; + PortParser from_port_parser(tap_from_port_name); + BasicPort from_port = from_port_parser.port(); + if (!from_port.is_valid()) { + VTR_LOG_ERROR("Invalid from port name '%s' whose index is not valid\n", + tap_from_port_name.c_str()); + exit(1); + } + if (from_port.get_width() != 1) { + VTR_LOG_ERROR("Invalid from port name '%s' whose width is not 1\n", + tap_from_port_name.c_str()); + exit(1); + } + if (from_port.get_lsb() != size_t(clk_pin_id)) { + continue; + } + /* Filter out unmatched coordinates */ + if (!valid_tap_coord_in_bb(tap_id, tap_coord)) { + continue; + } std::string tap_name = tap_to_ports_[tap_id]; StringToken tokenizer(tap_name); std::vector pin_tokens = tokenizer.split("."); diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index e5236ab10..57ed39cb9 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -164,7 +164,7 @@ class ClockNetwork { * resource graph Note that the clk_pin_id limits only 1 clock to be accessed */ std::vector tree_flatten_tap_to_ports( - const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const; + const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, const vtr::Point& tap_coord) const; /* Find a spine with a given name, if not found, return an valid id, otherwise * return an invalid one */ ClockSpineId find_spine(const std::string& name) const; @@ -264,6 +264,8 @@ class ClockNetwork { const ClockInternalDriverId& int_driver_id) const; /* Show if the tap id is a valid for data queries */ bool valid_tap_id(const ClockTapId& tap_id) const; + /* Check if a given coordinate matches the requirements for a tap point */ + bool valid_tap_coord_in_bb(const ClockTapId& tap_id, const vtr::Point& tap_coord) const; private: /* Private mutators */ /* Build internal links between spines under a given tree */ diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 53cad0453..d5f325ca6 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -400,7 +400,7 @@ static void try_find_and_add_clock_track2ipin_node( t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : - clk_ntwk.tree_flatten_taps(clk_tree, clk_pin)) { + clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) { /* tap pin name could be 'io[5:5].a2f[0]' */ int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name); if (grid_pin_idx == grid_type->num_pins) { From 576a861b8d04106389eedfbf8551a966a3a77fab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 17:54:31 -0700 Subject: [PATCH 044/230] [core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks --- openfpga/src/annotation/route_clock_rr_graph.cpp | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index d669304c0..1fa47b836 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -94,6 +94,10 @@ static int route_clock_tree_rr_graph( VTR_LOGV(verbose, "Routing spine '%s'...\n", clk_ntwk.spine_name(ispine).c_str()); for (auto ipin : clk_ntwk.pins(clk_tree)) { + /* Do not route unused clock spines */ + if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + continue; + } /* Route the spine from starting point to ending point */ std::vector> spine_coords = clk_ntwk.spine_coordinates(ispine); @@ -165,6 +169,17 @@ static int route_clock_tree_rr_graph( for (RREdgeId edge : rr_graph.edge_range(src_node)) { RRNodeId des_node = rr_graph.edge_sink_node(edge); if (rr_graph.node_type(des_node) == IPIN) { + /* Check if the IPIN is mapped, if not, do not connect */ + /* if the IPIN is mapped, only connect when net mapping is expected */ + if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + continue; + } + if (!vpr_routing_annotation.rr_node_net(des_node)) { + continue; + } + if (vpr_routing_annotation.rr_node_net(des_node) != tree2clk_pin_map.at(ipin)) { + continue; + } VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, From 59404e5487ad0d76e299436e3c017ff5a05679d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 17:55:23 -0700 Subject: [PATCH 045/230] [core] add verbose output --- openfpga/src/annotation/route_clock_rr_graph.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 1fa47b836..6e237f482 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -96,6 +96,8 @@ static int route_clock_tree_rr_graph( for (auto ipin : clk_ntwk.pins(clk_tree)) { /* Do not route unused clock spines */ if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + VTR_LOGV(verbose, "Skip routing backbone of unused spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); continue; } /* Route the spine from starting point to ending point */ From 59be95b22751a224c85ab85592f942d94bf07c05 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 17:58:26 -0700 Subject: [PATCH 046/230] [core] code format --- .../src/base/clock_network.cpp | 79 ++++++++++++------- .../src/base/clock_network.h | 39 ++++----- .../src/io/read_xml_clock_network.cpp | 71 +++++++++-------- .../src/annotation/route_clock_rr_graph.cpp | 8 +- 4 files changed, 115 insertions(+), 82 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 488deab6e..70fd840f6 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -363,7 +363,8 @@ std::string ClockNetwork::tap_to_port(const ClockTapId& tap_id) const { return tap_to_ports_[tap_id]; } -ClockNetwork::e_tap_type ClockNetwork::tap_type(const ClockTapId& tap_id) const { +ClockNetwork::e_tap_type ClockNetwork::tap_type( + const ClockTapId& tap_id) const { VTR_ASSERT(valid_tap_id(tap_id)); /* If not a region, it is a default type covering all the coordinates*/ if (tap_bbs_[tap_id] == empty_tap_bb_) { @@ -378,56 +379,62 @@ ClockNetwork::e_tap_type ClockNetwork::tap_type(const ClockTapId& tap_id) const size_t ClockNetwork::tap_x(const ClockTapId& tap_id) const { VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE); - return tap_bbs_[tap_id].xmin(); + return tap_bbs_[tap_id].xmin(); } size_t ClockNetwork::tap_y(const ClockTapId& tap_id) const { VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE); - return tap_bbs_[tap_id].ymin(); + return tap_bbs_[tap_id].ymin(); } -vtr::Rect ClockNetwork::tap_bounding_box(const ClockTapId& tap_id) const { +vtr::Rect ClockNetwork::tap_bounding_box( + const ClockTapId& tap_id) const { VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION); - return tap_bbs_[tap_id]; + return tap_bbs_[tap_id]; } size_t ClockNetwork::tap_step_x(const ClockTapId& tap_id) const { VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION); - return tap_bb_steps_[tap_id].x(); + return tap_bb_steps_[tap_id].x(); } size_t ClockNetwork::tap_step_y(const ClockTapId& tap_id) const { VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION); - return tap_bb_steps_[tap_id].y(); + return tap_bb_steps_[tap_id].y(); } -bool ClockNetwork::valid_tap_coord_in_bb(const ClockTapId& tap_id, const vtr::Point& tap_coord) const { +bool ClockNetwork::valid_tap_coord_in_bb( + const ClockTapId& tap_id, const vtr::Point& tap_coord) const { VTR_ASSERT(valid_tap_id(tap_id)); if (tap_type(tap_id) == ClockNetwork::e_tap_type::ALL) { return true; } - if (tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE && tap_bbs_[tap_id].strictly_contains(tap_coord)) { + if (tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE && + tap_bbs_[tap_id].strictly_contains(tap_coord)) { return true; } - if (tap_type(tap_id) == ClockNetwork::e_tap_type::REGION && tap_bbs_[tap_id].strictly_contains(tap_coord)) { + if (tap_type(tap_id) == ClockNetwork::e_tap_type::REGION && + tap_bbs_[tap_id].strictly_contains(tap_coord)) { /* Check if steps are considered, coords still matches */ bool x_in_bb = false; - for (size_t ix = tap_bbs_[tap_id].xmin(); ix < tap_bbs_[tap_id].xmax(); ix = ix + tap_bb_steps_[tap_id].x()) { + for (size_t ix = tap_bbs_[tap_id].xmin(); ix < tap_bbs_[tap_id].xmax(); + ix = ix + tap_bb_steps_[tap_id].x()) { if (tap_coord.x() == ix) { x_in_bb = true; break; - } + } } /* Early exit */ if (!x_in_bb) { return false; } bool y_in_bb = false; - for (size_t iy = tap_bbs_[tap_id].ymin(); iy < tap_bbs_[tap_id].ymax(); iy = iy + tap_bb_steps_[tap_id].y()) { + for (size_t iy = tap_bbs_[tap_id].ymin(); iy < tap_bbs_[tap_id].ymax(); + iy = iy + tap_bb_steps_[tap_id].y()) { if (tap_coord.y() == iy) { y_in_bb = true; break; - } + } } if (y_in_bb && x_in_bb) { return true; @@ -437,7 +444,8 @@ bool ClockNetwork::valid_tap_coord_in_bb(const ClockTapId& tap_id, const vtr::Po } std::vector ClockNetwork::tree_flatten_tap_to_ports( - const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, const vtr::Point& tap_coord) const { + const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, + const vtr::Point& tap_coord) const { VTR_ASSERT(valid_tree_id(tree_id)); std::vector flatten_taps; for (ClockTapId tap_id : tree_taps_[tree_id]) { @@ -459,7 +467,7 @@ std::vector ClockNetwork::tree_flatten_tap_to_ports( if (from_port.get_lsb() != size_t(clk_pin_id)) { continue; } - /* Filter out unmatched coordinates */ + /* Filter out unmatched coordinates */ if (!valid_tap_coord_in_bb(tap_id, tap_coord)) { continue; } @@ -761,7 +769,8 @@ ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, const std::string& from_port, const std::string& to_port) { VTR_ASSERT(valid_tree_id(tree_id)); - /* TODO: Consider find existing tap template and avoid duplication in storage */ + /* TODO: Consider find existing tap template and avoid duplication in storage + */ ClockTapId tap_id = ClockTapId(tap_ids_.size()); tap_ids_.push_back(tap_id); tap_from_ports_.push_back(from_port); @@ -772,34 +781,46 @@ ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, return tap_id; } -bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect& bb) { +bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, + const vtr::Rect& bb) { VTR_ASSERT(valid_tap_id(tap_id)); /* Check the bounding box, ensure it must be valid */ if (bb.xmax() < bb.xmin() || bb.ymax() < bb.ymin()) { - VTR_LOG_ERROR("Invalid bounding box (xlow=%lu, ylow=%lu) -> (xhigh=%lu, yhigh=%lu)! Must follow: xlow <= xhigh, ylow <= yhigh!\n", bb.xmin(), bb.ymin(), bb.xmax(), bb.ymax()); - return false; + VTR_LOG_ERROR( + "Invalid bounding box (xlow=%lu, ylow=%lu) -> (xhigh=%lu, yhigh=%lu)! " + "Must follow: xlow <= xhigh, ylow <= yhigh!\n", + bb.xmin(), bb.ymin(), bb.xmax(), bb.ymax()); + return false; } tap_bbs_[tap_id] = bb; return true; } -bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id, const size_t& step) { +bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id, + const size_t& step) { VTR_ASSERT(valid_tap_id(tap_id)); /* Must be a valid step >= 1 */ if (step == 0) { - VTR_LOG_ERROR("Invalid x-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step); - return false; + VTR_LOG_ERROR( + "Invalid x-direction step (=%lu) for any bounding box! Expect an integer " + ">= 1!\n", + step); + return false; } tap_bb_steps_[tap_id].set_x(step); return true; } -bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id, const size_t& step) { +bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id, + const size_t& step) { VTR_ASSERT(valid_tap_id(tap_id)); /* Must be a valid step >= 1 */ if (step == 0) { - VTR_LOG_ERROR("Invalid y-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step); - return false; + VTR_LOG_ERROR( + "Invalid y-direction step (=%lu) for any bounding box! Expect an integer " + ">= 1!\n", + step); + return false; } tap_bb_steps_[tap_id].set_y(step); return true; @@ -957,10 +978,8 @@ bool ClockNetwork::valid_internal_driver_id( (int_driver_id == internal_driver_ids_[int_driver_id]); } -bool ClockNetwork::valid_tap_id( - const ClockTapId& tap_id) const { - return (size_t(tap_id) < tap_ids_.size()) && - (tap_id == tap_ids_[tap_id]); +bool ClockNetwork::valid_tap_id(const ClockTapId& tap_id) const { + return (size_t(tap_id) < tap_ids_.size()) && (tap_id == tap_ids_[tap_id]); } bool ClockNetwork::valid_level_id(const ClockTreeId& tree_id, diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 57ed39cb9..25042524a 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -49,12 +49,7 @@ class ClockNetwork { typedef vtr::Range clock_internal_driver_range; /* Type of tap points */ - enum class e_tap_type : unsigned char { - ALL = 0, - SINGLE, - REGION, - NUM_TYPES - }; + enum class e_tap_type : unsigned char { ALL = 0, SINGLE, REGION, NUM_TYPES }; public: /* Constructors */ ClockNetwork(); @@ -148,23 +143,25 @@ class ClockNetwork { /* Find the type of tap point: * all -> all coordinates in efpga are required to tap * single -> only 1 coordinate is required to tap - * region -> coordinates in a region required to tap. Steps in region may be required + * region -> coordinates in a region required to tap. Steps in region may be + * required */ e_tap_type tap_type(const ClockTapId& tap_id) const; /* Require the type of single */ - size_t tap_x(const ClockTapId& tap_id) const; - size_t tap_y(const ClockTapId& tap_id) const; + size_t tap_x(const ClockTapId& tap_id) const; + size_t tap_y(const ClockTapId& tap_id) const; /* Require the type of region */ - vtr::Rect tap_bounding_box(const ClockTapId& tap_id) const; + vtr::Rect tap_bounding_box(const ClockTapId& tap_id) const; /* Steps are only available when type is region */ - size_t tap_step_x(const ClockTapId& tap_id) const; - size_t tap_step_y(const ClockTapId& tap_id) const; + size_t tap_step_x(const ClockTapId& tap_id) const; + size_t tap_step_y(const ClockTapId& tap_id) const; /* Return the list of flatten tap pins. For example: clb[0:1].clk[2:2] is * flatten to { clb[0].clk[2], clb[1].clk[2] } Useful to build clock routing * resource graph Note that the clk_pin_id limits only 1 clock to be accessed */ std::vector tree_flatten_tap_to_ports( - const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, const vtr::Point& tap_coord) const; + const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, + const vtr::Point& tap_coord) const; /* Find a spine with a given name, if not found, return an valid id, otherwise * return an invalid one */ ClockSpineId find_spine(const std::string& name) const; @@ -218,8 +215,11 @@ class ClockNetwork { ClockInternalDriverId add_spine_switch_point_internal_driver( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, const std::string& internal_driver_port); - ClockTapId add_tree_tap(const ClockTreeId& tree_id, const std::string& from_port, const std::string& to_port); - bool set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect& bb); + ClockTapId add_tree_tap(const ClockTreeId& tree_id, + const std::string& from_port, + const std::string& to_port); + bool set_tap_bounding_box(const ClockTapId& tap_id, + const vtr::Rect& bb); bool set_tap_step_x(const ClockTapId& tap_id, const size_t& step); bool set_tap_step_y(const ClockTapId& tap_id, const size_t& step); /* Build internal links between clock tree, spines etc. This is also an @@ -265,7 +265,8 @@ class ClockNetwork { /* Show if the tap id is a valid for data queries */ bool valid_tap_id(const ClockTapId& tap_id) const; /* Check if a given coordinate matches the requirements for a tap point */ - bool valid_tap_coord_in_bb(const ClockTapId& tap_id, const vtr::Point& tap_coord) const; + bool valid_tap_coord_in_bb(const ClockTapId& tap_id, + const vtr::Point& tap_coord) const; private: /* Private mutators */ /* Build internal links between spines under a given tree */ @@ -312,8 +313,10 @@ class ClockNetwork { vtr::vector tap_ids_; vtr::vector tap_from_ports_; vtr::vector tap_to_ports_; - vtr::vector> tap_bbs_; /* Bounding box for tap points, (xlow, ylow) -> (xhigh, yhigh) */ - vtr::vector> tap_bb_steps_; /* x() -> x-direction step, y() -> y-direction step */ + vtr::vector> + tap_bbs_; /* Bounding box for tap points, (xlow, ylow) -> (xhigh, yhigh) */ + vtr::vector> + tap_bb_steps_; /* x() -> x-direction step, y() -> y-direction step */ /* Default routing resource */ std::string default_segment_name_; /* The routing segment representing the diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index fe90cd7f0..492649788 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -29,8 +29,8 @@ namespace openfpga { // Begin namespace openfpga *******************************************************************/ static void read_xml_clock_tree_tap_type_all(pugi::xml_node& xml_tap, const pugiutil::loc_data& loc_data, - ClockNetwork& clk_ntwk, - const ClockTreeId& tree_id) { + ClockNetwork& clk_ntwk, + const ClockTreeId& tree_id) { if (!clk_ntwk.valid_tree_id(tree_id)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap), "Invalid id of a clock tree!\n"); @@ -48,10 +48,9 @@ static void read_xml_clock_tree_tap_type_all(pugi::xml_node& xml_tap, /******************************************************************** * Parse XML codes of a to an object of ClockNetwork *******************************************************************/ -static void read_xml_clock_tree_tap_type_single(pugi::xml_node& xml_tap, - const pugiutil::loc_data& loc_data, - ClockNetwork& clk_ntwk, - const ClockTreeId& tree_id) { +static void read_xml_clock_tree_tap_type_single( + pugi::xml_node& xml_tap, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) { if (!clk_ntwk.valid_tree_id(tree_id)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap), "Invalid id of a clock tree!\n"); @@ -63,25 +62,26 @@ static void read_xml_clock_tree_tap_type_single(pugi::xml_node& xml_tap, std::string to_pin_name = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) .as_string(); - ClockTapId tap_id = clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + ClockTapId tap_id = + clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); /* Single tap only require a coordinate */ - size_t tap_x = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, loc_data, pugiutil::ReqOpt::REQUIRED) - .as_int(); - size_t tap_y = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, loc_data, pugiutil::ReqOpt::REQUIRED) - .as_int(); - clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect(tap_x, tap_y, tap_x, tap_y)); + size_t tap_x = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, + loc_data, pugiutil::ReqOpt::REQUIRED) + .as_int(); + size_t tap_y = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, + loc_data, pugiutil::ReqOpt::REQUIRED) + .as_int(); + clk_ntwk.set_tap_bounding_box(tap_id, + vtr::Rect(tap_x, tap_y, tap_x, tap_y)); } /******************************************************************** * Parse XML codes of a to an object of ClockNetwork *******************************************************************/ -static void read_xml_clock_tree_tap_type_region(pugi::xml_node& xml_tap, - const pugiutil::loc_data& loc_data, - ClockNetwork& clk_ntwk, - const ClockTreeId& tree_id) { +static void read_xml_clock_tree_tap_type_region( + pugi::xml_node& xml_tap, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) { if (!clk_ntwk.valid_tree_id(tree_id)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap), "Invalid id of a clock tree!\n"); @@ -93,22 +93,26 @@ static void read_xml_clock_tree_tap_type_region(pugi::xml_node& xml_tap, std::string to_pin_name = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) .as_string(); - ClockTapId tap_id = clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + ClockTapId tap_id = + clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); /* Region require a bounding box */ size_t tap_start_x = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data, pugiutil::ReqOpt::REQUIRED) + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data, + pugiutil::ReqOpt::REQUIRED) .as_int(); size_t tap_start_y = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data, pugiutil::ReqOpt::REQUIRED) + get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data, + pugiutil::ReqOpt::REQUIRED) .as_int(); - size_t tap_end_x = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, loc_data, pugiutil::ReqOpt::REQUIRED) - .as_int(); - size_t tap_end_y = - get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, loc_data, pugiutil::ReqOpt::REQUIRED) - .as_int(); - clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect(tap_start_x, tap_start_y, tap_end_x, tap_end_y)); + size_t tap_end_x = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, + loc_data, pugiutil::ReqOpt::REQUIRED) + .as_int(); + size_t tap_end_y = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, + loc_data, pugiutil::ReqOpt::REQUIRED) + .as_int(); + clk_ntwk.set_tap_bounding_box( + tap_id, vtr::Rect(tap_start_x, tap_start_y, tap_end_x, tap_end_y)); /* Default step is all 1 */ size_t tap_step_x = @@ -129,12 +133,17 @@ static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps, /* Error out if the XML child has an invalid name! */ if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_ALL_NODE_NAME)) { read_xml_clock_tree_tap_type_all(xml_tap, loc_data, clk_ntwk, tree_id); - } else if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_REGION_NODE_NAME)) { + } else if (xml_tap.name() == + std::string(XML_CLOCK_TREE_TAP_REGION_NODE_NAME)) { read_xml_clock_tree_tap_type_region(xml_tap, loc_data, clk_ntwk, tree_id); - } else if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME)) { + } else if (xml_tap.name() == + std::string(XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME)) { read_xml_clock_tree_tap_type_single(xml_tap, loc_data, clk_ntwk, tree_id); } else { - bad_tag(xml_taps, loc_data, xml_tap, {XML_CLOCK_TREE_TAP_ALL_NODE_NAME, XML_CLOCK_TREE_TAP_REGION_NODE_NAME, XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME}); + bad_tag( + xml_taps, loc_data, xml_tap, + {XML_CLOCK_TREE_TAP_ALL_NODE_NAME, XML_CLOCK_TREE_TAP_REGION_NODE_NAME, + XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME}); } } } diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 6e237f482..66d9bb810 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -171,15 +171,17 @@ static int route_clock_tree_rr_graph( for (RREdgeId edge : rr_graph.edge_range(src_node)) { RRNodeId des_node = rr_graph.edge_sink_node(edge); if (rr_graph.node_type(des_node) == IPIN) { - /* Check if the IPIN is mapped, if not, do not connect */ - /* if the IPIN is mapped, only connect when net mapping is expected */ + /* Check if the IPIN is mapped, if not, do not connect */ + /* if the IPIN is mapped, only connect when net mapping is + * expected */ if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { continue; } if (!vpr_routing_annotation.rr_node_net(des_node)) { continue; } - if (vpr_routing_annotation.rr_node_net(des_node) != tree2clk_pin_map.at(ipin)) { + if (vpr_routing_annotation.rr_node_net(des_node) != + tree2clk_pin_map.at(ipin)) { continue; } VTR_ASSERT(rr_graph.valid_node(src_node)); From cab649893bdc8e10d21410ad612eb24b5a170452 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 18:06:39 -0700 Subject: [PATCH 047/230] [core] update clock architecture --- libs/libclkarchopenfpga/arch/example.xml | 8 ++++---- .../libclkarchopenfpga/arch/example_internal_drivers.xml | 9 +++++---- .../config/clk_arch_1clk_1rst_2layer.xml | 4 ++-- .../config/clk_arch_1clk_1rst_2layer_int_driver.xml | 4 ++-- .../homo_1clock_2layer/config/clk_arch_1clk_2layer.xml | 2 +- .../config/clk_arch_1clk_2layer.xml | 2 +- .../homo_2clock_2layer/config/clk_arch_2clk_2layer.xml | 4 ++-- 7 files changed, 17 insertions(+), 16 deletions(-) diff --git a/libs/libclkarchopenfpga/arch/example.xml b/libs/libclkarchopenfpga/arch/example.xml index ac251bd3c..9cb31bdc6 100644 --- a/libs/libclkarchopenfpga/arch/example.xml +++ b/libs/libclkarchopenfpga/arch/example.xml @@ -17,10 +17,10 @@ - - - - + + + + diff --git a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml index 2b8a5fe0d..7a46a2094 100644 --- a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml +++ b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml @@ -21,10 +21,11 @@ - - - - + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml index fde2c515a..6c05921c7 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml @@ -11,7 +11,7 @@ - + @@ -26,7 +26,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml index 78f156469..ed43a26b5 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml @@ -19,7 +19,7 @@ - + @@ -34,7 +34,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml index 6aaf1b9b4..7a41f1216 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml @@ -11,7 +11,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml index 6aaf1b9b4..7a41f1216 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml @@ -11,7 +11,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml index fdf1dc149..8c224318c 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml @@ -11,8 +11,8 @@ - - + + From d5d9531eec85e5b02e030739c2267b784d74c8ee Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 21:52:45 -0700 Subject: [PATCH 048/230] [core] comment out buggy codes where global net mapping is not annotated in OpenFPGA --- .../src/annotation/route_clock_rr_graph.cpp | 20 ++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 66d9bb810..01a7dbf1c 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -175,15 +175,21 @@ static int route_clock_tree_rr_graph( /* if the IPIN is mapped, only connect when net mapping is * expected */ if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the tree is not used\n", + clk_ntwk.spine_name(ispine).c_str()); continue; } - if (!vpr_routing_annotation.rr_node_net(des_node)) { - continue; - } - if (vpr_routing_annotation.rr_node_net(des_node) != - tree2clk_pin_map.at(ipin)) { - continue; - } + //if (!vpr_routing_annotation.rr_node_net(des_node)) { + // VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the IPIN is not mapped\n", + // clk_ntwk.spine_name(ispine).c_str()); + // continue; + //} + //if (vpr_routing_annotation.rr_node_net(des_node) != + // tree2clk_pin_map.at(ipin)) { + // VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the net mapping does not match clock net\n", + // clk_ntwk.spine_name(ispine).c_str()); + // continue; + //} VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, From 5d0b0b9a8cbc8e32a50ccd064296805b11d69191 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 22:46:12 -0700 Subject: [PATCH 049/230] [core] now global nets mapping are applied to clock routing --- .../annotation/openfpga_annotate_routing.cpp | 44 +++++++++++++++++++ .../annotation/openfpga_annotate_routing.h | 6 +++ .../src/annotation/route_clock_rr_graph.cpp | 29 +++++++----- .../src/annotation/route_clock_rr_graph.h | 1 + .../src/base/openfpga_link_arch_template.h | 1 + 5 files changed, 69 insertions(+), 12 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 780b1d99d..8c19cd2c7 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -8,10 +8,54 @@ #include "old_traceback.h" #include "vtr_assert.h" #include "vtr_log.h" +#include "vtr_time.h" /* begin namespace openfpga */ namespace openfpga { +/******************************************************************** + * Create a mapping between each rr_node and its mapped nets + * - Only applicable to global nets for dedicated clock routing purpose + * - Note that this function is different than annotate_vpr_rr_nodes() + * Please do not annotate global nets in vpr_routing_annotation! + *******************************************************************/ +vtr::vector annotate_rr_node_global_net(const DeviceContext& device_ctx, + const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, + const bool& verbose) { + vtr::vector rr_node_nets; + + size_t counter = 0; + vtr::ScopedStartFinishTimer timer("Annotating rr_node with global nets"); + + const auto& rr_graph = device_ctx.rr_graph; + + rr_node_nets.resize(rr_graph.num_nodes(), ClusterNetId::INVALID()); + + size_t layer = 0; + + for (ClusterNetId net_id : cluster_nlist.nets()) { + if (!cluster_nlist.net_is_ignored(net_id)) { + continue; + } + /* Walk through all the sinks */ + for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) { + ClusterBlockId block_id = cluster_nlist.pin_block(pin_id); + t_block_loc blk_loc = get_block_loc(block_id, false); + int phy_pin = placement_ctx.physical_pins[pin_id]; + std::vector curr_rr_nodes = rr_graph.node_lookup().find_nodes_at_all_sides(layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin); + for (RRNodeId curr_rr_node : curr_rr_nodes) { + rr_node_nets[curr_rr_node] = net_id; + } + } + } + + VTR_LOGV(verbose, "Done with %d nodes mapping\n", counter); + + + return rr_node_nets; +} + /******************************************************************** * Create a mapping between each rr_node and its mapped nets * based on VPR routing results diff --git a/openfpga/src/annotation/openfpga_annotate_routing.h b/openfpga/src/annotation/openfpga_annotate_routing.h index aa79e69d5..2578e86bd 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.h +++ b/openfpga/src/annotation/openfpga_annotate_routing.h @@ -15,6 +15,12 @@ /* begin namespace openfpga */ namespace openfpga { +vtr::vector annotate_rr_node_global_net(const DeviceContext& device_ctx, + const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, + const bool& verbose); + + void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const RoutingContext& routing_ctx, diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 01a7dbf1c..77de0175b 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -6,6 +6,7 @@ #include "vtr_geometry.h" #include "vtr_log.h" #include "vtr_time.h" +#include "openfpga_annotate_routing.h" /* begin namespace openfpga */ namespace openfpga { @@ -87,6 +88,7 @@ static int build_clock_tree_net_map( static int route_clock_tree_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const bool& verbose) { @@ -179,17 +181,16 @@ static int route_clock_tree_rr_graph( clk_ntwk.spine_name(ispine).c_str()); continue; } - //if (!vpr_routing_annotation.rr_node_net(des_node)) { - // VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the IPIN is not mapped\n", - // clk_ntwk.spine_name(ispine).c_str()); - // continue; - //} - //if (vpr_routing_annotation.rr_node_net(des_node) != - // tree2clk_pin_map.at(ipin)) { - // VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the net mapping does not match clock net\n", - // clk_ntwk.spine_name(ispine).c_str()); - // continue; - //} + if (!rr_node_gnets[des_node]) { + VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the IPIN is not mapped\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } + if (rr_node_gnets[des_node] != tree2clk_pin_map.at(ipin)) { + VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the net mapping does not match clock net\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, @@ -219,6 +220,7 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, @@ -253,6 +255,9 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, return CMD_EXEC_FATAL_ERROR; } + /* Build rr_node-to-net mapping for global nets */ + vtr::vector rr_node_gnets = annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, verbose); + /* Route spines one by one */ for (auto itree : clk_ntwk.trees()) { VTR_LOGV(verbose, "Build clock name to clock tree '%s' pin mapping...\n", @@ -269,7 +274,7 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, VTR_LOGV(verbose, "Routing clock tree '%s'...\n", clk_ntwk.tree_name(itree).c_str()); status = route_clock_tree_rr_graph( - vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, + vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index 6a1b2cad4..e12767e9b 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -22,6 +22,7 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index cb16de224..319c89086 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -231,6 +231,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, return route_clock_rr_graph( openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.placement(), openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, cmd_context.option_enable(cmd, opt_verbose)); From ac1ad527951b8e7dee1e05869812dbe160245152 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 22:47:29 -0700 Subject: [PATCH 050/230] [core] code format --- .../annotation/openfpga_annotate_routing.cpp | 18 ++++----- .../annotation/openfpga_annotate_routing.h | 8 ++-- .../src/annotation/route_clock_rr_graph.cpp | 39 +++++++++++-------- .../src/annotation/route_clock_rr_graph.h | 17 ++++---- .../src/base/openfpga_link_arch_template.h | 3 +- 5 files changed, 42 insertions(+), 43 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 8c19cd2c7..ad84d86e2 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -19,10 +19,9 @@ namespace openfpga { * - Note that this function is different than annotate_vpr_rr_nodes() * Please do not annotate global nets in vpr_routing_annotation! *******************************************************************/ -vtr::vector annotate_rr_node_global_net(const DeviceContext& device_ctx, - const ClusteredNetlist& cluster_nlist, - const PlacementContext& placement_ctx, - const bool& verbose) { +vtr::vector annotate_rr_node_global_net( + const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, const bool& verbose) { vtr::vector rr_node_nets; size_t counter = 0; @@ -31,7 +30,7 @@ vtr::vector annotate_rr_node_global_net(const DeviceCont const auto& rr_graph = device_ctx.rr_graph; rr_node_nets.resize(rr_graph.num_nodes(), ClusterNetId::INVALID()); - + size_t layer = 0; for (ClusterNetId net_id : cluster_nlist.nets()) { @@ -39,11 +38,13 @@ vtr::vector annotate_rr_node_global_net(const DeviceCont continue; } /* Walk through all the sinks */ - for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) { + for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) { ClusterBlockId block_id = cluster_nlist.pin_block(pin_id); - t_block_loc blk_loc = get_block_loc(block_id, false); + t_block_loc blk_loc = get_block_loc(block_id, false); int phy_pin = placement_ctx.physical_pins[pin_id]; - std::vector curr_rr_nodes = rr_graph.node_lookup().find_nodes_at_all_sides(layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin); + std::vector curr_rr_nodes = + rr_graph.node_lookup().find_nodes_at_all_sides( + layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin); for (RRNodeId curr_rr_node : curr_rr_nodes) { rr_node_nets[curr_rr_node] = net_id; } @@ -52,7 +53,6 @@ vtr::vector annotate_rr_node_global_net(const DeviceCont VTR_LOGV(verbose, "Done with %d nodes mapping\n", counter); - return rr_node_nets; } diff --git a/openfpga/src/annotation/openfpga_annotate_routing.h b/openfpga/src/annotation/openfpga_annotate_routing.h index 2578e86bd..dc5d28db3 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.h +++ b/openfpga/src/annotation/openfpga_annotate_routing.h @@ -15,11 +15,9 @@ /* begin namespace openfpga */ namespace openfpga { -vtr::vector annotate_rr_node_global_net(const DeviceContext& device_ctx, - const ClusteredNetlist& cluster_nlist, - const PlacementContext& placement_ctx, - const bool& verbose); - +vtr::vector annotate_rr_node_global_net( + const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, const bool& verbose); void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 77de0175b..327a51f40 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -1,12 +1,12 @@ #include "route_clock_rr_graph.h" #include "command_exit_codes.h" +#include "openfpga_annotate_routing.h" #include "openfpga_atom_netlist_utils.h" #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_log.h" #include "vtr_time.h" -#include "openfpga_annotate_routing.h" /* begin namespace openfpga */ namespace openfpga { @@ -177,17 +177,23 @@ static int route_clock_tree_rr_graph( /* if the IPIN is mapped, only connect when net mapping is * expected */ if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { - VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the tree is not used\n", + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the tree is " + "not used\n", clk_ntwk.spine_name(ispine).c_str()); continue; } if (!rr_node_gnets[des_node]) { - VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the IPIN is not mapped\n", + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the IPIN is " + "not mapped\n", clk_ntwk.spine_name(ispine).c_str()); continue; } if (rr_node_gnets[des_node] != tree2clk_pin_map.at(ipin)) { - VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the net mapping does not match clock net\n", + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the net " + "mapping does not match clock net\n", clk_ntwk.spine_name(ispine).c_str()); continue; } @@ -216,16 +222,13 @@ static int route_clock_tree_rr_graph( * - configure the routing annotation w.r.t. the clock node connections * - quick check to ensure routing is valid *******************************************************************/ -int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const AtomContext& atom_ctx, - const ClusteredNetlist& cluster_nlist, - const PlacementContext& vpr_place_ctx, - const VprNetlistAnnotation& netlist_annotation, - const RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& verbose) { +int route_clock_rr_graph( + VprRoutingAnnotation& vpr_routing_annotation, + const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, + const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, + const VprNetlistAnnotation& netlist_annotation, + const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, + const PinConstraints& pin_constraints, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Route programmable clock network based on routing resource graph"); @@ -256,7 +259,9 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, } /* Build rr_node-to-net mapping for global nets */ - vtr::vector rr_node_gnets = annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, verbose); + vtr::vector rr_node_gnets = + annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, + verbose); /* Route spines one by one */ for (auto itree : clk_ntwk.trees()) { @@ -274,8 +279,8 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, VTR_LOGV(verbose, "Routing clock tree '%s'...\n", clk_ntwk.tree_name(itree).c_str()); status = route_clock_tree_rr_graph( - vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, rr_node_gnets, - tree2clk_pin_map, clk_ntwk, itree, verbose); + vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, + rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; } diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index e12767e9b..f0d60642c 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -18,16 +18,13 @@ /* begin namespace openfpga */ namespace openfpga { -int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const AtomContext& atom_ctx, - const ClusteredNetlist& cluster_nlist, - const PlacementContext& vpr_place_ctx, - const VprNetlistAnnotation& netlist_annotation, - const RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& verbose); +int route_clock_rr_graph( + VprRoutingAnnotation& vpr_routing_annotation, + const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, + const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, + const VprNetlistAnnotation& netlist_annotation, + const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, + const PinConstraints& pin_constraints, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index 319c89086..2e742742a 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -230,8 +230,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, return route_clock_rr_graph( openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), - g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, - g_vpr_ctx.placement(), + g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, cmd_context.option_enable(cmd, opt_verbose)); From ec85bfc7046f60518afdc3803a00a80027e68fd6 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 27 Jun 2024 06:41:45 +0000 Subject: [PATCH 051/230] Bump yosys from `1288166` to `07daf61` Bumps [yosys](https://github.com/YosysHQ/yosys) from `1288166` to `07daf61`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/1288166f7ac03456b6beb0acff5d4fc84f63f57c...07daf61ae6fbe935b582a24c13e863b7d52052bd) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 1288166f7..07daf61ae 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 1288166f7ac03456b6beb0acff5d4fc84f63f57c +Subproject commit 07daf61ae6fbe935b582a24c13e863b7d52052bd From 1f4fda25eb5447bfa4d7830f183dca6d2d8bd02b Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 27 Jun 2024 16:44:38 +0000 Subject: [PATCH 052/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index c4ceed717..492aa9035 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2282 +1.2.2286 From 9ce552495ac92790686ce5959cee8ded7f682f4a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 10:17:08 -0700 Subject: [PATCH 053/230] [core] now internal drivers can be routed in dedicated clock network --- .../src/annotation/route_clock_rr_graph.cpp | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 327a51f40..9fe0a4ad6 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -147,6 +147,34 @@ static int route_clock_tree_rr_graph( des_spine_level, ipin, des_spine_direction); VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); + /* Internal drivers may appear at the switch point. Check if there are any defined and related rr_node found as incoming edges. If the global net is mapped to the internal driver, use it as the previous node */ + size_t use_int_driver = 0; + for (!spine_switch_point_internal_drivers(ispine, switch_point_id).empty() && tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { + RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); + if (OPIN != rr_graph.node_type(opin_node)) { + continue; + } + if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(ipin)) { + continue; + } + /* This is the opin node we need, use it as the internal driver */ + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + opin_node); + vpr_routing_annotation.set_rr_node_net(opin_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); + use_int_driver++; + } + } + if (use_int_driver > 1) { + VTR_LOG_ERROR("Found %lu internal drivers for the switching point (%lu, %lu) for spine '%s'!\n Expect only 1!\n", use_int_driver, src_coord.x(), src_coord.y(), clk_ntwk.spine_name(ispine).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + if (use_int_driver == 1) { + continue; /* Used internal driver, early pass */ + } vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); /* It could happen that there is no net mapped some clock pin, skip the From 64a7a4ce26f3980c75a799ef717d41d31133e66b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 10:19:14 -0700 Subject: [PATCH 054/230] [core] syntax --- openfpga/src/annotation/route_clock_rr_graph.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 9fe0a4ad6..06d9c1d5a 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -149,7 +149,7 @@ static int route_clock_tree_rr_graph( VTR_ASSERT(rr_graph.valid_node(des_node)); /* Internal drivers may appear at the switch point. Check if there are any defined and related rr_node found as incoming edges. If the global net is mapped to the internal driver, use it as the previous node */ size_t use_int_driver = 0; - for (!spine_switch_point_internal_drivers(ispine, switch_point_id).empty() && tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + if (!clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty() && tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); if (OPIN != rr_graph.node_type(opin_node)) { From 6fceb81110bbd46f176f254258765d48778ba13e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 10:19:40 -0700 Subject: [PATCH 055/230] [core] code format --- openfpga/src/annotation/route_clock_rr_graph.cpp | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 06d9c1d5a..7a540d040 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -147,9 +147,15 @@ static int route_clock_tree_rr_graph( des_spine_level, ipin, des_spine_direction); VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); - /* Internal drivers may appear at the switch point. Check if there are any defined and related rr_node found as incoming edges. If the global net is mapped to the internal driver, use it as the previous node */ + /* Internal drivers may appear at the switch point. Check if there are + * any defined and related rr_node found as incoming edges. If the + * global net is mapped to the internal driver, use it as the previous + * node */ size_t use_int_driver = 0; - if (!clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty() && tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + if (!clk_ntwk + .spine_switch_point_internal_drivers(ispine, switch_point_id) + .empty() && + tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); if (OPIN != rr_graph.node_type(opin_node)) { @@ -169,7 +175,11 @@ static int route_clock_tree_rr_graph( } } if (use_int_driver > 1) { - VTR_LOG_ERROR("Found %lu internal drivers for the switching point (%lu, %lu) for spine '%s'!\n Expect only 1!\n", use_int_driver, src_coord.x(), src_coord.y(), clk_ntwk.spine_name(ispine).c_str()); + VTR_LOG_ERROR( + "Found %lu internal drivers for the switching point (%lu, %lu) for " + "spine '%s'!\n Expect only 1!\n", + use_int_driver, src_coord.x(), src_coord.y(), + clk_ntwk.spine_name(ispine).c_str()); return CMD_EXEC_FATAL_ERROR; } if (use_int_driver == 1) { From 3fb891094b4c4b2d491e085bf6e285f1764a145c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 11:02:37 -0700 Subject: [PATCH 056/230] [doc] add new syntax --- .../manual/file_formats/clock_network.rst | 60 ++++++++++++++++--- 1 file changed, 53 insertions(+), 7 deletions(-) diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index d998c63a9..da359f400 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -30,7 +30,9 @@ Using the clock network description language, users can define multiple clock ne - + + + @@ -209,23 +211,67 @@ where the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` Tap Point Settings ^^^^^^^^^^^^^^^^^^ -The following syntax are applicable to the XML definition tagged by ``tap``. +The following syntax are applicable to the XML definition tagged by ``all``, ``region`` and ``single``. Note that a number of tap points can be defined under the node ``taps``. -.. option:: tile_pin="" +.. option:: from_pin="" - Define the pin of a programmable block to be tapped by a clock network. The pin must be a valid pin defined in the VPR architecture description file. + Define the source pin of a programmable block to be tapped by a clock network. The pin must be a valid pin of the global ports defined in the tile_annotation part of OpenFPGA architecture description file. + +.. option:: to_pin="" + + Define the destination pin of a programmable block to be tapped by a clock network. The pin must be a valid pin defined in the VPR architecture description file. .. note:: Only the leaf clock spine (not switch points to drive other clock spine) can tap pins of programmable blocks. +.. note:: Each coordinate must be a valid integer within the device height and width that are defined in VPR architecture!!! + +.. warning:: The following syntax are only applicable to ``single`` tap mode. + +.. option:: x="" + + Define the x coordinate of the tap point, which is applied to the destination pin ``to_pin`` + +.. option:: y="" + + Define the y coordinate of the tap point, which is applied to the destination pin ``to_pin`` + +.. warning:: The following syntax are only applicable to ``region`` tap mode. + +.. option:: start_x="" + + Define the starting x coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: start_y="" + + Define the starting y coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: end_x="" + + Define the ending x coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: end_y="" + + Define the ending y coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: repeat_x="" + + Define the repeating factor on x coordinate of the tap region, which is applied to the destination pin ``to_pin`` + +.. option:: repeat_y="" + + Define the repeating factor on y coordinate of the tap region, which is applied to the destination pin ``to_pin`` + For example, .. code-block:: xml - + - + + + @@ -235,7 +281,7 @@ where all the clock spines of the clock network ``clk_tree_0`` tap the clock pin - + From 7892c2340c637782191fbf0b5f793d79f1b87dae Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 12:01:54 -0700 Subject: [PATCH 057/230] [core] add a new option 'disable_unused_trees' to route clock rr graph --- openfpga/src/annotation/route_clock_rr_graph.cpp | 12 +++++++++--- openfpga/src/annotation/route_clock_rr_graph.h | 5 ++++- openfpga/src/base/openfpga_link_arch_template.h | 4 ++++ openfpga/src/base/openfpga_setup_command_template.h | 2 ++ 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 7a540d040..05aaca922 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -91,13 +91,14 @@ static int route_clock_tree_rr_graph( const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const bool& disable_unused_trees, const bool& verbose) { for (auto ispine : clk_ntwk.spines(clk_tree)) { VTR_LOGV(verbose, "Routing spine '%s'...\n", clk_ntwk.spine_name(ispine).c_str()); for (auto ipin : clk_ntwk.pins(clk_tree)) { /* Do not route unused clock spines */ - if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + if (disable_unused_trees && tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { VTR_LOGV(verbose, "Skip routing backbone of unused spine '%s'...\n", clk_ntwk.spine_name(ispine).c_str()); continue; @@ -172,6 +173,8 @@ static int route_clock_tree_rr_graph( vpr_routing_annotation.set_rr_node_net(des_node, tree2clk_pin_map.at(ipin)); use_int_driver++; + VTR_LOGV(verbose, "Routing switch points of spine '%s' at the switching point (%lu, %lu) using internal driver\n", + clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y()); } } if (use_int_driver > 1) { @@ -266,7 +269,10 @@ int route_clock_rr_graph( const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, const bool& verbose) { + const PinConstraints& pin_constraints, + const bool& disable_unused_trees, + const bool& disable_unused_spines, + const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Route programmable clock network based on routing resource graph"); @@ -318,7 +324,7 @@ int route_clock_rr_graph( clk_ntwk.tree_name(itree).c_str()); status = route_clock_tree_rr_graph( vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, - rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, verbose); + rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, disable_unused_trees, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; } diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index f0d60642c..13bff0eea 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -24,7 +24,10 @@ int route_clock_rr_graph( const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, const bool& verbose); + const PinConstraints& pin_constraints, + const bool& disable_unused_trees, + const bool& disable_unused_spines, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index 2e742742a..e0fec4742 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -219,6 +219,8 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, /* add an option '--pin_constraints_file in short '-pcf' */ CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); + CommandOptionId opt_disable_unused_trees = cmd.option("disable_unused_trees"); + CommandOptionId opt_disable_unused_spines = cmd.option("disable_unused_spines"); CommandOptionId opt_verbose = cmd.option("verbose"); /* If pin constraints are enabled by command options, read the file */ @@ -233,6 +235,8 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, + cmd_context.option_enable(cmd, opt_disable_unused_trees), + cmd_context.option_enable(cmd, opt_disable_unused_spines), cmd_context.option_enable(cmd, opt_verbose)); } diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 3d178ee17..169d3cf9a 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -710,6 +710,8 @@ ShellCommandId add_route_clock_rr_graph_command_template( shell_cmd.set_option_short_name(opt_file, "pcf"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + shell_cmd.add_option("disable_unused_trees", false, "Disable entire clock trees when they are not used by any clock nets. Useful to reduce clock power"); + shell_cmd.add_option("disable_unused_spines", false, "Disable part of the clock tree which are used by clock nets. Useful to reduce clock power"); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); From e75fd57af26f966c202edbc7c240bd8804f5305b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 12:39:18 -0700 Subject: [PATCH 058/230] [core] refactor codes --- .../src/annotation/route_clock_rr_graph.cpp | 344 ++++++++++-------- 1 file changed, 202 insertions(+), 142 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 05aaca922..3c56b6d79 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -78,6 +78,201 @@ static int build_clock_tree_net_map( return CMD_EXEC_SUCCESS; } +/******************************************************************** + * Route a selected clock spine in a staight line + * - route the spine from the starting point to the ending point + *******************************************************************/ +static int route_straight_spines( + VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, + const RRClockSpatialLookup& clk_rr_lookup, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockSpineId& ispine, const ClockTreePinId& ipin, + const bool& verbose) { + std::vector> spine_coords = + clk_ntwk.spine_coordinates(ispine); + VTR_LOGV(verbose, "Routing backbone of spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); + for (size_t icoord = 0; icoord < spine_coords.size() - 1; ++icoord) { + vtr::Point src_coord = spine_coords[icoord]; + vtr::Point des_coord = spine_coords[icoord + 1]; + Direction src_spine_direction = clk_ntwk.spine_direction(ispine); + Direction des_spine_direction = clk_ntwk.spine_direction(ispine); + ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); + RRNodeId src_node = + clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, + src_spine_level, ipin, src_spine_direction); + RRNodeId des_node = + clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, + des_spine_level, ipin, des_spine_direction); + VTR_ASSERT(rr_graph.valid_node(src_node)); + VTR_ASSERT(rr_graph.valid_node(des_node)); + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + src_node); + } + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Route a switching points between spines + * - connect between two routing tracks (left or right turns) + * - connect internal driver to routing track + *******************************************************************/ +static int route_spine_switch_points( + VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, + const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, + const std::map& tree2clk_pin_map, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockSpineId& ispine, const ClockTreePinId& ipin, + const bool& verbose) { + VTR_LOGV(verbose, "Routing switch points of spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); + for (ClockSwitchPointId switch_point_id : + clk_ntwk.spine_switch_points(ispine)) { + vtr::Point src_coord = + clk_ntwk.spine_switch_point(ispine, switch_point_id); + ClockSpineId des_spine = + clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); + vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); + Direction src_spine_direction = clk_ntwk.spine_direction(ispine); + Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); + ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); + RRNodeId src_node = + clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, + src_spine_level, ipin, src_spine_direction); + RRNodeId des_node = + clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, + des_spine_level, ipin, des_spine_direction); + VTR_ASSERT(rr_graph.valid_node(src_node)); + VTR_ASSERT(rr_graph.valid_node(des_node)); + /* Internal drivers may appear at the switch point. Check if there are + * any defined and related rr_node found as incoming edges. If the + * global net is mapped to the internal driver, use it as the previous + * node */ + size_t use_int_driver = 0; + if (!clk_ntwk + .spine_switch_point_internal_drivers(ispine, switch_point_id) + .empty() && + tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { + RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); + if (OPIN != rr_graph.node_type(opin_node)) { + continue; + } + if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(ipin)) { + continue; + } + /* This is the opin node we need, use it as the internal driver */ + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + opin_node); + vpr_routing_annotation.set_rr_node_net(opin_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); + use_int_driver++; + VTR_LOGV(verbose, "Routing switch points of spine '%s' at the switching point (%lu, %lu) using internal driver\n", + clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y()); + } + } + if (use_int_driver > 1) { + VTR_LOG_ERROR( + "Found %lu internal drivers for the switching point (%lu, %lu) for " + "spine '%s'!\n Expect only 1!\n", + use_int_driver, src_coord.x(), src_coord.y(), + clk_ntwk.spine_name(ispine).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + if (use_int_driver == 1) { + continue; /* Used internal driver, early pass */ + } + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + src_node); + /* It could happen that there is no net mapped some clock pin, skip the + * net mapping */ + if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net(src_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); + } + } + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Route a spine to its tap points + * - Only connect to tap points which are mapped by a global net + *******************************************************************/ +static int route_spine_taps( + VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, + const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, + const std::map& tree2clk_pin_map, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockSpineId& ispine, const ClockTreePinId& ipin, + const bool& verbose) { + std::vector> spine_coords = + clk_ntwk.spine_coordinates(ispine); + /* Route the spine-to-IPIN connections (only for the last level) */ + if (clk_ntwk.is_last_level(ispine)) { + VTR_LOGV(verbose, "Routing clock taps of spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); + /* Connect to any fan-out node which is IPIN */ + for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { + vtr::Point src_coord = spine_coords[icoord]; + Direction src_spine_direction = clk_ntwk.spine_direction(ispine); + ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); + RRNodeId src_node = + clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, + src_spine_level, ipin, src_spine_direction); + for (RREdgeId edge : rr_graph.edge_range(src_node)) { + RRNodeId des_node = rr_graph.edge_sink_node(edge); + if (rr_graph.node_type(des_node) == IPIN) { + /* Check if the IPIN is mapped, if not, do not connect */ + /* if the IPIN is mapped, only connect when net mapping is + * expected */ + if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the tree is " + "not used\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } + if (!rr_node_gnets[des_node]) { + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the IPIN is " + "not mapped\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } + if (rr_node_gnets[des_node] != tree2clk_pin_map.at(ipin)) { + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the net " + "mapping does not match clock net\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } + VTR_ASSERT(rr_graph.valid_node(src_node)); + VTR_ASSERT(rr_graph.valid_node(des_node)); + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + src_node); + if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net( + src_node, tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net( + des_node, tree2clk_pin_map.at(ipin)); + } + } + } + } + } + + return CMD_EXEC_SUCCESS; +} + /******************************************************************** * Route a clock tree on an existing routing resource graph * The strategy is to route spine one by one @@ -106,151 +301,16 @@ static int route_clock_tree_rr_graph( /* Route the spine from starting point to ending point */ std::vector> spine_coords = clk_ntwk.spine_coordinates(ispine); - VTR_LOGV(verbose, "Routing backbone of spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - for (size_t icoord = 0; icoord < spine_coords.size() - 1; ++icoord) { - vtr::Point src_coord = spine_coords[icoord]; - vtr::Point des_coord = spine_coords[icoord + 1]; - Direction src_spine_direction = clk_ntwk.spine_direction(ispine); - Direction des_spine_direction = clk_ntwk.spine_direction(ispine); - ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); - RRNodeId src_node = - clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); - RRNodeId des_node = - clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); - VTR_ASSERT(rr_graph.valid_node(src_node)); - VTR_ASSERT(rr_graph.valid_node(des_node)); - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); + if (CMD_EXEC_SUCCESS != route_straight_spines(vpr_routing_annotation, rr_graph, clk_rr_lookup, clk_ntwk, clk_tree, ispine, ipin, verbose)) { + return CMD_EXEC_FATAL_ERROR; } - /* Route the spine-to-spine switching points */ - VTR_LOGV(verbose, "Routing switch points of spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - for (ClockSwitchPointId switch_point_id : - clk_ntwk.spine_switch_points(ispine)) { - vtr::Point src_coord = - clk_ntwk.spine_switch_point(ispine, switch_point_id); - ClockSpineId des_spine = - clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); - vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); - Direction src_spine_direction = clk_ntwk.spine_direction(ispine); - Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); - ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); - RRNodeId src_node = - clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); - RRNodeId des_node = - clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); - VTR_ASSERT(rr_graph.valid_node(src_node)); - VTR_ASSERT(rr_graph.valid_node(des_node)); - /* Internal drivers may appear at the switch point. Check if there are - * any defined and related rr_node found as incoming edges. If the - * global net is mapped to the internal driver, use it as the previous - * node */ - size_t use_int_driver = 0; - if (!clk_ntwk - .spine_switch_point_internal_drivers(ispine, switch_point_id) - .empty() && - tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { - for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { - RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); - if (OPIN != rr_graph.node_type(opin_node)) { - continue; - } - if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(ipin)) { - continue; - } - /* This is the opin node we need, use it as the internal driver */ - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - opin_node); - vpr_routing_annotation.set_rr_node_net(opin_node, - tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net(des_node, - tree2clk_pin_map.at(ipin)); - use_int_driver++; - VTR_LOGV(verbose, "Routing switch points of spine '%s' at the switching point (%lu, %lu) using internal driver\n", - clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y()); - } - } - if (use_int_driver > 1) { - VTR_LOG_ERROR( - "Found %lu internal drivers for the switching point (%lu, %lu) for " - "spine '%s'!\n Expect only 1!\n", - use_int_driver, src_coord.x(), src_coord.y(), - clk_ntwk.spine_name(ispine).c_str()); - return CMD_EXEC_FATAL_ERROR; - } - if (use_int_driver == 1) { - continue; /* Used internal driver, early pass */ - } - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); - /* It could happen that there is no net mapped some clock pin, skip the - * net mapping */ - if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { - vpr_routing_annotation.set_rr_node_net(src_node, - tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net(des_node, - tree2clk_pin_map.at(ipin)); - } + /* Route the opin/spine-to-spine switching points */ + if (CMD_EXEC_SUCCESS != route_spine_switch_points(vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, ispine, ipin, verbose)) { + return CMD_EXEC_FATAL_ERROR; } /* Route the spine-to-IPIN connections (only for the last level) */ - if (clk_ntwk.is_last_level(ispine)) { - VTR_LOGV(verbose, "Routing clock taps of spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - /* Connect to any fan-out node which is IPIN */ - for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { - vtr::Point src_coord = spine_coords[icoord]; - Direction src_spine_direction = clk_ntwk.spine_direction(ispine); - ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); - RRNodeId src_node = - clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); - for (RREdgeId edge : rr_graph.edge_range(src_node)) { - RRNodeId des_node = rr_graph.edge_sink_node(edge); - if (rr_graph.node_type(des_node) == IPIN) { - /* Check if the IPIN is mapped, if not, do not connect */ - /* if the IPIN is mapped, only connect when net mapping is - * expected */ - if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { - VTR_LOGV(verbose, - "Skip routing clock tap of spine '%s' as the tree is " - "not used\n", - clk_ntwk.spine_name(ispine).c_str()); - continue; - } - if (!rr_node_gnets[des_node]) { - VTR_LOGV(verbose, - "Skip routing clock tap of spine '%s' as the IPIN is " - "not mapped\n", - clk_ntwk.spine_name(ispine).c_str()); - continue; - } - if (rr_node_gnets[des_node] != tree2clk_pin_map.at(ipin)) { - VTR_LOGV(verbose, - "Skip routing clock tap of spine '%s' as the net " - "mapping does not match clock net\n", - clk_ntwk.spine_name(ispine).c_str()); - continue; - } - VTR_ASSERT(rr_graph.valid_node(src_node)); - VTR_ASSERT(rr_graph.valid_node(des_node)); - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); - if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { - vpr_routing_annotation.set_rr_node_net( - src_node, tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net( - des_node, tree2clk_pin_map.at(ipin)); - } - } - } - } + if (CMD_EXEC_SUCCESS != route_spine_taps(vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, ispine, ipin, verbose)) { + return CMD_EXEC_FATAL_ERROR; } } } From 4185235a690915bdbe59c4e5aae2dbc8319dc898 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 15:02:20 -0700 Subject: [PATCH 059/230] [core] now clock routing is based on tree expansion. Unused part can be disconnected --- .../src/base/clock_network.cpp | 14 + .../src/base/clock_network.h | 4 + .../src/annotation/route_clock_rr_graph.cpp | 330 +++++++++++------- 3 files changed, 217 insertions(+), 131 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 70fd840f6..a34868be5 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -333,6 +333,20 @@ vtr::Point ClockNetwork::spine_switch_point( return spine_switch_coords_[spine_id][size_t(switch_point_id)]; } +std::vector ClockNetwork::find_spine_switch_points_with_coord( + const ClockSpineId& spine_id, + const vtr::Point& coord) const { + VTR_ASSERT(valid_spine_id(spine_id)); + std::vector ret; + for (size_t i = 0; i < spine_switch_points_[spine_id].size(); ++i) { + if (spine_switch_coords_[spine_id][i] == coord) { + ret.push_back(ClockSwitchPointId(i)); + } + } + + return ret; +} + std::vector ClockNetwork::spine_switch_point_internal_drivers( const ClockSpineId& spine_id, diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 25042524a..0fc15e471 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -125,6 +125,10 @@ class ClockNetwork { vtr::Point spine_switch_point( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const; + + /* Find all the switching points at a given coordinate */ + std::vector find_spine_switch_points_with_coord(const ClockSpineId& spine_id, const vtr::Point& coord) const; + std::vector spine_switch_point_internal_drivers( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const; diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 3c56b6d79..cabb763c6 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -78,126 +78,90 @@ static int build_clock_tree_net_map( return CMD_EXEC_SUCCESS; } -/******************************************************************** - * Route a selected clock spine in a staight line - * - route the spine from the starting point to the ending point - *******************************************************************/ -static int route_straight_spines( - VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, - const RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, - const ClockSpineId& ispine, const ClockTreePinId& ipin, - const bool& verbose) { - std::vector> spine_coords = - clk_ntwk.spine_coordinates(ispine); - VTR_LOGV(verbose, "Routing backbone of spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - for (size_t icoord = 0; icoord < spine_coords.size() - 1; ++icoord) { - vtr::Point src_coord = spine_coords[icoord]; - vtr::Point des_coord = spine_coords[icoord + 1]; - Direction src_spine_direction = clk_ntwk.spine_direction(ispine); - Direction des_spine_direction = clk_ntwk.spine_direction(ispine); - ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); - RRNodeId src_node = - clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); - RRNodeId des_node = - clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); - VTR_ASSERT(rr_graph.valid_node(src_node)); - VTR_ASSERT(rr_graph.valid_node(des_node)); - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); - } - return CMD_EXEC_SUCCESS; -} - /******************************************************************** * Route a switching points between spines * - connect between two routing tracks (left or right turns) * - connect internal driver to routing track *******************************************************************/ -static int route_spine_switch_points( - VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, +static int route_clock_spine_switch_point( + VprRoutingAnnotation& vpr_routing_annotation, + const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const ClockSpineId& ispine, const ClockTreePinId& ipin, + const ClockSwitchPointId& switch_point_id, const bool& verbose) { VTR_LOGV(verbose, "Routing switch points of spine '%s'...\n", clk_ntwk.spine_name(ispine).c_str()); - for (ClockSwitchPointId switch_point_id : - clk_ntwk.spine_switch_points(ispine)) { - vtr::Point src_coord = - clk_ntwk.spine_switch_point(ispine, switch_point_id); - ClockSpineId des_spine = - clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); - vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); - Direction src_spine_direction = clk_ntwk.spine_direction(ispine); - Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); - ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); - RRNodeId src_node = - clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); - RRNodeId des_node = - clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); - VTR_ASSERT(rr_graph.valid_node(src_node)); - VTR_ASSERT(rr_graph.valid_node(des_node)); - /* Internal drivers may appear at the switch point. Check if there are - * any defined and related rr_node found as incoming edges. If the - * global net is mapped to the internal driver, use it as the previous - * node */ - size_t use_int_driver = 0; - if (!clk_ntwk - .spine_switch_point_internal_drivers(ispine, switch_point_id) - .empty() && - tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { - for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { - RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); - if (OPIN != rr_graph.node_type(opin_node)) { - continue; - } - if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(ipin)) { - continue; - } - /* This is the opin node we need, use it as the internal driver */ - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - opin_node); - vpr_routing_annotation.set_rr_node_net(opin_node, - tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net(des_node, - tree2clk_pin_map.at(ipin)); - use_int_driver++; - VTR_LOGV(verbose, "Routing switch points of spine '%s' at the switching point (%lu, %lu) using internal driver\n", - clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y()); + vtr::Point src_coord = + clk_ntwk.spine_switch_point(ispine, switch_point_id); + ClockSpineId des_spine = + clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); + vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); + Direction src_spine_direction = clk_ntwk.spine_direction(ispine); + Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); + ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); + RRNodeId src_node = + clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, + src_spine_level, ipin, src_spine_direction); + RRNodeId des_node = + clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, + des_spine_level, ipin, des_spine_direction); + VTR_ASSERT(rr_graph.valid_node(src_node)); + VTR_ASSERT(rr_graph.valid_node(des_node)); + /* Internal drivers may appear at the switch point. Check if there are + * any defined and related rr_node found as incoming edges. If the + * global net is mapped to the internal driver, use it as the previous + * node */ + size_t use_int_driver = 0; + if (!clk_ntwk + .spine_switch_point_internal_drivers(ispine, switch_point_id) + .empty() && + tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { + RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); + if (OPIN != rr_graph.node_type(opin_node)) { + continue; } - } - if (use_int_driver > 1) { - VTR_LOG_ERROR( - "Found %lu internal drivers for the switching point (%lu, %lu) for " - "spine '%s'!\n Expect only 1!\n", - use_int_driver, src_coord.x(), src_coord.y(), - clk_ntwk.spine_name(ispine).c_str()); - return CMD_EXEC_FATAL_ERROR; - } - if (use_int_driver == 1) { - continue; /* Used internal driver, early pass */ - } - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); - /* It could happen that there is no net mapped some clock pin, skip the - * net mapping */ - if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { - vpr_routing_annotation.set_rr_node_net(src_node, + if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(ipin)) { + continue; + } + /* This is the opin node we need, use it as the internal driver */ + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + opin_node); + vpr_routing_annotation.set_rr_node_net(opin_node, tree2clk_pin_map.at(ipin)); vpr_routing_annotation.set_rr_node_net(des_node, tree2clk_pin_map.at(ipin)); + use_int_driver++; + VTR_LOGV(verbose, "Routing switch points of spine '%s' at the switching point (%lu, %lu) using internal driver\n", + clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y()); } } + if (use_int_driver > 1) { + VTR_LOG_ERROR( + "Found %lu internal drivers for the switching point (%lu, %lu) for " + "spine '%s'!\n Expect only 1!\n", + use_int_driver, src_coord.x(), src_coord.y(), + clk_ntwk.spine_name(ispine).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + if (use_int_driver == 1) { + continue; /* Used internal driver, early pass */ + } + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + src_node); + /* It could happen that there is no net mapped some clock pin, skip the + * net mapping */ + if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net(src_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); + } return CMD_EXEC_SUCCESS; } @@ -207,7 +171,9 @@ static int route_spine_switch_points( * - Only connect to tap points which are mapped by a global net *******************************************************************/ static int route_spine_taps( - VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, + VprRoutingAnnotation& vpr_routing_annotation, + bool& spine_usage, + const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, @@ -216,6 +182,7 @@ static int route_spine_taps( const bool& verbose) { std::vector> spine_coords = clk_ntwk.spine_coordinates(ispine); + size_t spine_tap_cnt = 0; /* Route the spine-to-IPIN connections (only for the last level) */ if (clk_ntwk.is_last_level(ispine)) { VTR_LOGV(verbose, "Routing clock taps of spine '%s'...\n", @@ -259,16 +226,127 @@ static int route_spine_taps( VTR_ASSERT(rr_graph.valid_node(des_node)); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); - if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { - vpr_routing_annotation.set_rr_node_net( - src_node, tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net( - des_node, tree2clk_pin_map.at(ipin)); - } + vpr_routing_annotation.set_rr_node_net( + src_node, tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net( + des_node, tree2clk_pin_map.at(ipin)); + /* Increment upon any required tap */ + spine_tap_cnt++; } } } } + if (spine_tap_cnt) { + spine_usage = true; + } + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Recursively route a clock spine on an existing routing resource graph + * The strategy is to route spine one by one + * - route the spine from the ending point to starting point (straight line) + * - for each stops on the staight line, route the spine-to-spine switching points + * - for each switching point (des_spine_top|bottom), go recursively + * - If the downstream spine at any switching point is not used, disconnect + * - If any stop on the spine (straght line) is not used, disconnect + * - route the spine-to-IPIN connections (only for the last level) + * + * des_spine_top[0...N] + * ^ ^ ^ ^ + * | | | | + * spine_start ---->+---->+---->+---->+->spine_end + * | | | | + * v v v v + * des_spine_bottom[0...N] + * + * <-------------------------------------------- direction to walk through + * + *******************************************************************/ +static int rec_expand_and_route_clock_spine( + VprRoutingAnnotation& vpr_routing_annotation, + bool& spine_usage, + const RRGraphView& rr_graph, + const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, + const std::map& tree2clk_pin_map, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockSpineId& curr_spine, const ClockTreePinId& curr_pin, + const bool& disable_unused_spines, + const bool& verbose) { + int status = CMD_EXEC_SUCCESS; + bool curr_spine_usage = false; + std::vector> spine_coords = + clk_ntwk.spine_coordinates(curr_spine); + /* We expand from the the ending point to starting point on the straight line. As such, it is easy to turn off spines by any stop */ + std::reverse(spine_coords.begin(), spine_coords.end()); + /* The spine should go in a straight line, connect all the stops on the line */ + for (size_t icoord = 0; icoord < spine_coords.size() - 1; ++icoord) { + vtr::Point src_coord = spine_coords[icoord + 1]; + vtr::Point des_coord = spine_coords[icoord]; + bool curr_stop_usage = false; + /* Expand on the switching point here */ + for (ClockSwitchPointId switch_point_id : + clk_ntwk.find_spine_switch_points_with_coord(curr_spine, src_coord)) { + ClockSpineId des_spine = + clk_ntwk.spine_switch_point_tap(curr_spine, switch_point_id); + /* Go recursively for the destination spine */ + bool curr_branch_usage = false; + status = rec_expand_and_route_clock_spine(vpr_routing_annotation, curr_branch_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, des_spine, curr_pin, verbose); + if (CMD_EXEC_SUCCESS != status) { + return CMD_EXEC_FATAL_ERROR; + } + /* Connect only when the destination spine is used */ + if (disable_unused_spines && !curr_branch_usage) { + VTR_LOGV(verbose, "Disconnect switching from spine '%s' to spine '%s' as downstream is not used\n", + clk_ntwk.spine_name(curr_spine).c_str(), clk_ntwk.spine_name(des_spine).c_str()); + continue; + } + curr_stop_usage = true; + /* Now connect to next spine, internal drivers may join */ + status = route_clock_spine_switch_point(vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, switch_point_id, verbose); + if (CMD_EXEC_SUCCESS != status) { + return CMD_EXEC_FATAL_ERROR; + } + } + if (disable_unused_spines && !curr_stop_usage) { + VTR_LOGV(verbose, "Disconnect backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, y=%lu) as downstream is not used\n", + clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), src_coord.y(), des_coord.x(), des_coord.y()); + continue; + } + /* Connect only when next stop is used */ + Direction src_spine_direction = clk_ntwk.spine_direction(ispine); + Direction des_spine_direction = clk_ntwk.spine_direction(ispine); + ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); + RRNodeId src_node = + clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, + src_spine_level, ipin, src_spine_direction); + RRNodeId des_node = + clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, + des_spine_level, ipin, des_spine_direction); + VTR_ASSERT(rr_graph.valid_node(src_node)); + VTR_ASSERT(rr_graph.valid_node(des_node)); + VTR_LOGV(verbose, "Routing backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, y=%lu)...\n", + clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), src_coord.y(), des_coord.x(), des_coord.y()); + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + src_node); + curr_spine_usage = true; + } + + bool curr_tap_usage = false; + /* For last level, we just connect tap points */ + status = route_spine_taps(vpr_routing_annotation, curr_tap_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, verbose); + if (CMD_EXEC_SUCCESS != status) { + return CMD_EXEC_FATAL_ERROR; + } + if (curr_tap_usage) { + curr_spine_usage = true; + } + + /* Update status */ + spine_usage = curr_spine_usage; return CMD_EXEC_SUCCESS; } @@ -287,29 +365,19 @@ static int route_clock_tree_rr_graph( const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const bool& disable_unused_trees, + const bool& disable_unused_spines, const bool& verbose) { - for (auto ispine : clk_ntwk.spines(clk_tree)) { - VTR_LOGV(verbose, "Routing spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - for (auto ipin : clk_ntwk.pins(clk_tree)) { - /* Do not route unused clock spines */ - if (disable_unused_trees && tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { - VTR_LOGV(verbose, "Skip routing backbone of unused spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - continue; - } - /* Route the spine from starting point to ending point */ - std::vector> spine_coords = - clk_ntwk.spine_coordinates(ispine); - if (CMD_EXEC_SUCCESS != route_straight_spines(vpr_routing_annotation, rr_graph, clk_rr_lookup, clk_ntwk, clk_tree, ispine, ipin, verbose)) { - return CMD_EXEC_FATAL_ERROR; - } - /* Route the opin/spine-to-spine switching points */ - if (CMD_EXEC_SUCCESS != route_spine_switch_points(vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, ispine, ipin, verbose)) { - return CMD_EXEC_FATAL_ERROR; - } - /* Route the spine-to-IPIN connections (only for the last level) */ - if (CMD_EXEC_SUCCESS != route_spine_taps(vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, ispine, ipin, verbose)) { + for (auto ipin : clk_ntwk.pins(clk_tree)) { + /* Do not route unused clock spines */ + if (disable_unused_trees && tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + VTR_LOGV(verbose, "Skip routing unused tree '%s' pin '%lu'...\n", + clk_ntwk.tree_name(clk_tree).c_str(), size_t(ipin)); + continue; + } + /* Start with the top-level spines. Recursively walk through coordinates and expand on switch points */ + for (auto top_spine : clk_ntwk.tree_top_spine(clk_tree)) { + int status = rec_expand_and_route_clock_spine(vpr_routing_annotation, spine_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, top_spine, ipin, verbose); + if (CMD_EXEC_SUCCESS != status) { return CMD_EXEC_FATAL_ERROR; } } @@ -384,7 +452,7 @@ int route_clock_rr_graph( clk_ntwk.tree_name(itree).c_str()); status = route_clock_tree_rr_graph( vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, - rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, disable_unused_trees, verbose); + rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, disable_unused_trees, disable_unused_spines, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; } From f4f487099d94db4cf855a20c76051b8e9000e254 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 15:07:48 -0700 Subject: [PATCH 060/230] [core] syntax --- .../src/annotation/route_clock_rr_graph.cpp | 25 +++++++++++-------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index cabb763c6..433de2c7f 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -150,7 +150,7 @@ static int route_clock_spine_switch_point( return CMD_EXEC_FATAL_ERROR; } if (use_int_driver == 1) { - continue; /* Used internal driver, early pass */ + return CMD_EXEC_SUCCESS; /* Used internal driver, early pass */ } vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); @@ -293,7 +293,7 @@ static int rec_expand_and_route_clock_spine( clk_ntwk.spine_switch_point_tap(curr_spine, switch_point_id); /* Go recursively for the destination spine */ bool curr_branch_usage = false; - status = rec_expand_and_route_clock_spine(vpr_routing_annotation, curr_branch_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, des_spine, curr_pin, verbose); + status = rec_expand_and_route_clock_spine(vpr_routing_annotation, curr_branch_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, des_spine, curr_pin, disable_unused_spines, verbose); if (CMD_EXEC_SUCCESS != status) { return CMD_EXEC_FATAL_ERROR; } @@ -316,16 +316,16 @@ static int rec_expand_and_route_clock_spine( continue; } /* Connect only when next stop is used */ - Direction src_spine_direction = clk_ntwk.spine_direction(ispine); - Direction des_spine_direction = clk_ntwk.spine_direction(ispine); - ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); + Direction src_spine_direction = clk_ntwk.spine_direction(curr_spine); + Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine); + ClockLevelId src_spine_level = clk_ntwk.spine_level(curr_spine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(curr_spine); RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, - src_spine_level, ipin, src_spine_direction); + src_spine_level, curr_pin, src_spine_direction); RRNodeId des_node = clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); + des_spine_level, curr_pin, des_spine_direction); VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); VTR_LOGV(verbose, "Routing backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, y=%lu)...\n", @@ -375,12 +375,17 @@ static int route_clock_tree_rr_graph( continue; } /* Start with the top-level spines. Recursively walk through coordinates and expand on switch points */ - for (auto top_spine : clk_ntwk.tree_top_spine(clk_tree)) { - int status = rec_expand_and_route_clock_spine(vpr_routing_annotation, spine_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, top_spine, ipin, verbose); + bool tree_usage = false; + for (auto top_spine : clk_ntwk.tree_top_spines(clk_tree)) { + int status = rec_expand_and_route_clock_spine(vpr_routing_annotation, tree_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, top_spine, ipin, disable_unused_spines, verbose); if (CMD_EXEC_SUCCESS != status) { return CMD_EXEC_FATAL_ERROR; } } + if (!tree_usage) { + VTR_LOGV(verbose, "Detect unused tree '%s' pin '%lu'...\n", + clk_ntwk.tree_name(clk_tree).c_str(), size_t(ipin)); + } } return CMD_EXEC_SUCCESS; } From 5a7f618f297f7ef5529f39279710e430f4f90a16 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 15:44:17 -0700 Subject: [PATCH 061/230] [core] debugging --- .../src/annotation/route_clock_rr_graph.cpp | 58 +++++++++++-------- 1 file changed, 35 insertions(+), 23 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 433de2c7f..d401e3e90 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -137,7 +137,7 @@ static int route_clock_spine_switch_point( vpr_routing_annotation.set_rr_node_net(des_node, tree2clk_pin_map.at(ipin)); use_int_driver++; - VTR_LOGV(verbose, "Routing switch points of spine '%s' at the switching point (%lu, %lu) using internal driver\n", + VTR_LOGV(verbose, "Routed switch points of spine '%s' at the switching point (%lu, %lu) using internal driver\n", clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y()); } } @@ -152,6 +152,9 @@ static int route_clock_spine_switch_point( if (use_int_driver == 1) { return CMD_EXEC_SUCCESS; /* Used internal driver, early pass */ } + VTR_LOGV(verbose, "Routed switch points of spine '%s' from (x=%lu, y=%lu) to spine '%s' at (x=%lu, y=%lu)\n", + clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y(), + clk_ntwk.spine_name(des_spine).c_str(), des_coord.x(), des_coord.y()); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); /* It could happen that there is no net mapped some clock pin, skip the @@ -224,6 +227,9 @@ static int route_spine_taps( } VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); + VTR_LOGV(verbose, + "Routed clock tap of spine '%s'\n", + clk_ntwk.spine_name(ispine).c_str()); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); vpr_routing_annotation.set_rr_node_net( @@ -277,18 +283,28 @@ static int rec_expand_and_route_clock_spine( const bool& verbose) { int status = CMD_EXEC_SUCCESS; bool curr_spine_usage = false; + bool curr_tap_usage = false; + /* For last level, we just connect tap points */ + status = route_spine_taps(vpr_routing_annotation, curr_tap_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, verbose); + if (CMD_EXEC_SUCCESS != status) { + return CMD_EXEC_FATAL_ERROR; + } + if (curr_tap_usage) { + curr_spine_usage = true; + } + std::vector> spine_coords = clk_ntwk.spine_coordinates(curr_spine); - /* We expand from the the ending point to starting point on the straight line. As such, it is easy to turn off spines by any stop */ - std::reverse(spine_coords.begin(), spine_coords.end()); - /* The spine should go in a straight line, connect all the stops on the line */ - for (size_t icoord = 0; icoord < spine_coords.size() - 1; ++icoord) { - vtr::Point src_coord = spine_coords[icoord + 1]; - vtr::Point des_coord = spine_coords[icoord]; + /* We expand from the the ending point to starting point on the straight line. + * As such, it is easy to turn off spines by any stop. + * The spine should go in a straight line, connect all the stops on the line */ + bool prev_stop_usage = false; + for (size_t icoord = spine_coords.size() - 1; icoord >= 0; --icoord) { + vtr::Point switch_point_coord = spine_coords[icoord]; bool curr_stop_usage = false; /* Expand on the switching point here */ for (ClockSwitchPointId switch_point_id : - clk_ntwk.find_spine_switch_points_with_coord(curr_spine, src_coord)) { + clk_ntwk.find_spine_switch_points_with_coord(curr_spine, switch_point_coord)) { ClockSpineId des_spine = clk_ntwk.spine_switch_point_tap(curr_spine, switch_point_id); /* Go recursively for the destination spine */ @@ -310,12 +326,18 @@ static int rec_expand_and_route_clock_spine( return CMD_EXEC_FATAL_ERROR; } } - if (disable_unused_spines && !curr_stop_usage) { - VTR_LOGV(verbose, "Disconnect backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, y=%lu) as downstream is not used\n", - clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), src_coord.y(), des_coord.x(), des_coord.y()); + if (disable_unused_spines && !curr_stop_usage && !prev_stop_usage) { + VTR_LOGV(verbose, "Disconnect backbone of spine '%s' at (x=%lu, y=%lu) as downstream is not used\n", + clk_ntwk.spine_name(curr_spine).c_str(), switch_point_coord.x(), switch_point_coord.y()); continue; } + /* Skip the first stop */ + if (icoord == 0) { + continue; + } /* Connect only when next stop is used */ + vtr::Point src_coord = spine_coords[icoord - 1]; + vtr::Point des_coord = spine_coords[icoord]; Direction src_spine_direction = clk_ntwk.spine_direction(curr_spine); Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine); ClockLevelId src_spine_level = clk_ntwk.spine_level(curr_spine); @@ -328,23 +350,13 @@ static int rec_expand_and_route_clock_spine( des_spine_level, curr_pin, des_spine_direction); VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); - VTR_LOGV(verbose, "Routing backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, y=%lu)...\n", + VTR_LOGV(verbose, "Routed backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, y=%lu)...\n", clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), src_coord.y(), des_coord.x(), des_coord.y()); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); + prev_stop_usage = true; curr_spine_usage = true; } - - bool curr_tap_usage = false; - /* For last level, we just connect tap points */ - status = route_spine_taps(vpr_routing_annotation, curr_tap_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, verbose); - if (CMD_EXEC_SUCCESS != status) { - return CMD_EXEC_FATAL_ERROR; - } - if (curr_tap_usage) { - curr_spine_usage = true; - } - /* Update status */ spine_usage = curr_spine_usage; From 53ba2f0c295eef7ed15f8215bafe2cccb0bbae76 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jun 2024 15:53:17 -0700 Subject: [PATCH 062/230] [core] fixed a critical bug where some switching points are missing --- openfpga/src/annotation/route_clock_rr_graph.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index d401e3e90..ad80d520a 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -299,7 +299,8 @@ static int rec_expand_and_route_clock_spine( * As such, it is easy to turn off spines by any stop. * The spine should go in a straight line, connect all the stops on the line */ bool prev_stop_usage = false; - for (size_t icoord = spine_coords.size() - 1; icoord >= 0; --icoord) { + std::reverse(spine_coords.begin(), spine_coords.end()); + for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { vtr::Point switch_point_coord = spine_coords[icoord]; bool curr_stop_usage = false; /* Expand on the switching point here */ @@ -332,12 +333,14 @@ static int rec_expand_and_route_clock_spine( continue; } /* Skip the first stop */ - if (icoord == 0) { + if (icoord == spine_coords.size() - 1) { continue; } /* Connect only when next stop is used */ - vtr::Point src_coord = spine_coords[icoord - 1]; + vtr::Point src_coord = spine_coords[icoord + 1]; vtr::Point des_coord = spine_coords[icoord]; + VTR_LOGV(verbose, "(icoord=%lu) Expanding on backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, y=%lu)...\n", + icoord, clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), src_coord.y(), des_coord.x(), des_coord.y()); Direction src_spine_direction = clk_ntwk.spine_direction(curr_spine); Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine); ClockLevelId src_spine_level = clk_ntwk.spine_level(curr_spine); From f5b6774eb0c1cfba6631730b6961602389869d8f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 12:21:33 -0700 Subject: [PATCH 063/230] [core] add code comments and fixed some bugs --- .../src/annotation/route_clock_rr_graph.cpp | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index ad80d520a..393740309 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -268,6 +268,21 @@ static int route_spine_taps( * des_spine_bottom[0...N] * * <-------------------------------------------- direction to walk through + * + * + * On each stop, we expand the spine to switch points and tap points + * - If the previous stop is used (connection to des_spines are required), then the current stop should be connected to the previous stop + * - If previous stop is not used, while the des_spines are required to connect, then the current stop should be connected to the previous stop + * - Only when previous stops and des_spines are not used, the current stop will be NOT connected to the previous stop + * + * des_spine_top[i] + * ^ + * | + * spine_curr_stop ---->+->spine_prev_stop + * | + * v + * des_spine_bottom[i] + * *******************************************************************/ static int rec_expand_and_route_clock_spine( @@ -303,6 +318,9 @@ static int rec_expand_and_route_clock_spine( for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { vtr::Point switch_point_coord = spine_coords[icoord]; bool curr_stop_usage = false; + if (icoord == 0) { + prev_stop_usage = true; /* The first stop is always used */ + } /* Expand on the switching point here */ for (ClockSwitchPointId switch_point_id : clk_ntwk.find_spine_switch_points_with_coord(curr_spine, switch_point_coord)) { From 1094af9f7331e2010ae05d2d3390c97eb86ba3d6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 12:38:40 -0700 Subject: [PATCH 064/230] [doc] add new options to route clock graph --- .../openfpga_commands/setup_commands.rst | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index ea2a20723..2bf9e4ccb 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -130,8 +130,17 @@ Clock signals will be auto-detected and routed based on pin constraints which ar .. option:: --pin_constraints_file or -pcf - Specify the *Pin Constraints File* (PCF) when the clock network contains multiple clock pins. For example, ``-pin_constraints_file pin_constraints.xml`` - Strongly recommend for multi-clock network. See detailed file format about :ref:`file_format_pin_constraints_file`. + Specify the *Pin Constraints File* (PCF) when the clock network contains multiple clock pins. For example, ``-pin_constraints_file pin_constraints.xml``. Strongly recommend for multi-clock network. See detailed file format about :ref:`file_format_pin_constraints_file`. + +.. note:: If there is a global net, e.g., ``clk`` or ``reset``, which will be driven by an internal resource, it should also be defined in the PCF file. + + .. option:: --disable_unused_trees + + Disable entire clock trees when they are not used by any clock nets. Useful to reduce clock power + + .. option:: --disable_unused_spines + + Disable part of the clock tree which are used by clock nets. Useful to reduce clock power .. option:: --verbose From ad5795bece97f75ccd9860c8048507d3d7b9d29a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 13:39:41 -0700 Subject: [PATCH 065/230] [test] add extra options to route clock rr_graph command in examples --- .../example_clkntwk_full_tb_script.openfpga | 2 +- .../example_clkntwk_no_ace_script.openfpga | 2 +- .../openfpga_shell_scripts/example_clkntwk_script.openfpga | 2 +- .../clock_network/homo_1clock_1reset_2layer/config/task.conf | 1 + .../homo_1clock_1reset_2layer_internal_driver/config/task.conf | 1 + .../clock_network/homo_1clock_2layer/config/task.conf | 1 + .../clock_network/homo_1clock_2layer_full_tb/config/task.conf | 1 + .../clock_network/homo_2clock_2layer/config/task.conf | 1 + 8 files changed, 8 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga index 92cd639ca..24821bc91 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga @@ -22,7 +22,7 @@ append_clock_rr_graph link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges # Route clock based on clock network definition -route_clock_rr_graph +route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga index f62d62ecc..f48be422f 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga @@ -22,7 +22,7 @@ append_clock_rr_graph link_openfpga_arch --sort_gsb_chan_node_in_edges # Route clock based on clock network definition -route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga index 83cc44860..4d9b21770 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga @@ -22,7 +22,7 @@ append_clock_rr_graph link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges # Route clock based on clock network definition -route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf index d47ef31c7..e6204e15a 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf @@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf index 6bc568fb0..a88b6c9b1 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf index b05af260f..295943e3e 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf @@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=24 openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/dummy_repack_constraints.xml openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/dummy_pin_constraints.xml +openfpga_route_clock_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf index ef0ce93fd..f42445c51 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf @@ -22,6 +22,7 @@ openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=24 +openfpga_route_clock_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf index 190ff11e0..d75606c31 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf @@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=24 openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml +openfpga_route_clock_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml From f1a4304ee75cecaf635b3e190364d0bdb8171923 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 13:43:53 -0700 Subject: [PATCH 066/230] [test] add new testcases for validate clock tree disable functions --- .../config/clk_arch_1clk_1rst_2layer.xml | 32 +++++++++++ .../config/pin_constraints_reset.xml | 7 +++ .../config/pin_constraints_resetb.xml | 7 +++ .../config/repack_pin_constraints.xml | 4 ++ .../config/task.conf | 54 +++++++++++++++++++ .../config/clk_arch_2clk_2layer.xml | 18 +++++++ .../config/pin_constraints.xml | 4 ++ .../config/repack_constraints.xml | 5 ++ .../config/task.conf | 41 ++++++++++++++ .../config/clk_arch_2clk_2layer.xml | 18 +++++++ .../config/pin_constraints.xml | 4 ++ .../config/repack_constraints.xml | 5 ++ .../config/task.conf | 41 ++++++++++++++ 13 files changed, 240 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..6c05921c7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml new file mode 100644 index 000000000..abcf209f6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..cdef2ad86 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf new file mode 100644 index 000000000..50f4280f3 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options=--disable_unused_spines + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml new file mode 100644 index 000000000..8c224318c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/pin_constraints.xml new file mode 100644 index 000000000..1989d1eea --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml new file mode 100644 index 000000000..eb0c4435a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/task.conf new file mode 100644 index 000000000..d08fcf15a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_2clk_2layer.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=24 +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml +openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml +openfpga_route_clock_options=--disable_unused_trees --disable_unused_spines + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_latch + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml new file mode 100644 index 000000000..8c224318c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/pin_constraints.xml new file mode 100644 index 000000000..1989d1eea --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml new file mode 100644 index 000000000..eb0c4435a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/task.conf new file mode 100644 index 000000000..8e58aec0c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_2clk_2layer.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=24 +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml +openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml +openfpga_route_clock_options=--disable_unused_trees + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_latch + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From f4dd222c47299604993cc00a4fbd476319b25123 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 13:45:36 -0700 Subject: [PATCH 067/230] [test] deploy new testcases to basic reg tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 20b2e3bf0..476e8c010 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -232,7 +232,10 @@ echo -e "Testing programmable clock architecture"; run-task basic_tests/clock_network/homo_1clock_2layer $@ run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ run-task basic_tests/clock_network/homo_2clock_2layer $@ +run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ +run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ run-task basic_tests/clock_network/homo_1clock_1_reset_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_disable_unused_spines $@ run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_internal_driver $@ echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; From 5cfd23747ba0d2c21c053cd20d769766202b7d20 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 13:47:03 -0700 Subject: [PATCH 068/230] [core] code format --- .../src/base/clock_network.cpp | 6 +- .../src/base/clock_network.h | 3 +- .../src/annotation/route_clock_rr_graph.cpp | 157 ++++++++++-------- .../src/annotation/route_clock_rr_graph.h | 6 +- .../src/base/openfpga_link_arch_template.h | 3 +- .../base/openfpga_setup_command_template.h | 8 +- 6 files changed, 104 insertions(+), 79 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index a34868be5..ed8e050e7 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -333,9 +333,9 @@ vtr::Point ClockNetwork::spine_switch_point( return spine_switch_coords_[spine_id][size_t(switch_point_id)]; } -std::vector ClockNetwork::find_spine_switch_points_with_coord( - const ClockSpineId& spine_id, - const vtr::Point& coord) const { +std::vector +ClockNetwork::find_spine_switch_points_with_coord( + const ClockSpineId& spine_id, const vtr::Point& coord) const { VTR_ASSERT(valid_spine_id(spine_id)); std::vector ret; for (size_t i = 0; i < spine_switch_points_[spine_id].size(); ++i) { diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 0fc15e471..2921340fd 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -127,7 +127,8 @@ class ClockNetwork { const ClockSwitchPointId& switch_point_id) const; /* Find all the switching points at a given coordinate */ - std::vector find_spine_switch_points_with_coord(const ClockSpineId& spine_id, const vtr::Point& coord) const; + std::vector find_spine_switch_points_with_coord( + const ClockSpineId& spine_id, const vtr::Point& coord) const; std::vector spine_switch_point_internal_drivers( const ClockSpineId& spine_id, diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 393740309..9fbc55747 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -84,15 +84,13 @@ static int build_clock_tree_net_map( * - connect internal driver to routing track *******************************************************************/ static int route_clock_spine_switch_point( - VprRoutingAnnotation& vpr_routing_annotation, - const RRGraphView& rr_graph, + VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const ClockSpineId& ispine, const ClockTreePinId& ipin, - const ClockSwitchPointId& switch_point_id, - const bool& verbose) { + const ClockSwitchPointId& switch_point_id, const bool& verbose) { VTR_LOGV(verbose, "Routing switch points of spine '%s'...\n", clk_ntwk.spine_name(ispine).c_str()); vtr::Point src_coord = @@ -117,8 +115,7 @@ static int route_clock_spine_switch_point( * global net is mapped to the internal driver, use it as the previous * node */ size_t use_int_driver = 0; - if (!clk_ntwk - .spine_switch_point_internal_drivers(ispine, switch_point_id) + if (!clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id) .empty() && tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { @@ -137,8 +134,11 @@ static int route_clock_spine_switch_point( vpr_routing_annotation.set_rr_node_net(des_node, tree2clk_pin_map.at(ipin)); use_int_driver++; - VTR_LOGV(verbose, "Routed switch points of spine '%s' at the switching point (%lu, %lu) using internal driver\n", - clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y()); + VTR_LOGV(verbose, + "Routed switch points of spine '%s' at the switching point " + "(%lu, %lu) using internal driver\n", + clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), + src_coord.y()); } } if (use_int_driver > 1) { @@ -152,18 +152,18 @@ static int route_clock_spine_switch_point( if (use_int_driver == 1) { return CMD_EXEC_SUCCESS; /* Used internal driver, early pass */ } - VTR_LOGV(verbose, "Routed switch points of spine '%s' from (x=%lu, y=%lu) to spine '%s' at (x=%lu, y=%lu)\n", + VTR_LOGV(verbose, + "Routed switch points of spine '%s' from (x=%lu, y=%lu) to spine " + "'%s' at (x=%lu, y=%lu)\n", clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y(), - clk_ntwk.spine_name(des_spine).c_str(), des_coord.x(), des_coord.y()); - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); + clk_ntwk.spine_name(des_spine).c_str(), des_coord.x(), + des_coord.y()); + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); /* It could happen that there is no net mapped some clock pin, skip the * net mapping */ if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { - vpr_routing_annotation.set_rr_node_net(src_node, - tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net(des_node, - tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(src_node, tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, tree2clk_pin_map.at(ipin)); } return CMD_EXEC_SUCCESS; @@ -174,15 +174,12 @@ static int route_clock_spine_switch_point( * - Only connect to tap points which are mapped by a global net *******************************************************************/ static int route_spine_taps( - VprRoutingAnnotation& vpr_routing_annotation, - bool& spine_usage, - const RRGraphView& rr_graph, - const RRClockSpatialLookup& clk_rr_lookup, + VprRoutingAnnotation& vpr_routing_annotation, bool& spine_usage, + const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, - const ClockSpineId& ispine, const ClockTreePinId& ipin, - const bool& verbose) { + const ClockSpineId& ispine, const ClockTreePinId& ipin, const bool& verbose) { std::vector> spine_coords = clk_ntwk.spine_coordinates(ispine); size_t spine_tap_cnt = 0; @@ -227,15 +224,14 @@ static int route_spine_taps( } VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); - VTR_LOGV(verbose, - "Routed clock tap of spine '%s'\n", + VTR_LOGV(verbose, "Routed clock tap of spine '%s'\n", clk_ntwk.spine_name(ispine).c_str()); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); - vpr_routing_annotation.set_rr_node_net( - src_node, tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net( - des_node, tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(src_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); /* Increment upon any required tap */ spine_tap_cnt++; } @@ -253,12 +249,13 @@ static int route_spine_taps( * Recursively route a clock spine on an existing routing resource graph * The strategy is to route spine one by one * - route the spine from the ending point to starting point (straight line) - * - for each stops on the staight line, route the spine-to-spine switching points + * - for each stops on the staight line, route the spine-to-spine switching + points * - for each switching point (des_spine_top|bottom), go recursively * - If the downstream spine at any switching point is not used, disconnect * - If any stop on the spine (straght line) is not used, disconnect * - route the spine-to-IPIN connections (only for the last level) - * + * * des_spine_top[0...N] * ^ ^ ^ ^ * | | | | @@ -271,10 +268,13 @@ static int route_spine_taps( * * * On each stop, we expand the spine to switch points and tap points - * - If the previous stop is used (connection to des_spines are required), then the current stop should be connected to the previous stop - * - If previous stop is not used, while the des_spines are required to connect, then the current stop should be connected to the previous stop - * - Only when previous stops and des_spines are not used, the current stop will be NOT connected to the previous stop - * + * - If the previous stop is used (connection to des_spines are required), then + the current stop should be connected to the previous stop + * - If previous stop is not used, while the des_spines are required to + connect, then the current stop should be connected to the previous stop + * - Only when previous stops and des_spines are not used, the current stop + will be NOT connected to the previous stop + * * des_spine_top[i] * ^ * | @@ -286,21 +286,20 @@ static int route_spine_taps( * *******************************************************************/ static int rec_expand_and_route_clock_spine( - VprRoutingAnnotation& vpr_routing_annotation, - bool& spine_usage, - const RRGraphView& rr_graph, - const RRClockSpatialLookup& clk_rr_lookup, + VprRoutingAnnotation& vpr_routing_annotation, bool& spine_usage, + const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const ClockSpineId& curr_spine, const ClockTreePinId& curr_pin, - const bool& disable_unused_spines, - const bool& verbose) { + const bool& disable_unused_spines, const bool& verbose) { int status = CMD_EXEC_SUCCESS; bool curr_spine_usage = false; bool curr_tap_usage = false; /* For last level, we just connect tap points */ - status = route_spine_taps(vpr_routing_annotation, curr_tap_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, verbose); + status = route_spine_taps(vpr_routing_annotation, curr_tap_usage, rr_graph, + clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, + clk_ntwk, clk_tree, curr_spine, curr_pin, verbose); if (CMD_EXEC_SUCCESS != status) { return CMD_EXEC_FATAL_ERROR; } @@ -312,7 +311,8 @@ static int rec_expand_and_route_clock_spine( clk_ntwk.spine_coordinates(curr_spine); /* We expand from the the ending point to starting point on the straight line. * As such, it is easy to turn off spines by any stop. - * The spine should go in a straight line, connect all the stops on the line */ + * The spine should go in a straight line, connect all the stops on the line + */ bool prev_stop_usage = false; std::reverse(spine_coords.begin(), spine_coords.end()); for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { @@ -323,33 +323,46 @@ static int rec_expand_and_route_clock_spine( } /* Expand on the switching point here */ for (ClockSwitchPointId switch_point_id : - clk_ntwk.find_spine_switch_points_with_coord(curr_spine, switch_point_coord)) { + clk_ntwk.find_spine_switch_points_with_coord(curr_spine, + switch_point_coord)) { ClockSpineId des_spine = clk_ntwk.spine_switch_point_tap(curr_spine, switch_point_id); /* Go recursively for the destination spine */ bool curr_branch_usage = false; - status = rec_expand_and_route_clock_spine(vpr_routing_annotation, curr_branch_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, des_spine, curr_pin, disable_unused_spines, verbose); + status = rec_expand_and_route_clock_spine( + vpr_routing_annotation, curr_branch_usage, rr_graph, clk_rr_lookup, + rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, des_spine, + curr_pin, disable_unused_spines, verbose); if (CMD_EXEC_SUCCESS != status) { return CMD_EXEC_FATAL_ERROR; } /* Connect only when the destination spine is used */ if (disable_unused_spines && !curr_branch_usage) { - VTR_LOGV(verbose, "Disconnect switching from spine '%s' to spine '%s' as downstream is not used\n", - clk_ntwk.spine_name(curr_spine).c_str(), clk_ntwk.spine_name(des_spine).c_str()); + VTR_LOGV(verbose, + "Disconnect switching from spine '%s' to spine '%s' as " + "downstream is not used\n", + clk_ntwk.spine_name(curr_spine).c_str(), + clk_ntwk.spine_name(des_spine).c_str()); continue; - } + } curr_stop_usage = true; /* Now connect to next spine, internal drivers may join */ - status = route_clock_spine_switch_point(vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, switch_point_id, verbose); + status = route_clock_spine_switch_point( + vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, + tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, + switch_point_id, verbose); if (CMD_EXEC_SUCCESS != status) { return CMD_EXEC_FATAL_ERROR; } } if (disable_unused_spines && !curr_stop_usage && !prev_stop_usage) { - VTR_LOGV(verbose, "Disconnect backbone of spine '%s' at (x=%lu, y=%lu) as downstream is not used\n", - clk_ntwk.spine_name(curr_spine).c_str(), switch_point_coord.x(), switch_point_coord.y()); + VTR_LOGV(verbose, + "Disconnect backbone of spine '%s' at (x=%lu, y=%lu) as " + "downstream is not used\n", + clk_ntwk.spine_name(curr_spine).c_str(), switch_point_coord.x(), + switch_point_coord.y()); continue; - } + } /* Skip the first stop */ if (icoord == spine_coords.size() - 1) { continue; @@ -357,8 +370,11 @@ static int rec_expand_and_route_clock_spine( /* Connect only when next stop is used */ vtr::Point src_coord = spine_coords[icoord + 1]; vtr::Point des_coord = spine_coords[icoord]; - VTR_LOGV(verbose, "(icoord=%lu) Expanding on backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, y=%lu)...\n", - icoord, clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), src_coord.y(), des_coord.x(), des_coord.y()); + VTR_LOGV(verbose, + "(icoord=%lu) Expanding on backbone of spine '%s' from (x=%lu, " + "y=%lu) to (x=%lu, y=%lu)...\n", + icoord, clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), + src_coord.y(), des_coord.x(), des_coord.y()); Direction src_spine_direction = clk_ntwk.spine_direction(curr_spine); Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine); ClockLevelId src_spine_level = clk_ntwk.spine_level(curr_spine); @@ -371,15 +387,17 @@ static int rec_expand_and_route_clock_spine( des_spine_level, curr_pin, des_spine_direction); VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); - VTR_LOGV(verbose, "Routed backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, y=%lu)...\n", - clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), src_coord.y(), des_coord.x(), des_coord.y()); - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - src_node); + VTR_LOGV(verbose, + "Routed backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, " + "y=%lu)...\n", + clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), + src_coord.y(), des_coord.x(), des_coord.y()); + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); prev_stop_usage = true; curr_spine_usage = true; } /* Update status */ - spine_usage = curr_spine_usage; + spine_usage = curr_spine_usage; return CMD_EXEC_SUCCESS; } @@ -397,20 +415,24 @@ static int route_clock_tree_rr_graph( const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, - const bool& disable_unused_trees, - const bool& disable_unused_spines, + const bool& disable_unused_trees, const bool& disable_unused_spines, const bool& verbose) { for (auto ipin : clk_ntwk.pins(clk_tree)) { /* Do not route unused clock spines */ - if (disable_unused_trees && tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { + if (disable_unused_trees && + tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { VTR_LOGV(verbose, "Skip routing unused tree '%s' pin '%lu'...\n", clk_ntwk.tree_name(clk_tree).c_str(), size_t(ipin)); continue; } - /* Start with the top-level spines. Recursively walk through coordinates and expand on switch points */ + /* Start with the top-level spines. Recursively walk through coordinates and + * expand on switch points */ bool tree_usage = false; for (auto top_spine : clk_ntwk.tree_top_spines(clk_tree)) { - int status = rec_expand_and_route_clock_spine(vpr_routing_annotation, tree_usage, rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, top_spine, ipin, disable_unused_spines, verbose); + int status = rec_expand_and_route_clock_spine( + vpr_routing_annotation, tree_usage, rr_graph, clk_rr_lookup, + rr_node_gnets, tree2clk_pin_map, clk_ntwk, clk_tree, top_spine, ipin, + disable_unused_spines, verbose); if (CMD_EXEC_SUCCESS != status) { return CMD_EXEC_FATAL_ERROR; } @@ -435,10 +457,8 @@ int route_clock_rr_graph( const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& disable_unused_trees, - const bool& disable_unused_spines, - const bool& verbose) { + const PinConstraints& pin_constraints, const bool& disable_unused_trees, + const bool& disable_unused_spines, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Route programmable clock network based on routing resource graph"); @@ -490,7 +510,8 @@ int route_clock_rr_graph( clk_ntwk.tree_name(itree).c_str()); status = route_clock_tree_rr_graph( vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, - rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, disable_unused_trees, disable_unused_spines, verbose); + rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, disable_unused_trees, + disable_unused_spines, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; } diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index 13bff0eea..ee962d6d4 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -24,10 +24,8 @@ int route_clock_rr_graph( const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& disable_unused_trees, - const bool& disable_unused_spines, - const bool& verbose); + const PinConstraints& pin_constraints, const bool& disable_unused_trees, + const bool& disable_unused_spines, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index e0fec4742..24971105c 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -220,7 +220,8 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, /* add an option '--pin_constraints_file in short '-pcf' */ CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); CommandOptionId opt_disable_unused_trees = cmd.option("disable_unused_trees"); - CommandOptionId opt_disable_unused_spines = cmd.option("disable_unused_spines"); + CommandOptionId opt_disable_unused_spines = + cmd.option("disable_unused_spines"); CommandOptionId opt_verbose = cmd.option("verbose"); /* If pin constraints are enabled by command options, read the file */ diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 169d3cf9a..53e43f00f 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -710,8 +710,12 @@ ShellCommandId add_route_clock_rr_graph_command_template( shell_cmd.set_option_short_name(opt_file, "pcf"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - shell_cmd.add_option("disable_unused_trees", false, "Disable entire clock trees when they are not used by any clock nets. Useful to reduce clock power"); - shell_cmd.add_option("disable_unused_spines", false, "Disable part of the clock tree which are used by clock nets. Useful to reduce clock power"); + shell_cmd.add_option("disable_unused_trees", false, + "Disable entire clock trees when they are not used by " + "any clock nets. Useful to reduce clock power"); + shell_cmd.add_option("disable_unused_spines", false, + "Disable part of the clock tree which are used by clock " + "nets. Useful to reduce clock power"); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); From e0b9f7860b0dc7b7c4aa1ea79c341b54b02af792 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 14:10:14 -0700 Subject: [PATCH 069/230] [core] fixed a bug where counter for gnets are not activated --- openfpga/src/annotation/openfpga_annotate_routing.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index ad84d86e2..cfbb064ef 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -47,6 +47,7 @@ vtr::vector annotate_rr_node_global_net( layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin); for (RRNodeId curr_rr_node : curr_rr_nodes) { rr_node_nets[curr_rr_node] = net_id; + counter++; } } } From 0de3ff3eb8e7bad68ce6fea76778cb95ab97f3f6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 17:16:33 -0700 Subject: [PATCH 070/230] [core] debugging --- openfpga/src/annotation/route_clock_rr_graph.cpp | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 9fbc55747..f380fed6a 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -185,8 +185,8 @@ static int route_spine_taps( size_t spine_tap_cnt = 0; /* Route the spine-to-IPIN connections (only for the last level) */ if (clk_ntwk.is_last_level(ispine)) { - VTR_LOGV(verbose, "Routing clock taps of spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); + VTR_LOGV(verbose, "Routing clock taps of spine '%s' for pin '%d' of tree '%s'...\n", + clk_ntwk.spine_name(ispine).c_str(), size_t(ipin), clk_ntwk.tree_name(clk_tree).c_str()); /* Connect to any fan-out node which is IPIN */ for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { vtr::Point src_coord = spine_coords[icoord]; @@ -198,6 +198,8 @@ static int route_spine_taps( for (RREdgeId edge : rr_graph.edge_range(src_node)) { RRNodeId des_node = rr_graph.edge_sink_node(edge); if (rr_graph.node_type(des_node) == IPIN) { + VTR_LOGV(verbose, "Trying to route to IPIN '%s'\n", + rr_graph.node_coordinate_to_string(des_node).c_str()); /* Check if the IPIN is mapped, if not, do not connect */ /* if the IPIN is mapped, only connect when net mapping is * expected */ @@ -393,6 +395,13 @@ static int rec_expand_and_route_clock_spine( clk_ntwk.spine_name(curr_spine).c_str(), src_coord.x(), src_coord.y(), des_coord.x(), des_coord.y()); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); + /* It could happen that there is no net mapped some clock pin, skip the + * net mapping */ + if (tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net(src_node, tree2clk_pin_map.at(curr_pin)); + vpr_routing_annotation.set_rr_node_net(des_node, tree2clk_pin_map.at(curr_pin)); + } + prev_stop_usage = true; curr_spine_usage = true; } From 1c693659386840055821a351bbf31a3e8abce762 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 18:17:38 -0700 Subject: [PATCH 071/230] [core] debugging --- .../src/annotation/route_clock_rr_graph.cpp | 58 ++++++++----------- .../src/annotation/route_clock_rr_graph.h | 4 +- .../src/base/openfpga_link_arch_template.h | 4 +- .../openfpga_clustered_netlist_utils.cpp | 35 +++++++++++ .../utils/openfpga_clustered_netlist_utils.h | 24 ++++++++ .../config/pin_constraints_reset.xml | 1 + .../config/pin_constraints_resetb.xml | 1 + 7 files changed, 88 insertions(+), 39 deletions(-) create mode 100644 openfpga/src/utils/openfpga_clustered_netlist_utils.cpp create mode 100644 openfpga/src/utils/openfpga_clustered_netlist_utils.h diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index f380fed6a..7b10262fa 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -2,7 +2,7 @@ #include "command_exit_codes.h" #include "openfpga_annotate_routing.h" -#include "openfpga_atom_netlist_utils.h" +#include "openfpga_clustered_netlist_utils.h" #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_log.h" @@ -22,27 +22,26 @@ namespace openfpga { static int build_clock_tree_net_map( std::map& tree2clk_pin_map, const ClusteredNetlist& cluster_nlist, const PinConstraints& pin_constraints, - const std::vector& clk_names, const ClockNetwork& clk_ntwk, + const std::vector& gnets, const ClockNetwork& clk_ntwk, const ClockTreeId clk_tree, const bool& verbose) { /* Find the pin id for each clock name, error out if there is any mismatch */ - if (clk_names.size() == 1 && clk_ntwk.tree_width(clk_tree) == 1) { + if (clk_ntwk.num_trees() == 1 && gnets.size() == 1 && clk_ntwk.tree_width(clk_tree) == 1) { /* Find cluster net id */ - ClusterNetId clk_net = cluster_nlist.find_net(clk_names[0]); - if (!cluster_nlist.valid_net_id(clk_net)) { - VTR_LOG_ERROR("Invalid clock name '%s'! Cannot found from netlists!\n", - clk_names[0].c_str()); + if (!cluster_nlist.valid_net_id(gnets[0])) { + VTR_LOG_ERROR("Invalid clock name '%s'! Cannot be found from netlists!\n", + cluster_nlist.net_name(gnets[0]).c_str()); return CMD_EXEC_FATAL_ERROR; } - tree2clk_pin_map[ClockTreePinId(0)] = clk_net; + tree2clk_pin_map[ClockTreePinId(0)] = gnets[0]; } else { - for (std::string clk_name : clk_names) { + for (ClusterNetId gnet : gnets) { /* Find the pin information that the net should be mapped to */ - BasicPort tree_pin = pin_constraints.net_pin(clk_name); + std::string gnet_name = cluster_nlist.net_name(gnet); + BasicPort tree_pin = pin_constraints.net_pin(gnet_name); if (!tree_pin.is_valid()) { VTR_LOG_ERROR( - "Invalid tree pin for clock '%s'! Clock name may not be valid " - "(mismatched with netlists)!\n", - clk_name.c_str()); + "Global net '%s' is not mapped to a valid pin '%s' in pin constraints!\n", + gnet_name.c_str(), tree_pin.to_verilog_string().c_str()); return CMD_EXEC_FATAL_ERROR; } if (tree_pin.get_width() != 1) { @@ -50,7 +49,7 @@ static int build_clock_tree_net_map( "Invalid tree pin %s[%lu:%lu] for clock '%s'! Clock pin must have " "only a width of 1!\n", tree_pin.get_name().c_str(), tree_pin.get_lsb(), tree_pin.get_msb(), - clk_name.c_str()); + gnet_name.c_str()); return CMD_EXEC_FATAL_ERROR; } if (tree_pin.get_lsb() >= clk_ntwk.tree_width(clk_tree)) { @@ -60,15 +59,8 @@ static int build_clock_tree_net_map( clk_ntwk.tree_width(clk_tree)); return CMD_EXEC_FATAL_ERROR; } - /* Find cluster net id */ - ClusterNetId clk_net = cluster_nlist.find_net(clk_name); - if (!cluster_nlist.valid_net_id(clk_net)) { - VTR_LOG_ERROR("Invalid clock name '%s'! Cannot found from netlists!\n", - clk_name.c_str()); - return CMD_EXEC_FATAL_ERROR; - } /* Register the pin mapping */ - tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = clk_net; + tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = gnet; } } @@ -462,9 +454,8 @@ static int route_clock_tree_rr_graph( *******************************************************************/ int route_clock_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, + const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, - const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, const PinConstraints& pin_constraints, const bool& disable_unused_trees, const bool& disable_unused_spines, const bool& verbose) { @@ -479,21 +470,20 @@ int route_clock_rr_graph( return CMD_EXEC_SUCCESS; } - /* If there are multiple clock signals from the netlist, require pin + /* If there are multiple global signals from the netlist, require pin * constraints */ - std::vector clock_net_names = - find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); - if (clock_net_names.empty()) { + std::vector gnets = find_clustered_netlist_global_nets(cluster_nlist); + if (gnets.empty()) { VTR_LOG( - "Skip due to 0 clocks found from netlist\nDouble check your HDL design " + "Skip due to 0 global nets found from netlist\nDouble check your HDL design " "if this is unexpected\n"); return CMD_EXEC_SUCCESS; } - if (clock_net_names.size() > 1 && pin_constraints.empty()) { + if (gnets.size() > 1 && pin_constraints.empty()) { VTR_LOG( - "There is %lu clock nets (more than 1). Require pin constraints to be " + "There is %lu global nets (more than 1). Require pin constraints to be " "specified\n", - clock_net_names.size()); + gnets.size()); return CMD_EXEC_FATAL_ERROR; } @@ -504,13 +494,13 @@ int route_clock_rr_graph( /* Route spines one by one */ for (auto itree : clk_ntwk.trees()) { - VTR_LOGV(verbose, "Build clock name to clock tree '%s' pin mapping...\n", + VTR_LOGV(verbose, "Build global net name to clock tree '%s' pin mapping...\n", clk_ntwk.tree_name(itree).c_str()); std::map tree2clk_pin_map; int status = CMD_EXEC_SUCCESS; status = build_clock_tree_net_map(tree2clk_pin_map, cluster_nlist, pin_constraints, - clock_net_names, clk_ntwk, itree, verbose); + gnets, clk_ntwk, itree, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; } diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index ee962d6d4..443e3d11b 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -8,7 +8,6 @@ #include "pin_constraints.h" #include "rr_clock_spatial_lookup.h" #include "vpr_context.h" -#include "vpr_netlist_annotation.h" #include "vpr_routing_annotation.h" /******************************************************************** @@ -20,9 +19,8 @@ namespace openfpga { int route_clock_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, + const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, - const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, const PinConstraints& pin_constraints, const bool& disable_unused_trees, const bool& disable_unused_spines, const bool& verbose); diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index 24971105c..cfb5b430f 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -233,8 +233,8 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, return route_clock_rr_graph( openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), - g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), - openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.clock_rr_lookup(), + g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), + openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, cmd_context.option_enable(cmd, opt_disable_unused_trees), cmd_context.option_enable(cmd, opt_disable_unused_spines), diff --git a/openfpga/src/utils/openfpga_clustered_netlist_utils.cpp b/openfpga/src/utils/openfpga_clustered_netlist_utils.cpp new file mode 100644 index 000000000..e4823b873 --- /dev/null +++ b/openfpga/src/utils/openfpga_clustered_netlist_utils.cpp @@ -0,0 +1,35 @@ +/*************************************************************************************** + * This file includes most utilized functions that are used to acquire data from + * VPR clustered netlist (post-packing netlist) + ***************************************************************************************/ + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from vtrutil library */ +#include "openfpga_clustered_netlist_utils.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/*************************************************************************************** + * Find the names of all the atom blocks that drive clock nets + * This function will find if the block has been renamed due to contain + *sensitive characters that violates the Verilog syntax + ***************************************************************************************/ +std::vector find_clustered_netlist_global_nets( + const ClusteredNetlist& clb_nlist) { + std::vector gnets; + + for (ClusterNetId net_id : clb_nlist.nets()) { + if (clb_nlist.net_is_ignored(net_id)) { + gnets.push_back(net_id); + } + } + + return gnets; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/utils/openfpga_clustered_netlist_utils.h b/openfpga/src/utils/openfpga_clustered_netlist_utils.h new file mode 100644 index 000000000..252bd99f4 --- /dev/null +++ b/openfpga/src/utils/openfpga_clustered_netlist_utils.h @@ -0,0 +1,24 @@ +#ifndef OPENFPGA_CLUSTERED_NETLIST_UTILS_H +#define OPENFPGA_CLUSTERED_NETLIST_UTILS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include + +#include "clustered_netlist.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +std::vector find_clustered_netlist_global_nets( + const ClusteredNetlist& clb_nlist); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml index abcf209f6..3788a1411 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml @@ -3,5 +3,6 @@ - the reset signal to the op_reset[0] port of the FPGA fabric --> + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml index cdef2ad86..1311926f5 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml @@ -3,5 +3,6 @@ - the reset signal to the op_reset[0] port of the FPGA fabric --> + From 8bc37080fa492047b4231b21bafc71e62a9ab89e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 28 Jun 2024 23:06:21 -0700 Subject: [PATCH 072/230] [core] debuggging --- openfpga/src/annotation/route_clock_rr_graph.cpp | 4 +++- .../clock_network/homo_1clock_1reset_2layer/config/task.conf | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 7b10262fa..01b780ed5 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -59,6 +59,7 @@ static int build_clock_tree_net_map( clk_ntwk.tree_width(clk_tree)); return CMD_EXEC_FATAL_ERROR; } + /* TODO: Check the tree_pin.get_name(), see if matches the tree from ports */ /* Register the pin mapping */ tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = gnet; } @@ -457,7 +458,8 @@ int route_clock_rr_graph( const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, const bool& disable_unused_trees, + const PinConstraints& pin_constraints, + const bool& disable_unused_trees, const bool& disable_unused_spines, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Route programmable clock network based on routing resource graph"); diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf index e6204e15a..04489c15e 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf @@ -42,11 +42,11 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter -bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml bench0_openfpga_verilog_testbench_port_mapping= bench1_top = counter -bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml bench1_openfpga_verilog_testbench_port_mapping= [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 67554cb8d84c0760b15c75ff93fc2ad4232c9918 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 10:04:03 -0700 Subject: [PATCH 073/230] [test] now use correct pcf for clock network testcases --- .../config/pin_constraints_reset.xml | 1 + .../config/pin_constraints_resetb.xml | 1 + .../config/task.conf | 4 ++-- .../config/pin_constraints_reset.xml | 1 + .../config/pin_constraints_resetb.xml | 1 + .../config/task.conf | 4 ++-- 6 files changed, 8 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml index abcf209f6..3788a1411 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml @@ -3,5 +3,6 @@ - the reset signal to the op_reset[0] port of the FPGA fabric --> + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml index cdef2ad86..1311926f5 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml @@ -3,5 +3,6 @@ - the reset signal to the op_reset[0] port of the FPGA fabric --> + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf index 50f4280f3..f0fe1b077 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf @@ -42,11 +42,11 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter -bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml bench0_openfpga_verilog_testbench_port_mapping= bench1_top = counter -bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml bench1_openfpga_verilog_testbench_port_mapping= [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml index abcf209f6..3788a1411 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml @@ -3,5 +3,6 @@ - the reset signal to the op_reset[0] port of the FPGA fabric --> + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml index cdef2ad86..1311926f5 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml @@ -3,5 +3,6 @@ - the reset signal to the op_reset[0] port of the FPGA fabric --> + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf index a88b6c9b1..70565880f 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -42,11 +42,11 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter -bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml bench0_openfpga_verilog_testbench_port_mapping= bench1_top = counter -bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml bench1_openfpga_verilog_testbench_port_mapping= [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 34fb00391116b68808385bf0f6b7bd3d81b4ba8e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 10:46:00 -0700 Subject: [PATCH 074/230] [core] replace width syntax with global port name --- libs/libclkarchopenfpga/arch/example.xml | 2 +- .../arch/example_internal_drivers.xml | 2 +- .../src/base/clock_network.cpp | 19 +++++++++++++++---- .../src/base/clock_network.h | 6 ++++-- .../src/io/clock_network_xml_constants.h | 2 +- .../src/io/read_xml_clock_network.cpp | 11 ++++++----- .../src/io/write_xml_clock_network.cpp | 4 ++-- 7 files changed, 30 insertions(+), 16 deletions(-) diff --git a/libs/libclkarchopenfpga/arch/example.xml b/libs/libclkarchopenfpga/arch/example.xml index 9cb31bdc6..9ba53a2f7 100644 --- a/libs/libclkarchopenfpga/arch/example.xml +++ b/libs/libclkarchopenfpga/arch/example.xml @@ -1,5 +1,5 @@ - + diff --git a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml index 7a46a2094..6215ba443 100644 --- a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml +++ b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml @@ -1,5 +1,5 @@ - + diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index ed8e050e7..1d3ab5b47 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -217,9 +217,14 @@ size_t ClockNetwork::max_tree_depth() const { return max_size; } +BasicPort ClockNetwork::tree_global_port(const ClockTreeId& tree_id) const { + VTR_ASSERT(valid_tree_id(tree_id)); + return tree_global_ports_[tree_id]; +} + size_t ClockNetwork::tree_width(const ClockTreeId& tree_id) const { VTR_ASSERT(valid_tree_id(tree_id)); - return tree_widths_[tree_id]; + return tree_global_ports_[tree_id].get_width(); } size_t ClockNetwork::tree_depth(const ClockTreeId& tree_id) const { @@ -606,7 +611,7 @@ void ClockNetwork::reserve_spines(const size_t& num_spines) { void ClockNetwork::reserve_trees(const size_t& num_trees) { tree_ids_.reserve(num_trees); tree_names_.reserve(num_trees); - tree_widths_.reserve(num_trees); + tree_global_ports_.reserve(num_trees); tree_top_spines_.reserve(num_trees); tree_taps_.reserve(num_trees); } @@ -635,13 +640,19 @@ void ClockNetwork::set_default_driver_switch_name(const std::string& name) { default_driver_switch_name_ = name; } -ClockTreeId ClockNetwork::create_tree(const std::string& name, size_t width) { +ClockTreeId ClockNetwork::create_tree(const std::string& name, const BasicPort& global_port) { + /* Sanity checks */ + if (!global_port.is_valid()) { + VTR_LOG_ERROR("Invalid global port '%s' for clock tree name '%s'\n", + global_port.to_verilog_string().c_str(), name.c_str()); + exit(1); + } /* Create a new id */ ClockTreeId tree_id = ClockTreeId(tree_ids_.size()); tree_ids_.push_back(tree_id); tree_names_.push_back(name); - tree_widths_.push_back(width); + tree_global_ports_.push_back(global_port); tree_depths_.emplace_back(); tree_taps_.emplace_back(); tree_top_spines_.emplace_back(); diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 2921340fd..7775b6fbf 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -16,6 +16,7 @@ #include "clock_network_fwd.h" #include "rr_graph_fwd.h" #include "rr_node_types.h" +#include "openfpga_port.h" namespace openfpga { // Begin namespace openfpga @@ -87,6 +88,7 @@ class ClockNetwork { RRSwitchId default_driver_switch() const; std::string default_driver_switch_name() const; std::string tree_name(const ClockTreeId& tree_id) const; + BasicPort tree_global_port(const ClockTreeId& tree_id) const; size_t tree_width(const ClockTreeId& tree_id) const; size_t tree_depth(const ClockTreeId& tree_id) const; size_t max_tree_width() const; @@ -196,7 +198,7 @@ class ClockNetwork { void set_default_driver_switch_name(const std::string& name); /* Create a new tree, by default the tree can accomodate only 1 clock signal; * use width to adjust the size */ - ClockTreeId create_tree(const std::string& name, size_t width = 1); + ClockTreeId create_tree(const std::string& name, const BasicPort& global_port); /* Create a new spine, if the spine is already created, return an invalid id */ ClockSpineId create_spine(const std::string& name); @@ -289,7 +291,7 @@ class ClockNetwork { /* Basic information of each tree */ vtr::vector tree_ids_; vtr::vector tree_names_; - vtr::vector tree_widths_; + vtr::vector tree_global_ports_; vtr::vector tree_depths_; vtr::vector> tree_top_spines_; vtr::vector> tree_taps_; diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index cfa5c306d..a63141870 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -12,7 +12,7 @@ constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_DRIVER_SWITCH = "default_driver_switch"; constexpr const char* XML_CLOCK_TREE_NODE_NAME = "clock_network"; constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_NAME = "name"; -constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_WIDTH = "width"; +constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT = "global_port"; constexpr const char* XML_CLOCK_SPINE_NODE_NAME = "spine"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_NAME = "name"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_START_X = "start_x"; diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 492649788..84aea0587 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -338,14 +338,15 @@ static void read_xml_clock_tree(pugi::xml_node& xml_clk_tree, const pugiutil::loc_data& loc_data, ClockNetwork& clk_ntwk) { std::string clk_tree_name = - get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data) + get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data, pugiutil::ReqOpt::REQUIRED) + .as_string(); + std::string clk_global_port_str = + get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, loc_data, pugiutil::ReqOpt::REQUIRED) .as_string(); - int clk_tree_width = - get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_WIDTH, loc_data) - .as_int(); /* Create a new tree in the storage */ - ClockTreeId tree_id = clk_ntwk.create_tree(clk_tree_name, clk_tree_width); + PortParser gport_parser(clk_global_port_str); + ClockTreeId tree_id = clk_ntwk.create_tree(clk_tree_name, gport_parser.port()); if (false == clk_ntwk.valid_tree_id(tree_id)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_clk_tree), diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index cdcc12ecf..5ef8e4d3d 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -194,8 +194,8 @@ static int write_xml_clock_tree(std::fstream& fp, const ClockNetwork& clk_ntwk, write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_NAME, clk_ntwk.tree_name(tree_id).c_str()); - write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_WIDTH, - clk_ntwk.tree_width(tree_id)); + write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, + clk_ntwk.tree_global_port(tree_id).to_verilog_string().c_str()); fp << ">" << "\n"; From 5fa674be24157bed2d88bb2f8f764914994b61ff Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 10:51:45 -0700 Subject: [PATCH 075/230] [core] fixed the bug on matching global net from pcf --- openfpga/src/annotation/route_clock_rr_graph.cpp | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 01b780ed5..8918f0b2b 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -24,6 +24,7 @@ static int build_clock_tree_net_map( const ClusteredNetlist& cluster_nlist, const PinConstraints& pin_constraints, const std::vector& gnets, const ClockNetwork& clk_ntwk, const ClockTreeId clk_tree, const bool& verbose) { + BasicPort tree_gport = clk_ntwk.tree_global_port(clk_tree); /* Find the pin id for each clock name, error out if there is any mismatch */ if (clk_ntwk.num_trees() == 1 && gnets.size() == 1 && clk_ntwk.tree_width(clk_tree) == 1) { /* Find cluster net id */ @@ -37,6 +38,7 @@ static int build_clock_tree_net_map( for (ClusterNetId gnet : gnets) { /* Find the pin information that the net should be mapped to */ std::string gnet_name = cluster_nlist.net_name(gnet); + /* The pin should match be global port name of the tree */ BasicPort tree_pin = pin_constraints.net_pin(gnet_name); if (!tree_pin.is_valid()) { VTR_LOG_ERROR( @@ -52,11 +54,15 @@ static int build_clock_tree_net_map( gnet_name.c_str()); return CMD_EXEC_FATAL_ERROR; } - if (tree_pin.get_lsb() >= clk_ntwk.tree_width(clk_tree)) { + if (tree_gport.get_name() != tree_pin.get_name()) { + continue; + } + if (!tree_gport.contained(tree_pin)) { VTR_LOG_ERROR( - "Invalid tree pin %s[%lu] is out of range of clock tree size '%lu'\n", - tree_pin.get_name().c_str(), tree_pin.get_lsb(), - clk_ntwk.tree_width(clk_tree)); + "Invalid pin constraint port '%s' which is out of range of the global port '%s' of clock tree '%s'\n", + tree_pin.to_verilog_string().c_str(), + tree_gport.to_verilog_string().c_str(), + clk_ntwk.tree_name(clk_tree).c_str()); return CMD_EXEC_FATAL_ERROR; } /* TODO: Check the tree_pin.get_name(), see if matches the tree from ports */ From 4f787a5cfc5545539d62fb591c93357069299f92 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 10:54:08 -0700 Subject: [PATCH 076/230] [core] add more debugging message --- openfpga/src/annotation/route_clock_rr_graph.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 8918f0b2b..fb4afda93 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -68,6 +68,8 @@ static int build_clock_tree_net_map( /* TODO: Check the tree_pin.get_name(), see if matches the tree from ports */ /* Register the pin mapping */ tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = gnet; + VTR_LOGV(verbose, "Mapped net '%s' to pin '%s' of clock tree '%s'.\n", + gnet_name.c_str(), tree_pin.to_verilog_string().c_str(), clk_ntwk.tree_name(clk_tree).c_str()); } } From 286df309471a73934e1b6b778f5a33fe1a20c218 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 11:02:17 -0700 Subject: [PATCH 077/230] [test] update clock arch xml syntax --- .../config/clk_arch_1clk_1rst_2layer.xml | 8 ++++---- .../config/clk_arch_1clk_1rst_2layer.xml | 8 ++++---- .../config/clk_arch_1clk_1rst_2layer_int_driver.xml | 8 ++++---- .../homo_1clock_2layer/config/clk_arch_1clk_2layer.xml | 2 +- .../config/clk_arch_1clk_2layer.xml | 2 +- .../homo_2clock_2layer/config/clk_arch_2clk_2layer.xml | 2 +- .../config/clk_arch_2clk_2layer.xml | 2 +- .../config/clk_arch_2clk_2layer.xml | 2 +- 8 files changed, 17 insertions(+), 17 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml index 6c05921c7..3f499fedf 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml @@ -1,5 +1,5 @@ - + @@ -11,10 +11,10 @@ - + - + @@ -26,7 +26,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml index 6c05921c7..3f499fedf 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml @@ -1,5 +1,5 @@ - + @@ -11,10 +11,10 @@ - + - + @@ -26,7 +26,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml index ed43a26b5..c88e8ccd4 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml @@ -1,5 +1,5 @@ - + @@ -19,10 +19,10 @@ - + - + @@ -34,7 +34,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml index 7a41f1216..6f289dbf4 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml @@ -1,5 +1,5 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml index 7a41f1216..6f289dbf4 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml @@ -1,5 +1,5 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml index 8c224318c..98e91d27a 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml @@ -1,5 +1,5 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml index 8c224318c..98e91d27a 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml @@ -1,5 +1,5 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml index 8c224318c..98e91d27a 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml @@ -1,5 +1,5 @@ - + From bc2f02866d056aa6dea27260d98c26a2d75a3cd2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 17:17:05 -0700 Subject: [PATCH 078/230] [test] update testcase for 2-clk on programmable clock network --- .../openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml | 4 ++-- .../homo_2clock_2layer/config/clk_arch_2clk_2layer.xml | 4 ++-- openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml index 90109d00b..66aa9b4b3 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml @@ -173,8 +173,8 @@ - - + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml index 98e91d27a..ff5734d10 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml @@ -11,8 +11,8 @@ - - + + diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml index f4e40b275..231aef08b 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml @@ -59,7 +59,7 @@ - + @@ -250,7 +250,7 @@ - + From 5dd0549aed60c162dc1150aa270821104f995a12 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 17:17:54 -0700 Subject: [PATCH 079/230] [core] typo --- .../homo_2clock_2layer/config/clk_arch_2clk_2layer.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml index ff5734d10..3ef33c270 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml @@ -11,8 +11,8 @@ - - + + From 1fd974d544ef421a1cc087c889031e0ab84600f9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 17:35:47 -0700 Subject: [PATCH 080/230] [core] fixed a bug where clock network size cannot impact global port on top module --- libs/libarchopenfpga/src/tile_annotation.cpp | 6 +++++ libs/libarchopenfpga/src/tile_annotation.h | 2 ++ .../fabric/build_top_module_connection.cpp | 24 ++++++++++++------- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/libs/libarchopenfpga/src/tile_annotation.cpp b/libs/libarchopenfpga/src/tile_annotation.cpp index 2ffacd1d0..c6c71c4b2 100644 --- a/libs/libarchopenfpga/src/tile_annotation.cpp +++ b/libs/libarchopenfpga/src/tile_annotation.cpp @@ -96,6 +96,12 @@ size_t TileAnnotation::global_port_default_value( return global_port_default_values_[global_port_id]; } +bool TileAnnotation::global_port_thru_dedicated_network( + const TileGlobalPortId& global_port_id) const { + return !global_port_clock_arch_tree_name(global_port_id).empty(); +} + + std::string TileAnnotation::global_port_clock_arch_tree_name( const TileGlobalPortId& global_port_id) const { VTR_ASSERT(valid_global_port_id(global_port_id)); diff --git a/libs/libarchopenfpga/src/tile_annotation.h b/libs/libarchopenfpga/src/tile_annotation.h index 36af8a9b4..f2f3f3d75 100644 --- a/libs/libarchopenfpga/src/tile_annotation.h +++ b/libs/libarchopenfpga/src/tile_annotation.h @@ -54,6 +54,8 @@ class TileAnnotation { bool global_port_is_clock(const TileGlobalPortId& global_port_id) const; bool global_port_is_set(const TileGlobalPortId& global_port_id) const; bool global_port_is_reset(const TileGlobalPortId& global_port_id) const; + bool global_port_thru_dedicated_network( + const TileGlobalPortId& global_port_id) const; std::string global_port_clock_arch_tree_name( const TileGlobalPortId& global_port_id) const; size_t global_port_default_value( diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 84c901945..e0c86ab17 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1242,11 +1242,11 @@ static int build_top_module_global_net_from_clock_arch_tree( if (clk_ntwk.tree_width(clk_tree) != module_manager.module_port(top_module, top_module_port).get_width()) { VTR_LOG( - "Clock tree '%s' does not have the same width '%lu' as the port '%'s of " + "Clock tree '%s' does not have the same width '%lu' as the port '%s' of " "FPGA top module", clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree), module_manager.module_port(top_module, top_module_port) - .get_name() + .to_verilog_string() .c_str()); return CMD_EXEC_FATAL_ERROR; } @@ -1323,12 +1323,19 @@ int add_top_module_global_ports_from_grid_modules( BasicPort global_port_to_add; global_port_to_add.set_name( tile_annotation.global_port_name(tile_global_port)); - size_t max_port_size = 0; - for (const BasicPort& tile_port : - tile_annotation.global_port_tile_ports(tile_global_port)) { - max_port_size = std::max(tile_port.get_width(), max_port_size); + /* Dedicated network has their own sizes of port */ + if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) { + std::string clk_tree_name = tile_annotation.global_port_clock_arch_tree_name(tile_global_port); + ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name); + global_port_to_add.set_width(clk_ntwk.tree_width(clk_tree)); + } else { + size_t max_port_size = 0; + for (const BasicPort& tile_port : + tile_annotation.global_port_tile_ports(tile_global_port)) { + max_port_size = std::max(tile_port.get_width(), max_port_size); + } + global_port_to_add.set_width(max_port_size); } - global_port_to_add.set_width(max_port_size); global_ports_to_add.push_back(global_port_to_add); } } @@ -1352,8 +1359,7 @@ int add_top_module_global_ports_from_grid_modules( * - If the net will be directly wired to tiles, the net will drive an input * of a tile */ - if (!tile_annotation.global_port_clock_arch_tree_name(tile_global_port) - .empty()) { + if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) { status = build_top_module_global_net_from_clock_arch_tree( module_manager, top_module, top_module_port, rr_graph, device_rr_gsb, cb_instance_ids, clk_ntwk, From 12c9686c27d99fb460bfd9ad9bd3bac6b33a42ab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 17:38:34 -0700 Subject: [PATCH 081/230] [test] fixed some bugs on arch --- .../openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml | 2 +- .../homo_2clock_2layer/config/repack_constraints.xml | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml index 66aa9b4b3..91dd34815 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml @@ -173,7 +173,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml index eb0c4435a..f32f6afde 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml @@ -1,5 +1,4 @@ - From 28e3cb799e3b2eaa2a429b3148686f0ddb5c42cf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 29 Jun 2024 17:40:20 -0700 Subject: [PATCH 082/230] [test] update 2-clock arch and pcf --- .../config/clk_arch_2clk_2layer.xml | 2 +- .../config/repack_constraints.xml | 1 - .../config/clk_arch_2clk_2layer.xml | 2 +- .../config/repack_constraints.xml | 1 - 4 files changed, 2 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml index 98e91d27a..3ef33c270 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml @@ -12,7 +12,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml index eb0c4435a..f32f6afde 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml @@ -1,5 +1,4 @@ - diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml index 98e91d27a..3ef33c270 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml @@ -12,7 +12,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml index eb0c4435a..f32f6afde 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml @@ -1,5 +1,4 @@ - From 3afb92d6a5f5c92294fbdf0481eb732086473f9a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 30 Jun 2024 22:48:15 -0700 Subject: [PATCH 083/230] [core] code format --- libs/libarchopenfpga/src/tile_annotation.cpp | 1 - .../src/base/clock_network.cpp | 3 +- .../src/base/clock_network.h | 5 +- .../src/io/read_xml_clock_network.cpp | 11 +++-- .../src/io/write_xml_clock_network.cpp | 5 +- .../src/annotation/route_clock_rr_graph.cpp | 49 ++++++++++++------- .../src/annotation/route_clock_rr_graph.h | 4 +- .../src/base/openfpga_link_arch_template.h | 3 +- .../fabric/build_top_module_connection.cpp | 6 ++- 9 files changed, 52 insertions(+), 35 deletions(-) diff --git a/libs/libarchopenfpga/src/tile_annotation.cpp b/libs/libarchopenfpga/src/tile_annotation.cpp index c6c71c4b2..77adcff18 100644 --- a/libs/libarchopenfpga/src/tile_annotation.cpp +++ b/libs/libarchopenfpga/src/tile_annotation.cpp @@ -101,7 +101,6 @@ bool TileAnnotation::global_port_thru_dedicated_network( return !global_port_clock_arch_tree_name(global_port_id).empty(); } - std::string TileAnnotation::global_port_clock_arch_tree_name( const TileGlobalPortId& global_port_id) const { VTR_ASSERT(valid_global_port_id(global_port_id)); diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 1d3ab5b47..6f254530b 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -640,7 +640,8 @@ void ClockNetwork::set_default_driver_switch_name(const std::string& name) { default_driver_switch_name_ = name; } -ClockTreeId ClockNetwork::create_tree(const std::string& name, const BasicPort& global_port) { +ClockTreeId ClockNetwork::create_tree(const std::string& name, + const BasicPort& global_port) { /* Sanity checks */ if (!global_port.is_valid()) { VTR_LOG_ERROR("Invalid global port '%s' for clock tree name '%s'\n", diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 7775b6fbf..242720dce 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -14,9 +14,9 @@ /* Headers from openfpgautil library */ #include "clock_network_fwd.h" +#include "openfpga_port.h" #include "rr_graph_fwd.h" #include "rr_node_types.h" -#include "openfpga_port.h" namespace openfpga { // Begin namespace openfpga @@ -198,7 +198,8 @@ class ClockNetwork { void set_default_driver_switch_name(const std::string& name); /* Create a new tree, by default the tree can accomodate only 1 clock signal; * use width to adjust the size */ - ClockTreeId create_tree(const std::string& name, const BasicPort& global_port); + ClockTreeId create_tree(const std::string& name, + const BasicPort& global_port); /* Create a new spine, if the spine is already created, return an invalid id */ ClockSpineId create_spine(const std::string& name); diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 84aea0587..4d47ad18e 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -338,15 +338,18 @@ static void read_xml_clock_tree(pugi::xml_node& xml_clk_tree, const pugiutil::loc_data& loc_data, ClockNetwork& clk_ntwk) { std::string clk_tree_name = - get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data, pugiutil::ReqOpt::REQUIRED) + get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data, + pugiutil::ReqOpt::REQUIRED) .as_string(); std::string clk_global_port_str = - get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, loc_data, pugiutil::ReqOpt::REQUIRED) + get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, loc_data, + pugiutil::ReqOpt::REQUIRED) .as_string(); /* Create a new tree in the storage */ - PortParser gport_parser(clk_global_port_str); - ClockTreeId tree_id = clk_ntwk.create_tree(clk_tree_name, gport_parser.port()); + PortParser gport_parser(clk_global_port_str); + ClockTreeId tree_id = + clk_ntwk.create_tree(clk_tree_name, gport_parser.port()); if (false == clk_ntwk.valid_tree_id(tree_id)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_clk_tree), diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 5ef8e4d3d..3473a6350 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -194,8 +194,9 @@ static int write_xml_clock_tree(std::fstream& fp, const ClockNetwork& clk_ntwk, write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_NAME, clk_ntwk.tree_name(tree_id).c_str()); - write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, - clk_ntwk.tree_global_port(tree_id).to_verilog_string().c_str()); + write_xml_attribute( + fp, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, + clk_ntwk.tree_global_port(tree_id).to_verilog_string().c_str()); fp << ">" << "\n"; diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index fb4afda93..0be7cdf84 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -26,7 +26,8 @@ static int build_clock_tree_net_map( const ClockTreeId clk_tree, const bool& verbose) { BasicPort tree_gport = clk_ntwk.tree_global_port(clk_tree); /* Find the pin id for each clock name, error out if there is any mismatch */ - if (clk_ntwk.num_trees() == 1 && gnets.size() == 1 && clk_ntwk.tree_width(clk_tree) == 1) { + if (clk_ntwk.num_trees() == 1 && gnets.size() == 1 && + clk_ntwk.tree_width(clk_tree) == 1) { /* Find cluster net id */ if (!cluster_nlist.valid_net_id(gnets[0])) { VTR_LOG_ERROR("Invalid clock name '%s'! Cannot be found from netlists!\n", @@ -42,7 +43,8 @@ static int build_clock_tree_net_map( BasicPort tree_pin = pin_constraints.net_pin(gnet_name); if (!tree_pin.is_valid()) { VTR_LOG_ERROR( - "Global net '%s' is not mapped to a valid pin '%s' in pin constraints!\n", + "Global net '%s' is not mapped to a valid pin '%s' in pin " + "constraints!\n", gnet_name.c_str(), tree_pin.to_verilog_string().c_str()); return CMD_EXEC_FATAL_ERROR; } @@ -59,17 +61,20 @@ static int build_clock_tree_net_map( } if (!tree_gport.contained(tree_pin)) { VTR_LOG_ERROR( - "Invalid pin constraint port '%s' which is out of range of the global port '%s' of clock tree '%s'\n", + "Invalid pin constraint port '%s' which is out of range of the " + "global port '%s' of clock tree '%s'\n", tree_pin.to_verilog_string().c_str(), tree_gport.to_verilog_string().c_str(), clk_ntwk.tree_name(clk_tree).c_str()); return CMD_EXEC_FATAL_ERROR; } - /* TODO: Check the tree_pin.get_name(), see if matches the tree from ports */ + /* TODO: Check the tree_pin.get_name(), see if matches the tree from ports + */ /* Register the pin mapping */ tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = gnet; VTR_LOGV(verbose, "Mapped net '%s' to pin '%s' of clock tree '%s'.\n", - gnet_name.c_str(), tree_pin.to_verilog_string().c_str(), clk_ntwk.tree_name(clk_tree).c_str()); + gnet_name.c_str(), tree_pin.to_verilog_string().c_str(), + clk_ntwk.tree_name(clk_tree).c_str()); } } @@ -186,8 +191,10 @@ static int route_spine_taps( size_t spine_tap_cnt = 0; /* Route the spine-to-IPIN connections (only for the last level) */ if (clk_ntwk.is_last_level(ispine)) { - VTR_LOGV(verbose, "Routing clock taps of spine '%s' for pin '%d' of tree '%s'...\n", - clk_ntwk.spine_name(ispine).c_str(), size_t(ipin), clk_ntwk.tree_name(clk_tree).c_str()); + VTR_LOGV(verbose, + "Routing clock taps of spine '%s' for pin '%d' of tree '%s'...\n", + clk_ntwk.spine_name(ispine).c_str(), size_t(ipin), + clk_ntwk.tree_name(clk_tree).c_str()); /* Connect to any fan-out node which is IPIN */ for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { vtr::Point src_coord = spine_coords[icoord]; @@ -397,11 +404,13 @@ static int rec_expand_and_route_clock_spine( src_coord.y(), des_coord.x(), des_coord.y()); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); /* It could happen that there is no net mapped some clock pin, skip the - * net mapping */ - if (tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { - vpr_routing_annotation.set_rr_node_net(src_node, tree2clk_pin_map.at(curr_pin)); - vpr_routing_annotation.set_rr_node_net(des_node, tree2clk_pin_map.at(curr_pin)); - } + * net mapping */ + if (tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net(src_node, + tree2clk_pin_map.at(curr_pin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(curr_pin)); + } prev_stop_usage = true; curr_spine_usage = true; @@ -463,11 +472,10 @@ static int route_clock_tree_rr_graph( *******************************************************************/ int route_clock_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, + const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& disable_unused_trees, + const PinConstraints& pin_constraints, const bool& disable_unused_trees, const bool& disable_unused_spines, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Route programmable clock network based on routing resource graph"); @@ -482,10 +490,12 @@ int route_clock_rr_graph( /* If there are multiple global signals from the netlist, require pin * constraints */ - std::vector gnets = find_clustered_netlist_global_nets(cluster_nlist); + std::vector gnets = + find_clustered_netlist_global_nets(cluster_nlist); if (gnets.empty()) { VTR_LOG( - "Skip due to 0 global nets found from netlist\nDouble check your HDL design " + "Skip due to 0 global nets found from netlist\nDouble check your HDL " + "design " "if this is unexpected\n"); return CMD_EXEC_SUCCESS; } @@ -504,7 +514,8 @@ int route_clock_rr_graph( /* Route spines one by one */ for (auto itree : clk_ntwk.trees()) { - VTR_LOGV(verbose, "Build global net name to clock tree '%s' pin mapping...\n", + VTR_LOGV(verbose, + "Build global net name to clock tree '%s' pin mapping...\n", clk_ntwk.tree_name(itree).c_str()); std::map tree2clk_pin_map; int status = CMD_EXEC_SUCCESS; diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index 443e3d11b..2bd4ec178 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -19,8 +19,8 @@ namespace openfpga { int route_clock_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, + const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, const PinConstraints& pin_constraints, const bool& disable_unused_trees, const bool& disable_unused_spines, const bool& verbose); diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index cfb5b430f..bb061de09 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -234,8 +234,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, return route_clock_rr_graph( openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), - openfpga_ctx.clock_rr_lookup(), - openfpga_ctx.clock_arch(), pin_constraints, + openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, cmd_context.option_enable(cmd, opt_disable_unused_trees), cmd_context.option_enable(cmd, opt_disable_unused_spines), cmd_context.option_enable(cmd, opt_verbose)); diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index e0c86ab17..e6a98cd46 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1324,8 +1324,10 @@ int add_top_module_global_ports_from_grid_modules( global_port_to_add.set_name( tile_annotation.global_port_name(tile_global_port)); /* Dedicated network has their own sizes of port */ - if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) { - std::string clk_tree_name = tile_annotation.global_port_clock_arch_tree_name(tile_global_port); + if (tile_annotation.global_port_thru_dedicated_network( + tile_global_port)) { + std::string clk_tree_name = + tile_annotation.global_port_clock_arch_tree_name(tile_global_port); ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name); global_port_to_add.set_width(clk_ntwk.tree_width(clk_tree)); } else { From 18e2b994ac88497ba568ddf156c2cb8bb87b1aab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 30 Jun 2024 22:56:31 -0700 Subject: [PATCH 084/230] [doc] update syntax on clock network file --- docs/source/manual/arch_lang/annotate_vpr_arch.rst | 3 +++ docs/source/manual/file_formats/clock_network.rst | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst index 9fd1024a7..cd119f69a 100644 --- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst +++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst @@ -79,6 +79,7 @@ For subtile port merge support (see an illustrative example in :numref:`fig_subt .. note:: When defined, the given port of all the subtiles of a tile will be merged into one port. For example, a tile consists of 8 subtile ``A`` and 6 subtile ``B`` and all the subtiles have a port ``clk``, in the FPGA fabric, all the ``clk`` of the subtiles ``A`` and ``B`` will be wired to a common port ``clk`` at tile level. +.. note:: Note that when a dedicated clock network is defined, the size of the global port will follow the ``global_port`` defined in the clock network description file (See details in :ref:`file_formats_clock_network`) .. note:: When merged, the port will have a default side of ``TOP`` and index of ``0`` on all the attributes, such as width, height etc. @@ -99,6 +100,8 @@ For global port support: - ``clock_arch_tree_name=""`` defines the name of the programmable clock network, which the global port will drive. The name of the programmable clock network must be a valid name (See details in :ref:`file_formats_clock_network`) +.. note:: ``clock_arch_tree_name`` is applicable to clock, reset and set signals. + - ``is_reset=""`` define if the global port is a reset port at the top-level FPGA fabric. An operating reset port will be driven by proper signals in testbenches. - ``is_set=""`` define if the global port is a set port at the top-level FPGA fabric. An operating set port will be driven by proper signals in testbenches. diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index da359f400..5979c2f24 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -23,7 +23,7 @@ Using the clock network description language, users can define multiple clock ne .. code-block:: xml - + @@ -107,9 +107,9 @@ where the clock network is used to drive the global clock pin ``clk0`` in OpenFP -.. option:: width="" +.. option:: global_port="" - The maximum number of clock pins that a clock network can drive. + Define the source port of the clock network. For example, ``clk[0:7]``. Note that the global port name should match the ``from_pin`` when defining the tap points (See details in :ref:`file_formats_clock_network_clock_tap_point`). .. _file_formats_clock_network_clock_spine: From e00709411208bac8f216b00ead2db836dd98b7a5 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 1 Jul 2024 06:06:57 +0000 Subject: [PATCH 085/230] Bump yosys from `07daf61` to `a739e21` Bumps [yosys](https://github.com/YosysHQ/yosys) from `07daf61` to `a739e21`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/07daf61ae6fbe935b582a24c13e863b7d52052bd...a739e21a5f3b4fdd888d4c62f1578a1300c43f00) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 07daf61ae..a739e21a5 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 07daf61ae6fbe935b582a24c13e863b7d52052bd +Subproject commit a739e21a5f3b4fdd888d4c62f1578a1300c43f00 From 24e28298990d3ab83e12c39f8b42c15951ae6d95 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 1 Jul 2024 23:26:27 +0000 Subject: [PATCH 086/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 492aa9035..98319eb52 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2286 +1.2.2290 From 7c487eadc90a38381cef980326154b315e4403f9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 16:58:23 -0700 Subject: [PATCH 087/230] [core] now clock network keep port info in a native data structure --- libs/libclkarchopenfpga/src/base/clock_network.cpp | 12 +++++------- libs/libclkarchopenfpga/src/base/clock_network.h | 6 +++--- .../src/io/read_xml_clock_network.cpp | 9 ++++++--- .../src/io/write_xml_clock_network.cpp | 6 +++--- 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 6f254530b..e95df9f68 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -372,7 +372,7 @@ std::vector ClockNetwork::tree_taps( return tree_taps_[tree_id]; } -std::string ClockNetwork::tap_from_port(const ClockTapId& tap_id) const { +BasicPort ClockNetwork::tap_from_port(const ClockTapId& tap_id) const { VTR_ASSERT(valid_tap_id(tap_id)); return tap_from_ports_[tap_id]; } @@ -470,17 +470,15 @@ std::vector ClockNetwork::tree_flatten_tap_to_ports( for (ClockTapId tap_id : tree_taps_[tree_id]) { VTR_ASSERT(valid_tap_id(tap_id)); /* Filter out unmatched from ports. Expect [clk_pin_id:clk_pin_id] */ - std::string tap_from_port_name = tap_from_ports_[tap_id]; - PortParser from_port_parser(tap_from_port_name); - BasicPort from_port = from_port_parser.port(); + BasicPort from_port = tap_from_ports_[tap_id]; if (!from_port.is_valid()) { VTR_LOG_ERROR("Invalid from port name '%s' whose index is not valid\n", - tap_from_port_name.c_str()); + from_port.to_verilog_string().c_str()); exit(1); } if (from_port.get_width() != 1) { VTR_LOG_ERROR("Invalid from port name '%s' whose width is not 1\n", - tap_from_port_name.c_str()); + from_port.to_verilog_string().c_str()); exit(1); } if (from_port.get_lsb() != size_t(clk_pin_id)) { @@ -792,7 +790,7 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( } ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, - const std::string& from_port, + const BasicPort& from_port, const std::string& to_port) { VTR_ASSERT(valid_tree_id(tree_id)); /* TODO: Consider find existing tap template and avoid duplication in storage diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 242720dce..ebfcbf038 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -144,7 +144,7 @@ class ClockNetwork { */ std::vector tree_taps(const ClockTreeId& tree_id) const; /* Return the source ports for a given tap */ - std::string tap_from_port(const ClockTapId& tap_id) const; + BasicPort tap_from_port(const ClockTapId& tap_id) const; /* Return the destination ports for a given tap */ std::string tap_to_port(const ClockTapId& tap_id) const; /* Find the type of tap point: @@ -224,7 +224,7 @@ class ClockNetwork { const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, const std::string& internal_driver_port); ClockTapId add_tree_tap(const ClockTreeId& tree_id, - const std::string& from_port, + const BasicPort& from_port, const std::string& to_port); bool set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect& bb); @@ -319,7 +319,7 @@ class ClockNetwork { vtr::vector internal_driver_ports_; /* Basic information about tap */ vtr::vector tap_ids_; - vtr::vector tap_from_ports_; + vtr::vector tap_from_ports_; vtr::vector tap_to_ports_; vtr::vector> tap_bbs_; /* Bounding box for tap points, (xlow, ylow) -> (xhigh, yhigh) */ diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 4d47ad18e..c56b152fd 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -42,7 +42,8 @@ static void read_xml_clock_tree_tap_type_all(pugi::xml_node& xml_tap, std::string to_pin_name = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) .as_string(); - clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + PortParser from_port_parser(from_pin_name); + clk_ntwk.add_tree_tap(tree_id, from_port_parser.port(), to_pin_name); } /******************************************************************** @@ -62,8 +63,9 @@ static void read_xml_clock_tree_tap_type_single( std::string to_pin_name = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) .as_string(); + PortParser from_port_parser(from_pin_name); ClockTapId tap_id = - clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + clk_ntwk.add_tree_tap(tree_id, from_port_parser.port(), to_pin_name); /* Single tap only require a coordinate */ size_t tap_x = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, @@ -93,8 +95,9 @@ static void read_xml_clock_tree_tap_type_region( std::string to_pin_name = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data) .as_string(); + PortParser from_port_parser(from_pin_name); ClockTapId tap_id = - clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name); + clk_ntwk.add_tree_tap(tree_id, from_port_parser.port(), to_pin_name); /* Region require a bounding box */ size_t tap_start_x = diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 3473a6350..fbdea521d 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -35,7 +35,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_ALL_NODE_NAME << ""; write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).c_str()); + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); fp << "/>" @@ -46,7 +46,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).c_str()); + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, @@ -61,7 +61,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).c_str()); + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, From df23daf0265eb318494da155e1a8b3dfb8bbef61 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 17:37:16 -0700 Subject: [PATCH 088/230] [lib] sanity check on global port name and from pin name of tap points --- .../src/base/clock_network.cpp | 19 ++++++++++++++++++- .../src/base/clock_network.h | 1 + 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index e95df9f68..440870f29 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -859,6 +859,23 @@ bool ClockNetwork::link() { return true; } +bool ClockNetwork::validate_tree_taps() const { + for (ClockTreeId tree_id : trees()) { + for (ClockTapId tap_id : tree_taps(tree_id)) { + /* The from pin name should match the global port */ + if (!tree_global_port(tree_id).mergeable(tap_from_port(tap_id)) || !tree_global_port(tree_id).contained(tap_from_port(tap_id))) { + VTR_LOG_ERROR( + "Tap point from_port '%s' is not part of the global port '%s' of tree '%s'\n", + tap_from_port(tap_id).to_verilog_string().c_str(), + tree_global_port(tree_id).to_verilog_string().c_str(), + tree_name(tree_id).c_str()); + return false; + } + } + } + return true; +} + bool ClockNetwork::validate_tree() const { for (ClockTreeId tree_id : trees()) { for (ClockSpineId spine_id : spines(tree_id)) { @@ -920,7 +937,7 @@ bool ClockNetwork::validate_tree() const { bool ClockNetwork::validate() const { is_dirty_ = true; if (default_segment_id_ && default_tap_switch_id_ && - default_driver_switch_id_ && validate_tree()) { + default_driver_switch_id_ && validate_tree() && validate_tree_taps()) { is_dirty_ = false; } return true; diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index ebfcbf038..ffec611df 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -266,6 +266,7 @@ class ClockNetwork { private: /* Public invalidators/validators */ /* Ensure tree data is clean. All the spines are valid, and switch points are * valid */ + bool validate_tree_taps() const; bool validate_tree() const; /* Show if the internal driver id is a valid for data queries */ bool valid_internal_driver_id( From 70428fd969c57016203bf797b183632be17482e8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 17:56:29 -0700 Subject: [PATCH 089/230] [lib] add sanity checks on global port name and clock network's global port name --- .../src/utils/clock_network_utils.cpp | 26 +++++++++++++++++++ .../src/utils/clock_network_utils.h | 4 +++ .../src/base/openfpga_read_arch_template.h | 6 +++++ 3 files changed, 36 insertions(+) diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp index 3d82f9c23..449352403 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp @@ -96,4 +96,30 @@ int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, return status; } +/** Check for each global ports in tile annotation + * If a clock tree is required for a global port, the global port name define in the tile annotation should match the one in clock clock + */ +int check_clock_network_tile_annotation(const ClockNetwork& clk_ntwk, + const TileAnnotation& tile_annotation) { + for (const TileGlobalPortId& gport_id : tile_annotation.global_ports()) { + if (!tile_annotation.global_port_thru_dedicated_network(gport_id)) { + continue; + } + std::string gport_name = tile_annotation.global_port_name(gport_id); + std::string clk_tree_name = tile_annotation.global_port_clock_arch_tree_name(gport_id); + ClockTreeId clk_tree_id = clk_ntwk.find_tree(clk_tree_name); + if (!clk_ntwk.valid_tree_id(clk_tree_id)) { + VTR_LOG_ERROR("Invalid clock tree name '%s' defined for global port '%s' in tile annotation! Must be a valid name defined in the clock network description!\n", + clk_tree_name.c_str(), gport_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + if (clk_ntwk.tree_global_port(clk_tree_id).get_name() != gport_name) { + VTR_LOG_ERROR("Global port '%s' of clock tree name '%s' must match the name of assoicated global port '%s' in tile annotation! Must be a valid name defined in the clock network description!\n", + clk_ntwk.tree_global_port(clk_tree_id).to_verilog_string().c_str(), clk_tree_name.c_str(), gport_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + } + return CMD_EXEC_SUCCESS; +} + } // End of namespace openfpga diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.h b/libs/libclkarchopenfpga/src/utils/clock_network_utils.h index 0a266c188..f87c80a53 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.h +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.h @@ -6,6 +6,7 @@ *******************************************************************/ #include "clock_network.h" #include "rr_graph_view.h" +#include "tile_annotation.h" /******************************************************************** * Function declaration @@ -16,6 +17,9 @@ namespace openfpga { // Begin namespace openfpga int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, const RRGraphView& rr_graph); +int check_clock_network_tile_annotation(const ClockNetwork& clk_ntwk, + const TileAnnotation& tile_annotation); + } // End of namespace openfpga #endif diff --git a/openfpga/src/base/openfpga_read_arch_template.h b/openfpga/src/base/openfpga_read_arch_template.h index 4ee895977..e0dd9dd34 100644 --- a/openfpga/src/base/openfpga_read_arch_template.h +++ b/openfpga/src/base/openfpga_read_arch_template.h @@ -246,6 +246,12 @@ int read_openfpga_clock_arch_template(T& openfpga_context, const Command& cmd, VTR_LOG_ERROR("Link clock network to routing architecture failed!"); return CMD_EXEC_FATAL_ERROR; } + if (CMD_EXEC_SUCCESS != + check_clock_network_tile_annotation(openfpga_context.clock_arch(), + openfpga_context.arch().tile_annotations)) { + VTR_LOG_ERROR("Check clock network consistency with tile annotation failed!"); + return CMD_EXEC_FATAL_ERROR; + } /* Ensure clean data */ openfpga_context.clock_arch().validate(); if (!openfpga_context.clock_arch().is_valid()) { From a85a6f1674171909caceb485295f7a2cd7f10380 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 17:57:10 -0700 Subject: [PATCH 090/230] [core] code format --- .../src/base/clock_network.cpp | 6 ++++-- .../src/io/write_xml_clock_network.cpp | 15 +++++++------ .../src/utils/clock_network_utils.cpp | 21 +++++++++++++------ .../src/base/openfpga_read_arch_template.h | 9 ++++---- 4 files changed, 33 insertions(+), 18 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 440870f29..2889876ab 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -863,9 +863,11 @@ bool ClockNetwork::validate_tree_taps() const { for (ClockTreeId tree_id : trees()) { for (ClockTapId tap_id : tree_taps(tree_id)) { /* The from pin name should match the global port */ - if (!tree_global_port(tree_id).mergeable(tap_from_port(tap_id)) || !tree_global_port(tree_id).contained(tap_from_port(tap_id))) { + if (!tree_global_port(tree_id).mergeable(tap_from_port(tap_id)) || + !tree_global_port(tree_id).contained(tap_from_port(tap_id))) { VTR_LOG_ERROR( - "Tap point from_port '%s' is not part of the global port '%s' of tree '%s'\n", + "Tap point from_port '%s' is not part of the global port '%s' of " + "tree '%s'\n", tap_from_port(tap_id).to_verilog_string().c_str(), tree_global_port(tree_id).to_verilog_string().c_str(), tree_name(tree_id).c_str()); diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index fbdea521d..1e03bc0ba 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -34,8 +34,9 @@ static int write_xml_clock_tree_taps(std::fstream& fp, case ClockNetwork::e_tap_type::ALL: { openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_ALL_NODE_NAME << ""; - write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); + write_xml_attribute( + fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); fp << "/>" @@ -45,8 +46,9 @@ static int write_xml_clock_tree_taps(std::fstream& fp, case ClockNetwork::e_tap_type::SINGLE: { openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; - write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); + write_xml_attribute( + fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, @@ -60,8 +62,9 @@ static int write_xml_clock_tree_taps(std::fstream& fp, case ClockNetwork::e_tap_type::REGION: { openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; - write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); + write_xml_attribute( + fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp index 449352403..6f78b26fe 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp @@ -97,7 +97,8 @@ int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, } /** Check for each global ports in tile annotation - * If a clock tree is required for a global port, the global port name define in the tile annotation should match the one in clock clock + * If a clock tree is required for a global port, the global port name define + * in the tile annotation should match the one in clock clock */ int check_clock_network_tile_annotation(const ClockNetwork& clk_ntwk, const TileAnnotation& tile_annotation) { @@ -106,16 +107,24 @@ int check_clock_network_tile_annotation(const ClockNetwork& clk_ntwk, continue; } std::string gport_name = tile_annotation.global_port_name(gport_id); - std::string clk_tree_name = tile_annotation.global_port_clock_arch_tree_name(gport_id); + std::string clk_tree_name = + tile_annotation.global_port_clock_arch_tree_name(gport_id); ClockTreeId clk_tree_id = clk_ntwk.find_tree(clk_tree_name); if (!clk_ntwk.valid_tree_id(clk_tree_id)) { - VTR_LOG_ERROR("Invalid clock tree name '%s' defined for global port '%s' in tile annotation! Must be a valid name defined in the clock network description!\n", - clk_tree_name.c_str(), gport_name.c_str()); + VTR_LOG_ERROR( + "Invalid clock tree name '%s' defined for global port '%s' in tile " + "annotation! Must be a valid name defined in the clock network " + "description!\n", + clk_tree_name.c_str(), gport_name.c_str()); return CMD_EXEC_FATAL_ERROR; } if (clk_ntwk.tree_global_port(clk_tree_id).get_name() != gport_name) { - VTR_LOG_ERROR("Global port '%s' of clock tree name '%s' must match the name of assoicated global port '%s' in tile annotation! Must be a valid name defined in the clock network description!\n", - clk_ntwk.tree_global_port(clk_tree_id).to_verilog_string().c_str(), clk_tree_name.c_str(), gport_name.c_str()); + VTR_LOG_ERROR( + "Global port '%s' of clock tree name '%s' must match the name of " + "assoicated global port '%s' in tile annotation! Must be a valid name " + "defined in the clock network description!\n", + clk_ntwk.tree_global_port(clk_tree_id).to_verilog_string().c_str(), + clk_tree_name.c_str(), gport_name.c_str()); return CMD_EXEC_FATAL_ERROR; } } diff --git a/openfpga/src/base/openfpga_read_arch_template.h b/openfpga/src/base/openfpga_read_arch_template.h index e0dd9dd34..346deae5f 100644 --- a/openfpga/src/base/openfpga_read_arch_template.h +++ b/openfpga/src/base/openfpga_read_arch_template.h @@ -246,10 +246,11 @@ int read_openfpga_clock_arch_template(T& openfpga_context, const Command& cmd, VTR_LOG_ERROR("Link clock network to routing architecture failed!"); return CMD_EXEC_FATAL_ERROR; } - if (CMD_EXEC_SUCCESS != - check_clock_network_tile_annotation(openfpga_context.clock_arch(), - openfpga_context.arch().tile_annotations)) { - VTR_LOG_ERROR("Check clock network consistency with tile annotation failed!"); + if (CMD_EXEC_SUCCESS != check_clock_network_tile_annotation( + openfpga_context.clock_arch(), + openfpga_context.arch().tile_annotations)) { + VTR_LOG_ERROR( + "Check clock network consistency with tile annotation failed!"); return CMD_EXEC_FATAL_ERROR; } /* Ensure clean data */ From 1bfcf7574c2e130dd492deca354597b210cceef3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 20:33:28 -0700 Subject: [PATCH 091/230] [test] validate region and single syntax --- .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/clk_arch_1clk_1rst_2layer.xml | 36 +++++++++++++ .../config/pin_constraints_reset.xml | 8 +++ .../config/pin_constraints_resetb.xml | 8 +++ .../config/repack_pin_constraints.xml | 4 ++ .../config/task.conf | 54 +++++++++++++++++++ 6 files changed, 111 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_resetb.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 476e8c010..f8742d781 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -235,6 +235,7 @@ run-task basic_tests/clock_network/homo_2clock_2layer $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ run-task basic_tests/clock_network/homo_1clock_1_reset_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_syntax $@ run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_disable_unused_spines $@ run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_internal_driver $@ diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..ccdc3bc46 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf new file mode 100644 index 000000000..04489c15e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From e00312d29e627fa62fbf4d0f8c1e54a3d4dbe356 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 20:34:37 -0700 Subject: [PATCH 092/230] [test] typo --- .../config/clk_arch_1clk_1rst_2layer.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml index ccdc3bc46..41a1aed69 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml @@ -11,7 +11,7 @@ - + @@ -28,7 +28,7 @@ - + From 60e6e27e54872a1172853234cd1cb27c23ec458a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 20:45:55 -0700 Subject: [PATCH 093/230] [core] fixed a bug on tap point identificatin --- libs/libclkarchopenfpga/src/base/clock_network.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 2889876ab..78a0a9c60 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -429,11 +429,11 @@ bool ClockNetwork::valid_tap_coord_in_bb( return true; } if (tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE && - tap_bbs_[tap_id].strictly_contains(tap_coord)) { + tap_bbs_[tap_id].coincident(tap_coord)) { return true; } if (tap_type(tap_id) == ClockNetwork::e_tap_type::REGION && - tap_bbs_[tap_id].strictly_contains(tap_coord)) { + tap_bbs_[tap_id].coincident(tap_coord)) { /* Check if steps are considered, coords still matches */ bool x_in_bb = false; for (size_t ix = tap_bbs_[tap_id].xmin(); ix < tap_bbs_[tap_id].xmax(); From 73b30841a78b8be0b996dd39e161ec61658f7517 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 20:56:27 -0700 Subject: [PATCH 094/230] [lib] typo --- libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 1e03bc0ba..e36ed9ed8 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -61,7 +61,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp, } case ClockNetwork::e_tap_type::REGION: { openfpga::write_tab_to_file(fp, 4); - fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; + fp << "<" << XML_CLOCK_TREE_TAP_REGION_NODE_NAME << ""; write_xml_attribute( fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); From 578d7c8ec03fecf1c47db548b8825e3b1e811866 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 20:58:41 -0700 Subject: [PATCH 095/230] [core] fixed a bug on region tap point identification --- libs/libclkarchopenfpga/src/base/clock_network.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 78a0a9c60..bd02259b7 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -436,7 +436,7 @@ bool ClockNetwork::valid_tap_coord_in_bb( tap_bbs_[tap_id].coincident(tap_coord)) { /* Check if steps are considered, coords still matches */ bool x_in_bb = false; - for (size_t ix = tap_bbs_[tap_id].xmin(); ix < tap_bbs_[tap_id].xmax(); + for (size_t ix = tap_bbs_[tap_id].xmin(); ix <= tap_bbs_[tap_id].xmax(); ix = ix + tap_bb_steps_[tap_id].x()) { if (tap_coord.x() == ix) { x_in_bb = true; @@ -448,7 +448,7 @@ bool ClockNetwork::valid_tap_coord_in_bb( return false; } bool y_in_bb = false; - for (size_t iy = tap_bbs_[tap_id].ymin(); iy < tap_bbs_[tap_id].ymax(); + for (size_t iy = tap_bbs_[tap_id].ymin(); iy <= tap_bbs_[tap_id].ymax(); iy = iy + tap_bb_steps_[tap_id].y()) { if (tap_coord.y() == iy) { y_in_bb = true; From ec7ca1add1431ff79a7cfb4aec7f49e9f7a5a100 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 21:41:33 -0700 Subject: [PATCH 096/230] [doc] add example to example clock network --- .../manual/file_formats/clock_network.rst | 32 +++++++++++++----- .../figures/prog_clk_network_example_2x2.png | Bin 0 -> 64210 bytes 2 files changed, 24 insertions(+), 8 deletions(-) create mode 100644 docs/source/manual/file_formats/figures/prog_clk_network_example_2x2.png diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index 5979c2f24..0b99fea10 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -37,6 +37,14 @@ Using the clock network description language, users can define multiple clock ne +.. _fig_prog_clock_network_example_2x2: + +.. figure:: figures/prog_clock_network_example_2x2.png + :width: 100% + :alt: An example of programmable clock network considering a 2x2 FPGA fabric + + An example of programmable clock network considering a 2x2 FPGA fabric + General Settings ^^^^^^^^^^^^^^^^ @@ -44,7 +52,7 @@ The following syntax are applicable to the XML definition under the root node `` .. option:: default_segment="" - Define the default routing segment to be used when building the routing tracks for the clock network. Must be a valid routing segment defined in the VPR architecture file. For example, + Define the default routing segment to be used when building the routing tracks for the clock network. The routing segments are used to build the spines of clock networks as shown in :numref:`fig_prog_clock_network_example_2x2`. Must be a valid routing segment defined in the VPR architecture file. For example, .. code-block:: xml @@ -62,11 +70,13 @@ where the segment is defined in the VPR architecture file: .. option:: default_tap_switch="" - Define the default routing switch to be used when interconnects the routing tracks to the input pins of programmable blocks in the clock network. Must be a valid routing switch defined in the VPR architecture file. See the example in the ``default_driver_switch``. + Define the default routing switch to be used when interconnects the routing tracks to the input pins of programmable blocks in the clock network. The tap switches are used to build the taps of clock networks as shown in :numref:`fig_prog_clock_network_example_2x2`. Must be a valid routing switch defined in the VPR architecture file. See the example in the ``default_driver_switch``. .. option:: default_driver_switch="" - Define the default routing switch to be used when interconnects the routing tracks in the clock network. Must be a valid routing switch defined in the VPR architecture file. For example, + .. note:: For internal drivers, suggest to use the same driver switch for the output pins of a programmable block as defined in VPR architecture. + + Define the default routing switch to be used when interconnects the routing tracks in the clock network. The driver switches are used to build the switch points of clock networks as shown in :numref:`fig_prog_clock_network_example_2x2`. Must be a valid routing switch defined in the VPR architecture file. For example, .. code-block:: xml @@ -103,13 +113,18 @@ where the clock network is used to drive the global clock pin ``clk0`` in OpenFP - + -.. option:: global_port="" +.. option:: global_port="" - Define the source port of the clock network. For example, ``clk[0:7]``. Note that the global port name should match the ``from_pin`` when defining the tap points (See details in :ref:`file_formats_clock_network_clock_tap_point`). + .. note:: When programmable clock network is specified for a global port in OpenFPGA architecure description file, the width of clock tree will be the final size of the global port. + + Define the source port of the clock network. For example, ``clk[0:7]``. Note that the global port name should match + + - the ``from_pin`` when defining the tap points (See details in :ref:`file_formats_clock_network_clock_tap_point`). + - the ``name`` of global port definition in OpenFPGA architecture description file .. _file_formats_clock_network_clock_spine: @@ -145,7 +160,7 @@ For example, -where a horizental clock spine ``spine0`` is defined which spans from (1, 1) to (2, 1) +where a horizental clock spine ``spine0`` is defined which spans from (1, 1) to (2, 1), as highlighted in orange in the :numref:`fig_prog_clock_network_example_2x2` .. note:: We only support clock spines in horizental and vertical directions. Diagonal clock spine is not supported! @@ -177,7 +192,7 @@ For example, -where clock spine ``spine0`` will drive another clock spine ``spine1`` at (1, 1). +where clock spine ``spine0`` will drive another clock spine ``spine1`` at (1, 1), as highlighted in blue in the :numref:`fig_prog_clock_network_example_2x2` For each switch point, outputs of neighbouring programmable blocks are allowed to drive the spine at next level, through syntax ``internal_driver``. @@ -285,3 +300,4 @@ where all the clock spines of the clock network ``clk_tree_0`` tap the clock pin + diff --git a/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2.png b/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2.png new file mode 100644 index 0000000000000000000000000000000000000000..eae255144ba225c55ceb0307bb04ee6a37a39c18 GIT binary patch literal 64210 zcmeFZ1yodT+b>Lt2!aaIf=UTW4N@|K1xQOvcO#wBf*>%|(5;{#-6@TLLyC0AkdgyP z$JrYNd7kH8XPtG{`ObR3@B6cs%VBfJ6~8O)YhU;Hy^s>Qe2L-`8XDSV(dW-((a>t5>ge-fd9~KWJR8!<#bRj0KZ@vK9+ophL#_Ucc6_8{O#fk33(ylIqG6iVsUU@^8pY}9>6y@%vn{1_v$Jz^bMtxr^Q~nI5o!zh0Sgt(i%}Yji;GLqngAEe zF~`VuMF(j~%A6yu7jwJlmd-u)gpM z*zk*vW(*ztH8C-jC>NtJzHe@0Nf9t)fB|9XgUY2_mFPg^C_*}0%2B&sINjj}xC14) z1E*sgstd_$g^z(bDva9s}Ezoopw}-kpMDsafqdLsYRkUgMr^ zQ2r;tsB=E~1Wu&|rjp`SPf$N5JF+K9hMRzce zkbK9NzPz@BPUUJZeqHeGAA%(&);I3>nJ{^;;Q%pA=dl#TM|{g?|1IIzHJ4KND>#3| z5L4SYCj(Cr2ey4ybF!Kq9jyg}{gI<(*yFZk;?pfX#XD1oK~8T0oCaW%Bfg0{-nVfH zyP8)b_eT;PSUJ#O+0Ou3zJC_d-Shtx<92v0YeW1%hnD@^NLFB^Hy+6A-4k9l7TyUJopK-LVVItGJ`iv@ z&t&YG*^%-PWSIVh;rrD{J^Z}!dqn_DAnrLvz@Rnj?T&F))}&Vtw{|o(A%Ad? zfU9Opz5L?*$jQwio)m>d*Y&UB_%wBo|6~~qmR(LowDAhS$T5$THA7*QpI+`8knuaT z>?{xyUOvUI1h1wI2yQSVYJ5YA_|^@*^cBa_u#|kG>fImoH1mbTh|7H-y#_R?l)jdqF z@b@TsT2~tz)(R#pNoIqF?J3@oa^kT#PH@DCaI~CFj{B)f>3cd8ZutasBv^po%AepRC#0@LNVcC& z#Rl=pc`~&bK_;~%DfgEo7TyP-3xlG8ptp>MRkrg&Q7w|lbBxb}?!xl&3FF$3^{-?2 zoUb6=wi}+OE`?Xc8YGR62~CF|>%a?&%rPQ-2)2?MO| zTsUF%4tay+4~~V@xz0X_U|q!-d@%asML4zPfq{--s+~V^lib)xlx>=Z&!Iajfc4Bq zLo`m{Pj#}Xm)eY$epyI zS978V1ij-do&>GRje#eglj!2P*g^XqfXV?T2$c}ACMCiNhQ!ES*H;yqvvDvv9yiRt zCIt=l0Ih`(1kGb+a-ygFiK)BnJzABT)oZ=AsL~tbXOi)}+ev#x7_`D0_=6IhK5?S#f>5bJj$zV}v{wkp@Ac+Oav82YzSD8Ujb1enehKxhA)kN-K${{w@6YC8W^%l4x@aD<8;W~!vPwxA$-0?2E0X#G(;K{o3MBcZA_G|m3&-Ewoetx(2F5?@?8`}xE zib@+vN>-y{_N5yNy267q+)HEDl)v`B@-RZRALod8W=gtTP^g?&ow`4D30z~{fi~kV*kHr6h%70_yyiR<$v%4|JM(B35 z)AWH~C;OoJBY(>g%-mFnXxudG^i{e&UZPT~#bi(D%gS$^Nzm7L zax>0@s-l-o()EZRdY*U>RU!Un$GoiwtuTJ>6{1|ReSN4ialA4a^Em&^R|9LrCs8^h zbRT~P_*<1`RSg!y1>%)TcIL7R`oz8{_1DMZS#4vju-~NCD_>}#M%v+KGZ>hpx-i{w+rCqa zhe0K-BQJedXs)j8<@Sh*Fv`z=bV;4S5L21)sDWUhZ8fk7h071gfF&`%Ov{lV4sk&6y=8<+K+#QB9Bu{n7u8WcMlN|*X|ML?JDIDA21*~u_g1WC#P%&o4Vd9(EE#*d?nX-eN~Fk+TBR)+-l z`i!aDa%L*Upz(g{S)iT;uLl+YEgIO>Qjx( z2RD3L4-9WE8IdxCS5aJ2Qpi42ChpQL9_b0VIhoVIf(>*bwUcxL(aasggN6GJR*tDm7GxC5L;MqKfgs3obL)FX z>1#KPDB{iO=6bUq<`lk48B+s4Rqk>YD;!mjO;(H+HCUpM&$LpE2uf@pxu_oS?2?+0 zzs(_;Fj%#ovUPNnD9bWoiGU?Df-x9R3ujp+v!Btj>ypEpYgA>%YGL7Vtl11l%+w@W z$xx|K5k~LDYxIO`c^Bn`_=Xq7SW>>vXz9#9Gz+)!&rKuB$y5=iPnpLBqW|c&HcnMX z=%yV9MeAk#`e#=e!}W1R%wsD^VHQ)QV%xN=R_}jh_i++r*8C$cDfSc&CDRkG$*(b z-*)w0<%k!<$~l55F8KMa^DdX}|0p=K%GHJoQ(d@|73w$zUKU}n{V$$GEhFL0rHIf2 z+_#Gv73pu2%cizgt?eyrekfJFeY=iF^q_(j7T0r%#%VByrQE(p+=x9l$=7c}{>l3CN=d++am|>zNdH@_FcoHUA!#tJ zsg}0Ke7i`%zs8VgjgT0(?OvPelCXN=@41fKG5;&PUcXdYSSqdQOT1Hxw^em3VqcOi z??rXOIPN5bKIIA)U>6`Ixn3-44%>Q__OuSusV))AJ3ki^KgEoFl}u-|L3MDvuw52j z(P2UICL?`Tt#vf3;^oRR{%U)i@%{^+eecDs1d^sz>!i9tz1iN-IG@QXh9E(ywcsJ% z;Ltc>FL&j3%U<)99=&T@7yNa;Z>(V}nUZTBeuxyTHh)8fA1?R~acJUuLrq`#uj+9x zhieN?7Q`_ki-%#fJP&OncGkPekMwj?70p{jtL}fb?8=GM9{3ne;vaoEH`!AyduA#% zv|sNiS&8h9d#$Ks_k(fW%6CB3Zy@!r?uaPYX5v~c2Xio4l7_21NK6?W{+^ei#BkNJw$8$n3 z++X`5+!TT%GYaka@*ZMSz&0@(dww4NdaTvDO%WKZ?f1Bobk(>#i04L2EWL>`I?oaTB`@;+tznY)vU^{w9a$bP(S4fO!9!+a<5M(^6R_a zBOug73A0409s}sHkA)A%&TS1a$(}l&Hwjn|+%cMWi5Zay9DZq@;u7j3wH9G{W=bcM z&Oy}_)9||mVohNxtYfp$xIEc2v#wGmx*KiOU(To?nViR^Vw8`E5sBoY)L8iEIPAI; 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z)jWirCC27sCgwD8muHw<@|BxZE@9pJZ|rsf1wBElO;2Q;g*OV44fZlW%u*!!6Yn2b>)jvWT-3ew8jl2B zOWkonS-M(YF{KOd_rAC#_PO7viuYTUhnbXECrfrk4GBg;%$zfBj=<$_9UAnnvadUQ{3bhAV-JvoNGV(<}MB_+58$V^050GExQSbC#9vgE|gZGx| zt67|kwimxV93xPN>olmMR#=Ul-336FlT3kP{H}0B6N4fV1$23#fuw&u7rhj$Q- zy9$MMqpsb}sjb}A>k4fqG%frfN^}2j--;tI^7vndX>E)mlM4o5!gusJfSEP!FWU*% zhEwIdiU|N?ZkaoZmX8O1Ul~+&)+(!8^84s8qkm24cF+5smoVWn1MsP}QnpInd^qI8 zPOVOE9CU?TGtN$wU1v3a^7dKwq5QazDm|6!$JBztrzaC-n=0Q_L}@xq zbwmY%A~urh?vNHX1Fk{@bfoWla`Pij~Q8U2nc=5U_28cr+I%b%Bz$#!t0} z8Kd&7d*A!QwK|nA6j4PA#xPnGo$HdlDFO0nN&5r;0@G$eg zZTu9fNWHNymQB)zFzHm*4w&iXs-ddCc$8e2HPEHJagC zfnn z{_?NSmdH5NPuLPS41~sWQtEY-h Date: Tue, 2 Jul 2024 09:33:16 -0700 Subject: [PATCH 097/230] [test] fix a bug in arch --- .../openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml index 7a7154031..cc4d00f54 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml @@ -197,6 +197,7 @@ + From 29452a7442bf2a48749e271884fead3eb38c83d8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Jul 2024 11:52:19 -0700 Subject: [PATCH 098/230] [test] fixed a bug on out-of-date arch --- .../config/clk_arch_1clk_2layer.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml index 0570406fd..6f289dbf4 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml @@ -1,5 +1,5 @@ - - + + @@ -11,7 +11,7 @@ - + From 1e7cca8cebfb4991885863c0463c2f5ffd2f4fc9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Jul 2024 11:52:30 -0700 Subject: [PATCH 099/230] [arch] code format --- openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index ad21e6f59..013466e5c 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -108,8 +108,8 @@ - - + + clb.reset clb.clk clb.O[4:7] clb.I[6:11] clb.O[0:3] clb.I[0:5] From 7e461b09f88e479499dd84b41bcf135ebb3ee5c2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Jul 2024 13:22:41 -0700 Subject: [PATCH 100/230] [core] add missing file --- .../config/repack_pin_constraints.xml | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/repack_pin_constraints.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + From 078fad1e74d2dd7cc4e05350c2b4a78cd71b7c9a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Jul 2024 14:57:24 -0700 Subject: [PATCH 101/230] [test] typo --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index f8742d781..72f1c01d6 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -234,10 +234,10 @@ run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ run-task basic_tests/clock_network/homo_2clock_2layer $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ -run-task basic_tests/clock_network/homo_1clock_1_reset_2layer $@ -run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_syntax $@ -run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_disable_unused_spines $@ -run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_internal_driver $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; run-task basic_tests/verific_test $@ From 6d30871f1101e5560cb9a1ebad3b4689cad15738 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 3 Jul 2024 00:15:44 +0000 Subject: [PATCH 102/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 98319eb52..823466c7b 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2290 +1.2.2381 From e3a258a5ab3db18588142318fd90e9bc9f7de67c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Jul 2024 19:31:45 -0700 Subject: [PATCH 103/230] [doc] typo --- docs/source/manual/file_formats/clock_network.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index 0b99fea10..f9c94b5a3 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -39,7 +39,7 @@ Using the clock network description language, users can define multiple clock ne .. _fig_prog_clock_network_example_2x2: -.. figure:: figures/prog_clock_network_example_2x2.png +.. figure:: figures/prog_clk_network_example_2x2.png :width: 100% :alt: An example of programmable clock network considering a 2x2 FPGA fabric From 50e87232ede6cf08cb781cc9774565c7bd628ead Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 3 Jul 2024 04:10:48 +0000 Subject: [PATCH 104/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 823466c7b..2e87e34ef 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2381 +1.2.2386 From 60f0c087d87d6f11069aa8cfcdf9d5b3d2a89fc8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 16:54:34 -0700 Subject: [PATCH 105/230] [lib] update vtr to latest --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 6a4f0cac3..3095c28d3 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 6a4f0cac3b180bdb78f53f58c9f3f23912858173 +Subproject commit 3095c28d3c2795e8042710d54f941be76ab1819d From f681c6a903a18f0de6c53be6574441a8b0f7a4d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 17:04:06 -0700 Subject: [PATCH 106/230] [core] update API call due to vtr upgrade --- .../src/annotation/append_clock_rr_graph.cpp | 25 ++++++++++++------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index d5f325ca6..d05fd136d 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -45,6 +45,7 @@ static size_t estimate_clock_rr_graph_num_chan_nodes( *******************************************************************/ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, const size_t& layer, + const bool& perimeter_cb, const bool& through_channel, const ClockNetwork& clk_ntwk) { size_t num_nodes = 0; @@ -55,7 +56,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, layer, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } /* Estimate the routing tracks required by clock routing only */ @@ -69,7 +70,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, layer, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } /* Estimate the routing tracks required by clock routing only */ @@ -151,7 +152,9 @@ static void add_rr_graph_block_clock_nodes( static void add_rr_graph_clock_nodes( RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, const DeviceGrid& grids, - const size_t& layer, const bool& through_channel, + const size_t& layer, + const bool& perimeter_cb, + const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { /* Pre-allocate memory: Must do otherwise data will be messed up! */ clk_rr_lookup.reserve_nodes(grids.width(), grids.height(), @@ -165,7 +168,7 @@ static void add_rr_graph_clock_nodes( /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, layer, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_nodes( @@ -187,7 +190,7 @@ static void add_rr_graph_clock_nodes( /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, layer, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_nodes( @@ -729,7 +732,9 @@ static int add_rr_graph_opin2clk_edges( static void add_rr_graph_clock_edges( RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, - const DeviceGrid& grids, const size_t& layer, const bool& through_channel, + const DeviceGrid& grids, const size_t& layer, + const bool& perimeter_cb, + const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { /* Add edges which is driven by X-direction clock routing tracks */ for (size_t iy = 0; iy < grids.height() - 1; ++iy) { @@ -738,7 +743,7 @@ static void add_rr_graph_clock_edges( /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, layer, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, @@ -754,7 +759,7 @@ static void add_rr_graph_clock_edges( /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, layer, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, @@ -793,7 +798,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, /* Estimate the number of nodes and pre-allocate */ size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes(); size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes( - vpr_device_ctx.grid, 0, vpr_device_ctx.arch->through_channel, clk_ntwk); + vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, clk_ntwk); vpr_device_ctx.rr_graph_builder.unlock_storage(); vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes + orig_num_nodes); @@ -805,6 +810,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, /* Add clock nodes */ add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup, vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, + vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); VTR_LOGV(verbose, @@ -820,6 +826,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, vpr_device_ctx.rr_graph_builder, num_clock_edges, static_cast(clk_rr_lookup), vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, + vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); VTR_LOGV(verbose, "Added %lu clock edges to routing " From a27325d987f55f6c85e3fe3d3af4737f7be5eb28 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 17:05:27 -0700 Subject: [PATCH 107/230] [core] code format --- .../src/annotation/append_clock_rr_graph.cpp | 27 +++++++++---------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index d05fd136d..ffe49e146 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -152,9 +152,7 @@ static void add_rr_graph_block_clock_nodes( static void add_rr_graph_clock_nodes( RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, const DeviceGrid& grids, - const size_t& layer, - const bool& perimeter_cb, - const bool& through_channel, + const size_t& layer, const bool& perimeter_cb, const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { /* Pre-allocate memory: Must do otherwise data will be messed up! */ clk_rr_lookup.reserve_nodes(grids.width(), grids.height(), @@ -732,10 +730,9 @@ static int add_rr_graph_opin2clk_edges( static void add_rr_graph_clock_edges( RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, - const DeviceGrid& grids, const size_t& layer, - const bool& perimeter_cb, - const bool& through_channel, - const ClockNetwork& clk_ntwk, const bool& verbose) { + const DeviceGrid& grids, const size_t& layer, const bool& perimeter_cb, + const bool& through_channel, const ClockNetwork& clk_ntwk, + const bool& verbose) { /* Add edges which is driven by X-direction clock routing tracks */ for (size_t iy = 0; iy < grids.height() - 1; ++iy) { for (size_t ix = 1; ix < grids.width() - 1; ++ix) { @@ -798,7 +795,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, /* Estimate the number of nodes and pre-allocate */ size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes(); size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes( - vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, clk_ntwk); + vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, + vpr_device_ctx.arch->through_channel, clk_ntwk); vpr_device_ctx.rr_graph_builder.unlock_storage(); vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes + orig_num_nodes); @@ -808,11 +806,10 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, num_clock_nodes, (float)(num_clock_nodes / orig_num_nodes)); /* Add clock nodes */ - add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup, - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, - vpr_device_ctx.arch->perimeter_cb, - vpr_device_ctx.arch->through_channel, clk_ntwk, - verbose); + add_rr_graph_clock_nodes( + vpr_device_ctx.rr_graph_builder, clk_rr_lookup, vpr_device_ctx.rr_graph, + vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, + vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); VTR_LOGV(verbose, "Added %lu clock nodes to routing " "resource graph.\n", @@ -826,8 +823,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, vpr_device_ctx.rr_graph_builder, num_clock_edges, static_cast(clk_rr_lookup), vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, - vpr_device_ctx.arch->perimeter_cb, - vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); + vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, + clk_ntwk, verbose); VTR_LOGV(verbose, "Added %lu clock edges to routing " "resource graph.\n", From a78fddc3cbd43fcb869bf84df73e2e72e7e32e41 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 19:59:24 -0700 Subject: [PATCH 108/230] [test] add a new testcase to validate perimeter cb --- .../regression_test_scripts/basic_reg_test.sh | 2 ++ .../perimeter_cb/config/task.conf | 36 +++++++++++++++++++ openfpga_flow/vpr_arch/README.md | 1 + 3 files changed, 39 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 72f1c01d6..e8902632c 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -190,6 +190,8 @@ run-task basic_tests/tile_organization/tileable_io $@ echo -e "Testing tiles with I/O consisting of subtiles"; run-task basic_tests/tile_organization/io_subtile $@ run-task basic_tests/tile_organization/io_subtile_strong $@ +echo -e "Testing tiles with routing tracks around I/O"; +run-task basic_tests/tile_organization/perimeter_cb $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; run-task basic_tests/tile_organization/homo_fabric_tile $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf new file mode 100644 index 000000000..4e6a514f3 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x3 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 7f8a000b5..2c69935c6 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -23,6 +23,7 @@ Please reveal the following architecture features in the names to help quickly s - reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs - registerable\_io: If I/Os are registerable (can be either combinational or sequential) - IoSubtile: If I/O block contains sub tiles (more compact with a higher density of I/Os) +- PerimeterCb: If connection blocks can occur on perimeter I/Os (I/O tile has more routability) - CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax - rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture - localClkGen: The clock signal of CLB can be generated by internal programmable resources From 3d19e10611a335378ae4e33725320c16dd1b8ee2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 21:48:37 -0700 Subject: [PATCH 109/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 3095c28d3..64bbd2454 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 3095c28d3c2795e8042710d54f941be76ab1819d +Subproject commit 64bbd2454e81ea4790b27a7846cd5e454f5bc3f9 From bc94e08c77cdef86b84149f11892e02bd00bfb53 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 22:28:22 -0700 Subject: [PATCH 110/230] [lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled --- openfpga/src/annotation/annotate_rr_graph.cpp | 11 +++++++++-- vtr-verilog-to-routing | 2 +- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 291d9cd9b..613364de2 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -420,6 +420,9 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, */ vtr::Point gsb_range(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); + if (vpr_device_ctx.arch->perimeter_cb) { + gsb_range.set(vpr_device_ctx.grid.width(), vpr_device_ctx.grid.height()); + } device_rr_gsb.reserve(gsb_range); VTR_LOGV(verbose_output, "Start annotation GSB up to [%lu][%lu]\n", @@ -434,10 +437,14 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, * the GSBs at the borderside correctly sort drive_rr_nodes should be * called if required by users */ + vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 2, + vpr_device_ctx.grid.height() - 2); + if (vpr_device_ctx.arch->perimeter_cb) { + sub_gsb_range.set(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); + } const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, - vtr::Point(vpr_device_ctx.grid.width() - 2, - vpr_device_ctx.grid.height() - 2), + sub_gsb_range, layer, vtr::Point(ix, iy), include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 64bbd2454..7aa23041f 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 64bbd2454e81ea4790b27a7846cd5e454f5bc3f9 +Subproject commit 7aa23041f18ce07a10b62fa7459166f613d039d2 From e06b53658c333e3284814bfe00bf88e97ecc5dd8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 22:33:48 -0700 Subject: [PATCH 111/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 7aa23041f..97c106cd8 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 7aa23041f18ce07a10b62fa7459166f613d039d2 +Subproject commit 97c106cd89bcd3c4a6d29dfea5101cd15554d3f3 From 550ce0c3901b4b2bcf524fbff6a379447b3f923f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 10:58:44 -0700 Subject: [PATCH 112/230] [core] fixed the bug on build gsb when cbs are on perimeters --- openfpga/src/annotation/annotate_rr_graph.cpp | 32 +++++++++++++++---- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 613364de2..badeca9de 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -126,7 +126,12 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - /* For the border, we should take special care */ + /* For the border, we should take special care + * For the fabric where no cbs are on perimeter tiles (y = H - 1), + * the the border should be on the y = H - 2 + * For the fabric where cbs are on perimeter tiles, + * the border should be on the y = H - 1 + */ if (gsb_coord.y() == gsb_range.y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; @@ -157,7 +162,12 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, break; case RIGHT: /* RIGHT = 1 */ - /* For the border, we should take special care */ + /* For the border, we should take special care + * For the fabric where no cbs are on perimeter tiles (x = W - 1), + * the the border should be on the x = W - 2 + * For the fabric where cbs are on perimeter tiles, + * the border should be on the x = W - 1 + */ if (gsb_coord.x() == gsb_range.x()) { rr_gsb.clear_one_side(side_manager.get_side()); break; @@ -189,8 +199,13 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - /* For the border, we should take special care */ - if (gsb_coord.y() == 0) { + /* For the border, we should take special care + * For the fabric where no cbs are on perimeter tiles (y = 0), + * the the border should be on the y = 0 + * For the fabric where cbs are on perimeter tiles, + * the border should be on the y = - 1, leading to no border + */ + if (!vpr_device_ctx.arch->perimeter_cb && gsb_coord.y() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -220,8 +235,13 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - /* For the border, we should take special care */ - if (gsb_coord.x() == 0) { + /* For the border, we should take special care + * For the fabric where no cbs are on perimeter tiles (x = 0), + * the the border should be on the x = 0 + * For the fabric where cbs are on perimeter tiles, + * the border should be on the x = - 1, leading to no border + */ + if (!vpr_device_ctx.arch->perimeter_cb && gsb_coord.x() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } From 724c14d1f7fe53c200060429ea328a031e4f6759 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 11:09:01 -0700 Subject: [PATCH 113/230] [core] fixed a bug on build top module connections on perimeter gsb when cbs occur --- openfpga/src/fabric/build_top_module_connection.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index e6a98cd46..38b0491a9 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -760,6 +760,12 @@ static void add_top_module_nets_connect_sb_and_cb( } if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + /* Only for the condition where cbs are on perimeter, the neighbour cb will be invalid + * Bypass in such case on finding neighbour cbs + */ + if (instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x() || instance_sb_coordinate.y() == 0) { + continue; + } const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate); if (false == adjacent_gsb.is_cb_exist(cb_type)) { From 93649a12440db99d450f9bd7b93c891e5ce04559 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:16:32 -0700 Subject: [PATCH 114/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 97c106cd8..b172d26a0 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 97c106cd89bcd3c4a6d29dfea5101cd15554d3f3 +Subproject commit b172d26a0c75dbabdaf78fc37d6260f74f22ff4c From 5736f45f769b552b3912b1dbf8a3c79cbbbf9366 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:18:20 -0700 Subject: [PATCH 115/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index b172d26a0..ae9eb2dbb 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit b172d26a0c75dbabdaf78fc37d6260f74f22ff4c +Subproject commit ae9eb2dbb0e685d6a2bff11d01713498f12e2b27 From 48590df452c13f7e559a9375d32bec30d23b2e3e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:20:20 -0700 Subject: [PATCH 116/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index ae9eb2dbb..159bea4ff 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit ae9eb2dbb0e685d6a2bff11d01713498f12e2b27 +Subproject commit 159bea4ff7e2df8eedaa219cf1765b5dee1921f1 From a7178823047d6283775ccb906febd4193ca83a17 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:44:48 -0700 Subject: [PATCH 117/230] [core] now when perimeter_cb is on, I/O pins can access three sides of routing tracks --- openfpga/src/fabric/build_device_module.cpp | 2 +- .../build_grid_module_duplicated_pins.cpp | 20 +++++++------ .../build_grid_module_duplicated_pins.h | 6 ++-- .../src/fabric/build_grid_module_utils.cpp | 18 +++++++++--- openfpga/src/fabric/build_grid_module_utils.h | 4 +-- openfpga/src/fabric/build_grid_modules.cpp | 28 +++++++++++-------- openfpga/src/fabric/build_tile_modules.cpp | 15 ++++++---- openfpga/src/fabric/build_tile_modules.h | 1 + 8 files changed, 60 insertions(+), 34 deletions(-) diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 757171c78..e03ee2510 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -128,7 +128,7 @@ int build_device_module_graph( openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph, openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib, sram_model, openfpga_ctx.arch().config_protocol.type(), - name_module_using_index, frame_view, verbose); + name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view, verbose); } /* Build FPGA fabric top-level module */ diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index 32304bdc7..7e628e459 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -55,7 +55,8 @@ void add_grid_module_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(false == is_empty_type(grid_type_descriptor)); @@ -66,7 +67,7 @@ void add_grid_module_duplicated_pb_type_ports( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -172,7 +173,9 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( const size_t& child_inst_subtile_index, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) { + const e_side& border_side, + const bool& perimeter_cb, + const e_pin2pin_interc_type& pin2pin_interc_type) { /* Make sure this is ONLY applied to output pins */ VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type); @@ -183,7 +186,7 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -316,7 +319,8 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(false == is_empty_type(grid_type_descriptor)); @@ -334,7 +338,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } @@ -345,7 +349,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->output_pins[iport][ipin]), border_side, - OUTPUT2OUTPUT_INTERC); + perimeter_cb, OUTPUT2OUTPUT_INTERC); } } @@ -356,7 +360,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } } diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.h b/openfpga/src/fabric/build_grid_module_duplicated_pins.h index 4f2eafee2..9f95b7dd7 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.h +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.h @@ -21,14 +21,16 @@ void add_grid_module_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side); + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb); void add_grid_module_nets_connect_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side); + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 3b3f14203..e78981ca2 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -24,7 +24,7 @@ namespace openfpga { * 5. I/O grids in the center part of FPGA can have ports on any side *******************************************************************/ std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb) { /* We must have an regular (non-I/O) type here */ VTR_ASSERT(true == is_io_type(grid_type_descriptor)); SideManager side_manager(border_side); @@ -33,7 +33,16 @@ std::vector find_grid_module_pin_sides( return {TOP, RIGHT, BOTTOM, LEFT}; } - return std::vector(1, side_manager.get_opposite()); + if (!perimeter_cb) { + return std::vector(1, side_manager.get_opposite()); + } + /* For cbs on perimeter, exclude the border side. All the other 3 sides are ok */ + std::vector pin_sides; + pin_sides.reserve(3); + for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) { + pin_sides.push_back(pin_side); + } + return pin_sides; } /******************************************************************** @@ -47,7 +56,8 @@ void add_grid_module_net_connect_pb_graph_pin( const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) { + const e_side& border_side, const bool& perimeter_cb, + const e_pin2pin_interc_type& pin2pin_interc_type) { /* Find the pin side for I/O grids*/ std::vector grid_pin_sides; /* For I/O grids, we care only one side @@ -55,7 +65,7 @@ void add_grid_module_net_connect_pb_graph_pin( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } diff --git a/openfpga/src/fabric/build_grid_module_utils.h b/openfpga/src/fabric/build_grid_module_utils.h index a8d5f9d12..1051ae601 100644 --- a/openfpga/src/fabric/build_grid_module_utils.h +++ b/openfpga/src/fabric/build_grid_module_utils.h @@ -19,7 +19,7 @@ namespace openfpga { std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side); + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb); void add_grid_module_net_connect_pb_graph_pin( ModuleManager& module_manager, const ModuleId& grid_module, @@ -28,7 +28,7 @@ void add_grid_module_net_connect_pb_graph_pin( const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, + const e_side& border_side, const bool& perimeter_cb, const enum e_pin2pin_interc_type& pin2pin_interc_type); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index eaa24246b..8ffe94fda 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -42,7 +42,9 @@ static void add_grid_module_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, + const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -53,7 +55,7 @@ static void add_grid_module_pb_type_ports( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -125,7 +127,8 @@ static void add_grid_module_nets_connect_pb_type_ports( const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -144,7 +147,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } @@ -155,7 +158,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->output_pins[iport][ipin]), - border_side, OUTPUT2OUTPUT_INTERC); + border_side, perimeter_cb, OUTPUT2OUTPUT_INTERC); } } @@ -166,7 +169,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } } @@ -1168,6 +1171,7 @@ static int build_physical_tile_module( const TileAnnotation& tile_annotation, const e_side& border_side, const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, const bool& duplicate_grid_pin, const bool& group_config_block, + const bool& perimeter_cb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; /* Create a Module for the top-level physical block, and add to module manager @@ -1247,7 +1251,7 @@ static int build_physical_tile_module( /* Default way to add these ports by following the definition in pb_types */ add_grid_module_pb_type_ports(module_manager, grid_module, vpr_device_annotation, phy_block_type, - tile_annotation, border_side); + tile_annotation, border_side, perimeter_cb); /* Add module nets to connect the pb_type ports to sub modules */ for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) { VTR_ASSERT(sub_tile.equivalent_sites.size() == 1); @@ -1264,7 +1268,7 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); } } } else { @@ -1272,7 +1276,7 @@ static int build_physical_tile_module( /* Add these ports with duplication */ add_grid_module_duplicated_pb_type_ports( module_manager, grid_module, vpr_device_annotation, phy_block_type, - tile_annotation, border_side); + tile_annotation, border_side, perimeter_cb); /* Add module nets to connect the duplicated pb_type ports to sub modules */ for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) { @@ -1290,7 +1294,7 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); } } } @@ -1436,7 +1440,7 @@ int build_grid_modules( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, io_type_side, ql_memory_bank_config_setting, duplicate_grid_pin, - group_config_block, verbose); + group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1446,7 +1450,7 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES, - ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, + ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index 74797aa39..f93cd07bf 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -1175,6 +1175,7 @@ static int build_tile_port_and_nets_from_pb( const TileAnnotation& tile_annotation, const vtr::Point& pb_coord, const std::vector& pb_instances, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const size_t& ipb, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { size_t pb_instance = pb_instances[ipb]; t_physical_tile_type_ptr phy_tile = grids.get_physical_type( @@ -1201,7 +1202,7 @@ static int build_tile_port_and_nets_from_pb( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(phy_tile)) { - grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side); + grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -1378,6 +1379,7 @@ static int build_tile_module_ports_and_nets( const FabricTileId& fabric_tile_id, const std::vector& pb_instances, const std::map>& cb_instances, const std::vector& sb_instances, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; @@ -1441,7 +1443,7 @@ static int build_tile_module_ports_and_nets( status_code = build_tile_port_and_nets_from_pb( module_manager, tile_module, grids, layer, vpr_device_annotation, rr_graph_view, tile_annotation, pb_coord, pb_instances, fabric_tile, - fabric_tile_id, ipb, frame_view, verbose); + fabric_tile_id, ipb, perimeter_cb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1487,7 +1489,9 @@ static int build_tile_module( const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, const bool& frame_view, + const bool& name_module_using_index, + const bool& perimeter_cb, + const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; @@ -1635,7 +1639,7 @@ static int build_tile_module( module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, fabric_tile, fabric_tile_id, pb_instances, cb_instances, sb_instances, name_module_using_index, - frame_view, verbose); + perimeter_cb, frame_view, verbose); /* Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), @@ -1709,6 +1713,7 @@ int build_tile_modules(ModuleManager& module_manager, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric"); @@ -1722,7 +1727,7 @@ int build_tile_modules(ModuleManager& module_manager, module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, circuit_lib, sram_model, sram_orgz_type, name_module_using_index, - frame_view, verbose); + perimeter_cb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_tile_modules.h b/openfpga/src/fabric/build_tile_modules.h index 83f219610..e3a629808 100644 --- a/openfpga/src/fabric/build_tile_modules.h +++ b/openfpga/src/fabric/build_tile_modules.h @@ -36,6 +36,7 @@ int build_tile_modules(ModuleManager& module_manager, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ From a3723b33b35a9482f8e8692aedbbe9379a7278de Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:52:29 -0700 Subject: [PATCH 118/230] [core] fixed a minor bug --- openfpga/src/fabric/build_grid_module_utils.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index e78981ca2..951e2429d 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -40,7 +40,9 @@ std::vector find_grid_module_pin_sides( std::vector pin_sides; pin_sides.reserve(3); for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) { - pin_sides.push_back(pin_side); + if (pin_side != border_side) { + pin_sides.push_back(pin_side); + } } return pin_sides; } From b80ed8d15cf328e180319dafb433997a406b6b3e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:58:16 -0700 Subject: [PATCH 119/230] [core] fixed a bug --- openfpga/src/fabric/build_top_module_connection.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 38b0491a9..2493c20c9 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -763,7 +763,10 @@ static void add_top_module_nets_connect_sb_and_cb( /* Only for the condition where cbs are on perimeter, the neighbour cb will be invalid * Bypass in such case on finding neighbour cbs */ - if (instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x() || instance_sb_coordinate.y() == 0) { + if (BOTTOM == side_manager.get_side() && instance_sb_coordinate.y() == 0) { + continue; + } + if (RIGHT == side_manager.get_side() && instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) { continue; } const RRGSB& adjacent_gsb = From 75407b1e8c0fafbfb6923fa4932f11a02f802973 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 13:15:54 -0700 Subject: [PATCH 120/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 159bea4ff..fbbf53d82 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 159bea4ff7e2df8eedaa219cf1765b5dee1921f1 +Subproject commit fbbf53d8207d55df8c6c62e1a0505f94ccba612a From d2a68ff9c5316b2a4db6941c0629ca6aebda48f2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 13:25:57 -0700 Subject: [PATCH 121/230] [core] now corner tile are considered as config child --- openfpga/src/fabric/build_top_module_memory.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 5dae3f0f4..302bd6675 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -458,12 +458,12 @@ void organize_top_module_memory_modules( std::map>> io_coords; /* BOTTOM side I/Os */ - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { io_coords[BOTTOM].push_back(vtr::Point(ix, 0)); } /* RIGHT side I/Os */ - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { io_coords[RIGHT].push_back(vtr::Point(grids.width() - 1, iy)); } @@ -483,13 +483,13 @@ void organize_top_module_memory_modules( * +--------+ +--------+ * */ - for (size_t ix = grids.width() - 2; ix >= 1; --ix) { + for (size_t ix = grids.width() - 1; ix >= 1; --ix) { io_coords[TOP].push_back(vtr::Point(ix, grids.height() - 1)); } io_coords[TOP].push_back(vtr::Point(0, grids.height() - 1)); /* LEFT side I/Os */ - for (size_t iy = grids.height() - 2; iy >= 1; --iy) { + for (size_t iy = grids.height() - 1; iy >= 1; --iy) { io_coords[LEFT].push_back(vtr::Point(0, iy)); } From 4b53e57c92a8c571ec68667ec59d2dd2a7383643 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 13:33:04 -0700 Subject: [PATCH 122/230] [core] fixed a bug --- .../src/fabric/build_top_module_memory.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 302bd6675..47238685e 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -370,12 +370,13 @@ void build_top_module_configurable_regions( * Note: the organization of inter-tile aims to reduce the wire length * to connect between tiles. Therefore, it is organized as a snake * where we can avoid long wires between rows and columns + * Note: Corner I/Os only occur when perimeter cb is allowed * * +--------------------------------------------------------+ - * | +------+------+-----+------+ | - * | | I/O | I/O | ... | I/O | | - * | | TOP | TOP | | TOP | | - * | +------+------+-----+------+ | + * | +------+ +------+------+-----+------+ +------+ | + * | | I/O | | I/O | I/O | ... | I/O | | I/O | | + * | | LEFT | | TOP | TOP | | TOP | | TOP | | + * | +------+ +------+------+-----+------+ +------+ | * | +---------------------------------->tail | * | +------+ | +------+------+-----+------+ +------+ | * | | | | | | | | | | | | @@ -397,10 +398,10 @@ void build_top_module_configurable_regions( * | | LEFT | | [0] | [1] | | [i] | | |RIGHT | | * | +------+ +------+------+-----+------+ | +------+ | * +-------------------------------------------+ | - * +------+------+-----+------+ | - * | I/O | I/O | ... | I/O | | - * |BOTTOM|BOTTOM| |BOTTOM| | - * +------+------+-----+------+ | + * +------+ +------+------+-----+------+ +------+ | + * | I/O | | I/O | I/O | ... | I/O | | I/O | | + * |BOTTOM| |BOTTOM|BOTTOM| |BOTTOM| |RIGHT | | + * +------+ +------+------+-----+------+ +------+ | * head >-----------------------------------------------+ * * Inner tile connection: @@ -486,7 +487,6 @@ void organize_top_module_memory_modules( for (size_t ix = grids.width() - 1; ix >= 1; --ix) { io_coords[TOP].push_back(vtr::Point(ix, grids.height() - 1)); } - io_coords[TOP].push_back(vtr::Point(0, grids.height() - 1)); /* LEFT side I/Os */ for (size_t iy = grids.height() - 1; iy >= 1; --iy) { From a8850d4f0f10eb68b70520b536fb1a76414f9d66 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:22:30 -0700 Subject: [PATCH 123/230] [core] now verbose mode is applicable to more build top module cb instances --- openfpga/src/fabric/build_top_module.cpp | 2 +- .../build_top_module_child_fine_grained_instance.cpp | 11 +++++++---- .../build_top_module_child_fine_grained_instance.h | 3 ++- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 238004e4d..bce676019 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -79,7 +79,7 @@ int build_top_module( rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol, sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin, - fabric_key, group_config_block); + fabric_key, group_config_block, verbose); } else { /* Build the tile instances under the top module */ status = build_top_module_tile_child_instances( diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 7640a969c..e3abe7c07 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -244,7 +244,7 @@ static vtr::Matrix add_top_module_switch_block_instances( static vtr::Matrix add_top_module_connection_block_instances( ModuleManager& module_manager, const ModuleId& top_module, const DeviceRRGSB& device_rr_gsb, const t_rr_type& cb_type, - const bool& compact_routing_hierarchy) { + const bool& compact_routing_hierarchy, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Add connection block instances to top module"); @@ -264,6 +264,7 @@ static vtr::Matrix add_top_module_connection_block_instances( vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); if (false == rr_gsb.is_cb_exist(cb_type)) { + VTR_LOGV(verbose, "Skip connnection block at (%lu, %lu) as it does not exist\n", cb_coordinate.x(), cb_coordinate.y()); continue; } /* If we use compact routing hierarchy, we should instanciate the unique @@ -295,6 +296,7 @@ static vtr::Matrix add_top_module_connection_block_instances( top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], cb_instance_name); + VTR_LOGV(verbose, "Added connnection block '%s' (module '%s')\n", cb_instance_name.c_str(), cb_module_name.c_str()); } } @@ -445,7 +447,8 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block) { + const bool& group_config_block, + const bool& verbose) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; @@ -460,10 +463,10 @@ int build_top_module_fine_grained_child_instances( /* Add all the CBX and CBYs across the fabric */ cb_instance_ids[CHANX] = add_top_module_connection_block_instances( module_manager, top_module, device_rr_gsb, CHANX, - compact_routing_hierarchy); + compact_routing_hierarchy, verbose); cb_instance_ids[CHANY] = add_top_module_connection_block_instances( module_manager, top_module, device_rr_gsb, CHANY, - compact_routing_hierarchy); + compact_routing_hierarchy, verbose); /* Update I/O children list */ add_top_module_io_children(module_manager, top_module, grids, layer, diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index f54e07c24..dd4f8e24d 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -44,7 +44,8 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block); + const bool& group_config_block, + const bool& verbose); } /* end namespace openfpga */ From f560fb83816b90844769fe6dc34fa878e3f5f833 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:27:17 -0700 Subject: [PATCH 124/230] [core] more verbose --- .../fabric/build_top_module_child_fine_grained_instance.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index e3abe7c07..3978339a2 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -264,7 +264,7 @@ static vtr::Matrix add_top_module_connection_block_instances( vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); if (false == rr_gsb.is_cb_exist(cb_type)) { - VTR_LOGV(verbose, "Skip connnection block at (%lu, %lu) as it does not exist\n", cb_coordinate.x(), cb_coordinate.y()); + VTR_LOGV(verbose, "Skip %s connnection block at (%lu, %lu) as it does not exist\n", cb_type == CHANX ? "X-" : "Y-", cb_coordinate.x(), cb_coordinate.y()); continue; } /* If we use compact routing hierarchy, we should instanciate the unique @@ -296,7 +296,7 @@ static vtr::Matrix add_top_module_connection_block_instances( top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], cb_instance_name); - VTR_LOGV(verbose, "Added connnection block '%s' (module '%s')\n", cb_instance_name.c_str(), cb_module_name.c_str()); + VTR_LOGV(verbose, "Added %s connnection block '%s' (module '%s')\n", cb_type == CHANX ? "X-" : "Y-", cb_instance_name.c_str(), cb_module_name.c_str()); } } From 6d798897fd60b0a1a204ce956e9229aa1f5a9039 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:46:57 -0700 Subject: [PATCH 125/230] [lib] update vtr --- .../src/fabric/build_top_module_child_fine_grained_instance.cpp | 1 + vtr-verilog-to-routing | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 3978339a2..2e7a33182 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -261,6 +261,7 @@ static vtr::Matrix add_top_module_connection_block_instances( * We will skip those modules */ const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); + VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n", cb_type == CHANX ? "X-" : "Y-", ix, iy); vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); if (false == rr_gsb.is_cb_exist(cb_type)) { diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index fbbf53d82..19fa43cc6 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit fbbf53d8207d55df8c6c62e1a0505f94ccba612a +Subproject commit 19fa43cc62bf7a38e4151c1c3867a760ba683719 From 93af72f1e362aa22a8dbbf0b734b9c7a9f703f0b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:57:36 -0700 Subject: [PATCH 126/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 19fa43cc6..589b6bcd8 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 19fa43cc62bf7a38e4151c1c3867a760ba683719 +Subproject commit 589b6bcd8bd37ac445c55239af02c757223f5d4f From 1dd03d0fddc71d8b2359d60fc60012379df8a96b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 18:34:39 -0700 Subject: [PATCH 127/230] [core] on a new feature to connect undriven pins to ground --- .../fpga_verilog/verilog_module_writer.cpp | 100 ++++++++++++------ 1 file changed, 65 insertions(+), 35 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index af901e592..7feaa1c28 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -139,6 +139,67 @@ static BasicPort generate_verilog_port_for_module_net( return port_to_return; } +/******************************************************************** + * Find all the undriven nets that are going to be local wires + * And organize it in a vector of ports + * Verilog wire writter function will use the output of this function + * to write up local wire declaration in Verilog format + *******************************************************************/ +static void +find_verilog_module_local_undriven_wires( + std::map>& local_wires; + const ModuleManager& module_manager, + const ModuleId& module_id, + const std::vector& port_type_blacklist) { + + /* Local wires could also happen for undriven ports of child module */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + for (size_t instance : + module_manager.child_module_instances(module_id, child)) { + for (const ModulePortId& child_port_id : + module_manager.module_ports(child)) { + BasicPort child_port = module_manager.module_port(child, child_port_id); + ModuleManager::e_module_port_type child_port_type = module_manager.port_type(child, child_port_id); + bool filter_out = false; + for (ModuleManager::e_module_port_type curr_port_type : port_type_blacklist) { + if (child_port_type == curr_port_type) { + filter_out = true; + break; + } + } + if (filter_out) { + continue; + } + std::vector undriven_pins; + for (size_t child_pin : child_port.pins()) { + /* Find the net linked to the pin */ + ModuleNetId net = module_manager.module_instance_port_net( + module_id, child, instance, child_port_id, child_pin); + /* We only care undriven ports */ + if (ModuleNetId::INVALID() == net) { + undriven_pins.push_back(child_pin); + } + } + if (true == undriven_pins.empty()) { + continue; + } + /* Reach here, we need a local wire, we will create a port only for the + * undriven pins of the port! */ + BasicPort instance_port; + instance_port.set_name(generate_verilog_undriven_local_wire_name( + module_manager, module_id, child, instance, child_port_id)); + /* We give the same port name as child module, this case happens to + * global ports */ + instance_port.set_width( + *std::min_element(undriven_pins.begin(), undriven_pins.end()), + *std::max_element(undriven_pins.begin(), undriven_pins.end())); + + local_wires[instance_port.get_name()].push_back(instance_port); + } + } + } +} + /******************************************************************** * Find all the nets that are going to be local wires * And organize it in a vector of ports @@ -206,41 +267,7 @@ find_verilog_module_local_wires(const ModuleManager& module_manager, } } - /* Local wires could also happen for undriven ports of child module */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - for (size_t instance : - module_manager.child_module_instances(module_id, child)) { - for (const ModulePortId& child_port_id : - module_manager.module_ports(child)) { - BasicPort child_port = module_manager.module_port(child, child_port_id); - std::vector undriven_pins; - for (size_t child_pin : child_port.pins()) { - /* Find the net linked to the pin */ - ModuleNetId net = module_manager.module_instance_port_net( - module_id, child, instance, child_port_id, child_pin); - /* We only care undriven ports */ - if (ModuleNetId::INVALID() == net) { - undriven_pins.push_back(child_pin); - } - } - if (true == undriven_pins.empty()) { - continue; - } - /* Reach here, we need a local wire, we will create a port only for the - * undriven pins of the port! */ - BasicPort instance_port; - instance_port.set_name(generate_verilog_undriven_local_wire_name( - module_manager, module_id, child, instance, child_port_id)); - /* We give the same port name as child module, this case happens to - * global ports */ - instance_port.set_width( - *std::min_element(undriven_pins.begin(), undriven_pins.end()), - *std::max_element(undriven_pins.begin(), undriven_pins.end())); - - local_wires[instance_port.get_name()].push_back(instance_port); - } - } - } + find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector()); return local_wires; } @@ -575,6 +602,9 @@ void write_verilog_module_to_file( } } + /* Use constant to drive undriven local wires */ + find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector()); + /* Print an empty line as splitter */ fp << std::endl; From 4e21bbb3f1bae2e15c018bf5dce54936b6be6313 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 20:32:56 -0700 Subject: [PATCH 128/230] [core] now support constant undriven local wires in verilog writer --- .../fpga_verilog/fabric_verilog_options.cpp | 7 ++++++ .../src/fpga_verilog/fabric_verilog_options.h | 3 +++ openfpga/src/fpga_verilog/verilog_grid.cpp | 3 +++ openfpga/src/fpga_verilog/verilog_lut.cpp | 1 + openfpga/src/fpga_verilog/verilog_memory.cpp | 5 ++++ .../fpga_verilog/verilog_module_writer.cpp | 24 +++++++++++++++++-- .../src/fpga_verilog/verilog_module_writer.h | 1 + openfpga/src/fpga_verilog/verilog_mux.cpp | 2 ++ openfpga/src/fpga_verilog/verilog_routing.cpp | 2 ++ .../verilog_shift_register_banks.cpp | 2 ++ openfpga/src/fpga_verilog/verilog_tile.cpp | 1 + .../src/fpga_verilog/verilog_top_module.cpp | 2 ++ 12 files changed, 51 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp index 17fdad397..44da5e47c 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp @@ -21,6 +21,7 @@ FabricVerilogOption::FabricVerilogOption() { default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE; time_stamp_ = true; use_relative_path_ = false; + constant_undriven_inputs_ = false; verbose_output_ = false; } @@ -53,6 +54,8 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const { return default_net_type_; } +bool FabricVerilogOption::constant_undriven_inputs() const { return constant_undriven_inputs_; } + bool FabricVerilogOption::verbose_output() const { return verbose_output_; } /****************************************************************************** @@ -106,6 +109,10 @@ void FabricVerilogOption::set_default_net_type( } } +void FabricVerilogOption::set_constant_undriven_inputs(const bool& enabled) { + constant_undriven_inputs_ = enabled; +} + void FabricVerilogOption::set_verbose_output(const bool& enabled) { verbose_output_ = enabled; } diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h index dfa7844e9..c8d5cc5eb 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.h +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h @@ -28,6 +28,7 @@ class FabricVerilogOption { bool compress_routing() const; e_verilog_default_net_type default_net_type() const; bool print_user_defined_template() const; + bool constant_undriven_inputs() const; bool verbose_output() const; public: /* Public mutators */ @@ -39,6 +40,7 @@ class FabricVerilogOption { void set_compress_routing(const bool& enabled); void set_print_user_defined_template(const bool& enabled); void set_default_net_type(const std::string& default_net_type); + void set_constant_undriven_inputs(const bool& enabled); void set_verbose_output(const bool& enabled); private: /* Internal Data */ @@ -50,6 +52,7 @@ class FabricVerilogOption { e_verilog_default_net_type default_net_type_; bool time_stamp_; bool use_relative_path_; + bool constant_undriven_inputs_; bool verbose_output_; }; diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index 7d79f3a4d..7ccdd35d4 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -114,6 +114,7 @@ static void print_verilog_primitive_block( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, primitive_module, true, + options.constant_undriven_inputs(), options.default_net_type()); /* Close file handler */ @@ -234,6 +235,7 @@ static void rec_print_verilog_logical_tile( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, pb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( @@ -348,6 +350,7 @@ static void print_verilog_physical_tile_netlist( module_manager.module_name(grid_module) + " -----")); write_verilog_module_to_file(fp, module_manager, grid_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index fab9205e4..b20b1d07a 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -63,6 +63,7 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager, fp, module_manager, lut_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(lut_model), + options.constant_undriven_inputs(), options.default_net_type()); } diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 8c56e5e8e..0e0972269 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -61,6 +61,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -84,6 +85,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, feedthru_mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -208,6 +210,7 @@ void print_verilog_submodule_memories( write_verilog_module_to_file(fp, module_manager, mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -228,6 +231,7 @@ void print_verilog_submodule_memories( write_verilog_module_to_file(fp, module_manager, feedthru_mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -241,6 +245,7 @@ void print_verilog_submodule_memories( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, mem_group_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 7feaa1c28..1c5ce17ad 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -147,7 +147,7 @@ static BasicPort generate_verilog_port_for_module_net( *******************************************************************/ static void find_verilog_module_local_undriven_wires( - std::map>& local_wires; + std::map>& local_wires, const ModuleManager& module_manager, const ModuleId& module_id, const std::vector& port_type_blacklist) { @@ -572,6 +572,7 @@ static void write_verilog_instance_to_file(std::fstream& fp, void write_verilog_module_to_file( std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id, const bool& use_explicit_port_map, + const bool& constant_local_undriven_wires, const e_verilog_default_net_type& default_net_type) { VTR_ASSERT(true == valid_file_stream(fp)); @@ -603,7 +604,26 @@ void write_verilog_module_to_file( } /* Use constant to drive undriven local wires */ - find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector()); + if (constant_local_undriven_wires) { + std::vector blacklist = { + ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT, + ModuleManager::e_module_port_type::MODULE_GPIN_PORT, + ModuleManager::e_module_port_type::MODULE_GPOUT_PORT, + ModuleManager::e_module_port_type::MODULE_GPIO_PORT, + ModuleManager::e_module_port_type::MODULE_INOUT_PORT, + ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT, + ModuleManager::e_module_port_type::MODULE_CLOCK_PORT + }; + std::map> local_undriven_wires; + find_verilog_module_local_undriven_wires(local_undriven_wires, module_manager, module_id, blacklist); + for (std::pair> port_group : + local_undriven_wires) { + for (const BasicPort& local_undriven_wire : port_group.second) { + fp << generate_verilog_port_constant_values(local_undriven_wire, std::vector(local_undriven_wire.get_width(), 0), false) << ";" + << std::endl; + } + } + } /* Print an empty line as splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.h b/openfpga/src/fpga_verilog/verilog_module_writer.h index 8e11637a7..0657c3985 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.h +++ b/openfpga/src/fpga_verilog/verilog_module_writer.h @@ -19,6 +19,7 @@ namespace openfpga { void write_verilog_module_to_file( std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id, const bool& use_explicit_port_map, + const bool& constant_local_undriven_wires, const e_verilog_default_net_type& default_net_type); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index 6fd2b2df4..38fcc0224 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -679,6 +679,7 @@ static void generate_verilog_mux_branch_module( fp, module_manager, mux_module, use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model), + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; @@ -1423,6 +1424,7 @@ static void generate_verilog_mux_module( circuit_lib.dump_explicit_port_map(mux_model) || circuit_lib.dump_explicit_port_map( circuit_lib.pass_gate_logic_model(mux_model))), + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp index dbe59e935..3826a2552 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.cpp +++ b/openfpga/src/fpga_verilog/verilog_routing.cpp @@ -117,6 +117,7 @@ static void print_verilog_routing_connection_box_unique_module( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, cb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -238,6 +239,7 @@ static void print_verilog_routing_switch_box_unique_module( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, sb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Close file handler */ diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp index f2c0e02e6..6d4707b1e 100644 --- a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp +++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp @@ -58,6 +58,7 @@ void print_verilog_submodule_shift_register_banks( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -69,6 +70,7 @@ void print_verilog_submodule_shift_register_banks( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp index da32fc58c..f6b10beaf 100644 --- a/openfpga/src/fpga_verilog/verilog_tile.cpp +++ b/openfpga/src/fpga_verilog/verilog_tile.cpp @@ -60,6 +60,7 @@ static int print_verilog_tile_module_netlist( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, tile_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index b8c302f21..60ed91956 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -63,6 +63,7 @@ void print_verilog_core_module(NetlistManager& netlist_manager, /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, core_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -129,6 +130,7 @@ void print_verilog_top_module(NetlistManager& netlist_manager, /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, top_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ From 72ee39f178dcc583dcc4776c48ecb0bf2fbf27b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 20:39:02 -0700 Subject: [PATCH 129/230] [core] add new command line option 'constant_undriven_inputs' --- openfpga/src/base/openfpga_verilog_command_template.h | 4 ++++ openfpga/src/base/openfpga_verilog_template.h | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h index 5fa7d6171..2cd03278e 100644 --- a/openfpga/src/base/openfpga_verilog_command_template.h +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -30,6 +30,10 @@ ShellCommandId add_write_fabric_verilog_command_template( shell_cmd.set_option_short_name(output_opt, "f"); shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + /* Add an option '--constant_undriven_inputs' */ + shell_cmd.add_option("constant_undriven_inputs", false, + "Use constant gnd for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric"); + /* Add an option '--explicit_port_mapping' */ shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists"); diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index 2c9656eaa..53893fe62 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -28,6 +28,8 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); + CommandOptionId opt_constant_undriven_inputs = + cmd.option("constant_undriven_inputs"); CommandOptionId opt_include_timing = cmd.option("include_timing"); CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template"); @@ -56,6 +58,15 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, } options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing()); + /* For perimeter cb, enable the constant undriven inputs, unless it is off by user */ + if (g_vpr_ctx.device().arch->perimeter_cb) { + options.set_constant_undriven_inputs(true); + VTR_LOG("Automatically enable the constant_undriven_input option as perimeter connection blocks are seen in FPGA fabric\n"); + if (!cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) { + VTR_LOG("User forces to disable the constant_undriven_input option even when perimeter connection blocks are enabled\n"); + } + } + options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); return fpga_fabric_verilog( openfpga_ctx.mutable_module_graph(), From 1f8c2436efbb91b188adedb1dd0ddfcd39f13a40 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 20:46:38 -0700 Subject: [PATCH 130/230] [core] now constant_undriven_inputs are force to enable when perimeter_cb is selected --- openfpga/src/base/openfpga_verilog_template.h | 6 ++---- openfpga/src/fpga_verilog/verilog_module_writer.cpp | 3 +-- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index 53893fe62..19109ce21 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -62,11 +62,9 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, if (g_vpr_ctx.device().arch->perimeter_cb) { options.set_constant_undriven_inputs(true); VTR_LOG("Automatically enable the constant_undriven_input option as perimeter connection blocks are seen in FPGA fabric\n"); - if (!cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) { - VTR_LOG("User forces to disable the constant_undriven_input option even when perimeter connection blocks are enabled\n"); - } + } else { + options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); } - options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); return fpga_fabric_verilog( openfpga_ctx.mutable_module_graph(), diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 1c5ce17ad..3b52c2d87 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -619,8 +619,7 @@ void write_verilog_module_to_file( for (std::pair> port_group : local_undriven_wires) { for (const BasicPort& local_undriven_wire : port_group.second) { - fp << generate_verilog_port_constant_values(local_undriven_wire, std::vector(local_undriven_wire.get_width(), 0), false) << ";" - << std::endl; + print_verilog_wire_constant_values(fp, local_undriven_wire, std::vector(local_undriven_wire.get_width(), 0)); } } } From 5865aebf93c03c108ff61321a3000f8814a77245 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 21:12:26 -0700 Subject: [PATCH 131/230] [test] add new arch --- ...N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 345 ++++++++++++++++++ 1 file changed, 345 insertions(+) create mode 100644 openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml new file mode 100644 index 000000000..ee4d3cf11 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -0,0 +1,345 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + fpga_input_center[1:0].inpad + fpga_input_center[3:2].inpad + fpga_input_center[4:4].inpad + fpga_input_center[5:5].inpad + + + + + + + + + + fpga_output_center[1:0].outpad + + fpga_output_center[3:2].outpad + + + + + + + + + + + + + fpga_input[0:0].inpad + + fpga_input[1:1].inpad + fpga_input[2:3].inpad + + + + + + + + + + + + fpga_output[0:0].outpad + fpga_output[1:1].outpad + + + + + + + + + + + + fpga_input[0:0].inpad + + fpga_input[1:1].inpad + fpga_input[2:3].inpad + + + + + + + + + + + + fpga_output[0:0].outpad + fpga_output[1:1].outpad + + + + + + + + + + + + + + fpga_input.inpad + + + + + + + + + + + + + fpga_output.outpad + + + + + + + + + + + + + + fpga_input[0:1].inpad + fpga_input[2:3].inpad + + + + + + + + + + + + fpga_output[0:0].outpad + fpga_output[1:1].outpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 4064c29d495016db9367b91584abf0540a2cd283 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 21:23:15 -0700 Subject: [PATCH 132/230] [test] updating arch for perimeter cb --- ...N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index ee4d3cf11..1af2645f1 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -65,10 +65,10 @@ - fpga_input[0:0].inpad + - fpga_input[1:1].inpad - fpga_input[2:3].inpad + + fpga_input[0:3].inpad @@ -80,8 +80,8 @@ - fpga_output[0:0].outpad - fpga_output[1:1].outpad + + fpga_output[0:1].outpad @@ -93,10 +93,10 @@ - fpga_input[0:0].inpad + fpga_input[0:3].inpad - fpga_input[1:1].inpad - fpga_input[2:3].inpad + + @@ -106,10 +106,10 @@ - + fpga_output[0:1].outpad - fpga_output[0:0].outpad - fpga_output[1:1].outpad + + @@ -150,8 +150,8 @@ - fpga_input[0:1].inpad - fpga_input[2:3].inpad + fpga_input[0:3].inpad + @@ -163,8 +163,8 @@ - fpga_output[0:0].outpad - fpga_output[1:1].outpad + fpga_output[0:1].outpad + From fe73e03c690b59d9f2b0c7bd679c57d614adfdc5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 21:31:43 -0700 Subject: [PATCH 133/230] [test] changing arch --- ...k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index 1af2645f1..11b4d4d4e 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -67,8 +67,8 @@ - - fpga_input[0:3].inpad + fpga_input[0:1].inpad + fpga_input[2:3].inpad @@ -80,8 +80,8 @@ - - fpga_output[0:1].outpad + fpga_output[0:0].outpad + fpga_output[1:1].outpad @@ -150,9 +150,9 @@ - fpga_input[0:3].inpad + fpga_input[0:1].inpad - + fpga_input[2:3].inpad @@ -163,9 +163,9 @@ - fpga_output[0:1].outpad + fpga_output[0:0].outpad - + fpga_output[1:1].outpad From 47ba57a27c9d4ce697a7def4f1b51c48f3ef9af7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:16:50 -0700 Subject: [PATCH 134/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 589b6bcd8..ba0576d43 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 589b6bcd8bd37ac445c55239af02c757223f5d4f +Subproject commit ba0576d43d1a019ff76d350b01332f0cc7bd32e3 From 266c2686d46154bed603d048d5b73942721fe9be Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:32:33 -0700 Subject: [PATCH 135/230] [core] adapt new gsb coordinate system --- openfpga/src/annotation/annotate_rr_graph.cpp | 64 ++++++++++--------- 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index badeca9de..8c721c5d0 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -98,7 +98,32 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, const vtr::Point& gsb_range, const size_t& layer, const vtr::Point& gsb_coord, + const bool& perimeter_cb, const bool& include_clock) { + /* Bounding box for GSB ranges on routing tracks. + * Note that when perimeter connection blocks are not allowed, + * - top side routing tracks for any GSB exist on y = [0, H-2) + * - right side routing tracks for any GSB exist on x = [0, W-2) + * - bottom side routing tracks for any GSB exist on y = [1, H-1) + * - left side routing tracks for any GSB exist on x = [1, W-1) + * Note that when perimeter connection blocks are allowed, + * - top side routing tracks for any GSB exist on y = [0, H-1) + * - right side routing tracks for any GSB exist on x = [0, W-1) + * - bottom side routing tracks for any GSB exist on y = [0, H) + * - left side routing tracks for any GSB exist on x = [0, W) + */ + std::map> track_range; + track_range[TOP] = vtr::Point(0, gsb_range.y(); + track_range[RIGHT] = vtr::Point(0, gsb_range.x()); + track_range[BOTTOM] = vtr::Point(1, gsb_range.y()); + track_range[LEFT] = vtr::Point(1, gsb_range.x()); + if (perimeter_cb) { + track_range[TOP] = vtr::Point(0, gsb_range.y() + 1); + track_range[RIGHT] = vtr::Point(0, gsb_range.x() + 1); + track_range[BOTTOM] = vtr::Point(0, gsb_range.y() + 2); + track_range[LEFT] = vtr::Point(0, gsb_range.x() + 2); + } + /* Create an object to return */ RRGSB rr_gsb; @@ -126,13 +151,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - /* For the border, we should take special care - * For the fabric where no cbs are on perimeter tiles (y = H - 1), - * the the border should be on the y = H - 2 - * For the fabric where cbs are on perimeter tiles, - * the border should be on the y = H - 1 - */ - if (gsb_coord.y() == gsb_range.y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -168,7 +187,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, * For the fabric where cbs are on perimeter tiles, * the border should be on the x = W - 1 */ - if (gsb_coord.x() == gsb_range.x()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -199,13 +218,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - /* For the border, we should take special care - * For the fabric where no cbs are on perimeter tiles (y = 0), - * the the border should be on the y = 0 - * For the fabric where cbs are on perimeter tiles, - * the border should be on the y = - 1, leading to no border - */ - if (!vpr_device_ctx.arch->perimeter_cb && gsb_coord.y() == 0) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -235,13 +248,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - /* For the border, we should take special care - * For the fabric where no cbs are on perimeter tiles (x = 0), - * the the border should be on the x = 0 - * For the fabric where cbs are on perimeter tiles, - * the border should be on the x = - 1, leading to no border - */ - if (!vpr_device_ctx.arch->perimeter_cb && gsb_coord.x() == 0) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -355,9 +362,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Check if TOP side chan width is 0 or not */ chan_side = TOP; /* Build the connection block: ipin and ipin_grid_side */ - /* LEFT side INPUT Pins of Grid[x+1][y+1] */ + /* LEFT side INPUT Pins of Grid[x+1][y] */ ix = rr_gsb.get_sb_x() + 1; - iy = rr_gsb.get_sb_y() + 1; + iy = rr_gsb.get_sb_y(); ipin_rr_node_grid_side = LEFT; break; case BOTTOM: /* BOTTOM = 2*/ @@ -375,9 +382,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Check if left side chan width is 0 or not */ chan_side = TOP; /* Build the connection block: ipin and ipin_grid_side */ - /* RIGHT side INPUT Pins of Grid[x][y+1] */ + /* RIGHT side INPUT Pins of Grid[x][y] */ ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; + iy = rr_gsb.get_sb_y(); ipin_rr_node_grid_side = RIGHT; break; default: @@ -459,13 +466,10 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, */ vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 2, vpr_device_ctx.grid.height() - 2); - if (vpr_device_ctx.arch->perimeter_cb) { - sub_gsb_range.set(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); - } const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, sub_gsb_range, - layer, vtr::Point(ix, iy), include_clock); + layer, vtr::Point(ix, iy), perimeter_cb, include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); device_rr_gsb.add_rr_gsb(gsb_coordinate, rr_gsb); From 1dc602a849468439118006783f26a90a53663f5d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:38:26 -0700 Subject: [PATCH 136/230] [core] syntax --- openfpga/src/annotation/annotate_rr_graph.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 8c721c5d0..b811b3521 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -113,7 +113,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, * - left side routing tracks for any GSB exist on x = [0, W) */ std::map> track_range; - track_range[TOP] = vtr::Point(0, gsb_range.y(); + track_range[TOP] = vtr::Point(0, gsb_range.y()); track_range[RIGHT] = vtr::Point(0, gsb_range.x()); track_range[BOTTOM] = vtr::Point(1, gsb_range.y()); track_range[LEFT] = vtr::Point(1, gsb_range.x()); @@ -151,7 +151,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -187,7 +187,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, * For the fabric where cbs are on perimeter tiles, * the border should be on the x = W - 1 */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.x() || gsb_coord.x() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -218,7 +218,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -248,7 +248,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -469,7 +469,7 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, sub_gsb_range, - layer, vtr::Point(ix, iy), perimeter_cb, include_clock); + layer, vtr::Point(ix, iy), vpr_device_ctx.arch->perimeter_cb, include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); device_rr_gsb.add_rr_gsb(gsb_coordinate, rr_gsb); From b6e89b8943a09975cfb3084e2820aa806bcffae3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:52:35 -0700 Subject: [PATCH 137/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index ba0576d43..826a10be4 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit ba0576d43d1a019ff76d350b01332f0cc7bd32e3 +Subproject commit 826a10be4e6e45976f64ea3a0f6503516a8d777d From ba1482f53335c676eac64b669b1a41075ebe1c5f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:01:31 -0700 Subject: [PATCH 138/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 826a10be4..b06f2ee34 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 826a10be4e6e45976f64ea3a0f6503516a8d777d +Subproject commit b06f2ee34036a8c981a2c202ec06251c1bb2b81a From f6adca15452405bcbb63adcfae4315ead242cd12 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:02:01 -0700 Subject: [PATCH 139/230] [core] fixed a bug --- openfpga/src/annotation/annotate_rr_graph.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index b811b3521..d0833ae19 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -151,7 +151,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -187,7 +187,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, * For the fabric where cbs are on perimeter tiles, * the border should be on the x = W - 1 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.x() || gsb_coord.x() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.x() || gsb_coord.x() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -218,7 +218,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -248,7 +248,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } From fdbc427f70aea0cd1bfe98e4be8e70edc2b931ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:17:05 -0700 Subject: [PATCH 140/230] [core] debug --- openfpga/src/annotation/annotate_rr_graph.cpp | 8 ++++---- vtr-verilog-to-routing | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index d0833ae19..78ff7c356 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -115,13 +115,13 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, std::map> track_range; track_range[TOP] = vtr::Point(0, gsb_range.y()); track_range[RIGHT] = vtr::Point(0, gsb_range.x()); - track_range[BOTTOM] = vtr::Point(1, gsb_range.y()); - track_range[LEFT] = vtr::Point(1, gsb_range.x()); + track_range[BOTTOM] = vtr::Point(0, gsb_range.y()); + track_range[LEFT] = vtr::Point(0, gsb_range.x()); if (perimeter_cb) { track_range[TOP] = vtr::Point(0, gsb_range.y() + 1); track_range[RIGHT] = vtr::Point(0, gsb_range.x() + 1); - track_range[BOTTOM] = vtr::Point(0, gsb_range.y() + 2); - track_range[LEFT] = vtr::Point(0, gsb_range.x() + 2); + track_range[BOTTOM] = vtr::Point(0, gsb_range.y() + 1); + track_range[LEFT] = vtr::Point(0, gsb_range.x() + 1); } /* Create an object to return */ diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index b06f2ee34..de0d0bc21 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit b06f2ee34036a8c981a2c202ec06251c1bb2b81a +Subproject commit de0d0bc214419cae53c10e6a1349d4ae251625f8 From e5d75cc51e92a78875f0271cab07a90596230886 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:47:04 -0700 Subject: [PATCH 141/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index de0d0bc21..0a1bc20b0 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit de0d0bc214419cae53c10e6a1349d4ae251625f8 +Subproject commit 0a1bc20b08da6ad0d0fbf5fe9e931b1bbdac09a1 From 46e3b4b0712a2de61346b6812190ee549a42d6d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:50:41 -0700 Subject: [PATCH 142/230] [core] debug --- openfpga/src/annotation/annotate_rr_graph.cpp | 42 +++---------------- 1 file changed, 6 insertions(+), 36 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 78ff7c356..915dae2fd 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -100,30 +100,6 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, const vtr::Point& gsb_coord, const bool& perimeter_cb, const bool& include_clock) { - /* Bounding box for GSB ranges on routing tracks. - * Note that when perimeter connection blocks are not allowed, - * - top side routing tracks for any GSB exist on y = [0, H-2) - * - right side routing tracks for any GSB exist on x = [0, W-2) - * - bottom side routing tracks for any GSB exist on y = [1, H-1) - * - left side routing tracks for any GSB exist on x = [1, W-1) - * Note that when perimeter connection blocks are allowed, - * - top side routing tracks for any GSB exist on y = [0, H-1) - * - right side routing tracks for any GSB exist on x = [0, W-1) - * - bottom side routing tracks for any GSB exist on y = [0, H) - * - left side routing tracks for any GSB exist on x = [0, W) - */ - std::map> track_range; - track_range[TOP] = vtr::Point(0, gsb_range.y()); - track_range[RIGHT] = vtr::Point(0, gsb_range.x()); - track_range[BOTTOM] = vtr::Point(0, gsb_range.y()); - track_range[LEFT] = vtr::Point(0, gsb_range.x()); - if (perimeter_cb) { - track_range[TOP] = vtr::Point(0, gsb_range.y() + 1); - track_range[RIGHT] = vtr::Point(0, gsb_range.x() + 1); - track_range[BOTTOM] = vtr::Point(0, gsb_range.y() + 1); - track_range[LEFT] = vtr::Point(0, gsb_range.x() + 1); - } - /* Create an object to return */ RRGSB rr_gsb; @@ -151,7 +127,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { + if (gsb_coord.y() == gsb_range.y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -181,13 +157,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, break; case RIGHT: /* RIGHT = 1 */ - /* For the border, we should take special care - * For the fabric where no cbs are on perimeter tiles (x = W - 1), - * the the border should be on the x = W - 2 - * For the fabric where cbs are on perimeter tiles, - * the border should be on the x = W - 1 - */ - if (track_range[side_manager.get_side()].x() > gsb_coord.x() || gsb_coord.x() > track_range[side_manager.get_side()].y()) { + if (gsb_coord.x() == gsb_range.x()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -218,7 +188,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { + if (!perimeter_cb && gsb_coord.y() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -248,7 +218,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { + if (!perimeter_cb && gsb_coord.x() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -464,8 +434,8 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, * the GSBs at the borderside correctly sort drive_rr_nodes should be * called if required by users */ - vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 2, - vpr_device_ctx.grid.height() - 2); + vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 1, + vpr_device_ctx.grid.height() - 1); const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, sub_gsb_range, From 36c0cfe645007479436591cfab0455dead961cb8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:14:14 -0700 Subject: [PATCH 143/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 0a1bc20b0..4da28ffbc 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 0a1bc20b08da6ad0d0fbf5fe9e931b1bbdac09a1 +Subproject commit 4da28ffbccf4eb2b31a57ec36a3c135225ef40f9 From f2506598a98feadbec3c8d676d4482ea44280fe7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:20:49 -0700 Subject: [PATCH 144/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 4da28ffbc..c71c3b9d3 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 4da28ffbccf4eb2b31a57ec36a3c135225ef40f9 +Subproject commit c71c3b9d3a1a17b6865511b29e5d2e14f5e9fe15 From 283aa3a1c9fea01cf1952a82da59612ed6e45c0c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:21:17 -0700 Subject: [PATCH 145/230] [core] debug --- openfpga/src/annotation/annotate_rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 915dae2fd..a1ad9c24c 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -330,7 +330,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, case RIGHT: /* RIGHT = 1 */ /* For the bording, we should take special care */ /* Check if TOP side chan width is 0 or not */ - chan_side = TOP; + chan_side = BOTTOM; /* Build the connection block: ipin and ipin_grid_side */ /* LEFT side INPUT Pins of Grid[x+1][y] */ ix = rr_gsb.get_sb_x() + 1; @@ -350,7 +350,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, case LEFT: /* LEFT = 3 */ /* For the bording, we should take special care */ /* Check if left side chan width is 0 or not */ - chan_side = TOP; + chan_side = BOTTOM; /* Build the connection block: ipin and ipin_grid_side */ /* RIGHT side INPUT Pins of Grid[x][y] */ ix = rr_gsb.get_sb_x(); From a41f4371096633cca8782c34121b293dc4ae77af Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:36:47 -0700 Subject: [PATCH 146/230] [core] now netlist look ok --- openfpga/src/fabric/build_top_module_connection.cpp | 6 +++--- openfpga/src/fabric/build_top_module_utils.cpp | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 2493c20c9..d5d4e7aea 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -753,17 +753,17 @@ static void add_top_module_nets_connect_sb_and_cb( * is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then * use is_cb_exist() */ - if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) { + if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) { if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } } - if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { /* Only for the condition where cbs are on perimeter, the neighbour cb will be invalid * Bypass in such case on finding neighbour cbs */ - if (BOTTOM == side_manager.get_side() && instance_sb_coordinate.y() == 0) { + if (TOP == side_manager.get_side() && instance_sb_coordinate.y() == device_rr_gsb.get_gsb_range().y()) { continue; } if (RIGHT == side_manager.get_side() && instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) { diff --git a/openfpga/src/fabric/build_top_module_utils.cpp b/openfpga/src/fabric/build_top_module_utils.cpp index ebf52eb77..8b7c8f2e6 100644 --- a/openfpga/src/fabric/build_top_module_utils.cpp +++ b/openfpga/src/fabric/build_top_module_utils.cpp @@ -100,13 +100,13 @@ vtr::Point find_top_module_gsb_coordinate_by_sb_side( vtr::Point gsb_coordinate; - if ((TOP == sb_side) || (LEFT == sb_side)) { + if ((BOTTOM == sb_side) || (LEFT == sb_side)) { gsb_coordinate.set_x(rr_gsb.get_x()); gsb_coordinate.set_y(rr_gsb.get_y()); return gsb_coordinate; } - VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side)); + VTR_ASSERT((RIGHT == sb_side) || (TOP == sb_side)); /* RIGHT side: x + 1 */ if (RIGHT == sb_side) { @@ -115,9 +115,9 @@ vtr::Point find_top_module_gsb_coordinate_by_sb_side( } /* BOTTOM side: y - 1 */ - if (BOTTOM == sb_side) { + if (TOP == sb_side) { gsb_coordinate.set_x(rr_gsb.get_x()); - gsb_coordinate.set_y(rr_gsb.get_y() - 1); + gsb_coordinate.set_y(rr_gsb.get_y() + 1); } return gsb_coordinate; From 5e89b950edc561e5b5b3e72f373abd3d62201c7b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 13:41:38 -0700 Subject: [PATCH 147/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index c71c3b9d3..d2be1c8b2 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit c71c3b9d3a1a17b6865511b29e5d2e14f5e9fe15 +Subproject commit d2be1c8b2629069479863826695ed317bf88618a From 46d916f0a056c9bdbfca4bab90eedb1fa8ba07f7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 16:59:08 -0700 Subject: [PATCH 148/230] [core] fixed the bugs in fabric tile build-up --- openfpga/src/fabric/build_fabric_tile.cpp | 261 +++++++++++++++------ openfpga/src/fabric/build_tile_modules.cpp | 4 +- 2 files changed, 186 insertions(+), 79 deletions(-) diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index a1e5f9460..c20c37537 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -22,12 +22,110 @@ namespace openfpga { /******************************************************************** - * Build tiles by following the top-level style. - * - The programmble block, e.g., clb, is placed on the top-left corner - * - The connection blocks and switch block are placed on the right and bottom - *sides + * With a given coordinate of a grid, find an existing fabric tile + * or create a new fabric tile + * - A grid may never exist in any fabric tile (no coordinate matches) + * Create a new one + * - A grid already in another fabric tile (occur in heterogeneous blocks) + * Find the existing one *******************************************************************/ -static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, +static int find_or_create_one_fabric_tile_from_grid( + FabricTile& fabric_tile, + FabricTileId& curr_tile_id, + const DeviceGrid& grids, + const t_physical_tile_loc& tile_loc, + const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, + const bool& verbose) { + t_physical_tile_type_ptr phy_tile_type = + grids.get_physical_type(tile_loc); + vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); + vtr::Point curr_gsb_coord(tile_loc.x, tile_loc.y); + + bool skip_add_pb = false; + /* For EMPTY grid, routing blocks may still be required if there is a gsb + */ + if (true == is_empty_type(phy_tile_type)) { + skip_add_pb = true; + if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", + curr_tile_coord.x(), curr_tile_coord.y()); + return CMD_EXEC_SUCCESS; + } + /* Need to create a new tile here */ + VTR_LOGV(verbose, + "Create tile[%lu][%lu] which only has routing but not a " + "programmable block\n", + curr_tile_coord.x(), curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); + } else if ((0 < grids.get_width_offset(tile_loc)) || + (0 < grids.get_height_offset(tile_loc))) { + /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ + /* Find the root of this grid, the instance id should be valid. + * We just copy it here + */ + vtr::Point root_tile_coord( + curr_tile_coord.x() - grids.get_width_offset(tile_loc), + curr_tile_coord.y() - grids.get_height_offset(tile_loc)); + skip_add_pb = true; + VTR_LOGV(verbose, + "Tile[%lu][%lu] contains a heterogeneous block which is " + "rooted from tile[%lu][%lu]\n", + curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(), + root_tile_coord.y()); + curr_tile_id = fabric_tile.find_tile(root_tile_coord); + /* Update the coordinates of the pb in tiles */ + size_t root_pb_idx_in_curr_tile = + fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord); + int status_code = fabric_tile.set_pb_max_coordinate( + curr_tile_id, root_pb_idx_in_curr_tile, curr_tile_coord); + if (status_code != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } + } else { + /* Need to create a new tile here */ + VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", + curr_tile_coord.x(), curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); + } + + /* Ensure that we have a valid id */ + if (!fabric_tile.valid_tile_id(curr_tile_id)) { + VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n", + curr_tile_coord.x(), curr_tile_coord.y()); + return CMD_EXEC_FATAL_ERROR; + } + + /* Add components: pb, cbx, cby, and sb if exists */ + if (!skip_add_pb) { + fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord, + curr_gsb_coord); + } + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Build tiles by following the bottom style. + * - The programmble block, e.g., clb, is placed on the bottom-left corner + * - The connection blocks and switch block are placed on the top and bottom + *sides + * This is exactly how GSB is organized. Just need to transfer data from one GSB + * The gsb coordinate is the same as the grid coordinate when the + * bottom-left style is considered + * + * ------------------------------ + * +----------+ +----------+ ^ + * | CBx | | SB | | + * | [x][y] | | [x][y] | GSB[x][y] + * +----------+ +----------+ | + * +----------+ +----------+ | + * | Grid | | CBy | | + * | [x][y] | | [x][y] | | + * +----------+ +----------+ v + * ------------------------------ + * + *******************************************************************/ +static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, const DeviceGrid& grids, const size_t& layer, const RRGraphView& rr_graph, @@ -39,82 +137,16 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); - t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(tile_loc); - bool skip_add_pb = false; - vtr::Point curr_tile_coord(ix, iy); - vtr::Point curr_gsb_coord(ix, iy - 1); FabricTileId curr_tile_id = FabricTileId::INVALID(); - /* For EMPTY grid, routing blocks may still be required if there is a gsb - */ - if (true == is_empty_type(phy_tile_type)) { - skip_add_pb = true; - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", - curr_tile_coord.x(), curr_tile_coord.y()); - continue; - } - /* Need to create a new tile here */ - VTR_LOGV(verbose, - "Create tile[%lu][%lu] which only has routing but not a " - "programmable block\n", - curr_tile_coord.x(), curr_tile_coord.y()); - curr_tile_id = fabric_tile.create_tile(curr_tile_coord); - } else if ((0 < grids.get_width_offset(tile_loc)) || - (0 < grids.get_height_offset(tile_loc))) { - /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ - /* Find the root of this grid, the instance id should be valid. - * We just copy it here - */ - vtr::Point root_tile_coord( - ix - grids.get_width_offset(tile_loc), - iy - grids.get_height_offset(tile_loc)); - skip_add_pb = true; - VTR_LOGV(verbose, - "Tile[%lu][%lu] contains a heterogeneous block which is " - "rooted from tile[%lu][%lu]\n", - curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(), - root_tile_coord.y()); - curr_tile_id = fabric_tile.find_tile(root_tile_coord); - /* Update the coordinates of the pb in tiles */ - size_t root_pb_idx_in_curr_tile = - fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord); - status_code = fabric_tile.set_pb_max_coordinate( - curr_tile_id, root_pb_idx_in_curr_tile, vtr::Point(ix, iy)); - if (status_code != CMD_EXEC_SUCCESS) { - return CMD_EXEC_FATAL_ERROR; - } - } else { - /* Need to create a new tile here */ - VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", - curr_tile_coord.x(), curr_tile_coord.y()); - curr_tile_id = fabric_tile.create_tile(curr_tile_coord); - } - - /* Ensure that we have a valid id */ - if (!fabric_tile.valid_tile_id(curr_tile_id)) { - VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n", ix, iy); + status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose); + if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } - - /* Add components: pb, cbx, cby, and sb if exists */ - if (!skip_add_pb) { - fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord, - curr_gsb_coord); + /* If no valid tile is created or spotted, the tile does not exist physically, skip */ + if (fabric_tile.valid_tile_id(curr_tile_id)) { + continue; } - /* The gsb coordinate is different than the grid coordinate when the - * top-left style is considered - * - * +----------+ +----------+ - * | Grid | | CBx | - * | [x][y] | | [x][y] | - * +----------+ +----------+ - * +----------+ +----------+ - * | CBy | | SB | - * | [x][y-1] | | [x][y-1] | - * +----------+ +----------+ - * - */ + vtr::Point curr_gsb_coord(ix, iy); if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { continue; } @@ -135,6 +167,77 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, return status_code; } + +/******************************************************************** + * Build tiles by following the top-left style. + * - The programmble block, e.g., clb, is placed on the top-left corner + * - The connection blocks and switch block are placed on the right and bottom + *sides + * Tile[x][y] + * ------------------------------ + * +----------+ +----------+ ^ + * | Grid | | CBy | GSB[x][y] + * | [x][y] | | [x][y] | | + * +----------+ +----------+ v + * ------------------------------ + * +----------+ +----------+ ^ + * | CBx | | SB | | + * | [x][y-1] | | [x][y-1] | GSB[x][y-1] + * +----------+ +----------+ | + * ------------------------------ + + *******************************************************************/ +static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, + const DeviceGrid& grids, + const size_t& layer, + const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, + const bool& verbose) { + int status_code = CMD_EXEC_SUCCESS; + + /* Walk through all the device rr_gsb and create tile one by one */ + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + t_physical_tile_loc tile_loc(ix, iy, layer); + FabricTileId curr_tile_id = FabricTileId::INVALID(); + status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose); + if (status_code != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } + /* If no valid tile is created or spotted, the tile does not exist physically, skip */ + if (fabric_tile.valid_tile_id(curr_tile_id)) { + continue; + } + /* For the cby in the same gsb */ + vtr::Point curr_gsb_coord(ix, iy); + if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + continue; + } + const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); + if (curr_rr_gsb.is_cb_exist(CHANY)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANY, + curr_rr_gsb.get_sb_coordinate()); + } + /* For the cbx and sb in the neighbour gsb */ + vtr::Point neighbor_gsb_coord(ix, iy - 1); + if (!device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { + continue; + } + const RRGSB& neighbor_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (neighbor_rr_gsb.is_cb_exist(CHANX)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANX, + neighbor_rr_gsb.get_sb_coordinate()); + } + if (neighbor_rr_gsb.is_sb_exist(rr_graph)) { + fabric_tile.add_sb_coordinate(curr_tile_id, + neighbor_rr_gsb.get_sb_coordinate()); + } + } + } + + return status_code; +} + /******************************************************************** * Build tile-level information for a given FPGA fabric, w.r.t. to configuration *******************************************************************/ @@ -152,6 +255,10 @@ int build_fabric_tile(FabricTile& fabric_tile, const TileConfig& tile_config, if (tile_config.style() == TileConfig::e_style::TOP_LEFT) { status_code = build_fabric_tile_style_top_left( fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose); + } else if (tile_config.style() == TileConfig::e_style::BOTTOM_LEFT) { + status_code = build_fabric_tile_style_bottom_left( + fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose); + } else { /* Error out for styles that are not supported yet! */ VTR_LOG_ERROR("Tile style '%s' is not supported yet!\n", diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index f93cd07bf..ab5b535fe 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -732,13 +732,13 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( * is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then * use is_cb_exist() */ - if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) { + if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) { if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } } - if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate); if (false == adjacent_gsb.is_cb_exist(cb_type)) { From cca9fb475663e2cf01f000178b76a98413fda47f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 17:55:19 -0700 Subject: [PATCH 149/230] [core] fixed a bug on bottom left tile organization --- openfpga/src/fabric/build_fabric_tile.cpp | 123 ++++++++++++++-------- 1 file changed, 78 insertions(+), 45 deletions(-) diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index c20c37537..9e4580600 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -34,8 +34,6 @@ static int find_or_create_one_fabric_tile_from_grid( FabricTileId& curr_tile_id, const DeviceGrid& grids, const t_physical_tile_loc& tile_loc, - const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const bool& verbose) { t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); @@ -46,18 +44,7 @@ static int find_or_create_one_fabric_tile_from_grid( /* For EMPTY grid, routing blocks may still be required if there is a gsb */ if (true == is_empty_type(phy_tile_type)) { - skip_add_pb = true; - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", - curr_tile_coord.x(), curr_tile_coord.y()); - return CMD_EXEC_SUCCESS; - } - /* Need to create a new tile here */ - VTR_LOGV(verbose, - "Create tile[%lu][%lu] which only has routing but not a " - "programmable block\n", - curr_tile_coord.x(), curr_tile_coord.y()); - curr_tile_id = fabric_tile.create_tile(curr_tile_coord); + return CMD_EXEC_SUCCESS; } else if ((0 < grids.get_width_offset(tile_loc)) || (0 < grids.get_height_offset(tile_loc))) { /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ @@ -138,28 +125,42 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); FabricTileId curr_tile_id = FabricTileId::INVALID(); - status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose); + status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } - /* If no valid tile is created or spotted, the tile does not exist physically, skip */ - if (fabric_tile.valid_tile_id(curr_tile_id)) { - continue; - } + /* If no tile is created for the pb, check if routing exists */ + vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); vtr::Point curr_gsb_coord(ix, iy); - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - continue; + if (!fabric_tile.valid_tile_id(curr_tile_id)) { + if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", + curr_tile_coord.x(), curr_tile_coord.y()); + continue; + } + /* Need to create a new tile here */ + VTR_LOGV(verbose, + "Create tile[%lu][%lu] which only has routing but not a " + "programmable block\n", + curr_tile_coord.x(), curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); for (t_rr_type cb_type : {CHANX, CHANY}) { if (curr_rr_gsb.is_cb_exist(cb_type)) { fabric_tile.add_cb_coordinate(curr_tile_id, cb_type, curr_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added %s connection block [%lu][%lu] to tile[%lu][%lu]\n", + cb_type == CHANX ? "x-" : "y-", curr_rr_gsb.get_cb_x(cb_type), curr_rr_gsb.get_cb_y(cb_type), + ix, iy); } } if (curr_rr_gsb.is_sb_exist(rr_graph)) { fabric_tile.add_sb_coordinate(curr_tile_id, curr_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", + curr_rr_gsb.get_sb_x(), curr_rr_gsb.get_sb_y(), + ix, iy); } } } @@ -200,37 +201,69 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); FabricTileId curr_tile_id = FabricTileId::INVALID(); - status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose); + status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } - /* If no valid tile is created or spotted, the tile does not exist physically, skip */ - if (fabric_tile.valid_tile_id(curr_tile_id)) { - continue; + /* If no valid tile is created/found by the pb, check if there is any routing inside */ + vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); + vtr::Point curr_gsb_coord(ix, iy); + vtr::Point neighbor_gsb_coord(ix, iy - 1); + if (!fabric_tile.valid_tile_id(curr_tile_id)) { + bool routing_exist = false; + if (device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + const RRGSB& routing_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); + if (routing_rr_gsb.is_cb_exist(CHANY)) { + routing_exist = true; + } + } + if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { + const RRGSB& routing_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (routing_rr_gsb.is_cb_exist(CHANX) || routing_rr_gsb.is_sb_exist(rr_graph)) { + routing_exist = true; + } + } + if (!routing_exist) { + VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", + curr_tile_coord.x(), curr_tile_coord.y()); + continue; + } + /* Need to create a new tile here */ + VTR_LOGV(verbose, + "Create tile[%lu][%lu] which only has routing but not a " + "programmable block\n", + curr_tile_coord.x(), curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } /* For the cby in the same gsb */ - vtr::Point curr_gsb_coord(ix, iy); - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - continue; - } - const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); - if (curr_rr_gsb.is_cb_exist(CHANY)) { - fabric_tile.add_cb_coordinate(curr_tile_id, CHANY, - curr_rr_gsb.get_sb_coordinate()); + if (device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); + if (curr_rr_gsb.is_cb_exist(CHANY)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANY, + curr_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added y- connection block [%lu][%lu] to tile[%lu][%lu]\n", + curr_rr_gsb.get_cb_x(CHANY), curr_rr_gsb.get_cb_y(CHANY), + ix, iy); + } } /* For the cbx and sb in the neighbour gsb */ - vtr::Point neighbor_gsb_coord(ix, iy - 1); - if (!device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { - continue; - } - const RRGSB& neighbor_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); - if (neighbor_rr_gsb.is_cb_exist(CHANX)) { - fabric_tile.add_cb_coordinate(curr_tile_id, CHANX, - neighbor_rr_gsb.get_sb_coordinate()); - } - if (neighbor_rr_gsb.is_sb_exist(rr_graph)) { - fabric_tile.add_sb_coordinate(curr_tile_id, - neighbor_rr_gsb.get_sb_coordinate()); + if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { + const RRGSB& neighbor_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (neighbor_rr_gsb.is_cb_exist(CHANX)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANX, + neighbor_rr_gsb.get_sb_coordinate()); + + VTR_LOGV(verbose, "Added x- connection block [%lu][%lu] to tile[%lu][%lu]\n", + neighbor_rr_gsb.get_cb_x(CHANX), neighbor_rr_gsb.get_cb_y(CHANX), + ix, iy); + } + if (neighbor_rr_gsb.is_sb_exist(rr_graph)) { + fabric_tile.add_sb_coordinate(curr_tile_id, + neighbor_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", + neighbor_rr_gsb.get_sb_x(), neighbor_rr_gsb.get_sb_y(), + ix, iy); + } } } } From a46820b7c1e820446a5e3557970ea46acb982535 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 18:00:37 -0700 Subject: [PATCH 150/230] [core] add a new test for bottom-left tile grouping --- .../regression_test_scripts/basic_reg_test.sh | 1 + .../homo_fabric_tile_bl/config/task.conf | 35 +++++++++++++++++++ .../config/tile_config.xml | 1 + 3 files changed, 37 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index e8902632c..cdb93ee16 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -194,6 +194,7 @@ echo -e "Testing tiles with routing tracks around I/O"; run-task basic_tests/tile_organization/perimeter_cb $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; run-task basic_tests/tile_organization/homo_fabric_tile $@ +run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf new file mode 100644 index 000000000..c07a08d33 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml new file mode 100644 index 000000000..026c140be --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml @@ -0,0 +1 @@ + From e95b264965eaf5063226a4ecb580d70af6d9767a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 18:08:48 -0700 Subject: [PATCH 151/230] [core] debugging --- openfpga/src/fabric/build_fabric_tile.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index 9e4580600..b8dd25938 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -145,6 +145,11 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, curr_tile_coord.x(), curr_tile_coord.y()); curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } + if (fabric_tile.valid_tile_id(curr_tile_id) && !device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV(verbose, "Skip to add routing to tile[%lu][%lu] as it is not required\n", + curr_tile_coord.x(), curr_tile_coord.y()); + continue; + } const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); for (t_rr_type cb_type : {CHANX, CHANY}) { if (curr_rr_gsb.is_cb_exist(cb_type)) { From 1f7fbfef64cd2b2657600341b0655725731606a7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 18:19:22 -0700 Subject: [PATCH 152/230] [core] fixed a bug on inter-tile connections in top module --- openfpga/src/fabric/build_top_module_child_tile_instance.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 3c1c86c1c..0ad953f68 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -802,13 +802,13 @@ static int build_top_module_tile_nets_between_sb_and_cb( * is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then * use is_cb_exist() */ - if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) { + if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) { if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } } - if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate); if (false == adjacent_gsb.is_cb_exist(cb_type)) { From 6024e35f89ce05eaa8431481008c00c945fa0ae6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 18:50:14 -0700 Subject: [PATCH 153/230] [core] fixed a bug --- openfpga/src/fabric/build_top_module_memory.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 47238685e..d9d65fbc2 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -141,7 +141,7 @@ static void organize_top_module_tile_memory_modules( const vtr::Point& tile_coord, const e_side& tile_border_side) { vtr::Point gsb_coord_range = device_rr_gsb.get_gsb_range(); - vtr::Point gsb_coord(tile_coord.x(), tile_coord.y() - 1); + vtr::Point gsb_coord(tile_coord.x(), tile_coord.y()); /* We do NOT consider SB and CBs if the gsb is not in the range! */ if ((gsb_coord.x() < gsb_coord_range.x()) && From 43ca3ec747e4232d54509d2c4c4d9add5518706e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 6 Jul 2024 12:11:31 -0700 Subject: [PATCH 154/230] [test] make arch pin loc for spread for perimeter cb validation --- ...k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index 11b4d4d4e..2bab2cd89 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -93,9 +93,9 @@ - fpga_input[0:3].inpad + fpga_input[0:1].inpad - + fpga_input[2:3].inpad @@ -106,9 +106,9 @@ - fpga_output[0:1].outpad + fpga_output[0:0].outpad - + fpga_output[1:1].outpad @@ -122,8 +122,8 @@ - - fpga_input.inpad + fpga_input[0:1].inpad + fpga_input[2:3].inpad @@ -135,8 +135,8 @@ - - fpga_output.outpad + fpga_output[0:0].outpad + fpga_output[1:1].outpad From 703cbddc9ed3812b0ff651765997516236bcc9af Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 6 Jul 2024 12:14:57 -0700 Subject: [PATCH 155/230] [core] code format --- openfpga/src/annotation/annotate_rr_graph.cpp | 10 +-- .../base/openfpga_verilog_command_template.h | 6 +- openfpga/src/base/openfpga_verilog_template.h | 10 ++- openfpga/src/fabric/build_device_module.cpp | 3 +- openfpga/src/fabric/build_fabric_tile.cpp | 87 ++++++++++--------- .../build_grid_module_duplicated_pins.cpp | 11 ++- .../src/fabric/build_grid_module_utils.cpp | 10 ++- openfpga/src/fabric/build_grid_module_utils.h | 3 +- openfpga/src/fabric/build_grid_modules.cpp | 20 ++--- openfpga/src/fabric/build_tile_modules.cpp | 38 ++++---- openfpga/src/fabric/build_tile_modules.h | 23 +++-- ...top_module_child_fine_grained_instance.cpp | 23 +++-- ...d_top_module_child_fine_grained_instance.h | 3 +- .../fabric/build_top_module_connection.cpp | 10 ++- .../fpga_verilog/fabric_verilog_options.cpp | 4 +- openfpga/src/fpga_verilog/verilog_grid.cpp | 14 ++- openfpga/src/fpga_verilog/verilog_lut.cpp | 3 +- openfpga/src/fpga_verilog/verilog_memory.cpp | 13 ++- .../fpga_verilog/verilog_module_writer.cpp | 39 +++++---- openfpga/src/fpga_verilog/verilog_mux.cpp | 6 +- openfpga/src/fpga_verilog/verilog_routing.cpp | 14 ++- .../verilog_shift_register_banks.cpp | 14 ++- openfpga/src/fpga_verilog/verilog_tile.cpp | 7 +- .../src/fpga_verilog/verilog_top_module.cpp | 14 ++- 24 files changed, 192 insertions(+), 193 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index a1ad9c24c..373607fb2 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -98,8 +98,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, const vtr::Point& gsb_range, const size_t& layer, const vtr::Point& gsb_coord, - const bool& perimeter_cb, - const bool& include_clock) { + const bool& perimeter_cb, const bool& include_clock) { /* Create an object to return */ RRGSB rr_gsb; @@ -436,10 +435,9 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, */ vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); - const RRGSB& rr_gsb = - build_rr_gsb(vpr_device_ctx, - sub_gsb_range, - layer, vtr::Point(ix, iy), vpr_device_ctx.arch->perimeter_cb, include_clock); + const RRGSB& rr_gsb = build_rr_gsb( + vpr_device_ctx, sub_gsb_range, layer, vtr::Point(ix, iy), + vpr_device_ctx.arch->perimeter_cb, include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); device_rr_gsb.add_rr_gsb(gsb_coordinate, rr_gsb); diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h index 2cd03278e..001f7ee40 100644 --- a/openfpga/src/base/openfpga_verilog_command_template.h +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -31,8 +31,10 @@ ShellCommandId add_write_fabric_verilog_command_template( shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); /* Add an option '--constant_undriven_inputs' */ - shell_cmd.add_option("constant_undriven_inputs", false, - "Use constant gnd for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric"); + shell_cmd.add_option( + "constant_undriven_inputs", false, + "Use constant gnd for undriven wires in Verilog netlists. Recommand to " + "enable when there are boundary routing tracks in FPGA fabric"); /* Add an option '--explicit_port_mapping' */ shell_cmd.add_option("explicit_port_mapping", false, diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index 19109ce21..93dc8035a 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -58,12 +58,16 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, } options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing()); - /* For perimeter cb, enable the constant undriven inputs, unless it is off by user */ + /* For perimeter cb, enable the constant undriven inputs, unless it is off by + * user */ if (g_vpr_ctx.device().arch->perimeter_cb) { options.set_constant_undriven_inputs(true); - VTR_LOG("Automatically enable the constant_undriven_input option as perimeter connection blocks are seen in FPGA fabric\n"); + VTR_LOG( + "Automatically enable the constant_undriven_input option as perimeter " + "connection blocks are seen in FPGA fabric\n"); } else { - options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); + options.set_constant_undriven_inputs( + cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); } return fpga_fabric_verilog( diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index e03ee2510..a04e9e015 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -128,7 +128,8 @@ int build_device_module_graph( openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph, openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib, sram_model, openfpga_ctx.arch().config_protocol.type(), - name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view, verbose); + name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view, + verbose); } /* Build FPGA fabric top-level module */ diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index b8dd25938..e9747e920 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -22,7 +22,7 @@ namespace openfpga { /******************************************************************** - * With a given coordinate of a grid, find an existing fabric tile + * With a given coordinate of a grid, find an existing fabric tile * or create a new fabric tile * - A grid may never exist in any fabric tile (no coordinate matches) * Create a new one @@ -30,13 +30,9 @@ namespace openfpga { * Find the existing one *******************************************************************/ static int find_or_create_one_fabric_tile_from_grid( - FabricTile& fabric_tile, - FabricTileId& curr_tile_id, - const DeviceGrid& grids, - const t_physical_tile_loc& tile_loc, - const bool& verbose) { - t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(tile_loc); + FabricTile& fabric_tile, FabricTileId& curr_tile_id, const DeviceGrid& grids, + const t_physical_tile_loc& tile_loc, const bool& verbose) { + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); vtr::Point curr_gsb_coord(tile_loc.x, tile_loc.y); @@ -71,8 +67,8 @@ static int find_or_create_one_fabric_tile_from_grid( } } else { /* Need to create a new tile here */ - VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", - curr_tile_coord.x(), curr_tile_coord.y()); + VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", curr_tile_coord.x(), + curr_tile_coord.y()); curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } @@ -100,7 +96,7 @@ static int find_or_create_one_fabric_tile_from_grid( * The gsb coordinate is the same as the grid coordinate when the * bottom-left style is considered * - * ------------------------------ + * ------------------------------ * +----------+ +----------+ ^ * | CBx | | SB | | * | [x][y] | | [x][y] | GSB[x][y] @@ -113,11 +109,11 @@ static int find_or_create_one_fabric_tile_from_grid( * *******************************************************************/ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, - const DeviceGrid& grids, - const size_t& layer, - const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, - const bool& verbose) { + const DeviceGrid& grids, + const size_t& layer, + const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, + const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; /* Walk through all the device rr_gsb and create tile one by one */ @@ -125,7 +121,8 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); FabricTileId curr_tile_id = FabricTileId::INVALID(); - status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, verbose); + status_code = find_or_create_one_fabric_tile_from_grid( + fabric_tile, curr_tile_id, grids, tile_loc, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -145,9 +142,12 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, curr_tile_coord.x(), curr_tile_coord.y()); curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } - if (fabric_tile.valid_tile_id(curr_tile_id) && !device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - VTR_LOGV(verbose, "Skip to add routing to tile[%lu][%lu] as it is not required\n", - curr_tile_coord.x(), curr_tile_coord.y()); + if (fabric_tile.valid_tile_id(curr_tile_id) && + !device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV( + verbose, + "Skip to add routing to tile[%lu][%lu] as it is not required\n", + curr_tile_coord.x(), curr_tile_coord.y()); continue; } const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); @@ -155,17 +155,17 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, if (curr_rr_gsb.is_cb_exist(cb_type)) { fabric_tile.add_cb_coordinate(curr_tile_id, cb_type, curr_rr_gsb.get_sb_coordinate()); - VTR_LOGV(verbose, "Added %s connection block [%lu][%lu] to tile[%lu][%lu]\n", - cb_type == CHANX ? "x-" : "y-", curr_rr_gsb.get_cb_x(cb_type), curr_rr_gsb.get_cb_y(cb_type), - ix, iy); + VTR_LOGV( + verbose, "Added %s connection block [%lu][%lu] to tile[%lu][%lu]\n", + cb_type == CHANX ? "x-" : "y-", curr_rr_gsb.get_cb_x(cb_type), + curr_rr_gsb.get_cb_y(cb_type), ix, iy); } } if (curr_rr_gsb.is_sb_exist(rr_graph)) { fabric_tile.add_sb_coordinate(curr_tile_id, curr_rr_gsb.get_sb_coordinate()); VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", - curr_rr_gsb.get_sb_x(), curr_rr_gsb.get_sb_y(), - ix, iy); + curr_rr_gsb.get_sb_x(), curr_rr_gsb.get_sb_y(), ix, iy); } } } @@ -173,19 +173,18 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, return status_code; } - /******************************************************************** * Build tiles by following the top-left style. * - The programmble block, e.g., clb, is placed on the top-left corner * - The connection blocks and switch block are placed on the right and bottom *sides * Tile[x][y] - * ------------------------------ + * ------------------------------ * +----------+ +----------+ ^ * | Grid | | CBy | GSB[x][y] * | [x][y] | | [x][y] | | * +----------+ +----------+ v - * ------------------------------ + * ------------------------------ * +----------+ +----------+ ^ * | CBx | | SB | | * | [x][y-1] | | [x][y-1] | GSB[x][y-1] @@ -206,11 +205,13 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); FabricTileId curr_tile_id = FabricTileId::INVALID(); - status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, verbose); + status_code = find_or_create_one_fabric_tile_from_grid( + fabric_tile, curr_tile_id, grids, tile_loc, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } - /* If no valid tile is created/found by the pb, check if there is any routing inside */ + /* If no valid tile is created/found by the pb, check if there is any + * routing inside */ vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); vtr::Point curr_gsb_coord(ix, iy); vtr::Point neighbor_gsb_coord(ix, iy - 1); @@ -223,8 +224,10 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, } } if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { - const RRGSB& routing_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); - if (routing_rr_gsb.is_cb_exist(CHANX) || routing_rr_gsb.is_sb_exist(rr_graph)) { + const RRGSB& routing_rr_gsb = + device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (routing_rr_gsb.is_cb_exist(CHANX) || + routing_rr_gsb.is_sb_exist(rr_graph)) { routing_exist = true; } } @@ -246,28 +249,30 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, if (curr_rr_gsb.is_cb_exist(CHANY)) { fabric_tile.add_cb_coordinate(curr_tile_id, CHANY, curr_rr_gsb.get_sb_coordinate()); - VTR_LOGV(verbose, "Added y- connection block [%lu][%lu] to tile[%lu][%lu]\n", - curr_rr_gsb.get_cb_x(CHANY), curr_rr_gsb.get_cb_y(CHANY), - ix, iy); + VTR_LOGV( + verbose, "Added y- connection block [%lu][%lu] to tile[%lu][%lu]\n", + curr_rr_gsb.get_cb_x(CHANY), curr_rr_gsb.get_cb_y(CHANY), ix, iy); } } /* For the cbx and sb in the neighbour gsb */ if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { - const RRGSB& neighbor_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); + const RRGSB& neighbor_rr_gsb = + device_rr_gsb.get_gsb(neighbor_gsb_coord); if (neighbor_rr_gsb.is_cb_exist(CHANX)) { fabric_tile.add_cb_coordinate(curr_tile_id, CHANX, neighbor_rr_gsb.get_sb_coordinate()); - VTR_LOGV(verbose, "Added x- connection block [%lu][%lu] to tile[%lu][%lu]\n", - neighbor_rr_gsb.get_cb_x(CHANX), neighbor_rr_gsb.get_cb_y(CHANX), - ix, iy); + VTR_LOGV(verbose, + "Added x- connection block [%lu][%lu] to tile[%lu][%lu]\n", + neighbor_rr_gsb.get_cb_x(CHANX), + neighbor_rr_gsb.get_cb_y(CHANX), ix, iy); } if (neighbor_rr_gsb.is_sb_exist(rr_graph)) { fabric_tile.add_sb_coordinate(curr_tile_id, neighbor_rr_gsb.get_sb_coordinate()); VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", - neighbor_rr_gsb.get_sb_x(), neighbor_rr_gsb.get_sb_y(), - ix, iy); + neighbor_rr_gsb.get_sb_x(), neighbor_rr_gsb.get_sb_y(), ix, + iy); } } } diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index 7e628e459..6118e673d 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -66,8 +66,8 @@ void add_grid_module_duplicated_pb_type_ports( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -173,8 +173,7 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( const size_t& child_inst_subtile_index, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, - const bool& perimeter_cb, + const e_side& border_side, const bool& perimeter_cb, const e_pin2pin_interc_type& pin2pin_interc_type) { /* Make sure this is ONLY applied to output pins */ VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type); @@ -185,8 +184,8 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 951e2429d..812038b10 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -24,7 +24,8 @@ namespace openfpga { * 5. I/O grids in the center part of FPGA can have ports on any side *******************************************************************/ std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb) { + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, + const bool& perimeter_cb) { /* We must have an regular (non-I/O) type here */ VTR_ASSERT(true == is_io_type(grid_type_descriptor)); SideManager side_manager(border_side); @@ -36,7 +37,8 @@ std::vector find_grid_module_pin_sides( if (!perimeter_cb) { return std::vector(1, side_manager.get_opposite()); } - /* For cbs on perimeter, exclude the border side. All the other 3 sides are ok */ + /* For cbs on perimeter, exclude the border side. All the other 3 sides are ok + */ std::vector pin_sides; pin_sides.reserve(3); for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -66,8 +68,8 @@ void add_grid_module_net_connect_pb_graph_pin( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } diff --git a/openfpga/src/fabric/build_grid_module_utils.h b/openfpga/src/fabric/build_grid_module_utils.h index 1051ae601..d83d9ab9f 100644 --- a/openfpga/src/fabric/build_grid_module_utils.h +++ b/openfpga/src/fabric/build_grid_module_utils.h @@ -19,7 +19,8 @@ namespace openfpga { std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb); + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, + const bool& perimeter_cb); void add_grid_module_net_connect_pb_graph_pin( ModuleManager& module_manager, const ModuleId& grid_module, diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index 8ffe94fda..051a53f4f 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -42,8 +42,7 @@ static void add_grid_module_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, - const e_side& border_side, + const TileAnnotation& tile_annotation, const e_side& border_side, const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -54,8 +53,8 @@ static void add_grid_module_pb_type_ports( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -1171,8 +1170,7 @@ static int build_physical_tile_module( const TileAnnotation& tile_annotation, const e_side& border_side, const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, const bool& duplicate_grid_pin, const bool& group_config_block, - const bool& perimeter_cb, - const bool& verbose) { + const bool& perimeter_cb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; /* Create a Module for the top-level physical block, and add to module manager */ @@ -1268,7 +1266,8 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, + perimeter_cb); } } } else { @@ -1294,7 +1293,8 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, + perimeter_cb); } } } @@ -1450,8 +1450,8 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES, - ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, device_ctx.arch->perimeter_cb, - verbose); + ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, + device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index ab5b535fe..f10d913bb 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -1175,8 +1175,7 @@ static int build_tile_port_and_nets_from_pb( const TileAnnotation& tile_annotation, const vtr::Point& pb_coord, const std::vector& pb_instances, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const size_t& ipb, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose) { + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { size_t pb_instance = pb_instances[ipb]; t_physical_tile_type_ptr phy_tile = grids.get_physical_type( t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer)); @@ -1202,7 +1201,8 @@ static int build_tile_port_and_nets_from_pb( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(phy_tile)) { - grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb); + grid_pin_sides = + find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -1379,8 +1379,7 @@ static int build_tile_module_ports_and_nets( const FabricTileId& fabric_tile_id, const std::vector& pb_instances, const std::map>& cb_instances, const std::vector& sb_instances, const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose) { + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; /* Get the submodule of Switch blocks one by one, build connections between sb @@ -1489,10 +1488,8 @@ static int build_tile_module( const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, - const bool& verbose) { + const bool& name_module_using_index, const bool& perimeter_cb, + const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; /* Create the module */ @@ -1702,19 +1699,16 @@ static int build_tile_module( /******************************************************************** * Build all the tile modules *******************************************************************/ -int build_tile_modules(ModuleManager& module_manager, - DecoderLibrary& decoder_lib, - const FabricTile& fabric_tile, const DeviceGrid& grids, - const VprDeviceAnnotation& vpr_device_annotation, - const DeviceRRGSB& device_rr_gsb, - const RRGraphView& rr_graph_view, - const TileAnnotation& tile_annotation, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose) { +int build_tile_modules( + ModuleManager& module_manager, DecoderLibrary& decoder_lib, + const FabricTile& fabric_tile, const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, + const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view, + const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& sram_orgz_type, + const bool& name_module_using_index, const bool& perimeter_cb, + const bool& frame_view, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric"); int status_code = CMD_EXEC_SUCCESS; diff --git a/openfpga/src/fabric/build_tile_modules.h b/openfpga/src/fabric/build_tile_modules.h index e3a629808..b1507e62c 100644 --- a/openfpga/src/fabric/build_tile_modules.h +++ b/openfpga/src/fabric/build_tile_modules.h @@ -25,19 +25,16 @@ /* begin namespace openfpga */ namespace openfpga { -int build_tile_modules(ModuleManager& module_manager, - DecoderLibrary& decoder_lib, - const FabricTile& fabric_tile, const DeviceGrid& grids, - const VprDeviceAnnotation& vpr_device_annotation, - const DeviceRRGSB& device_rr_gsb, - const RRGraphView& rr_graph_view, - const TileAnnotation& tile_annotation, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose); +int build_tile_modules( + ModuleManager& module_manager, DecoderLibrary& decoder_lib, + const FabricTile& fabric_tile, const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, + const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view, + const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& sram_orgz_type, + const bool& name_module_using_index, const bool& perimeter_cb, + const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 2e7a33182..d25a9af72 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -261,11 +261,15 @@ static vtr::Matrix add_top_module_connection_block_instances( * We will skip those modules */ const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); - VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n", cb_type == CHANX ? "X-" : "Y-", ix, iy); + VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n", + cb_type == CHANX ? "X-" : "Y-", ix, iy); vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); if (false == rr_gsb.is_cb_exist(cb_type)) { - VTR_LOGV(verbose, "Skip %s connnection block at (%lu, %lu) as it does not exist\n", cb_type == CHANX ? "X-" : "Y-", cb_coordinate.x(), cb_coordinate.y()); + VTR_LOGV( + verbose, + "Skip %s connnection block at (%lu, %lu) as it does not exist\n", + cb_type == CHANX ? "X-" : "Y-", cb_coordinate.x(), cb_coordinate.y()); continue; } /* If we use compact routing hierarchy, we should instanciate the unique @@ -297,7 +301,9 @@ static vtr::Matrix add_top_module_connection_block_instances( top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], cb_instance_name); - VTR_LOGV(verbose, "Added %s connnection block '%s' (module '%s')\n", cb_type == CHANX ? "X-" : "Y-", cb_instance_name.c_str(), cb_module_name.c_str()); + VTR_LOGV(verbose, "Added %s connnection block '%s' (module '%s')\n", + cb_type == CHANX ? "X-" : "Y-", cb_instance_name.c_str(), + cb_module_name.c_str()); } } @@ -448,8 +454,7 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, - const bool& verbose) { + const bool& group_config_block, const bool& verbose) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; @@ -463,11 +468,11 @@ int build_top_module_fine_grained_child_instances( compact_routing_hierarchy); /* Add all the CBX and CBYs across the fabric */ cb_instance_ids[CHANX] = add_top_module_connection_block_instances( - module_manager, top_module, device_rr_gsb, CHANX, - compact_routing_hierarchy, verbose); + module_manager, top_module, device_rr_gsb, CHANX, compact_routing_hierarchy, + verbose); cb_instance_ids[CHANY] = add_top_module_connection_block_instances( - module_manager, top_module, device_rr_gsb, CHANY, - compact_routing_hierarchy, verbose); + module_manager, top_module, device_rr_gsb, CHANY, compact_routing_hierarchy, + verbose); /* Update I/O children list */ add_top_module_io_children(module_manager, top_module, grids, layer, diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index dd4f8e24d..604cce99b 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -44,8 +44,7 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, - const bool& verbose); + const bool& group_config_block, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index d5d4e7aea..959532257 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -760,13 +760,15 @@ static void add_top_module_nets_connect_sb_and_cb( } if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { - /* Only for the condition where cbs are on perimeter, the neighbour cb will be invalid - * Bypass in such case on finding neighbour cbs + /* Only for the condition where cbs are on perimeter, the neighbour cb + * will be invalid Bypass in such case on finding neighbour cbs */ - if (TOP == side_manager.get_side() && instance_sb_coordinate.y() == device_rr_gsb.get_gsb_range().y()) { + if (TOP == side_manager.get_side() && + instance_sb_coordinate.y() == device_rr_gsb.get_gsb_range().y()) { continue; } - if (RIGHT == side_manager.get_side() && instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) { + if (RIGHT == side_manager.get_side() && + instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) { continue; } const RRGSB& adjacent_gsb = diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp index 44da5e47c..23f6aef12 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp @@ -54,7 +54,9 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const { return default_net_type_; } -bool FabricVerilogOption::constant_undriven_inputs() const { return constant_undriven_inputs_; } +bool FabricVerilogOption::constant_undriven_inputs() const { + return constant_undriven_inputs_; +} bool FabricVerilogOption::verbose_output() const { return verbose_output_; } diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index 7ccdd35d4..4da841564 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -233,10 +233,9 @@ static void rec_print_verilog_logical_tile( std::string(physical_pb_type->name) + " -----")); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, pb_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, pb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( fp, @@ -348,10 +347,9 @@ static void print_verilog_physical_tile_netlist( print_verilog_comment( fp, std::string("----- BEGIN Grid Verilog module: " + module_manager.module_name(grid_module) + " -----")); - write_verilog_module_to_file(fp, module_manager, grid_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, grid_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( fp, std::string("----- END Grid Verilog module: " + diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index b20b1d07a..45dc0b862 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -63,8 +63,7 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager, fp, module_manager, lut_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(lut_model), - options.constant_undriven_inputs(), - options.default_net_type()); + options.constant_undriven_inputs(), options.default_net_type()); } /* Close the file handler */ diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 0e0972269..99557e6b9 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -61,8 +61,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), - options.constant_undriven_inputs(), - options.default_net_type()); + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -85,8 +84,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, feedthru_mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), - options.constant_undriven_inputs(), - options.default_net_type()); + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -243,10 +241,9 @@ void print_verilog_submodule_memories( for (ModuleId mem_group_module : module_manager.modules_by_usage( ModuleManager::e_module_usage_type::MODULE_CONFIG_GROUP)) { /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, mem_group_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, mem_group_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 3b52c2d87..c99a088c0 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -145,13 +145,10 @@ static BasicPort generate_verilog_port_for_module_net( * Verilog wire writter function will use the output of this function * to write up local wire declaration in Verilog format *******************************************************************/ -static void -find_verilog_module_local_undriven_wires( +static void find_verilog_module_local_undriven_wires( std::map>& local_wires, - const ModuleManager& module_manager, - const ModuleId& module_id, + const ModuleManager& module_manager, const ModuleId& module_id, const std::vector& port_type_blacklist) { - /* Local wires could also happen for undriven ports of child module */ for (const ModuleId& child : module_manager.child_modules(module_id)) { for (size_t instance : @@ -159,9 +156,11 @@ find_verilog_module_local_undriven_wires( for (const ModulePortId& child_port_id : module_manager.module_ports(child)) { BasicPort child_port = module_manager.module_port(child, child_port_id); - ModuleManager::e_module_port_type child_port_type = module_manager.port_type(child, child_port_id); + ModuleManager::e_module_port_type child_port_type = + module_manager.port_type(child, child_port_id); bool filter_out = false; - for (ModuleManager::e_module_port_type curr_port_type : port_type_blacklist) { + for (ModuleManager::e_module_port_type curr_port_type : + port_type_blacklist) { if (child_port_type == curr_port_type) { filter_out = true; break; @@ -267,7 +266,9 @@ find_verilog_module_local_wires(const ModuleManager& module_manager, } } - find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector()); + find_verilog_module_local_undriven_wires( + local_wires, module_manager, module_id, + std::vector()); return local_wires; } @@ -606,20 +607,22 @@ void write_verilog_module_to_file( /* Use constant to drive undriven local wires */ if (constant_local_undriven_wires) { std::vector blacklist = { - ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT, - ModuleManager::e_module_port_type::MODULE_GPIN_PORT, - ModuleManager::e_module_port_type::MODULE_GPOUT_PORT, - ModuleManager::e_module_port_type::MODULE_GPIO_PORT, - ModuleManager::e_module_port_type::MODULE_INOUT_PORT, - ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT, - ModuleManager::e_module_port_type::MODULE_CLOCK_PORT - }; + ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT, + ModuleManager::e_module_port_type::MODULE_GPIN_PORT, + ModuleManager::e_module_port_type::MODULE_GPOUT_PORT, + ModuleManager::e_module_port_type::MODULE_GPIO_PORT, + ModuleManager::e_module_port_type::MODULE_INOUT_PORT, + ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT, + ModuleManager::e_module_port_type::MODULE_CLOCK_PORT}; std::map> local_undriven_wires; - find_verilog_module_local_undriven_wires(local_undriven_wires, module_manager, module_id, blacklist); + find_verilog_module_local_undriven_wires( + local_undriven_wires, module_manager, module_id, blacklist); for (std::pair> port_group : local_undriven_wires) { for (const BasicPort& local_undriven_wire : port_group.second) { - print_verilog_wire_constant_values(fp, local_undriven_wire, std::vector(local_undriven_wire.get_width(), 0)); + print_verilog_wire_constant_values( + fp, local_undriven_wire, + std::vector(local_undriven_wire.get_width(), 0)); } } } diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index 38fcc0224..6f7a2a282 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -679,8 +679,7 @@ static void generate_verilog_mux_branch_module( fp, module_manager, mux_module, use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model), - false, - default_net_type); + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; } else { @@ -1424,8 +1423,7 @@ static void generate_verilog_mux_module( circuit_lib.dump_explicit_port_map(mux_model) || circuit_lib.dump_explicit_port_map( circuit_lib.pass_gate_logic_model(mux_model))), - false, - default_net_type); + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; break; diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp index 3826a2552..00bcaeda5 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.cpp +++ b/openfpga/src/fpga_verilog/verilog_routing.cpp @@ -115,10 +115,9 @@ static void print_verilog_routing_connection_box_unique_module( VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, cb_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, cb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -237,10 +236,9 @@ static void print_verilog_routing_switch_box_unique_module( VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, sb_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, sb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Close file handler */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp index 6d4707b1e..6f548d8ec 100644 --- a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp +++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp @@ -56,10 +56,9 @@ void print_verilog_submodule_shift_register_banks( for (const ModuleId& sr_module : blwl_sr_banks.bl_bank_unique_modules()) { VTR_ASSERT(true == module_manager.valid_module_id(sr_module)); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, sr_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -68,10 +67,9 @@ void print_verilog_submodule_shift_register_banks( for (const ModuleId& sr_module : blwl_sr_banks.wl_bank_unique_modules()) { VTR_ASSERT(true == module_manager.valid_module_id(sr_module)); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, sr_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp index f6b10beaf..a3bb1e992 100644 --- a/openfpga/src/fpga_verilog/verilog_tile.cpp +++ b/openfpga/src/fpga_verilog/verilog_tile.cpp @@ -58,10 +58,9 @@ static int print_verilog_tile_module_netlist( options.time_stamp()); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, tile_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, tile_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index 60ed91956..26268e4c1 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -61,10 +61,9 @@ void print_verilog_core_module(NetlistManager& netlist_manager, options.time_stamp()); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, core_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, core_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -128,10 +127,9 @@ void print_verilog_top_module(NetlistManager& netlist_manager, fp, std::string("Top-level Verilog module for FPGA"), options.time_stamp()); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, top_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, top_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; From 201b2555e5cd10cb536b3db55abb6895bedef5d4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 6 Jul 2024 12:15:08 -0700 Subject: [PATCH 156/230] [test] code format --- ...N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index 2bab2cd89..e25a5a686 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -65,8 +65,8 @@ - - + + fpga_input[0:1].inpad fpga_input[2:3].inpad @@ -78,8 +78,8 @@ - - + + fpga_output[0:0].outpad fpga_output[1:1].outpad @@ -94,9 +94,9 @@ fpga_input[0:1].inpad - + fpga_input[2:3].inpad - + @@ -107,9 +107,9 @@ fpga_output[0:0].outpad - + fpga_output[1:1].outpad - + @@ -121,10 +121,10 @@ - + fpga_input[0:1].inpad fpga_input[2:3].inpad - + @@ -134,10 +134,10 @@ - + fpga_output[0:0].outpad fpga_output[1:1].outpad - + @@ -149,9 +149,9 @@ - + fpga_input[0:1].inpad - + fpga_input[2:3].inpad @@ -162,9 +162,9 @@ - + fpga_output[0:0].outpad - + fpga_output[1:1].outpad From 91f8bb584137d87a2a93365388cf7af989cc1a99 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 13:40:01 -0700 Subject: [PATCH 157/230] [doc] update figures for ecb --- .../figures/ecb_allowed_direct_connection.png | Bin 112293 -> 99353 bytes ...d_direct_connection_inner_tile_example.png | Bin 107355 -> 111180 bytes ...d_direct_connection_inter_tile_example.png | Bin 112800 -> 100259 bytes .../ecb_forbid_direct_connection_example.png | Bin 116620 -> 122110 bytes 4 files changed, 0 insertions(+), 0 deletions(-) diff --git a/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png index 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[PATCH 158/230] [test] fixed a bug on ecb support --- .../tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf | 2 +- ...gzBr_40nm.xml => k4_N4_ecb_tileable_TileOrgzBl_40nm.xml} | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) rename openfpga_flow/vpr_arch/{k4_N4_ecb_tileable_TileOrgzBr_40nm.xml => k4_N4_ecb_tileable_TileOrgzBl_40nm.xml} (99%) diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf index 87f77596d..035b92ed7 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf @@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_device_layout=2x2 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml similarity index 99% rename from openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml rename to openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml index 4597207bb..c9899d852 100644 --- a/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml @@ -65,10 +65,10 @@ - clb.clk - clb.I2[0:3] clb.I3[0:3] clb.O[2:3] + clb.clk + clb.I2[0:3] clb.I3[0:3] clb.O[2:3] - clb.I0[0:3] clb.I1[0:3] clb.O[0:1] + clb.I0[0:3] clb.I1[0:3] clb.O[0:1] From 4da5150a2631ab6b9ad89d98804233fb8342d9bd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 14:20:26 -0700 Subject: [PATCH 159/230] [doc] update for bottom-left tile organization --- .../figures/tile_style_bottom_left.png | Bin 0 -> 91240 bytes .../manual/file_formats/tile_config_file.rst | 13 ++++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 docs/source/manual/file_formats/figures/tile_style_bottom_left.png diff --git a/docs/source/manual/file_formats/figures/tile_style_bottom_left.png b/docs/source/manual/file_formats/figures/tile_style_bottom_left.png new file mode 100644 index 0000000000000000000000000000000000000000..393eab8621d1e73ec1270a6d2b448999870a96aa GIT binary patch literal 91240 zcmeFZcU05a7C-8YGvhE86c|wuxJnZh7?h#{i2{nDD&SxX89}89NG~DD9Sc=pBqB(Q zbU}qddP`=ci3pKqBsA$IkkAuIdnZApc%9$8Ki*pJt@YNrcR8^5o^$p-`|R@BpL2rG zn&@x+N$jT$8#Zi(ozXMfu;KfX4I92||M3U#n}w6REx|wExSQ$gY{+ihGYWqA&i177 z$qgHFBQ~?Heh+>YxOL{D`-TmN|Kk1soBh`=b!^zcO@ry3wD7SSXEW(H_2D161a2tt z5cIYq`ozW%}WzFTv%R#@i~)H z{v>C%8ZNIw;SEe*qZ@m@{w0l#JZ{%JvySQGWR5KLChTw6aPJ$b46>YI?MKNuI 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z3onz=nI*9;=chfBzPJJ-;DPq}E8nzZ@l7+#wZqmX{q*^X3sZUr`a_@kZ{H@thwEs3Uhf=2Ys@ Date: Sun, 7 Jul 2024 14:57:05 -0700 Subject: [PATCH 160/230] [core] now support perimeter cb in programmable clock network arch --- .../src/annotation/append_clock_rr_graph.cpp | 48 +++++++++++++++---- 1 file changed, 39 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index ffe49e146..e9e690d11 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -49,9 +49,16 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, const bool& through_channel, const ClockNetwork& clk_ntwk) { size_t num_nodes = 0; + vtr::Rect chanx_bb(1, 0, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chanx_bb.set_xmin(0); + chanx_bb.set_xmax(grids.width()); + chanx_bb.set_ymin(0); + chanx_bb.set_ymax(grids.height()); + } /* Check the number of CHANX nodes required */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { + for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are * not allowed */ @@ -64,8 +71,16 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, } } - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chany_bb.set_xmin(0); + chany_bb.set_xmax(grids.width()); + chany_bb.set_ymin(0); + chany_bb.set_ymax(grids.height()); + } + + for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { + for (size_t iy = chany_bb.xmin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ @@ -159,9 +174,16 @@ static void add_rr_graph_clock_nodes( clk_ntwk.num_trees(), clk_ntwk.max_tree_depth(), clk_ntwk.max_tree_width()); + vtr::Rect chanx_bb(1, 0, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chanx_bb.set_xmin(0); + chanx_bb.set_xmax(grids.width()); + chanx_bb.set_ymin(0); + chanx_bb.set_ymax(grids.height()); + } /* Add X-direction clock nodes */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { + for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are * not allowed */ @@ -182,8 +204,15 @@ static void add_rr_graph_clock_nodes( 1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); /* Add Y-direction clock nodes */ - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chany_bb.set_xmin(0); + chany_bb.set_xmax(grids.width()); + chany_bb.set_ymin(0); + chany_bb.set_ymax(grids.height()); + } + for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { + for (size_t iy = chany_bb.xmin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ @@ -780,7 +809,8 @@ static void add_rr_graph_clock_edges( *******************************************************************/ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, const bool& verbose) { + const ClockNetwork& clk_ntwk, + const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Appending programmable clock network to routing resource graph"); From db12532eb8644f29e450f3fb8a8ed992e70cd3d9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 21:41:39 -0700 Subject: [PATCH 161/230] [test] typo --- .../homo_fabric_tile_ecb_2x2_preconfig/config/task.conf | 2 +- .../homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf index 8f1b5aa53..08aca9064 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf @@ -27,7 +27,7 @@ openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml openfpga_verilog_testbench_options=--explicit_port_mapping [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml index 1a1f3f6e8..026c140be 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml @@ -1 +1 @@ - + From 1a5e2392fcc92aab0050cbb52ee8a13e12a9d861 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 22:32:13 -0700 Subject: [PATCH 162/230] [test] add a new testcase to validate clock network when perimeter cb is on --- ...nm_ClkNtwk_registerable_io_cc_openfpga.xml | 201 +++++++++ .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/clk_arch_1clk_2layer.xml | 22 + .../config/task.conf | 42 ++ .../config/tile_config.xml | 1 + ...rimeterCb_ClkNtwk_registerable_io_40nm.xml | 411 ++++++++++++++++++ 6 files changed, 678 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml create mode 100644 openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml new file mode 100644 index 000000000..cdb96e29b --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml @@ -0,0 +1,201 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index cdb93ee16..f4b872def 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -197,6 +197,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile $@ run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@ diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml new file mode 100644 index 000000000..c45687e52 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf new file mode 100644 index 000000000..f7c94606f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml new file mode 100644 index 000000000..de6fe0ac8 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -0,0 +1,411 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad[0:1] io.inpad[0:1] + + io.outpad[2:3] io.inpad[2:3] io.clk + io.outpad[4:5] io.inpad[4:5] + + + + + + + + + + + + + + + + io.outpad[0:0] io.inpad[0:0] io.clk + + io.outpad[1:1] io.inpad[1:1] + io.outpad[2:2] io.inpad[2:2] + + + + + + + + + + + + + + + + io.outpad[0:1] io.inpad[0:1] io.clk + + io.outpad[2:2] io.inpad[2:2] + io.outpad[3:4] io.inpad[3:4] + + + + + + + + + + + + + + + + io.outpad[0:1] io.inpad[0:1] io.clk + + io.outpad[2:3] io.inpad[2:3] + io.outpad[4:5] io.inpad[4:5] + + + + + + + + + + + + + + + + clb.I[0:4] clb.O[0:1] + clb.clk + clb.I[5:9] clb.O[2:3] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From f784e583831f2114c682e903a31cc51f35abe680 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 22:33:45 -0700 Subject: [PATCH 163/230] [test] typo --- ..._tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index de6fe0ac8..b028e180a 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -143,8 +143,8 @@ - - + + @@ -153,8 +153,8 @@ - - + + From 57a378ae59ccf4c9dffa5088181de30ae7c375e7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 22:35:14 -0700 Subject: [PATCH 164/230] [test] typo --- .../k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index b028e180a..0f086c0bc 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -94,7 +94,7 @@ io.outpad[0:1] io.inpad[0:1] io.clk io.outpad[2:2] io.inpad[2:2] - io.outpad[3:4] io.inpad[3:4] + io.outpad[3:3] io.inpad[3:3] From 686cd761b72ca015280827559d056835844d4e2b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 22:48:21 -0700 Subject: [PATCH 165/230] [test] debugging --- ...rimeterCb_ClkNtwk_registerable_io_40nm.xml | 37 ++++++++----------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index 0f086c0bc..c026c93b3 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -34,15 +34,10 @@ - - - - - - + @@ -53,15 +48,15 @@ - io.outpad[0:1] io.inpad[0:1] + io_top[0:1].outpad[0:0] io_top[0:1].inpad[0:0] - io.outpad[2:3] io.inpad[2:3] io.clk - io.outpad[4:5] io.inpad[4:5] + io_top[2:3].outpad[0:0] io_top[2:3].inpad[0:0] io_top[0:5].clk[0:0] + io_top[4:5].outpad[0:0] io_top[4:5].inpad[0:0] - + @@ -72,15 +67,15 @@ - io.outpad[0:0] io.inpad[0:0] io.clk + io_right[0:0].outpad[0:0] io_right[0:0].inpad[0:0] io_right[0:2].clk[0:0] - io.outpad[1:1] io.inpad[1:1] - io.outpad[2:2] io.inpad[2:2] + io_right[1:1].outpad[0:0] io_right[1:1].inpad[0:0] + io_right[2:2].outpad[0:0] io_right[2:2].inpad[0:0] - + @@ -91,15 +86,15 @@ - io.outpad[0:1] io.inpad[0:1] io.clk + io_bottom[0:1].outpad[0:0] io_bottom[0:1].inpad[0:0] io_bottom[0:3].clk[0:0] - io.outpad[2:2] io.inpad[2:2] - io.outpad[3:3] io.inpad[3:3] + io_bottom[2:2].outpad[0:0] io_bottom[2:2].inpad[0:0] + io_bottom[3:3].outpad[0:0] io_bottom[3:3].inpad[0:0] - + @@ -110,10 +105,10 @@ - io.outpad[0:1] io.inpad[0:1] io.clk + io_left[0:1].outpad[0:0] io_left[0:1].inpad[0:0] io_left[0:5].clk[0:0] - io.outpad[2:3] io.inpad[2:3] - io.outpad[4:5] io.inpad[4:5] + io_left[2:3].outpad[0:0] io_left[2:3].inpad[0:0] + io_left[4:5].outpad[0:0] io_left[4:5].inpad[0:0] From b0851a62998b4756970ec33a8c57f6c1f7248b83 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 23:05:37 -0700 Subject: [PATCH 166/230] [test] debugging --- ...rimeterCb_ClkNtwk_registerable_io_40nm.xml | 37 ++++++++++--------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index c026c93b3..6c1cb8d63 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -44,14 +44,14 @@ - + io_top[0:1].outpad[0:0] io_top[0:1].inpad[0:0] - io_top[2:3].outpad[0:0] io_top[2:3].inpad[0:0] io_top[0:5].clk[0:0] - io_top[4:5].outpad[0:0] io_top[4:5].inpad[0:0] + io_top[0:5].clk[0:0] + io_top[2:5].outpad[0:0] io_top[2:5].inpad[0:0] @@ -63,7 +63,7 @@ - + @@ -82,33 +82,33 @@ - + io_bottom[0:1].outpad[0:0] io_bottom[0:1].inpad[0:0] io_bottom[0:3].clk[0:0] - io_bottom[2:2].outpad[0:0] io_bottom[2:2].inpad[0:0] - io_bottom[3:3].outpad[0:0] io_bottom[3:3].inpad[0:0] + io_bottom[2:3].outpad[0:0] io_bottom[2:3].inpad[0:0] + - + - + - io_left[0:1].outpad[0:0] io_left[0:1].inpad[0:0] io_left[0:5].clk[0:0] + io_left[0:1].outpad[0:0] io_left[0:1].inpad[0:0] io_left[0:3].clk[0:0] - io_left[2:3].outpad[0:0] io_left[2:3].inpad[0:0] - io_left[4:5].outpad[0:0] io_left[4:5].inpad[0:0] + + io_left[2:3].outpad[0:0] io_left[2:3].inpad[0:0] @@ -120,14 +120,15 @@ - + - - clb.I[0:4] clb.O[0:1] - clb.clk - clb.I[5:9] clb.O[2:3] - + + clb.I[0:1] clb.O[0:0] + clb.I[2:3] clb.O[1:1] clb.clk + clb.I[4:6] clb.O[2:2] + clb.I[7:9] clb.O[3:3] + From ff56139a53e7f26811632cc2387b14f313611a10 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 23:07:51 -0700 Subject: [PATCH 167/230] [test] debugging --- .../k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml | 5 ++++- .../config/clk_arch_1clk_2layer.xml | 7 +++++-- .../fabric_tile_clkntwk_io_subtile/config/task.conf | 2 +- ...4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml | 4 ++-- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml index cdb96e29b..e0c4966c5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml @@ -175,7 +175,10 @@ - + + + + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml index c45687e52..4c4c38bb8 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml @@ -4,7 +4,7 @@ - + @@ -16,7 +16,10 @@ - + + + + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf index f7c94606f..f9c6517ab 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf @@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=2x2 -openfpga_vpr_route_chan_width=20 +openfpga_vpr_route_chan_width=40 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml openfpga_verilog_testbench_options=--explicit_port_mapping openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index 6c1cb8d63..09a0af616 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -206,12 +206,12 @@ - + 1 1 1 - + 1 1 1 1 1 1 1 1 1 From 7d9fcc1a7bb78260ec2f8f3e7e3e8005d5e7869f Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 8 Jul 2024 06:12:43 +0000 Subject: [PATCH 168/230] Bump yosys from `a739e21` to `dac5bd1` Bumps [yosys](https://github.com/YosysHQ/yosys) from `a739e21` to `dac5bd1`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/a739e21a5f3b4fdd888d4c62f1578a1300c43f00...dac5bd1983a5078e3e7426df1e8ee48d300ead7d) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index a739e21a5..dac5bd198 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit a739e21a5f3b4fdd888d4c62f1578a1300c43f00 +Subproject commit dac5bd1983a5078e3e7426df1e8ee48d300ead7d From 8449da0143813cb01ffb47afa962fd1cbd67a6d2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 23:36:13 -0700 Subject: [PATCH 169/230] [core] typo --- openfpga/src/annotation/append_clock_rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index e9e690d11..e60aaa50d 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -80,7 +80,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, } for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { - for (size_t iy = chany_bb.xmin(); iy < chany_bb.ymax(); ++iy) { + for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ @@ -212,7 +212,7 @@ static void add_rr_graph_clock_nodes( chany_bb.set_ymax(grids.height()); } for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { - for (size_t iy = chany_bb.xmin(); iy < chany_bb.ymax(); ++iy) { + for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ From cdd477ad80fbff3e749d378a7b5e8bbf5a14ea96 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 10:14:39 -0700 Subject: [PATCH 170/230] [core] remove restrictions on cb clock nodes --- openfpga/src/annotation/append_clock_rr_graph.cpp | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index e60aaa50d..b7b82c269 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -194,15 +194,9 @@ static void add_rr_graph_clock_nodes( add_rr_graph_block_clock_nodes( rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, chanx_coord, CHANX, CHANX_COST_INDEX_START, verbose); - VTR_ASSERT(rr_graph_view.valid_node( - clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), - ClockTreePinId(0), Direction::INC))); } } - VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node( - 1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); - /* Add Y-direction clock nodes */ vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); if (perimeter_cb) { @@ -224,13 +218,8 @@ static void add_rr_graph_clock_nodes( rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, chany_coord, CHANY, CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(), verbose); - VTR_ASSERT(rr_graph_view.valid_node( - clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), - ClockTreePinId(0), Direction::INC))); } } - VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node( - 1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); } /******************************************************************** From 5c9c4d93c5636d854dc01945919018eeabb1c48e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 10:46:47 -0700 Subject: [PATCH 171/230] [core] typo --- openfpga/src/annotation/route_clock_rr_graph.cpp | 4 ++-- .../config/clk_arch_1clk_2layer.xml | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 0be7cdf84..207b83d0e 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -186,8 +186,6 @@ static int route_spine_taps( const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const ClockSpineId& ispine, const ClockTreePinId& ipin, const bool& verbose) { - std::vector> spine_coords = - clk_ntwk.spine_coordinates(ispine); size_t spine_tap_cnt = 0; /* Route the spine-to-IPIN connections (only for the last level) */ if (clk_ntwk.is_last_level(ispine)) { @@ -195,6 +193,8 @@ static int route_spine_taps( "Routing clock taps of spine '%s' for pin '%d' of tree '%s'...\n", clk_ntwk.spine_name(ispine).c_str(), size_t(ipin), clk_ntwk.tree_name(clk_tree).c_str()); + std::vector> spine_coords = + clk_ntwk.spine_coordinates(ispine); /* Connect to any fan-out node which is IPIN */ for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { vtr::Point src_coord = spine_coords[icoord]; diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml index 4c4c38bb8..453d0b5d0 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml @@ -8,8 +8,8 @@ - - + + From 48ae3691c429b58590ffb1ec89ae5d6901293f29 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 10:57:54 -0700 Subject: [PATCH 172/230] [test] typo --- .../k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml index e0c4966c5..f9d09c73e 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml @@ -173,7 +173,7 @@ - + From 6492d43a01148a6ef987c8283cd98f10419d5d60 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 11:29:20 -0700 Subject: [PATCH 173/230] [test] add a new test to validate perimeter cb using global tile clock --- ...erimeterCb_registerable_io_cc_openfpga.xml | 204 ++++++++++++++++++ .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/task.conf | 41 ++++ .../config/tile_config.xml | 1 + 4 files changed, 247 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml new file mode 100644 index 000000000..341bf52e2 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml @@ -0,0 +1,204 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index f4b872def..4e1f55602 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -197,6 +197,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile $@ run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock_io_subtile $@ run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf new file mode 100644 index 000000000..20efcfa2d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml @@ -0,0 +1 @@ + From 7bd60f5f7d6d42ee546f61937d0b4432f0854596 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 12:39:54 -0700 Subject: [PATCH 174/230] [core] support perimeter cb when identify pins of I/Os tiles --- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 2 +- openfpga/src/fabric/build_device_module.cpp | 4 +++- openfpga/src/fabric/build_top_module.cpp | 8 +++++--- openfpga/src/fabric/build_top_module.h | 4 +++- ...d_top_module_child_fine_grained_instance.cpp | 6 ++++-- ...ild_top_module_child_fine_grained_instance.h | 4 +++- .../build_top_module_child_tile_instance.cpp | 17 +++++++++-------- .../build_top_module_child_tile_instance.h | 1 + .../src/fabric/build_top_module_connection.cpp | 17 ++++++++++------- .../src/fabric/build_top_module_connection.h | 3 ++- .../src/utils/openfpga_physical_tile_utils.cpp | 9 ++++++--- .../src/utils/openfpga_physical_tile_utils.h | 2 +- 12 files changed, 48 insertions(+), 29 deletions(-) diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 22bff36c4..e96e4d218 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -60,7 +60,7 @@ static void update_cluster_pin_with_post_routing_results( rr_node_type = IPIN; } std::vector pin_sides = - find_physical_tile_pin_side(physical_tile, physical_pin, border_side); + find_physical_tile_pin_side(physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb); /* As some grid has height/width offset, we may not have the pin on any side */ if (0 == pin_sides.size()) { diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index a04e9e015..3ffa869e8 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -142,7 +142,9 @@ int build_device_module_graph( openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol, sram_model, fabric_tile, name_module_using_index, frame_view, compress_routing, duplicate_grid_pin, fabric_key, - generate_random_fabric_key, group_config_block, verbose); + generate_random_fabric_key, group_config_block, + vpr_device_ctx.arch->perimeter_cb, + verbose); if (CMD_EXEC_FATAL_ERROR == status) { return status; diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index bce676019..54fd54702 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -58,7 +58,9 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, const bool& verbose) { + const bool& group_config_block, + const bool& perimeter_cb, + const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build FPGA fabric module"); int status = CMD_EXEC_SUCCESS; @@ -79,7 +81,7 @@ int build_top_module( rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol, sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin, - fabric_key, group_config_block, verbose); + fabric_key, group_config_block, perimeter_cb, verbose); } else { /* Build the tile instances under the top module */ status = build_top_module_tile_child_instances( @@ -87,7 +89,7 @@ int build_top_module( rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile, config_protocol, sram_model, fabric_key, group_config_block, - name_module_using_index, frame_view, verbose); + name_module_using_index, perimeter_cb, frame_view, verbose); } if (status != CMD_EXEC_SUCCESS) { diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index ee9d346d2..75c3649eb 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -45,7 +45,9 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, const bool& verbose); + const bool& group_config_block, + const bool& perimeter_cb, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index d25a9af72..7e3fcfa2f 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -454,7 +454,9 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, const bool& verbose) { + const bool& group_config_block, + const bool& perimeter_cb, + const bool& verbose) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; @@ -501,7 +503,7 @@ int build_top_module_fine_grained_child_instances( status = add_top_module_global_ports_from_grid_modules( module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer, rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids, - clk_ntwk, rr_clock_lookup); + clk_ntwk, rr_clock_lookup, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index 604cce99b..394f7a2df 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -44,7 +44,9 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, const bool& verbose); + const bool& group_config_block, + const bool& perimeter_cb, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 0ad953f68..bf12dabc6 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1295,7 +1295,7 @@ static int build_top_module_global_net_for_given_tile_module( const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const size_t& layer, const vtr::Point& grid_coordinate, const e_side& border_side, const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile) { + const FabricTile& fabric_tile, const bool& perimeter_cb) { /* Get the tile module and instance */ FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); @@ -1392,7 +1392,7 @@ static int build_top_module_global_net_for_given_tile_module( size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index]; std::vector pin_sides = find_physical_tile_pin_side( - physical_tile, grid_pin_index, border_side); + physical_tile, grid_pin_index, border_side, perimeter_cb); BasicPort grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, @@ -1452,7 +1452,7 @@ static int build_top_module_global_net_from_tile_modules( const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const size_t& layer, const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile) { + const FabricTile& fabric_tile, const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; std::map>> io_coordinates = @@ -1531,7 +1531,7 @@ static int build_top_module_global_net_from_tile_modules( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, - fabric_tile); + fabric_tile, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1578,7 +1578,7 @@ static int build_top_module_global_net_from_tile_modules( status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - io_coordinate, io_side, tile_instance_ids, fabric_tile); + io_coordinate, io_side, tile_instance_ids, fabric_tile, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1600,7 +1600,7 @@ static int add_top_module_global_ports_from_tile_modules( const size_t& layer, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, - const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) { + const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1657,7 +1657,7 @@ static int add_top_module_global_ports_from_tile_modules( status = build_top_module_global_net_from_tile_modules( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, vpr_device_annotation, grids, layer, - tile_instance_ids, fabric_tile); + tile_instance_ids, fabric_tile, perimeter_cb); } if (status == CMD_EXEC_FATAL_ERROR) { return status; @@ -1905,6 +1905,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status = CMD_EXEC_SUCCESS; vtr::Matrix tile_instance_ids; @@ -1942,7 +1943,7 @@ int build_top_module_tile_child_instances( status = add_top_module_global_ports_from_tile_modules( module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer, rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk, - rr_clock_lookup); + rr_clock_lookup, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.h b/openfpga/src/fabric/build_top_module_child_tile_instance.h index bec2a9fa1..74a8aea63 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.h +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.h @@ -44,6 +44,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 959532257..46907a1bb 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -956,7 +956,8 @@ static int build_top_module_global_net_for_given_grid_module( const BasicPort& tile_port_to_connect, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const size_t& layer, const vtr::Point& grid_coordinate, - const e_side& border_side, const vtr::Matrix& grid_instance_ids) { + const e_side& border_side, const vtr::Matrix& grid_instance_ids, + const bool& perimeter_cb) { t_physical_tile_type_ptr physical_tile = grids.get_physical_type( t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); /* Find the module name for this type of grid */ @@ -1033,7 +1034,7 @@ static int build_top_module_global_net_for_given_grid_module( size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index]; std::vector pin_sides = find_physical_tile_pin_side( - physical_tile, grid_pin_index, border_side); + physical_tile, grid_pin_index, border_side, perimeter_cb); BasicPort grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, @@ -1091,7 +1092,8 @@ static int build_top_module_global_net_from_grid_modules( const ModulePortId& top_module_port, const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, const vtr::Matrix& grid_instance_ids) { + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; std::map>> io_coordinates = @@ -1169,7 +1171,7 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids); + vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1216,7 +1218,7 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - io_coordinate, io_side, grid_instance_ids); + io_coordinate, io_side, grid_instance_ids, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1317,7 +1319,8 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup) { + const RRClockSpatialLookup& rr_clock_lookup, + const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1382,7 +1385,7 @@ int add_top_module_global_ports_from_grid_modules( status = build_top_module_global_net_from_grid_modules( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, vpr_device_annotation, grids, layer, - grid_instance_ids); + grid_instance_ids, perimeter_cb); } if (status == CMD_EXEC_FATAL_ERROR) { return status; diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index d4c18e7a7..08a642e07 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -42,7 +42,8 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup); + const RRClockSpatialLookup& rr_clock_lookup, + const bool& perimeter_cb); void add_top_module_nets_prog_clock(ModuleManager& module_manager, const ModuleId& top_module, diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 1f539ffcf..85768ff92 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -27,7 +27,7 @@ namespace openfpga { *******************************************************************/ std::vector find_physical_tile_pin_side( t_physical_tile_type_ptr physical_tile, const int& physical_pin, - const e_side& border_side) { + const e_side& border_side, const bool& perimeter_cb) { std::vector pin_sides; for (const e_side& side_cand : {TOP, RIGHT, BOTTOM, LEFT}) { int pin_width_offset = physical_tile->pin_width_offset[physical_pin]; @@ -40,17 +40,20 @@ std::vector find_physical_tile_pin_side( /* For regular grid, we should have pin only one side! * I/O grids: VPR creates the grid with duplicated pins on every side - * but the expected side (only used side) will be opposite side of the border + * - In regular cases: the expected side (only used side) will be on the opposite to the border * side! + * - When perimeter cb is on, the expected sides can be on any sides except the border side. But we only expect 1 side */ if (NUM_SIDES == border_side) { VTR_ASSERT(1 == pin_sides.size()); - } else { + } else if (!perimeter_cb) { SideManager side_manager(border_side); VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(), pin_sides.end(), side_manager.get_opposite())); pin_sides.clear(); pin_sides.push_back(side_manager.get_opposite()); + } else { + VTR_ASSERT(1 == pin_sides.size() && pin_sides[0] != border_side); } return pin_sides; diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.h b/openfpga/src/utils/openfpga_physical_tile_utils.h index 1ac98f321..68cb3972e 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.h +++ b/openfpga/src/utils/openfpga_physical_tile_utils.h @@ -20,7 +20,7 @@ namespace openfpga { std::vector find_physical_tile_pin_side( t_physical_tile_type_ptr physical_tile, const int& physical_pin, - const e_side& border_side); + const e_side& border_side, const bool& perimeter_cb); float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type, const int& pin); From ab454be831c8f3143acb8883e4131c803ea73ee5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 13:32:54 -0700 Subject: [PATCH 175/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index d2be1c8b2..5ca82e54c 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit d2be1c8b2629069479863826695ed317bf88618a +Subproject commit 5ca82e54c4a2fa007fa7c43e9e91e582b7cf03fe From 549dc6e7e60e5523618eda2fc0f9ada3a6ec6450 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 13:39:55 -0700 Subject: [PATCH 176/230] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 5ca82e54c..ddc3ac408 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 5ca82e54c4a2fa007fa7c43e9e91e582b7cf03fe +Subproject commit ddc3ac408aa123dc8d4da1685c6dec7e65038646 From b50acacfbaaba260473dd3e30dc54d106bb33088 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 15:09:31 -0700 Subject: [PATCH 177/230] [test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles --- .../config/task.conf | 2 +- ...rimeterCb_ClkNtwk_registerable_io_40nm.xml | 28 +++++++++---------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf index 20efcfa2d..99a16d52e 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf @@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=2x2 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_route_chan_width=20 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml openfpga_verilog_testbench_options=--explicit_port_mapping diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index 09a0af616..83d977423 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -48,10 +48,10 @@ - io_top[0:1].outpad[0:0] io_top[0:1].inpad[0:0] + io_top[0:1].outpad[0:0] - io_top[0:5].clk[0:0] - io_top[2:5].outpad[0:0] io_top[2:5].inpad[0:0] + io_top[2:3].outpad io_top[0:5].clk[0:0] + io_top[4:5].outpad[0:0] io_top[0:5].inpad[0:0] @@ -67,10 +67,10 @@ - io_right[0:0].outpad[0:0] io_right[0:0].inpad[0:0] io_right[0:2].clk[0:0] + io_right[0:0].outpad[0:0] io_right[0:2].inpad[0:0] io_right[0:2].clk[0:0] - io_right[1:1].outpad[0:0] io_right[1:1].inpad[0:0] - io_right[2:2].outpad[0:0] io_right[2:2].inpad[0:0] + io_right[1:1].outpad[0:0] + io_right[2:2].outpad[0:0] @@ -86,10 +86,10 @@ - io_bottom[0:1].outpad[0:0] io_bottom[0:1].inpad[0:0] io_bottom[0:3].clk[0:0] + io_bottom[0:1].outpad[0:0] io_bottom[0:3].clk[0:0] - io_bottom[2:3].outpad[0:0] io_bottom[2:3].inpad[0:0] - + io_bottom[2:2].outpad[0:0] io_bottom[0:3].inpad[0:0] + io_bottom[3:3].outpad[0:0] @@ -105,10 +105,10 @@ - io_left[0:1].outpad[0:0] io_left[0:1].inpad[0:0] io_left[0:3].clk[0:0] + io_left[0:1].outpad[0:0] io_left[0:3].inpad[0:0] io_left[0:3].clk[0:0] - - io_left[2:3].outpad[0:0] io_left[2:3].inpad[0:0] + io_left[2:2].outpad[0:0] + io_left[3:3].outpad[0:0] @@ -206,12 +206,12 @@ - + 1 1 1 - + 1 1 1 1 1 1 1 1 1 From 8bca3d79be5fdc284cb25bd8bce565982a385fe2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 15:17:24 -0700 Subject: [PATCH 178/230] [core] fixed a bug where tap points of clock network cannot reach perimeter cb --- .../src/annotation/append_clock_rr_graph.cpp | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index b7b82c269..0837e1fcd 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -751,9 +751,16 @@ static void add_rr_graph_clock_edges( const DeviceGrid& grids, const size_t& layer, const bool& perimeter_cb, const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { + vtr::Rect chanx_bb(1, 0, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chanx_bb.set_xmin(0); + chanx_bb.set_xmax(grids.width()); + chanx_bb.set_ymin(0); + chanx_bb.set_ymax(grids.height()); + } /* Add edges which is driven by X-direction clock routing tracks */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { + for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are * not allowed */ @@ -768,8 +775,15 @@ static void add_rr_graph_clock_edges( } /* Add edges which is driven by Y-direction clock routing tracks */ - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chany_bb.set_xmin(0); + chany_bb.set_xmax(grids.width()); + chany_bb.set_ymin(0); + chany_bb.set_ymax(grids.height()); + } + for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { + for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ From c30eafac9f7c511c95452a1435edd9d7b9ddd6a0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 15:26:16 -0700 Subject: [PATCH 179/230] [test] fixed a bug on clk ntwk arch where some io clocks are not tapped --- .../config/clk_arch_1clk_2layer.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml index 453d0b5d0..2b85f88cd 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml @@ -16,10 +16,10 @@ - - - - + + + + From 6dde383a7fbc0f4b049ee214553885d968598501 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 16:00:18 -0700 Subject: [PATCH 180/230] [core] debugging --- .../src/annotation/append_clock_rr_graph.cpp | 3 +++ .../utils/openfpga_physical_tile_utils.cpp | 20 +++++++++---------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 0837e1fcd..f9aadfc74 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -420,14 +420,17 @@ static void try_find_and_add_clock_track2ipin_node( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) { + VTR_LOG("Checking tap pin name: %s\n", tap_pin_name.c_str()); /* tap pin name could be 'io[5:5].a2f[0]' */ int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name); if (grid_pin_idx == grid_type->num_pins) { continue; } + VTR_LOG("Found a valid pin in physical tile\n"); RRNodeId des_node = rr_graph_view.node_lookup().find_node( layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side); if (rr_graph_view.valid_node(des_node)) { + VTR_LOG("Found a valid pin in rr graph\n"); des_nodes.push_back(des_node); } } diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 85768ff92..1cce2eeee 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -144,9 +144,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, } PortParser tile_parser(pin_tokens[0]); BasicPort tile_info = tile_parser.port(); - if (tile_info.get_name() != std::string(physical_tile->name)) { - return pin_idx; - } if (!tile_info.is_valid()) { VTR_LOG_ERROR( "Invalid pin name '%s' whose subtile index is not valid, expect [0, " @@ -162,13 +159,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, pin_name.c_str()); exit(1); } - if (tile_info.get_msb() > size_t(physical_tile->capacity) - 1) { - VTR_LOG_ERROR( - "Invalid pin name '%s' whose subtile index is out of range, expect [0, " - "%lu]\n", - pin_name.c_str(), physical_tile->capacity - 1); - exit(1); - } /* precheck: return unfound pin if the pin index does not match */ PortParser pin_parser(pin_tokens[1]); BasicPort pin_info = pin_parser.port(); @@ -183,9 +173,17 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, /* Spot the subtile by using the index */ for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) { - if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) { + /* Bypass unmatched subtiles*/ + if (tile_info.get_name() != std::string(sub_tile.name)) { continue; } + if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) { + VTR_LOG_ERROR( + "Invalid pin name '%s' whose subtile index is out of range, expect [%lu, " + "%lu]\n", + pin_name.c_str(), sub_tile.capacity.low, sub_tile.capacity.high); + exit(1); + } for (const t_physical_tile_port& sub_tile_port : sub_tile.ports) { if (std::string(sub_tile_port.name) != pin_info.get_name()) { continue; From e8f9deeeaf0730ffb964940e76acff3161ec9697 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 16:12:20 -0700 Subject: [PATCH 181/230] [core] fixed a critical bug on computing pin index for subtile in clock taps --- openfpga/src/utils/openfpga_physical_tile_utils.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 1cce2eeee..ee3b3b5db 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -205,8 +205,9 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, /* Reach here, we get the port we want, return the accumulated index */ size_t accumulated_pin_idx = sub_tile_port.absolute_first_pin_index + - sub_tile.num_phy_pins * (tile_info.get_lsb() - sub_tile.capacity.low) + + (sub_tile.num_phy_pins / sub_tile.capacity.total()) * (tile_info.get_lsb() - sub_tile.capacity.low) + pin_info.get_lsb(); + VTR_LOG("Pin index: %lu\n", accumulated_pin_idx); return accumulated_pin_idx; } } From db459b0e87df04f824c90420b6b8a983c4933d62 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 16:18:32 -0700 Subject: [PATCH 182/230] [core] add verbose outputs --- .../src/annotation/append_clock_rr_graph.cpp | 21 ++++++++++--------- .../utils/openfpga_physical_tile_utils.cpp | 1 - 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index f9aadfc74..d54c018a6 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -415,22 +415,22 @@ static void try_find_and_add_clock_track2ipin_node( const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& grid_coord, const e_side& pin_side, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, - const ClockTreePinId& clk_pin) { + const ClockTreePinId& clk_pin, const bool& verbose) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) { - VTR_LOG("Checking tap pin name: %s\n", tap_pin_name.c_str()); + VTR_LOGV(verbose, "Checking tap pin name: %s\n", tap_pin_name.c_str()); /* tap pin name could be 'io[5:5].a2f[0]' */ int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name); if (grid_pin_idx == grid_type->num_pins) { continue; } - VTR_LOG("Found a valid pin in physical tile\n"); + VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n", grid_pin_idx); RRNodeId des_node = rr_graph_view.node_lookup().find_node( layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side); if (rr_graph_view.valid_node(des_node)) { - VTR_LOG("Found a valid pin in rr graph\n"); + VTR_LOGV(verbose, "Found a valid pin in rr graph\n"); des_nodes.push_back(des_node); } } @@ -466,7 +466,8 @@ static std::vector find_clock_track2ipin_node( const DeviceGrid& grids, const RRGraphView& rr_graph_view, const t_rr_type& chan_type, const size_t& layer, const vtr::Point& chan_coord, const ClockNetwork& clk_ntwk, - const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) { + const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin, + const bool& verbose) { std::vector des_nodes; if (chan_type == CHANX) { @@ -474,26 +475,26 @@ static std::vector find_clock_track2ipin_node( vtr::Point bot_grid_coord(chan_coord.x(), chan_coord.y() + 1); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, layer, bot_grid_coord, BOTTOM, - clk_ntwk, clk_tree, clk_pin); + clk_ntwk, clk_tree, clk_pin, verbose); /* Get the clock IPINs at the TOP side of adjacent grids [x][y] */ vtr::Point top_grid_coord(chan_coord.x(), chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, layer, top_grid_coord, TOP, clk_ntwk, - clk_tree, clk_pin); + clk_tree, clk_pin, verbose); } else { VTR_ASSERT(chan_type == CHANY); /* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */ vtr::Point left_grid_coord(chan_coord.x() + 1, chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, layer, left_grid_coord, LEFT, - clk_ntwk, clk_tree, clk_pin); + clk_ntwk, clk_tree, clk_pin, verbose); /* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */ vtr::Point right_grid_coord(chan_coord.x(), chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, layer, right_grid_coord, RIGHT, - clk_ntwk, clk_tree, clk_pin); + clk_ntwk, clk_tree, clk_pin, verbose); } return des_nodes; @@ -560,7 +561,7 @@ static void add_rr_graph_block_clock_edges( size_t curr_edge_count = edge_count; for (RRNodeId des_node : find_clock_track2ipin_node( grids, rr_graph_view, chan_type, layer, chan_coord, clk_ntwk, - itree, ClockTreePinId(ipin))) { + itree, ClockTreePinId(ipin), verbose)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); rr_graph_builder.create_edge( diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index ee3b3b5db..652e7ecc7 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -207,7 +207,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, sub_tile_port.absolute_first_pin_index + (sub_tile.num_phy_pins / sub_tile.capacity.total()) * (tile_info.get_lsb() - sub_tile.capacity.low) + pin_info.get_lsb(); - VTR_LOG("Pin index: %lu\n", accumulated_pin_idx); return accumulated_pin_idx; } } From fe06c2f2b17641208b9923883e7215427a784a78 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 16:18:58 -0700 Subject: [PATCH 183/230] [core] code format --- .../src/annotation/append_clock_rr_graph.cpp | 24 +++++++++---------- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 4 ++-- openfpga/src/fabric/build_device_module.cpp | 3 +-- openfpga/src/fabric/build_top_module.cpp | 3 +-- openfpga/src/fabric/build_top_module.h | 3 +-- ...top_module_child_fine_grained_instance.cpp | 3 +-- ...d_top_module_child_fine_grained_instance.h | 3 +-- .../build_top_module_child_tile_instance.cpp | 10 ++++---- .../build_top_module_child_tile_instance.h | 3 +-- .../fabric/build_top_module_connection.cpp | 6 ++--- .../src/fabric/build_top_module_connection.h | 3 +-- .../utils/openfpga_physical_tile_utils.cpp | 13 ++++++---- 12 files changed, 37 insertions(+), 41 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index d54c018a6..d051634db 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -426,7 +426,8 @@ static void try_find_and_add_clock_track2ipin_node( if (grid_pin_idx == grid_type->num_pins) { continue; } - VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n", grid_pin_idx); + VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n", + grid_pin_idx); RRNodeId des_node = rr_graph_view.node_lookup().find_node( layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side); if (rr_graph_view.valid_node(des_node)) { @@ -473,9 +474,9 @@ static std::vector find_clock_track2ipin_node( if (chan_type == CHANX) { /* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */ vtr::Point bot_grid_coord(chan_coord.x(), chan_coord.y() + 1); - try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, bot_grid_coord, BOTTOM, - clk_ntwk, clk_tree, clk_pin, verbose); + try_find_and_add_clock_track2ipin_node( + des_nodes, grids, rr_graph_view, layer, bot_grid_coord, BOTTOM, clk_ntwk, + clk_tree, clk_pin, verbose); /* Get the clock IPINs at the TOP side of adjacent grids [x][y] */ vtr::Point top_grid_coord(chan_coord.x(), chan_coord.y()); @@ -486,15 +487,15 @@ static std::vector find_clock_track2ipin_node( VTR_ASSERT(chan_type == CHANY); /* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */ vtr::Point left_grid_coord(chan_coord.x() + 1, chan_coord.y()); - try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, left_grid_coord, LEFT, - clk_ntwk, clk_tree, clk_pin, verbose); + try_find_and_add_clock_track2ipin_node( + des_nodes, grids, rr_graph_view, layer, left_grid_coord, LEFT, clk_ntwk, + clk_tree, clk_pin, verbose); /* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */ vtr::Point right_grid_coord(chan_coord.x(), chan_coord.y()); - try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, right_grid_coord, RIGHT, - clk_ntwk, clk_tree, clk_pin, verbose); + try_find_and_add_clock_track2ipin_node( + des_nodes, grids, rr_graph_view, layer, right_grid_coord, RIGHT, clk_ntwk, + clk_tree, clk_pin, verbose); } return des_nodes; @@ -816,8 +817,7 @@ static void add_rr_graph_clock_edges( *******************************************************************/ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const bool& verbose) { + const ClockNetwork& clk_ntwk, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Appending programmable clock network to routing resource graph"); diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index e96e4d218..4d7e1cfd4 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -59,8 +59,8 @@ static void update_cluster_pin_with_post_routing_results( VTR_ASSERT(class_inf.type == RECEIVER); rr_node_type = IPIN; } - std::vector pin_sides = - find_physical_tile_pin_side(physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb); + std::vector pin_sides = find_physical_tile_pin_side( + physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb); /* As some grid has height/width offset, we may not have the pin on any side */ if (0 == pin_sides.size()) { diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 3ffa869e8..d517002a7 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -143,8 +143,7 @@ int build_device_module_graph( sram_model, fabric_tile, name_module_using_index, frame_view, compress_routing, duplicate_grid_pin, fabric_key, generate_random_fabric_key, group_config_block, - vpr_device_ctx.arch->perimeter_cb, - verbose); + vpr_device_ctx.arch->perimeter_cb, verbose); if (CMD_EXEC_FATAL_ERROR == status) { return status; diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 54fd54702..fc2831d95 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -58,8 +58,7 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, - const bool& perimeter_cb, + const bool& group_config_block, const bool& perimeter_cb, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build FPGA fabric module"); diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index 75c3649eb..4e560d4f3 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -45,8 +45,7 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, - const bool& perimeter_cb, + const bool& group_config_block, const bool& perimeter_cb, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 7e3fcfa2f..914e384e1 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -454,8 +454,7 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, - const bool& perimeter_cb, + const bool& group_config_block, const bool& perimeter_cb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index 394f7a2df..b4d1677d8 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -44,8 +44,7 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, - const bool& perimeter_cb, + const bool& group_config_block, const bool& perimeter_cb, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index bf12dabc6..05f1f9b51 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1530,8 +1530,8 @@ static int build_top_module_global_net_from_tile_modules( status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, - fabric_tile, perimeter_cb); + vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, fabric_tile, + perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1600,7 +1600,8 @@ static int add_top_module_global_ports_from_tile_modules( const size_t& layer, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, - const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) { + const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, + const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1905,8 +1906,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose) { + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status = CMD_EXEC_SUCCESS; vtr::Matrix tile_instance_ids; status = add_top_module_tile_instances(module_manager, top_module, diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.h b/openfpga/src/fabric/build_top_module_child_tile_instance.h index 74a8aea63..05b44d017 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.h +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.h @@ -44,8 +44,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose); + const bool& perimeter_cb, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 46907a1bb..0a754f352 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1171,7 +1171,8 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids, perimeter_cb); + vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids, + perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1319,8 +1320,7 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup, - const bool& perimeter_cb) { + const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index 08a642e07..1c04d0e25 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -42,8 +42,7 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup, - const bool& perimeter_cb); + const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb); void add_top_module_nets_prog_clock(ModuleManager& module_manager, const ModuleId& top_module, diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 652e7ecc7..fd77cc072 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -40,9 +40,10 @@ std::vector find_physical_tile_pin_side( /* For regular grid, we should have pin only one side! * I/O grids: VPR creates the grid with duplicated pins on every side - * - In regular cases: the expected side (only used side) will be on the opposite to the border - * side! - * - When perimeter cb is on, the expected sides can be on any sides except the border side. But we only expect 1 side + * - In regular cases: the expected side (only used side) will be on the + * opposite to the border side! + * - When perimeter cb is on, the expected sides can be on any sides except + * the border side. But we only expect 1 side */ if (NUM_SIDES == border_side) { VTR_ASSERT(1 == pin_sides.size()); @@ -179,7 +180,8 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, } if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) { VTR_LOG_ERROR( - "Invalid pin name '%s' whose subtile index is out of range, expect [%lu, " + "Invalid pin name '%s' whose subtile index is out of range, expect " + "[%lu, " "%lu]\n", pin_name.c_str(), sub_tile.capacity.low, sub_tile.capacity.high); exit(1); @@ -205,7 +207,8 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, /* Reach here, we get the port we want, return the accumulated index */ size_t accumulated_pin_idx = sub_tile_port.absolute_first_pin_index + - (sub_tile.num_phy_pins / sub_tile.capacity.total()) * (tile_info.get_lsb() - sub_tile.capacity.low) + + (sub_tile.num_phy_pins / sub_tile.capacity.total()) * + (tile_info.get_lsb() - sub_tile.capacity.low) + pin_info.get_lsb(); return accumulated_pin_idx; } From ad053cddca71ad7c4dc03c47b259f82a277b8a1d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 18:02:30 -0700 Subject: [PATCH 184/230] [test] code format --- ..._tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index 83d977423..fe403bd62 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -49,7 +49,7 @@ io_top[0:1].outpad[0:0] - + io_top[2:3].outpad io_top[0:5].clk[0:0] io_top[4:5].outpad[0:0] io_top[0:5].inpad[0:0] @@ -68,7 +68,7 @@ io_right[0:0].outpad[0:0] io_right[0:2].inpad[0:0] io_right[0:2].clk[0:0] - + io_right[1:1].outpad[0:0] io_right[2:2].outpad[0:0] @@ -87,7 +87,7 @@ io_bottom[0:1].outpad[0:0] io_bottom[0:3].clk[0:0] - + io_bottom[2:2].outpad[0:0] io_bottom[0:3].inpad[0:0] io_bottom[3:3].outpad[0:0] @@ -106,7 +106,7 @@ io_left[0:1].outpad[0:0] io_left[0:3].inpad[0:0] io_left[0:3].clk[0:0] - + io_left[2:2].outpad[0:0] io_left[3:3].outpad[0:0] From c7d6c3ab6169329701395574c3c3ac5208d0b159 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 18:34:13 -0700 Subject: [PATCH 185/230] [arch] now all the outputs of I/O can only on 1 side --- ...k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index e25a5a686..19caea0ac 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -67,8 +67,8 @@ - fpga_input[0:1].inpad - fpga_input[2:3].inpad + + fpga_input[0:3].inpad @@ -93,9 +93,9 @@ - fpga_input[0:1].inpad + fpga_input[0:3].inpad - fpga_input[2:3].inpad + @@ -122,8 +122,8 @@ - fpga_input[0:1].inpad - fpga_input[2:3].inpad + + fpga_input[0:3].inpad @@ -150,9 +150,9 @@ - fpga_input[0:1].inpad + fpga_input[0:3].inpad - fpga_input[2:3].inpad + From 03c1c6f9173e1bfd54be7b76582b8a991c505898 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 18:35:23 -0700 Subject: [PATCH 186/230] [test] code format --- .../k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index 19caea0ac..142784a73 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -67,7 +67,7 @@ - + fpga_input[0:3].inpad @@ -95,7 +95,7 @@ fpga_input[0:3].inpad - + @@ -122,7 +122,7 @@ - + fpga_input[0:3].inpad @@ -152,7 +152,7 @@ fpga_input[0:3].inpad - + From 8a5c33b1d642cd569c58084f9118e1637960bbf1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 19:01:16 -0700 Subject: [PATCH 187/230] [doc] new option for perimeter cb --- .../manual/arch_lang/addon_vpr_syntax.rst | 17 +++++++++++++++++ .../manual/arch_lang/figures/perimeter_cb.png | Bin 0 -> 5525581 bytes 2 files changed, 17 insertions(+) create mode 100644 docs/source/manual/arch_lang/figures/perimeter_cb.png diff --git a/docs/source/manual/arch_lang/addon_vpr_syntax.rst b/docs/source/manual/arch_lang/addon_vpr_syntax.rst index b2c88992c..95a8eec64 100644 --- a/docs/source/manual/arch_lang/addon_vpr_syntax.rst +++ b/docs/source/manual/arch_lang/addon_vpr_syntax.rst @@ -88,6 +88,23 @@ Layout .. warning:: Do NOT enable ``shrink_boundary`` if you are not using the tileable routing resource graph generator! +.. option:: perimeter_cb="" + + Allow connection blocks to appear around the perimeter programmable block (mainly I/Os). This is designed to enhance routability of I/Os on perimeter. Also strongly recommended when programmable clock network is required to touch clock pins on I/Os. As illustrated in :numref:`fig_perimeter_cb`, routing tracks can access three sides of each I/O when perimeter connection blocks are created. + By default, it is ``false``. + +.. warning:: When enabled, please only place outputs at one side of I/Os. For example, outputs of an I/O on the top side can only occur on the bottom side of the I/O tile. Otherwise, routability loss may be expected, leading to some pins cannot be reachable. Enable the ``opin2all_sides`` to recover routability loss. + + .. _fig_perimeter_cb: + + .. figure:: ./figures/perimeter_cb.png + :width: 100% + :alt: Impact of perimeter_cb + + Impact on routing architecture when perimeter connection blocks are : (a) disabled; (b) enabled. + + .. warning:: Do NOT enable ``perimeter_cb`` if you are not using the tileable routing resource graph generator! + .. option:: opin2all_sides="" Allow each output pin of a programmable block to drive the routing tracks on all the sides of its adjacent switch block (see an illustrative example in :numref:`fig_opin2all_sides`). This can improve the routability of an FPGA fabric with an increase in the sizes of routing multiplexers in each switch block. diff --git a/docs/source/manual/arch_lang/figures/perimeter_cb.png b/docs/source/manual/arch_lang/figures/perimeter_cb.png new file mode 100644 index 0000000000000000000000000000000000000000..e3a65833866e5c744504e5d357e786b8250578c1 GIT binary patch literal 5525581 zcmeEu=U-FXwl)G%M2esyh9X@A1x0D0sDOY7sO&8u(xe0>G(!hwGsaBhLt{P8Qx{J$ zFfec$=<7UYVBiA&*lx420G})t=)MG=PQV`P-DN1k3N8U}m?3wJ?l3Tv#&J;XP6F@Q zJ@hSL3=B6~j{i9 zj1;|py2$yDo9x+L&Nm~Su78{k=D3{AcIwJ{O%Mm;shUfdvo2?S=UQLwJKe58QJ^pq zZKlS&KS5o>UgXwCjWoM!N{38X{h7b+v#vqR{3~$znp7yyT{h8wd-$HJF#d!mv|8@p zKKuKW?{5^wr4nwNOaIUFdG1D>W@~pndFOTS|9L=+J=9z5|GL(H2KgWB{$K0(pXK_$ zR^>m|^}oIJKhF4{u<}2m>iphp37x45zSQ9Oe;rVYXKqtFb9~l`!SQjZtXWZofT9zwBa+XxEtFm9 z#ZL*8y5F|XO!I-D-$EJ$+WGF>6H7}_W-D}MxNvxKvdKzKO|8wn?;;4amf<_uy-0O$ z*b2LK^QO6rOF^M!HP#86UQ5GaL;|TAn8S@c$zzHMMx;T-?xAAfimRwpN)x2*Rm1Zxr3um@lH@ruMN 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openfpga_flow/regression_test_scripts/basic_reg_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 4e1f55602..0f3abd81d 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -197,7 +197,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile $@ run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ -run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@ run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ From 229adebe07e88b73c506c67bd44c31b24ffe33d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 21:06:12 -0700 Subject: [PATCH 189/230] [doc] new option to write_fabric_verilog --- .../openfpga_commands/fpga_verilog_commands.rst | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 2ad413605..b29ce75d8 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -14,6 +14,14 @@ write_fabric_verilog Specify the output directory for the Verilog netlists. For example, ``--file /temp/fabric_netlist/`` + .. option:: --constant_undriven_inputs + + .. note:: This option is automatically enabled when the option ``perimeter_cb`` of tileable routing resource graph is enabled (see details in :ref`addon_vpr_syntax`). + + .. note:: Enable this option may shadow issues in your FPGA architecture, which causes them difficult to be found in design verification. + + Use constant gnd for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric. + .. option:: --default_net_type Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. From bf484dbc7019a5d9db4a3a7543f4c6e8b1dbb21c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 21:25:12 -0700 Subject: [PATCH 190/230] [doc] add perimeter cb examples on prog clk network --- .../manual/file_formats/clock_network.rst | 15 +++++++++++++++ ...rog_clk_network_example_2x2_perimeter_cb.png | Bin 0 -> 82100 bytes 2 files changed, 15 insertions(+) create mode 100644 docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index f9c94b5a3..8bab91b43 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -14,6 +14,8 @@ Using the clock network description language, users can define multiple clock ne - A number of switch points which interconnects clock spines using programmable routing switches. See details in :ref:`file_formats_clock_network_switch_point`. - A number of tap points which connect the clock spines to programmable blocks, e.g., CLBs. See details in :ref:`file_formats_clock_network_tap_point`. +The entry point of a clock tree must be at a valid connection block. + .. note:: Please note that the levels of a clock network will be automatically inferred from the clock spines and switch points. Clock network will be **only** built based on the width and the number of levels, as well as the tap points. .. note:: The switch points and clock spines will be used to route a clock network. The switch points will not impact the physical clock network but only impact the configuration of the programmable routing switches in the physical clock network. @@ -45,6 +47,17 @@ Using the clock network description language, users can define multiple clock ne An example of programmable clock network considering a 2x2 FPGA fabric +Note that when the ``perimeter_cb`` is enabled for routing architecture (See details in :ref:`addon_vpr_syntax`), clock entry point can be indeed at the fringe of FPGA fabrics. See example in :numref:`prog_clock_network_example_2x2_perimeter_cb`. + +.. _fig_prog_clock_network_example_2x2_perimeter_cb: + +.. figure:: figures/prog_clk_network_example_2x2_perimeter_cb.png + :width: 100% + :alt: An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb + + An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb + + General Settings ^^^^^^^^^^^^^^^^ @@ -134,6 +147,8 @@ Clock Spine Settings The following syntax are applicable to the XML definition tagged by ``spine``. Note that a number of clock spines can be defined under the node ``clock_network``. +.. note:: Use coordinates of connection blocks to define the starting and ending points of clock spines. + .. option:: name="" The unique name of the clock spine. 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z6H|h=?qCKE{j?gBC74wF1ft-?_)IqyeLlkbu_D3HW<(GyUxFL#h}m=}*u}j4>^xz_ zu>_y{B*1M;V(mY}`_}(Ep_8`iup`Fvf5im<-?!_XcOW;_cwl*Mx3YE*NdXbz(9ty1 Js8e%@{2xe7fI9#H literal 0 HcmV?d00001 From 5cb104a5f69cea7f98b9f7f8149acb5d936d9055 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 22:04:40 -0700 Subject: [PATCH 191/230] [test] fixed a bug --- ...k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml | 6 +++--- .../global_tile_clock_subtile/config/task.conf | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml index 56186f37f..32f84fff8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml @@ -195,10 +195,10 @@ - + - - + + diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf index d7f7a848c..d6172bb2f 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf @@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2_hybrid_io -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=20 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml From 1cdb1c59959ca3b2fd4f76ff9ce6751dfb2385a4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 22:22:08 -0700 Subject: [PATCH 192/230] [core] fixed a bug on calculating subtile pins --- .../fabric/build_top_module_connection.cpp | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 0a754f352..494b4967f 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -975,6 +975,7 @@ static int build_top_module_global_net_for_given_grid_module( /* Walk through each instance considering the unique sub tile and capacity * range, each instance may have an independent pin to be driven by a global * net! */ + int curr_sub_tile_start_pin_index = 0; for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) { VTR_ASSERT(1 == sub_tile.equivalent_sites.size()); int grid_pin_start_index = physical_tile->num_pins; @@ -995,18 +996,19 @@ static int build_top_module_global_net_for_given_grid_module( /* Port size must match!!! */ if (false == ref_tile_port.contained(tile_port_to_connect)) { VTR_LOG_ERROR( - "Tile annotation '%s' port '%s[%lu:%lu]' is out of the range of " - "physical tile port '%s[%lu:%lu]'!", + "Tile annotation '%s' port '%s' is out of the range of " + "physical tile port '%s'!\n", tile_annotation.global_port_name(tile_global_port).c_str(), - tile_port_to_connect.get_name().c_str(), - tile_port_to_connect.get_lsb(), tile_port_to_connect.get_msb(), - ref_tile_port.get_name().c_str(), ref_tile_port.get_lsb(), - ref_tile_port.get_msb()); + tile_port_to_connect.to_verilog_string().c_str(), + ref_tile_port.to_verilog_string().c_str()); return CMD_EXEC_FATAL_ERROR; } - grid_pin_start_index = + grid_pin_start_index = curr_sub_tile_start_pin_index + (subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + tile_port.absolute_first_pin_index; + VTR_LOG( + "Index %lu for physical tile port '%s.%s.%s'\n!", grid_pin_start_index, + physical_tile->name, sub_tile.name, ref_tile_port.to_verilog_string().c_str()); physical_tile_port = tile_port; break; } @@ -1079,6 +1081,8 @@ static int build_top_module_global_net_for_given_grid_module( } } } + /* Note that the start pin index for a new type of tile should be calculated by the accumulated number of pins of previous sub tiles */ + curr_sub_tile_start_pin_index += sub_tile.num_phy_pins; } return CMD_EXEC_SUCCESS; @@ -1140,7 +1144,7 @@ static int build_top_module_global_net_from_grid_modules( if (true == out_of_range) { VTR_LOG_ERROR( "Coordinate (%lu, %lu) in tile annotation for tile '%s' is out of " - "range (%lu:%lu, %lu:%lu)!", + "range (%lu:%lu, %lu:%lu)!\n", range.x(), range.y(), tile_name.c_str(), start_coord.x(), end_coord.x(), start_coord.y(), end_coord.y()); return CMD_EXEC_FATAL_ERROR; From 04504e4d5db0e1d74b67e1e0e8fa230c6c28f469 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 22:22:59 -0700 Subject: [PATCH 193/230] [core] code format --- openfpga/src/fabric/build_top_module_connection.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 494b4967f..f8f2526bb 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1003,12 +1003,13 @@ static int build_top_module_global_net_for_given_grid_module( ref_tile_port.to_verilog_string().c_str()); return CMD_EXEC_FATAL_ERROR; } - grid_pin_start_index = curr_sub_tile_start_pin_index + + grid_pin_start_index = + curr_sub_tile_start_pin_index + (subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + tile_port.absolute_first_pin_index; - VTR_LOG( - "Index %lu for physical tile port '%s.%s.%s'\n!", grid_pin_start_index, - physical_tile->name, sub_tile.name, ref_tile_port.to_verilog_string().c_str()); + VTR_LOG("Index %lu for physical tile port '%s.%s.%s'\n!", + grid_pin_start_index, physical_tile->name, sub_tile.name, + ref_tile_port.to_verilog_string().c_str()); physical_tile_port = tile_port; break; } @@ -1081,7 +1082,8 @@ static int build_top_module_global_net_for_given_grid_module( } } } - /* Note that the start pin index for a new type of tile should be calculated by the accumulated number of pins of previous sub tiles */ + /* Note that the start pin index for a new type of tile should be calculated + * by the accumulated number of pins of previous sub tiles */ curr_sub_tile_start_pin_index += sub_tile.num_phy_pins; } From 092b8b038f08a42f951d8af2f636a84f051e54d1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 22:23:37 -0700 Subject: [PATCH 194/230] [core] remove verbose out --- openfpga/src/fabric/build_top_module_connection.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index f8f2526bb..508516a8d 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1007,9 +1007,6 @@ static int build_top_module_global_net_for_given_grid_module( curr_sub_tile_start_pin_index + (subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + tile_port.absolute_first_pin_index; - VTR_LOG("Index %lu for physical tile port '%s.%s.%s'\n!", - grid_pin_start_index, physical_tile->name, sub_tile.name, - ref_tile_port.to_verilog_string().c_str()); physical_tile_port = tile_port; break; } From 5efc9d0e00b766c796d9acc7a216a939ae3fb31b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 23:24:16 -0700 Subject: [PATCH 195/230] [test] update golden outputs --- .../and2_fpga_top_analysis.sdc | 56 +- .../ccff_timing.sdc | 840 +- .../disable_configurable_memory_outputs.sdc | 56 +- .../fabric_bitstream.bit | 256 +- .../fabric_bitstream.xml | 716 +- .../golden_outputs_no_time_stamp/fpga_top.v | 14 +- .../gsb_xml/cby_0__1_.xml | 120 +- .../gsb_xml/cby_1__1_.xml | 132 +- .../gsb_xml_no_rr_info/cby_0__1_.xml | 120 +- .../gsb_xml_no_rr_info/cby_1__1_.xml | 132 +- .../and2_fpga_top_analysis.sdc | 108 +- .../ccff_timing.sdc | 6708 +++++++------- .../disable_configurable_memory_outputs.sdc | 108 +- .../fabric_bitstream.bit | 284 +- .../fabric_bitstream.xml | 8124 ++++++++--------- .../golden_outputs_no_time_stamp/fpga_top.v | 104 +- .../gsb_xml/cby_0__1_.xml | 76 +- .../gsb_xml/cby_0__2_.xml | 76 +- .../gsb_xml/cby_0__3_.xml | 76 +- .../gsb_xml/cby_0__4_.xml | 76 +- .../gsb_xml/cby_1__1_.xml | 28 +- .../gsb_xml/cby_1__2_.xml | 28 +- .../gsb_xml/cby_1__3_.xml | 28 +- .../gsb_xml/cby_1__4_.xml | 28 +- .../gsb_xml/cby_2__1_.xml | 28 +- .../gsb_xml/cby_2__2_.xml | 28 +- .../gsb_xml/cby_2__3_.xml | 28 +- .../gsb_xml/cby_2__4_.xml | 28 +- .../gsb_xml/cby_3__1_.xml | 28 +- .../gsb_xml/cby_3__2_.xml | 28 +- .../gsb_xml/cby_3__3_.xml | 28 +- .../gsb_xml/cby_3__4_.xml | 28 +- .../gsb_xml/cby_4__1_.xml | 80 +- .../gsb_xml/cby_4__2_.xml | 80 +- .../gsb_xml/cby_4__3_.xml | 80 +- .../gsb_xml/cby_4__4_.xml | 80 +- .../gsb_xml_no_rr_info/cby_0__1_.xml | 76 +- .../gsb_xml_no_rr_info/cby_0__2_.xml | 76 +- .../gsb_xml_no_rr_info/cby_0__3_.xml | 76 +- .../gsb_xml_no_rr_info/cby_0__4_.xml | 76 +- .../gsb_xml_no_rr_info/cby_1__1_.xml | 28 +- .../gsb_xml_no_rr_info/cby_1__2_.xml | 28 +- .../gsb_xml_no_rr_info/cby_1__3_.xml | 28 +- .../gsb_xml_no_rr_info/cby_1__4_.xml | 28 +- .../gsb_xml_no_rr_info/cby_2__1_.xml | 28 +- .../gsb_xml_no_rr_info/cby_2__2_.xml | 28 +- .../gsb_xml_no_rr_info/cby_2__3_.xml | 28 +- .../gsb_xml_no_rr_info/cby_2__4_.xml | 28 +- .../gsb_xml_no_rr_info/cby_3__1_.xml | 28 +- .../gsb_xml_no_rr_info/cby_3__2_.xml | 28 +- .../gsb_xml_no_rr_info/cby_3__3_.xml | 28 +- .../gsb_xml_no_rr_info/cby_3__4_.xml | 28 +- .../gsb_xml_no_rr_info/cby_4__1_.xml | 80 +- .../gsb_xml_no_rr_info/cby_4__2_.xml | 80 +- .../gsb_xml_no_rr_info/cby_4__3_.xml | 80 +- .../gsb_xml_no_rr_info/cby_4__4_.xml | 80 +- .../and2_fpga_top_analysis.sdc | 56 +- .../ccff_timing.sdc | 840 +- .../disable_configurable_memory_outputs.sdc | 56 +- .../fabric_bitstream.bit | 256 +- .../fabric_bitstream.xml | 716 +- .../golden_outputs_no_time_stamp/fpga_top.v | 14 +- .../gsb_xml/cby_0__1_.xml | 120 +- .../gsb_xml/cby_1__1_.xml | 132 +- .../gsb_xml_no_rr_info/cby_0__1_.xml | 120 +- .../gsb_xml_no_rr_info/cby_1__1_.xml | 132 +- .../and2_fpga_top_analysis.sdc | 124 +- .../ccff_timing.sdc | 3092 +++---- .../disable_configurable_memory_outputs.sdc | 124 +- .../fabric_bitstream.bit | 266 +- .../fabric_bitstream.xml | 3308 +++---- .../golden_outputs_no_time_stamp/fpga_top.v | 36 +- .../gsb_xml/cby_0__1_.xml | 72 +- .../gsb_xml/cby_0__2_.xml | 72 +- .../gsb_xml/cby_1__1_.xml | 56 +- .../gsb_xml/cby_1__2_.xml | 56 +- .../gsb_xml/cby_2__1_.xml | 112 +- .../gsb_xml/cby_2__2_.xml | 112 +- .../gsb_xml_no_rr_info/cby_0__1_.xml | 72 +- .../gsb_xml_no_rr_info/cby_0__2_.xml | 72 +- .../gsb_xml_no_rr_info/cby_1__1_.xml | 56 +- .../gsb_xml_no_rr_info/cby_1__2_.xml | 56 +- .../gsb_xml_no_rr_info/cby_2__1_.xml | 112 +- .../gsb_xml_no_rr_info/cby_2__2_.xml | 112 +- 84 files changed, 15075 insertions(+), 15075 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 8237fc2f9..2ccec1ac6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -57,16 +57,24 @@ set_disable_timing gfpga_pad_GPIO_PAD[31] set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -77,6 +85,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -91,30 +103,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc index df2b04e23..5a3b9e3df 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,346 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5 @@ -465,84 +125,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/s set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 @@ -725,8 +309,424 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_ set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index 022a20fcf..8cd7edd67 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,16 +6,24 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -26,6 +34,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -40,30 +52,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit index 3387708eb..7c8512c57 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -197,18 +197,7 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 0 0 0 @@ -243,8 +232,19 @@ 0 0 0 -1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -267,67 +267,6 @@ 1 1 1 -1 -1 -1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 0 0 0 @@ -423,34 +362,61 @@ 1 0 1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -485,19 +451,8 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 +1 0 0 0 @@ -515,16 +470,61 @@ 1 1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml index 4edf9cf2b..c42176d6b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -344,721 +344,721 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v index c8c3d7300..e0098e212 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v @@ -162,7 +162,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -206,7 +206,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -284,7 +284,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:12]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:12]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -338,7 +338,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:12]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:12]), .ccff_tail(sb_1__0__0_ccff_tail)); @@ -365,7 +365,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]), .chanx_left_out(sb_1__1__0_chanx_left_out[0:12]), .ccff_tail(sb_1__1__0_ccff_tail)); @@ -414,7 +414,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:12]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:12]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_0__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -433,7 +433,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:12]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:12]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_1__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index 99aadddf5..1943afce4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index eefaf5cd9..d4af896d6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 5ecb11950..0e17019b1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index edec22d72..010e9b689 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 897ef728e..3ef8489eb 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -153,48 +153,44 @@ set_disable_timing gfpga_pad_GPIO_PAD[127] set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -207,12 +203,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q @@ -221,6 +221,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -231,6 +239,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -247,6 +257,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -255,32 +273,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -293,8 +295,6 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN ################################################## # Disable timing for Connection block cbx_1__0_ ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc index bc1f632f0..a44bb6090 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,1324 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/D 5 @@ -1399,82 +81,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/s set_min_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 @@ -1613,8 +221,1352 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_ set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -1909,148 +1861,136 @@ set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -2345,148 +2285,136 @@ set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -2781,144 +2709,128 @@ set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -3251,128 +3163,128 @@ set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -3705,136 +3617,136 @@ set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -4129,136 +4041,136 @@ set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -4553,136 +4465,136 @@ set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -4977,136 +4889,136 @@ set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -5401,136 +5313,136 @@ set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -5825,136 +5737,136 @@ set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -6249,128 +6161,128 @@ set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -6703,128 +6615,144 @@ set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_2_/D 5 @@ -7157,136 +7085,160 @@ set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_2_/D 5 @@ -7581,136 +7533,160 @@ set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_2_/D 5 @@ -8005,136 +7981,160 @@ set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index 3c755b028..e644f9251 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,48 +6,44 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -60,12 +56,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q @@ -74,6 +74,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -84,6 +92,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -100,6 +110,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -108,32 +126,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -146,5 +148,3 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit index fc17891b4..1a79dc354 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -221,6 +221,8 @@ 0 0 0 +1 +1 0 0 0 @@ -621,6 +623,9 @@ 0 0 0 +1 +1 +1 0 0 0 @@ -804,7 +809,6 @@ 0 0 0 -1 0 0 0 @@ -828,8 +832,6 @@ 0 0 0 -1 -1 0 0 0 @@ -840,9 +842,7 @@ 0 0 0 -1 0 -1 0 0 0 @@ -864,7 +864,6 @@ 0 0 0 -1 0 0 0 @@ -877,9 +876,6 @@ 0 0 0 -1 -1 -1 0 0 0 @@ -898,6 +894,8 @@ 0 0 0 +1 +1 0 0 0 @@ -910,6 +908,7 @@ 0 0 0 +1 0 0 0 @@ -922,13 +921,15 @@ 0 0 0 +1 +1 +1 0 0 0 0 0 0 -1 0 0 0 @@ -939,13 +940,9 @@ 0 0 0 -1 0 -1 0 -1 0 -1 0 0 0 @@ -975,6 +972,7 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- + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v index 560ad7620..8d1c9cd5f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v @@ -807,7 +807,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__0_ccff_tail), + .ccff_head(grid_io_top_1_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -829,7 +829,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__1_ccff_tail), + .ccff_head(grid_io_top_2_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -851,7 +851,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__2_ccff_tail), + .ccff_head(grid_io_top_3_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -873,7 +873,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__3_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -983,7 +983,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_1_ccff_tail), + .ccff_head(cbx_1__0__3_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1005,7 +1005,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_2_ccff_tail), + .ccff_head(cbx_1__0__2_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1027,7 +1027,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_3_ccff_tail), + .ccff_head(cbx_1__0__1_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1049,7 +1049,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1538,7 +1538,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_1_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:9]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:9]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -1568,7 +1568,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_2_ccff_tail), + .ccff_head(grid_io_left_1_ccff_tail), .chany_top_out(sb_0__1__0_chany_top_out[0:9]), .chanx_right_out(sb_0__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:9]), @@ -1599,7 +1599,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_3_ccff_tail), + .ccff_head(grid_io_left_2_ccff_tail), .chany_top_out(sb_0__1__1_chany_top_out[0:9]), .chanx_right_out(sb_0__1__1_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__1_chany_bottom_out[0:9]), @@ -1630,7 +1630,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__4__0_ccff_tail), + .ccff_head(grid_io_left_3_ccff_tail), .chany_top_out(sb_0__1__2_chany_top_out[0:9]), .chanx_right_out(sb_0__1__2_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__2_chany_bottom_out[0:9]), @@ -1688,7 +1688,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:9]), .chanx_right_out(sb_1__0__0_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:9]), @@ -1719,7 +1719,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_0_ccff_tail), + .ccff_head(grid_io_bottom_3_ccff_tail), .chany_top_out(sb_1__0__1_chany_top_out[0:9]), .chanx_right_out(sb_1__0__1_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__1_chanx_left_out[0:9]), @@ -1750,7 +1750,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_4_ccff_tail), + .ccff_head(grid_io_bottom_2_ccff_tail), .chany_top_out(sb_1__0__2_chany_top_out[0:9]), .chanx_right_out(sb_1__0__2_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__2_chanx_left_out[0:9]), @@ -1770,7 +1770,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__0_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_5_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_top_out(sb_1__1__0_chany_top_out[0:9]), .chanx_right_out(sb_1__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:9]), @@ -1791,7 +1791,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__1_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_1_ccff_tail), + .ccff_head(grid_clb_5_ccff_tail), .chany_top_out(sb_1__1__1_chany_top_out[0:9]), .chanx_right_out(sb_1__1__1_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__1_chany_bottom_out[0:9]), @@ -1812,7 +1812,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__2_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_7_ccff_tail), + .ccff_head(grid_clb_1_ccff_tail), .chany_top_out(sb_1__1__2_chany_top_out[0:9]), .chanx_right_out(sb_1__1__2_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__2_chany_bottom_out[0:9]), @@ -1833,7 +1833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__3_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_9_ccff_tail), + .ccff_head(grid_clb_0_ccff_tail), .chany_top_out(sb_1__1__3_chany_top_out[0:9]), .chanx_right_out(sb_1__1__3_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__3_chany_bottom_out[0:9]), @@ -1854,7 +1854,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__4_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_2_ccff_tail), + .ccff_head(grid_clb_9_ccff_tail), .chany_top_out(sb_1__1__4_chany_top_out[0:9]), .chanx_right_out(sb_1__1__4_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__4_chany_bottom_out[0:9]), @@ -1875,7 +1875,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__5_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_11_ccff_tail), + .ccff_head(grid_clb_2_ccff_tail), .chany_top_out(sb_1__1__5_chany_top_out[0:9]), .chanx_right_out(sb_1__1__5_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__5_chany_bottom_out[0:9]), @@ -1896,7 +1896,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__6_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_13_ccff_tail), + .ccff_head(grid_clb_4_ccff_tail), .chany_top_out(sb_1__1__6_chany_top_out[0:9]), .chanx_right_out(sb_1__1__6_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__6_chany_bottom_out[0:9]), @@ -1917,7 +1917,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__7_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_6_ccff_tail), + .ccff_head(grid_clb_13_ccff_tail), .chany_top_out(sb_1__1__7_chany_top_out[0:9]), .chanx_right_out(sb_1__1__7_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__7_chany_bottom_out[0:9]), @@ -1938,7 +1938,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__8_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_15_ccff_tail), + .ccff_head(grid_clb_6_ccff_tail), .chany_top_out(sb_1__1__8_chany_top_out[0:9]), .chanx_right_out(sb_1__1__8_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__8_chany_bottom_out[0:9]), @@ -1970,7 +1970,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_top_1_ccff_tail), + .ccff_head(grid_clb_7_ccff_tail), .chanx_right_out(sb_1__4__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__4__0_chany_bottom_out[0:9]), .chanx_left_out(sb_1__4__0_chanx_left_out[0:9]), @@ -2001,7 +2001,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_top_2_ccff_tail), + .ccff_head(grid_clb_11_ccff_tail), .chanx_right_out(sb_1__4__1_chanx_right_out[0:9]), .chany_bottom_out(sb_1__4__1_chany_bottom_out[0:9]), .chanx_left_out(sb_1__4__1_chanx_left_out[0:9]), @@ -2032,7 +2032,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_top_3_ccff_tail), + .ccff_head(grid_clb_15_ccff_tail), .chanx_right_out(sb_1__4__2_chanx_right_out[0:9]), .chany_bottom_out(sb_1__4__2_chany_bottom_out[0:9]), .chanx_left_out(sb_1__4__2_chanx_left_out[0:9]), @@ -2060,7 +2060,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_8_ccff_tail), + .ccff_head(grid_io_bottom_1_ccff_tail), .chany_top_out(sb_4__0__0_chany_top_out[0:9]), .chanx_left_out(sb_4__0__0_chanx_left_out[0:9]), .ccff_tail(sb_4__0__0_ccff_tail)); @@ -2090,7 +2090,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__9_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_12_ccff_tail), + .ccff_head(grid_clb_8_ccff_tail), .chany_top_out(sb_4__1__0_chany_top_out[0:9]), .chany_bottom_out(sb_4__1__0_chany_bottom_out[0:9]), .chanx_left_out(sb_4__1__0_chanx_left_out[0:9]), @@ -2121,7 +2121,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__10_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_10_ccff_tail), + .ccff_head(grid_clb_12_ccff_tail), .chany_top_out(sb_4__1__1_chany_top_out[0:9]), .chany_bottom_out(sb_4__1__1_chany_bottom_out[0:9]), .chanx_left_out(sb_4__1__1_chanx_left_out[0:9]), @@ -2152,7 +2152,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__11_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_14_ccff_tail), + .ccff_head(grid_clb_10_ccff_tail), .chany_top_out(sb_4__1__2_chany_top_out[0:9]), .chany_bottom_out(sb_4__1__2_chany_bottom_out[0:9]), .chanx_left_out(sb_4__1__2_chanx_left_out[0:9]), @@ -2180,7 +2180,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_clb_14_ccff_tail), .chany_bottom_out(sb_4__4__0_chany_bottom_out[0:9]), .chanx_left_out(sb_4__4__0_chanx_left_out[0:9]), .ccff_tail(sb_4__4__0_ccff_tail)); @@ -2529,7 +2529,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:9]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2548,7 +2548,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__0_chany_top_out[0:9]), .chany_top_in(sb_0__1__1_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(sb_0__1__1_ccff_tail), .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2567,7 +2567,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__1_chany_top_out[0:9]), .chany_top_in(sb_0__1__2_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__1_ccff_tail), + .ccff_head(sb_0__1__2_ccff_tail), .chany_bottom_out(cby_0__1__2_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__2_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2586,7 +2586,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__2_chany_top_out[0:9]), .chany_top_in(sb_0__4__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__2_ccff_tail), + .ccff_head(sb_0__4__0_ccff_tail), .chany_bottom_out(cby_0__1__3_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__3_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2605,7 +2605,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:9]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2619,7 +2619,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__0_chany_top_out[0:9]), .chany_top_in(sb_1__1__1_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(cbx_1__1__1_ccff_tail), .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2633,7 +2633,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__1_chany_top_out[0:9]), .chany_top_in(sb_1__1__2_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__1_ccff_tail), + .ccff_head(cbx_1__1__2_ccff_tail), .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__2_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2647,7 +2647,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__2_chany_top_out[0:9]), .chany_top_in(sb_1__4__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__2_ccff_tail), + .ccff_head(cbx_1__4__0_ccff_tail), .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__3_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2661,7 +2661,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__1_chany_top_out[0:9]), .chany_top_in(sb_1__1__3_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__1_ccff_tail), + .ccff_head(cbx_1__1__3_ccff_tail), .chany_bottom_out(cby_1__1__4_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__4_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__4_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2675,7 +2675,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__3_chany_top_out[0:9]), .chany_top_in(sb_1__1__4_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__3_ccff_tail), + .ccff_head(cbx_1__1__4_ccff_tail), .chany_bottom_out(cby_1__1__5_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__5_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__5_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2689,7 +2689,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__4_chany_top_out[0:9]), .chany_top_in(sb_1__1__5_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__4_ccff_tail), + .ccff_head(cbx_1__1__5_ccff_tail), .chany_bottom_out(cby_1__1__6_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__6_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__6_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2703,7 +2703,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__5_chany_top_out[0:9]), .chany_top_in(sb_1__4__1_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__5_ccff_tail), + .ccff_head(cbx_1__4__1_ccff_tail), .chany_bottom_out(cby_1__1__7_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__7_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__7_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2717,7 +2717,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__2_chany_top_out[0:9]), .chany_top_in(sb_1__1__6_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__2_ccff_tail), + .ccff_head(cbx_1__1__6_ccff_tail), .chany_bottom_out(cby_1__1__8_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__8_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__8_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2731,7 +2731,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__6_chany_top_out[0:9]), .chany_top_in(sb_1__1__7_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__6_ccff_tail), + .ccff_head(cbx_1__1__7_ccff_tail), .chany_bottom_out(cby_1__1__9_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__9_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__9_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2745,7 +2745,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__7_chany_top_out[0:9]), .chany_top_in(sb_1__1__8_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__7_ccff_tail), + .ccff_head(cbx_1__1__8_ccff_tail), .chany_bottom_out(cby_1__1__10_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__10_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__10_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2759,7 +2759,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__8_chany_top_out[0:9]), .chany_top_in(sb_1__4__2_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__8_ccff_tail), + .ccff_head(cbx_1__4__2_ccff_tail), .chany_bottom_out(cby_1__1__11_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__11_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__11_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2773,7 +2773,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__0__0_chany_top_out[0:9]), .chany_top_in(sb_4__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__3_ccff_tail), + .ccff_head(cbx_1__1__9_ccff_tail), .chany_bottom_out(cby_4__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -2793,7 +2793,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__1__0_chany_top_out[0:9]), .chany_top_in(sb_4__1__1_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__9_ccff_tail), + .ccff_head(cbx_1__1__10_ccff_tail), .chany_bottom_out(cby_4__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -2813,7 +2813,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__1__1_chany_top_out[0:9]), .chany_top_in(sb_4__1__2_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__10_ccff_tail), + .ccff_head(cbx_1__1__11_ccff_tail), .chany_bottom_out(cby_4__1__2_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__2_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -2833,7 +2833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__1__2_chany_top_out[0:9]), .chany_top_in(sb_4__4__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__11_ccff_tail), + .ccff_head(cbx_1__4__3_ccff_tail), .chany_bottom_out(cby_4__1__3_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__3_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index a9421575e..07928fe3f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml index 2b935694f..ce309ecbf 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml index 5dc83d65a..6131cf308 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml index 82f30d5b4..9691260da 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index 685366747..e3e56cf32 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml index af800832a..4050ce7e4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml index ee71fb230..cf7a01345 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml index 00d00a5fd..4faa064fa 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml index c93bbf890..18b761b42 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml index de31ff3cc..6b602276f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml index e10d1106b..cfdad6f99 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml index cd54a99c7..1e6dabda1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml index e3f7a395c..8abb31ff2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml index 4f8024349..709dbbb2e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml index c19441be6..c5573a4b5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml index 102048421..e2de46537 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml index f3007ec85..f86ea9caa 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml index 9f589a7be..0d5b16c52 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml index f9e0b6a9c..a3d189670 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml index dea12ded1..3646dcf7a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 793b5628b..e2b960d51 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml index 4533c39bc..f63dde147 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml index 176b9f5f6..dff12bf3c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml index bee8e919c..1eb7f09a9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index 11fbfd51f..682749130 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml index 0026bd554..7a5e114c5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml index 50006d9d2..e514f592d 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml index 4063f260e..ec581676c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml index 488bff99b..d65b5ca5c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml index ea86b5480..b69d7bd68 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml index c3ac067bd..15ba71944 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml index 387479a35..5a77185a4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml index a3b68c168..47a94e7cd 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml index 83e9f50db..414f19d95 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml index ccaa1b7fb..b4b8d746e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml index df8bca3f2..146fe9653 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml index 20f9f7b50..763e7a89a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml index d533a55a7..e98acc918 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml index c9874c86b..655ea8946 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml index 52722e4bb..5847f5e49 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 8237fc2f9..2ccec1ac6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -57,16 +57,24 @@ set_disable_timing gfpga_pad_GPIO_PAD[31] set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -77,6 +85,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -91,30 +103,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc index df2b04e23..5a3b9e3df 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,346 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5 @@ -465,84 +125,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/s set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 @@ -725,8 +309,424 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_ set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index 022a20fcf..8cd7edd67 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,16 +6,24 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -26,6 +34,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -40,30 +52,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit index 3387708eb..7c8512c57 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -197,18 +197,7 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 0 0 0 @@ -243,8 +232,19 @@ 0 0 0 -1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -267,67 +267,6 @@ 1 1 1 -1 -1 -1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 0 0 0 @@ -423,34 +362,61 @@ 1 0 1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -485,19 +451,8 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 +1 0 0 0 @@ -515,16 +470,61 @@ 1 1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml index 4edf9cf2b..c42176d6b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -344,721 +344,721 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v index c8c3d7300..e0098e212 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v @@ -162,7 +162,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -206,7 +206,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -284,7 +284,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:12]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:12]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -338,7 +338,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:12]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:12]), .ccff_tail(sb_1__0__0_ccff_tail)); @@ -365,7 +365,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]), .chanx_left_out(sb_1__1__0_chanx_left_out[0:12]), .ccff_tail(sb_1__1__0_ccff_tail)); @@ -414,7 +414,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:12]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:12]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_0__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -433,7 +433,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:12]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:12]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_1__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index 99aadddf5..1943afce4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index eefaf5cd9..d4af896d6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 5ecb11950..0e17019b1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index edec22d72..010e9b689 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index a45d6aa34..e96165350 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -90,58 +90,6 @@ set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing pReset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -168,6 +116,62 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q @@ -186,6 +190,10 @@ set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q @@ -194,24 +202,14 @@ set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -220,6 +218,8 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc index a07071979..ca7724279 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,822 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFFR_0_/D 5 @@ -897,132 +81,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFFR_1_/Q -to fpga_top/ set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFFR_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_2_/D 5 @@ -1285,8 +345,968 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_4_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_2_/D 5 @@ -1961,208 +1981,188 @@ set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 5 set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_2_/D 5 @@ -2921,188 +2921,176 @@ set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_7_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 5 set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_2_/D 5 @@ -3861,224 +3849,236 @@ set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_7_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 5 set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index b5e84a4e8..2a3f42473 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,58 +6,6 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -84,6 +32,62 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q @@ -102,6 +106,10 @@ set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q @@ -110,24 +118,14 @@ set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -136,6 +134,8 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit index 3575fa16e..5336e6ed6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -339,13 +339,13 @@ 0 0 0 +1 0 0 0 0 0 -0 -0 +1 0 0 0 @@ -357,11 +357,13 @@ 0 0 0 +1 +0 0 0 -1 0 0 +1 0 0 0 @@ -375,21 +377,21 @@ 0 1 0 -1 -0 0 0 0 0 +1 0 0 -1 0 0 0 +1 0 0 0 +1 0 1 0 @@ -397,7 +399,7 @@ 0 0 0 -1 +0 0 1 0 @@ -407,7 +409,7 @@ 0 0 0 -1 +0 0 0 0 @@ -421,7 +423,7 @@ 0 0 0 -1 +0 0 1 0 @@ -429,10 +431,14 @@ 0 0 0 +1 +0 0 0 1 0 +1 +0 0 0 0 @@ -445,7 +451,7 @@ 0 0 0 -1 +0 0 1 0 @@ -827,19 +833,19 @@ 0 0 0 +1 0 0 0 0 0 +1 0 0 0 0 0 -0 -0 -0 +1 0 0 0 @@ -863,11 +869,11 @@ 0 0 0 -1 -0 0 0 +1 0 +1 0 1 0 @@ -877,7 +883,6 @@ 0 0 0 -1 0 0 0 @@ -885,15 +890,15 @@ 0 0 0 -1 0 0 0 +1 +1 0 0 0 0 -1 0 0 0 @@ -904,16 +909,11 @@ 0 0 0 -1 -1 0 0 0 0 0 -1 -0 -1 0 0 0 @@ -1297,26 +1297,20 @@ 0 0 0 -1 -0 0 0 0 0 -1 0 0 0 0 0 -1 0 0 0 0 0 -1 -0 0 0 0 @@ -1345,6 +1339,7 @@ 0 0 0 +1 0 0 0 @@ -1352,6 +1347,7 @@ 0 0 0 +1 0 0 0 @@ -1359,6 +1355,7 @@ 0 0 0 +1 0 0 0 @@ -1366,13 +1363,7 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 +1 0 0 0 @@ -1390,10 +1381,9 @@ 0 0 0 +1 0 -0 -0 -0 +1 0 0 0 @@ -1735,25 +1725,21 @@ 0 0 0 -1 0 0 0 0 0 -1 0 0 0 0 0 -1 -0 0 0 +1 0 0 -1 0 0 0 @@ -1765,6 +1751,8 @@ 0 0 0 +0 +0 1 0 0 @@ -1773,15 +1761,15 @@ 0 1 0 +1 0 0 0 0 -1 -0 0 0 0 +1 0 0 0 @@ -1789,11 +1777,13 @@ 0 0 0 +1 0 0 0 0 0 +1 0 1 0 @@ -1811,13 +1801,13 @@ 0 0 0 -1 -0 0 0 +1 0 0 0 +1 0 1 0 @@ -1841,15 +1831,23 @@ 0 0 0 +1 0 +1 +1 +1 +1 +1 +1 +1 +1 +1 0 0 0 0 0 -0 -0 -0 +1 0 0 0 @@ -1868,14 +1866,6 @@ 0 0 1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 @@ -1909,7 +1899,7 @@ 0 0 0 -0 +1 0 1 0 @@ -1917,13 +1907,12 @@ 0 0 0 -1 0 0 +1 0 0 0 -1 0 0 0 @@ -1934,16 +1923,19 @@ 0 0 0 +1 0 0 0 0 0 +1 0 0 0 0 0 +1 0 0 0 @@ -1951,13 +1943,19 @@ 0 0 0 +1 0 0 +1 +0 0 +1 0 0 +1 0 0 +1 0 0 0 @@ -2027,13 +2025,10 @@ 0 0 0 -1 0 0 0 -1 0 -1 0 0 0 @@ -2041,7 +2036,6 @@ 0 0 0 -1 0 0 0 @@ -2055,12 +2049,54 @@ 0 0 0 -1 0 0 0 0 0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 1 0 0 @@ -2073,31 +2109,41 @@ 0 0 0 +1 +0 0 0 -1 0 0 1 0 0 -1 +0 0 0 1 0 0 +0 +0 +0 1 0 0 0 0 0 +1 0 0 0 0 0 +1 +0 +0 +0 +0 0 0 0 @@ -2127,38 +2173,38 @@ 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 0 -1 0 0 0 0 0 1 +1 0 0 0 0 0 -1 0 0 0 0 0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 1 0 0 @@ -2187,7 +2233,7 @@ 0 0 0 -1 +0 0 1 0 @@ -2195,6 +2241,10 @@ 0 0 0 +1 +0 +0 +0 0 0 1 @@ -2221,17 +2271,15 @@ 0 0 0 -1 0 0 +1 0 0 0 -1 0 0 0 -1 0 1 0 @@ -2250,38 +2298,28 @@ 0 0 1 -1 -1 -1 -1 -1 0 -1 -1 0 0 0 0 0 -1 0 +1 0 0 0 0 -1 0 0 0 0 0 -1 0 0 0 0 0 -1 0 0 0 @@ -2293,13 +2331,9 @@ 0 0 0 -0 -0 1 0 -1 0 -1 0 0 0 @@ -2317,8 +2351,6 @@ 0 0 0 -1 -1 0 0 0 @@ -2341,35 +2373,3 @@ 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml index a2bf18b06..09c3c7723 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -682,1161 +682,1161 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + 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- + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v index 0ca441363..cf224f409 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v @@ -359,7 +359,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__2__0_ccff_tail), + .ccff_head(grid_io_top_1_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -382,7 +382,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__2__1_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -451,7 +451,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_1_ccff_tail), + .ccff_head(cbx_1__0__1_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -474,7 +474,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -684,7 +684,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_1_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:9]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:9]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -715,7 +715,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__2__0_ccff_tail), + .ccff_head(grid_io_left_1_ccff_tail), .chany_top_out(sb_0__1__0_chany_top_out[0:9]), .chanx_right_out(sb_0__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:9]), @@ -781,7 +781,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:9]), .chanx_right_out(sb_1__0__0_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:9]), @@ -810,7 +810,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_5_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_6_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_7_), - .ccff_head(grid_clb_3_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_top_out(sb_1__1__0_chany_top_out[0:9]), .chanx_right_out(sb_1__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:9]), @@ -843,7 +843,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_top_1_ccff_tail), + .ccff_head(grid_clb_3_ccff_tail), .chanx_right_out(sb_1__2__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:9]), .chanx_left_out(sb_1__2__0_chanx_left_out[0:9]), @@ -878,7 +878,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_0_ccff_tail), + .ccff_head(grid_io_bottom_1_ccff_tail), .chany_top_out(sb_2__0__0_chany_top_out[0:9]), .chanx_left_out(sb_2__0__0_chanx_left_out[0:9]), .ccff_tail(sb_2__0__0_ccff_tail)); @@ -917,7 +917,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_5_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_6_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_7_), - .ccff_head(grid_clb_2_ccff_tail), + .ccff_head(grid_clb_0_ccff_tail), .chany_top_out(sb_2__1__0_chany_top_out[0:9]), .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:9]), .chanx_left_out(sb_2__1__0_chanx_left_out[0:9]), @@ -948,7 +948,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_5__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_clb_2_ccff_tail), .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:9]), .chanx_left_out(sb_2__2__0_chanx_left_out[0:9]), .ccff_tail(sb_2__2__0_ccff_tail)); @@ -1074,7 +1074,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:9]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1093,7 +1093,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__0_chany_top_out[0:9]), .chany_top_in(sb_0__2__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(sb_0__2__0_ccff_tail), .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_0__1__1_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1112,7 +1112,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:9]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1129,7 +1129,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__0_chany_top_out[0:9]), .chany_top_in(sb_1__2__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(cbx_1__2__0_ccff_tail), .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_1__1__1_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1146,7 +1146,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_2__0__0_chany_top_out[0:9]), .chany_top_in(sb_2__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__1_ccff_tail), + .ccff_head(cbx_1__1__1_ccff_tail), .chany_bottom_out(cby_2__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_2__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_2__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -1170,7 +1170,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_2__1__0_chany_top_out[0:9]), .chany_top_in(sb_2__2__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__1_ccff_tail), + .ccff_head(cbx_1__2__1_ccff_tail), .chany_bottom_out(cby_2__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_2__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_2__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index 8e3ce2cdb..58b265d13 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml index 598b91e22..15a476439 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index 4742a8f45..9fc5a8117 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml index d96c9a38d..405c9abaf 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml index 853598113..d3421c3bc 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml index a5aff3785..586a15615 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 3afea90e8..d09d7c254 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml index 3a9b8024d..6b47a0491 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index 2e584b8ab..6acef668f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml index f3b69185d..106e8f2bb 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml index 6561ddb64..c3c93bfa1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml index 5d742ce89..b99a0f7f3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + From f42884304aff1d0d05dd692cc1f0ba7617ab99aa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 11:40:41 -0700 Subject: [PATCH 196/230] [doc] update clock network details --- docs/source/manual/file_formats/clock_network.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index 8bab91b43..60cd10eff 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -187,6 +187,8 @@ Switch Point Settings The following syntax are applicable to the XML definition tagged by ``switch_point``. Note that a number of switch points can be defined under each clock spine ``spine``. +.. note:: Use the coordinate of switch block to define switching points! + .. option:: tap="" Define which clock spine will be tapped from the current clock spine. @@ -307,6 +309,8 @@ For example, where all the clock spines of the clock network ``clk_tree_0`` tap the clock pins ``clk`` of tile ``clb`` in a VPR architecture description file: +.. note:: Use the name of ``subtile`` in the ``to_pin`` when there are a number of subtiles in your tile! + .. code-block:: xml From f0e168c2b35cc4925448595648df376add97cb50 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 9 Jul 2024 21:54:39 +0000 Subject: [PATCH 197/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 2e87e34ef..5b5fa0de1 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2386 +1.2.2480 From 38bb5aa9063fe7a89240f910844c9946a0371950 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 18:42:39 -0700 Subject: [PATCH 198/230] [test] add a new benchmark to validate clock on LUT --- .../micro_benchmark/clk_on_lut/clk_on_lut.v | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v b/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v new file mode 100644 index 000000000..80814e49b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v @@ -0,0 +1,21 @@ +///////////////////////////////////////// +// Functionality: A register driven by a combinational logic with clk signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module clk_on_lut(a, b, q, out, clk); + +input wire clk; +input wire a; +input wire b; +output reg q; +output wire out; + +always @(posedge clk) begin + q <= a; +end + +assign out = b & clk; + +endmodule From 89e6a0483f453f8fc5b8a1b46e555f78da7a7ebd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 18:45:33 -0700 Subject: [PATCH 199/230] [test] add a new benchmark to validate rst and clk on LUTs --- .../rst_and_clk_on_lut/rst_and_clk_on_lut.v | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v b/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v new file mode 100644 index 000000000..12234984e --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v @@ -0,0 +1,29 @@ +///////////////////////////////////////// +// Functionality: A register driven by a combinational logic with reset signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module rst_on_lut(a, b, c, q, out0, out1, clk, rst); + +input wire rst; +input wire clk; +input wire a; +input wire b; +input wire c; +output reg q; +output wire out0; +output wire out1; + +always @(posedge rst or posedge clk) begin + if (rst) begin + q <= 0; + end else begin + q <= a; + end +end + +assign out0 = b & ~rst; +assign out1 = c & ~clk; + +endmodule From e5d146a67a1949f0b6d54ee2369f236f2cae13e6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 20:24:23 -0700 Subject: [PATCH 200/230] [test] add new tests to validate rst on lut and clk on lut features --- .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/clk_arch_1clk_1rst_2layer.xml | 34 +++++++++++ .../config/pin_constraints_clk.xml | 8 +++ .../config/pin_constraints_rst.xml | 8 +++ .../config/pin_constraints_rst_and_clk.xml | 8 +++ .../config/repack_pin_constraints.xml | 4 ++ .../config/task.conf | 56 +++++++++++++++++++ 7 files changed, 119 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/clk_arch_1clk_1rst_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_clk.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst_and_clk.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 0f3abd81d..85e0d9bfd 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -240,6 +240,7 @@ run-task basic_tests/clock_network/homo_2clock_2layer $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..b91512914 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_clk.xml new file mode 100644 index 000000000..f0b871511 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml new file mode 100644 index 000000000..28ab471d5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst_and_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst_and_clk.xml new file mode 100644 index 000000000..15df5148e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst_and_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf new file mode 100644 index 000000000..2c2c2c4f6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf @@ -0,0 +1,56 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = rst_on_lut +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst.xml + +bench1_top = clk_on_lut +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml + +bench1_top = rst_and_clk_on_lut +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 9ce4b57363c836ff84163a35a3d28e25d3e2cee2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 20:25:39 -0700 Subject: [PATCH 201/230] [test] typo --- .../homo_1clock_1reset_2layer_on_lut/config/task.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf index 2c2c2c4f6..d01dfd35a 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf @@ -48,8 +48,8 @@ bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_r bench1_top = clk_on_lut bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml -bench1_top = rst_and_clk_on_lut -bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml +bench2_top = rst_and_clk_on_lut +bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From 43dbeafd4447c888f24cd16d075ea894d2a53913 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 20:27:28 -0700 Subject: [PATCH 202/230] [test] typo --- .../config/pin_constraints_rst.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml index 28ab471d5..15df5148e 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml @@ -3,6 +3,6 @@ - the reset signal to the op_reset[0] port of the FPGA fabric --> - + From 0f7880375948814772e9cc36e53966e6993286cd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 20:47:15 -0700 Subject: [PATCH 203/230] [core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs --- libs/libclkarchopenfpga/src/base/clock_network.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index bd02259b7..04dd1fab4 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -514,9 +514,6 @@ std::vector ClockNetwork::tree_flatten_tap_to_ports( std::string flatten_tile_str = tile_info.get_name() + "[" + std::to_string(tile_idx) + "]"; for (size_t& pin_idx : pin_info.pins()) { - if (pin_idx != size_t(clk_pin_id)) { - continue; - } std::string flatten_pin_str = pin_info.get_name() + "[" + std::to_string(pin_idx) + "]"; flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str); From a16b3df063fc13784ea347b0340f23ebd468de78 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 20:59:44 -0700 Subject: [PATCH 204/230] [test] update arch to allow clock access on CLB inputs --- openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index 013466e5c..b87a12a76 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -107,11 +107,12 @@ + - clb.reset clb.clk clb.O[4:7] clb.I[6:11] - clb.O[0:3] clb.I[0:5] + clb.reset clb.clk clb.O[0:3] clb.I[0:5] + clb.O[4:7] clb.I[6:11] From 27e29f949cda120271585be30480248930c3fc33 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 22:53:12 -0700 Subject: [PATCH 205/230] [core] fixed a bug where the pin idx of global net on rr graph is not well annotated --- .../annotation/openfpga_annotate_routing.cpp | 32 +++++++++++++++++-- .../annotation/openfpga_annotate_routing.h | 5 ++- .../src/annotation/route_clock_rr_graph.cpp | 3 +- .../src/annotation/route_clock_rr_graph.h | 2 ++ .../src/base/openfpga_link_arch_template.h | 4 ++- 5 files changed, 41 insertions(+), 5 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index cfbb064ef..5c018e93e 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -21,7 +21,9 @@ namespace openfpga { *******************************************************************/ vtr::vector annotate_rr_node_global_net( const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, - const PlacementContext& placement_ctx, const bool& verbose) { + const PlacementContext& placement_ctx, + const VprClusteringAnnotation& clustering_annotation, + const bool& verbose) { vtr::vector rr_node_nets; size_t counter = 0; @@ -42,10 +44,36 @@ vtr::vector annotate_rr_node_global_net( ClusterBlockId block_id = cluster_nlist.pin_block(pin_id); t_block_loc blk_loc = get_block_loc(block_id, false); int phy_pin = placement_ctx.physical_pins[pin_id]; + t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type(t_physical_tile_loc(blk_loc.loc.x, blk_loc.loc.y, 0)); + int node_pin_num = phy_tile->num_pins; + /* Note that the phy_pin may not reflect the actual pin index at the top-level physical tile type. It could be one of the random pin to the same pin class. So here, we have to find an exact match of the pin index from the clustering results! */ + int subtile_idx = blk_loc.loc.sub_tile; + auto logical_block = cluster_nlist.block_type(block_id); + for (int j = 0; j < logical_block->pb_type->num_pins; j++) { + /* Find the net mapped to this pin in clustering results*/ + ClusterNetId cluster_net_id = + cluster_nlist.block_net(block_id, j); + /* Get the actual net id because it may be renamed during routing */ + if (true == clustering_annotation.is_net_renamed(block_id, j)) { + cluster_net_id = clustering_annotation.net(block_id, j); + } + /* Bypass unmatched pins */ + if (cluster_net_id != net_id) { + continue; + } + int curr_pin_num = get_physical_pin_at_sub_tile_location(phy_tile, logical_block, subtile_idx, j); + if (phy_tile->pin_class[curr_pin_num] != phy_tile->pin_class[phy_pin]) { + continue; + } + node_pin_num = curr_pin_num; + break; + } + VTR_ASSERT(node_pin_num < phy_tile->num_pins); std::vector curr_rr_nodes = rr_graph.node_lookup().find_nodes_at_all_sides( - layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin); + layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, node_pin_num); for (RRNodeId curr_rr_node : curr_rr_nodes) { + VTR_LOGV(verbose, "Annotate global net '%s' on '%s' pin '%d'\n", cluster_nlist.net_name(net_id).c_str(), phy_tile->name, node_pin_num); rr_node_nets[curr_rr_node] = net_id; counter++; } diff --git a/openfpga/src/annotation/openfpga_annotate_routing.h b/openfpga/src/annotation/openfpga_annotate_routing.h index dc5d28db3..332a74343 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.h +++ b/openfpga/src/annotation/openfpga_annotate_routing.h @@ -6,6 +6,7 @@ *******************************************************************/ #include "openfpga_context.h" #include "vpr_context.h" +#include "vpr_clustering_annotation.h" #include "vpr_routing_annotation.h" /******************************************************************** @@ -17,7 +18,9 @@ namespace openfpga { vtr::vector annotate_rr_node_global_net( const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, - const PlacementContext& placement_ctx, const bool& verbose); + const PlacementContext& placement_ctx, + const VprClusteringAnnotation& clustering_annotation, + const bool& verbose); void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 207b83d0e..bb252d6e2 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -472,6 +472,7 @@ static int route_clock_tree_rr_graph( *******************************************************************/ int route_clock_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, + const VprClusteringAnnotation& vpr_clustering_annotation, const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, @@ -509,7 +510,7 @@ int route_clock_rr_graph( /* Build rr_node-to-net mapping for global nets */ vtr::vector rr_node_gnets = - annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, + annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, vpr_clustering_annotation, verbose); /* Route spines one by one */ diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index 2bd4ec178..dfd856e76 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -9,6 +9,7 @@ #include "rr_clock_spatial_lookup.h" #include "vpr_context.h" #include "vpr_routing_annotation.h" +#include "vpr_clustering_annotation.h" /******************************************************************** * Function declaration @@ -19,6 +20,7 @@ namespace openfpga { int route_clock_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, + const VprClusteringAnnotation& vpr_clustering_annotation, const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index bb061de09..41098c013 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -232,7 +232,9 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, } return route_clock_rr_graph( - openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), + openfpga_ctx.mutable_vpr_routing_annotation(), + openfpga_ctx.vpr_clustering_annotation(), + g_vpr_ctx.device(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, cmd_context.option_enable(cmd, opt_disable_unused_trees), From 63f2a07c865268ecf537e7bdb1e5d555ab34bc7b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 22:54:33 -0700 Subject: [PATCH 206/230] [test] typo --- .../micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v b/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v index 12234984e..598d41dcf 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v @@ -4,7 +4,7 @@ //////////////////////////////////////// `timescale 1ns / 1ps -module rst_on_lut(a, b, c, q, out0, out1, clk, rst); +module rst_and_clk_on_lut(a, b, c, q, out0, out1, clk, rst); input wire rst; input wire clk; From 96bdcc8b35ae325062a0e9be2b184044c2c6d183 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 22:54:55 -0700 Subject: [PATCH 207/230] [core] code format --- .../annotation/openfpga_annotate_routing.cpp | 29 +++++++++++-------- .../annotation/openfpga_annotate_routing.h | 5 ++-- .../src/annotation/route_clock_rr_graph.cpp | 4 +-- .../src/annotation/route_clock_rr_graph.h | 2 +- .../src/base/openfpga_link_arch_template.h | 3 +- 5 files changed, 23 insertions(+), 20 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 5c018e93e..64854e8df 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -22,8 +22,7 @@ namespace openfpga { vtr::vector annotate_rr_node_global_net( const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, const PlacementContext& placement_ctx, - const VprClusteringAnnotation& clustering_annotation, - const bool& verbose) { + const VprClusteringAnnotation& clustering_annotation, const bool& verbose) { vtr::vector rr_node_nets; size_t counter = 0; @@ -44,15 +43,18 @@ vtr::vector annotate_rr_node_global_net( ClusterBlockId block_id = cluster_nlist.pin_block(pin_id); t_block_loc blk_loc = get_block_loc(block_id, false); int phy_pin = placement_ctx.physical_pins[pin_id]; - t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type(t_physical_tile_loc(blk_loc.loc.x, blk_loc.loc.y, 0)); + t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type( + t_physical_tile_loc(blk_loc.loc.x, blk_loc.loc.y, 0)); int node_pin_num = phy_tile->num_pins; - /* Note that the phy_pin may not reflect the actual pin index at the top-level physical tile type. It could be one of the random pin to the same pin class. So here, we have to find an exact match of the pin index from the clustering results! */ - int subtile_idx = blk_loc.loc.sub_tile; + /* Note that the phy_pin may not reflect the actual pin index at the + * top-level physical tile type. It could be one of the random pin to the + * same pin class. So here, we have to find an exact match of the pin + * index from the clustering results! */ + int subtile_idx = blk_loc.loc.sub_tile; auto logical_block = cluster_nlist.block_type(block_id); for (int j = 0; j < logical_block->pb_type->num_pins; j++) { /* Find the net mapped to this pin in clustering results*/ - ClusterNetId cluster_net_id = - cluster_nlist.block_net(block_id, j); + ClusterNetId cluster_net_id = cluster_nlist.block_net(block_id, j); /* Get the actual net id because it may be renamed during routing */ if (true == clustering_annotation.is_net_renamed(block_id, j)) { cluster_net_id = clustering_annotation.net(block_id, j); @@ -60,20 +62,23 @@ vtr::vector annotate_rr_node_global_net( /* Bypass unmatched pins */ if (cluster_net_id != net_id) { continue; - } - int curr_pin_num = get_physical_pin_at_sub_tile_location(phy_tile, logical_block, subtile_idx, j); + } + int curr_pin_num = get_physical_pin_at_sub_tile_location( + phy_tile, logical_block, subtile_idx, j); if (phy_tile->pin_class[curr_pin_num] != phy_tile->pin_class[phy_pin]) { continue; } node_pin_num = curr_pin_num; - break; + break; } - VTR_ASSERT(node_pin_num < phy_tile->num_pins); + VTR_ASSERT(node_pin_num < phy_tile->num_pins); std::vector curr_rr_nodes = rr_graph.node_lookup().find_nodes_at_all_sides( layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, node_pin_num); for (RRNodeId curr_rr_node : curr_rr_nodes) { - VTR_LOGV(verbose, "Annotate global net '%s' on '%s' pin '%d'\n", cluster_nlist.net_name(net_id).c_str(), phy_tile->name, node_pin_num); + VTR_LOGV(verbose, "Annotate global net '%s' on '%s' pin '%d'\n", + cluster_nlist.net_name(net_id).c_str(), phy_tile->name, + node_pin_num); rr_node_nets[curr_rr_node] = net_id; counter++; } diff --git a/openfpga/src/annotation/openfpga_annotate_routing.h b/openfpga/src/annotation/openfpga_annotate_routing.h index 332a74343..8c9f0e40a 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.h +++ b/openfpga/src/annotation/openfpga_annotate_routing.h @@ -5,8 +5,8 @@ * Include header files that are required by function declaration *******************************************************************/ #include "openfpga_context.h" -#include "vpr_context.h" #include "vpr_clustering_annotation.h" +#include "vpr_context.h" #include "vpr_routing_annotation.h" /******************************************************************** @@ -19,8 +19,7 @@ namespace openfpga { vtr::vector annotate_rr_node_global_net( const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, const PlacementContext& placement_ctx, - const VprClusteringAnnotation& clustering_annotation, - const bool& verbose); + const VprClusteringAnnotation& clustering_annotation, const bool& verbose); void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index bb252d6e2..a0e57bda5 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -510,8 +510,8 @@ int route_clock_rr_graph( /* Build rr_node-to-net mapping for global nets */ vtr::vector rr_node_gnets = - annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, vpr_clustering_annotation, - verbose); + annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, + vpr_clustering_annotation, verbose); /* Route spines one by one */ for (auto itree : clk_ntwk.trees()) { diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index dfd856e76..1c37bc8b6 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -7,9 +7,9 @@ #include "clock_network.h" #include "pin_constraints.h" #include "rr_clock_spatial_lookup.h" +#include "vpr_clustering_annotation.h" #include "vpr_context.h" #include "vpr_routing_annotation.h" -#include "vpr_clustering_annotation.h" /******************************************************************** * Function declaration diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index 41098c013..9898d5f75 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -233,8 +233,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, return route_clock_rr_graph( openfpga_ctx.mutable_vpr_routing_annotation(), - openfpga_ctx.vpr_clustering_annotation(), - g_vpr_ctx.device(), + openfpga_ctx.vpr_clustering_annotation(), g_vpr_ctx.device(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, cmd_context.option_enable(cmd, opt_disable_unused_trees), From 66a77c8658a9d8a775f013dd2ef39bc91fcc5d9e Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Wed, 10 Jul 2024 06:25:00 +0000 Subject: [PATCH 208/230] Bump yosys from `dac5bd1` to `b08688f` Bumps [yosys](https://github.com/YosysHQ/yosys) from `dac5bd1` to `b08688f`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/dac5bd1983a5078e3e7426df1e8ee48d300ead7d...b08688f71197316cd44859b8ced16136cf1b3957) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index dac5bd198..b08688f71 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit dac5bd1983a5078e3e7426df1e8ee48d300ead7d +Subproject commit b08688f71197316cd44859b8ced16136cf1b3957 From 81fe722d9873b9133f2770c6140dca829bf2fe1b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 23:49:01 -0700 Subject: [PATCH 209/230] [test] adjust W --- .../clock_network/homo_1clock_1reset_2layer/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf index 04489c15e..706b9b771 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_route_chan_width=60 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= From 191a3d1c5efd375a4f75ff46be775345de42cb85 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 10:01:31 -0700 Subject: [PATCH 210/230] [test] update W --- .../config/task.conf | 2 +- .../homo_1clock_1reset_2layer_internal_driver/config/task.conf | 2 +- .../homo_1clock_1reset_2layer_syntax/config/task.conf | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf index f0fe1b077..ba2b9b5e5 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_route_chan_width=60 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options=--disable_unused_spines diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf index 70565880f..05ed91de3 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_route_chan_width=60 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf index 04489c15e..706b9b771 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_route_chan_width=60 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= From 77304164f42ea464576278a1a985657914d80f44 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 10:13:41 -0700 Subject: [PATCH 211/230] [test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W --- .../homo_1clock_1reset_2layer/config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 14 ++++---------- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 4 ++-- 6 files changed, 10 insertions(+), 16 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf index 706b9b771..554a53d64 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf index ba2b9b5e5..622f0328e 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options=--disable_unused_spines diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf index 05ed91de3..038156d09 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= @@ -30,8 +30,7 @@ openfpga_route_clock_options= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v [SYNTHESIS_PARAM] # Yosys script parameters @@ -41,13 +40,8 @@ bench_read_verilog_options_common = -nolatches bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys -bench0_top = counter -bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml -bench0_openfpga_verilog_testbench_port_mapping= - -bench1_top = counter -bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml -bench1_openfpga_verilog_testbench_port_mapping= +bench0_top = clk_gate +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_gate.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf index d01dfd35a..a3d9b1a48 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf index 706b9b771..554a53d64 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index b87a12a76..b105149b1 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -110,9 +110,9 @@ - + clb.reset clb.clk clb.O[0:3] clb.I[0:5] - clb.O[4:7] clb.I[6:11] + clb.O[4:7] clb.I[6:11] From dbe8e63f53c530f82ac08ff3fb9159630aa6a3a2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 10:15:47 -0700 Subject: [PATCH 212/230] [test] remove unused files --- .../config/clk_arch_1clk_1rst_2layer_int_driver.xml | 1 + ...constraints_reset.xml => pin_constraints_clk_gate.xml} | 4 ++-- .../config/pin_constraints_resetb.xml | 8 -------- 3 files changed, 3 insertions(+), 10 deletions(-) rename openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/{pin_constraints_reset.xml => pin_constraints_clk_gate.xml} (66%) delete mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml index c88e8ccd4..a5707c9f5 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml @@ -20,6 +20,7 @@ + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_gate.xml similarity index 66% rename from openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml rename to openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_gate.xml index 3788a1411..cdcee36c2 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_gate.xml @@ -2,7 +2,7 @@ - - + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml deleted file mode 100644 index 1311926f5..000000000 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - From b6ff69faacb29fafe82294cb7dd7b458cec79a8c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 11:36:22 -0700 Subject: [PATCH 213/230] [test] reworking the testcase to validate clock network with internal drivers --- .../micro_benchmark/clk_cond/clk_cond.v | 21 +++++ ..._clkntwk_int_driver_no_ace_script.openfpga | 76 +++++++++++++++++++ .../clk_arch_1clk_1rst_2layer_int_driver.xml | 3 +- ..._gate.xml => pin_constraints_clk_cond.xml} | 3 +- .../config/task.conf | 10 ++- .../config/vpr_constraint_clk_cond.xml | 12 +++ 6 files changed, 119 insertions(+), 6 deletions(-) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v create mode 100644 openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga rename openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/{pin_constraints_clk_gate.xml => pin_constraints_clk_cond.xml} (71%) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_clk_cond.xml diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v b/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v new file mode 100644 index 000000000..d939c7ab3 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v @@ -0,0 +1,21 @@ +///////////////////////////////////////// +// Functionality: A locally generated clock signal which is to test clock network with internal drivers +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module clk_cond(clk_i, clk_cond_i, d_i, q_o); + +input wire clk_cond_i; +input wire clk_i; +input wire d_i; +output reg q_o; + +wire int_clk; +assign int_clk = clk_cond_i & clk_i; + +always @(posedge int_clk) begin + q_o <= d_i; +end + +endmodule diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga new file mode 100644 index 000000000..489162d11 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \ + --clock_modeling ideal \ + --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \ + --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} \ + --read_vpr_constraints ${OPENFPGA_VPR_CONSTRAINT_FILE} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Read OpenFPGA clock architecture +read_openfpga_clock_arch -f ${OPENFPGA_CLOCK_ARCH_FILE} + +# Append clock network to vpr's routing resource graph +append_clock_rr_graph + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Route clock based on clock network definition +route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack --design_constraints ${OPENFPGA_REPACK_CONSTRAINTS_FILE} #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml index a5707c9f5..38bc90f9d 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml @@ -1,5 +1,5 @@ - + @@ -21,6 +21,7 @@ + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_gate.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_cond.xml similarity index 71% rename from openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_gate.xml rename to openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_cond.xml index cdcee36c2..903c4bfac 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_gate.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_cond.xml @@ -2,7 +2,8 @@ - + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf index 038156d09..65b15b8bd 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 3*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml @@ -25,12 +25,13 @@ openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= +openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v [SYNTHESIS_PARAM] # Yosys script parameters @@ -40,8 +41,9 @@ bench_read_verilog_options_common = -nolatches bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys -bench0_top = clk_gate -bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_gate.xml +bench0_top = clk_cond +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_cond.xml +bench0_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_clk_cond.xml new file mode 100644 index 000000000..f9b30b022 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_clk_cond.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + From c6dd33a965a3a0d3856ccf22285fbbd434ca05c7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 11:59:25 -0700 Subject: [PATCH 214/230] [core] fixed a bug when annotating global nets on OPIN --- .../src/annotation/openfpga_annotate_routing.cpp | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 64854e8df..75da0fe8f 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -72,11 +72,22 @@ vtr::vector annotate_rr_node_global_net( break; } VTR_ASSERT(node_pin_num < phy_tile->num_pins); + t_rr_type rr_pin_type = IPIN; + if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == RECEIVER) { + rr_pin_type = IPIN; + } else if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == DRIVER) { + rr_pin_type = OPIN; + } else { + VTR_LOG_ERROR("When annotating global net '%s', invalid rr node pin type for '%s' pin '%d'\n", + cluster_nlist.net_name(net_id).c_str(), phy_tile->name, + node_pin_num); + exit(1); + } std::vector curr_rr_nodes = rr_graph.node_lookup().find_nodes_at_all_sides( - layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, node_pin_num); + layer, blk_loc.loc.x, blk_loc.loc.y, rr_pin_type, node_pin_num); for (RRNodeId curr_rr_node : curr_rr_nodes) { - VTR_LOGV(verbose, "Annotate global net '%s' on '%s' pin '%d'\n", + VTR_LOGV(verbose, "on '%s' pin '%d'\n", cluster_nlist.net_name(net_id).c_str(), phy_tile->name, node_pin_num); rr_node_nets[curr_rr_node] = net_id; From 48e159dd8d1f379aabb99c87301801fbec862b79 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 12:23:15 -0700 Subject: [PATCH 215/230] [core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches --- .../verilog_preconfig_top_module.cpp | 4 +++- .../verilog_preconfig_top_module_utils.cpp | 16 +++++++++++++++- .../verilog_preconfig_top_module_utils.h | 2 ++ .../verilog_testbench_io_connection.cpp | 2 +- 4 files changed, 21 insertions(+), 3 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 5c1c703e2..8e4a14170 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -65,6 +65,8 @@ static void print_verilog_preconfig_top_module_ports( /* The block may be renamed as it contains special characters which violate * Verilog syntax */ if (true == netlist_annotation.is_block_renamed(atom_blk)) { + VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", block_name.c_str(), + netlist_annotation.block_name(atom_blk).c_str()); block_name = netlist_annotation.block_name(atom_blk); } /* For output block, remove the prefix which is added by VPR */ @@ -445,7 +447,7 @@ int print_verilog_preconfig_top_module( /* Connect FPGA top module global ports to constant or benchmark global * signals! */ status = print_verilog_preconfig_top_module_connect_global_ports( - fp, module_manager, core_module, pin_constraints, global_ports, + fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports, benchmark_clock_port_names, std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX)); if (CMD_EXEC_FATAL_ERROR == status) { diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp index 944506c89..2649c2c64 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp @@ -57,6 +57,8 @@ void print_verilog_preconfig_top_module_internal_wires( int print_verilog_preconfig_top_module_connect_global_ports( std::fstream &fp, const ModuleManager &module_manager, const ModuleId &top_module, const PinConstraints &pin_constraints, + const AtomContext& atom_ctx, + const VprNetlistAnnotation &netlist_annotation, const FabricGlobalPortInfo &fabric_global_ports, const std::vector &benchmark_clock_port_names, const std::string &port_postfix) { @@ -121,7 +123,19 @@ int print_verilog_preconfig_top_module_connect_global_ports( } clock_name_to_connect = benchmark_clock_port_names[pin_id]; } - + /* The clock name must be a valid primary input. Otherwise, it could be a signal generated by internal logics, e.g., clb */ + AtomBlockId atom_blk = atom_ctx.nlist.find_block(clock_name_to_connect); + if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))) { + VTR_LOG("Global net '%s' is not a primary input of the netlist (which could a signal generated by internal logic). Will not wire it to any FPGA primary input pin\n", clock_name_to_connect.c_str()); + continue; + } + /* The block may be renamed as it contains special characters which violate + * Verilog syntax */ + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", clock_name_to_connect.c_str(), + netlist_annotation.block_name(atom_blk).c_str()); + clock_name_to_connect = netlist_annotation.block_name(atom_blk); + } BasicPort benchmark_clock_pin(clock_name_to_connect, 1); print_verilog_wire_connection(fp, module_clock_pin, benchmark_clock_pin, false); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h index 55c85eadd..a0eb1616f 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h @@ -35,6 +35,8 @@ void print_verilog_preconfig_top_module_internal_wires( int print_verilog_preconfig_top_module_connect_global_ports( std::fstream &fp, const ModuleManager &module_manager, const ModuleId &top_module, const PinConstraints &pin_constraints, + const AtomContext& atom_ctx, + const VprNetlistAnnotation &netlist_annotation, const FabricGlobalPortInfo &fabric_global_ports, const std::vector &benchmark_clock_port_names, const std::string &port_postfix); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp b/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp index 30018e400..41ce502c8 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp @@ -90,7 +90,7 @@ int print_verilog_testbench_io_connection( /* Connect FPGA top module global ports to constant or benchmark global * signals! */ status = print_verilog_preconfig_top_module_connect_global_ports( - fp, module_manager, core_module, pin_constraints, global_ports, + fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports, benchmark_clock_port_names, std::string()); if (CMD_EXEC_FATAL_ERROR == status) { return status; From 213914e4ac040658f1b59aa4a0f99325782d93f9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 12:23:57 -0700 Subject: [PATCH 216/230] [core] code format --- .../annotation/openfpga_annotate_routing.cpp | 13 +++++++---- .../verilog_preconfig_top_module.cpp | 10 ++++---- .../verilog_preconfig_top_module_utils.cpp | 23 ++++++++++++------- .../verilog_preconfig_top_module_utils.h | 3 +-- .../verilog_testbench_io_connection.cpp | 5 ++-- 5 files changed, 33 insertions(+), 21 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 75da0fe8f..489c80986 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -73,14 +73,17 @@ vtr::vector annotate_rr_node_global_net( } VTR_ASSERT(node_pin_num < phy_tile->num_pins); t_rr_type rr_pin_type = IPIN; - if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == RECEIVER) { + if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == + RECEIVER) { rr_pin_type = IPIN; - } else if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == DRIVER) { + } else if (phy_tile->class_inf[phy_tile->pin_class[node_pin_num]].type == + DRIVER) { rr_pin_type = OPIN; } else { - VTR_LOG_ERROR("When annotating global net '%s', invalid rr node pin type for '%s' pin '%d'\n", - cluster_nlist.net_name(net_id).c_str(), phy_tile->name, - node_pin_num); + VTR_LOG_ERROR( + "When annotating global net '%s', invalid rr node pin type for '%s' " + "pin '%d'\n", + cluster_nlist.net_name(net_id).c_str(), phy_tile->name, node_pin_num); exit(1); } std::vector curr_rr_nodes = diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 8e4a14170..3e47c6a16 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -65,8 +65,10 @@ static void print_verilog_preconfig_top_module_ports( /* The block may be renamed as it contains special characters which violate * Verilog syntax */ if (true == netlist_annotation.is_block_renamed(atom_blk)) { - VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", block_name.c_str(), - netlist_annotation.block_name(atom_blk).c_str()); + VTR_LOG( + "Replace pin name '%s' with '%s' as it is renamed to comply verilog " + "syntax\n", + block_name.c_str(), netlist_annotation.block_name(atom_blk).c_str()); block_name = netlist_annotation.block_name(atom_blk); } /* For output block, remove the prefix which is added by VPR */ @@ -447,8 +449,8 @@ int print_verilog_preconfig_top_module( /* Connect FPGA top module global ports to constant or benchmark global * signals! */ status = print_verilog_preconfig_top_module_connect_global_ports( - fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports, - benchmark_clock_port_names, + fp, module_manager, core_module, pin_constraints, atom_ctx, + netlist_annotation, global_ports, benchmark_clock_port_names, std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX)); if (CMD_EXEC_FATAL_ERROR == status) { return status; diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp index 2649c2c64..bca7b6709 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp @@ -57,8 +57,7 @@ void print_verilog_preconfig_top_module_internal_wires( int print_verilog_preconfig_top_module_connect_global_ports( std::fstream &fp, const ModuleManager &module_manager, const ModuleId &top_module, const PinConstraints &pin_constraints, - const AtomContext& atom_ctx, - const VprNetlistAnnotation &netlist_annotation, + const AtomContext &atom_ctx, const VprNetlistAnnotation &netlist_annotation, const FabricGlobalPortInfo &fabric_global_ports, const std::vector &benchmark_clock_port_names, const std::string &port_postfix) { @@ -123,17 +122,25 @@ int print_verilog_preconfig_top_module_connect_global_ports( } clock_name_to_connect = benchmark_clock_port_names[pin_id]; } - /* The clock name must be a valid primary input. Otherwise, it could be a signal generated by internal logics, e.g., clb */ + /* The clock name must be a valid primary input. Otherwise, it could be + * a signal generated by internal logics, e.g., clb */ AtomBlockId atom_blk = atom_ctx.nlist.find_block(clock_name_to_connect); if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))) { - VTR_LOG("Global net '%s' is not a primary input of the netlist (which could a signal generated by internal logic). Will not wire it to any FPGA primary input pin\n", clock_name_to_connect.c_str()); + VTR_LOG( + "Global net '%s' is not a primary input of the netlist (which " + "could a signal generated by internal logic). Will not wire it to " + "any FPGA primary input pin\n", + clock_name_to_connect.c_str()); continue; } - /* The block may be renamed as it contains special characters which violate - * Verilog syntax */ + /* The block may be renamed as it contains special characters which + * violate Verilog syntax */ if (true == netlist_annotation.is_block_renamed(atom_blk)) { - VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", clock_name_to_connect.c_str(), - netlist_annotation.block_name(atom_blk).c_str()); + VTR_LOG( + "Replace pin name '%s' with '%s' as it is renamed to comply " + "verilog syntax\n", + clock_name_to_connect.c_str(), + netlist_annotation.block_name(atom_blk).c_str()); clock_name_to_connect = netlist_annotation.block_name(atom_blk); } BasicPort benchmark_clock_pin(clock_name_to_connect, 1); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h index a0eb1616f..20ae797e2 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h @@ -35,8 +35,7 @@ void print_verilog_preconfig_top_module_internal_wires( int print_verilog_preconfig_top_module_connect_global_ports( std::fstream &fp, const ModuleManager &module_manager, const ModuleId &top_module, const PinConstraints &pin_constraints, - const AtomContext& atom_ctx, - const VprNetlistAnnotation &netlist_annotation, + const AtomContext &atom_ctx, const VprNetlistAnnotation &netlist_annotation, const FabricGlobalPortInfo &fabric_global_ports, const std::vector &benchmark_clock_port_names, const std::string &port_postfix); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp b/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp index 41ce502c8..0f4978c60 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp @@ -90,8 +90,9 @@ int print_verilog_testbench_io_connection( /* Connect FPGA top module global ports to constant or benchmark global * signals! */ status = print_verilog_preconfig_top_module_connect_global_ports( - fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports, - benchmark_clock_port_names, std::string()); + fp, module_manager, core_module, pin_constraints, atom_ctx, + netlist_annotation, global_ports, benchmark_clock_port_names, + std::string()); if (CMD_EXEC_FATAL_ERROR == status) { return status; } From af996e563eaed5353be4ba79c4ab1a3600a54fab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 14:11:06 -0700 Subject: [PATCH 217/230] [test] add a new test to validate reset generated by internal driver through programmable clock network --- .../micro_benchmark/rst_cond/rst_cond.v | 26 ++++++++++++++ ..._arch_1clk_1rst_2layer_int_driver_clk.xml} | 0 ...k_arch_1clk_1rst_2layer_int_driver_rst.xml | 36 +++++++++++++++++++ .../config/pin_constraints_rst_cond.xml | 8 +++++ .../config/task.conf | 7 ++++ .../config/vpr_constraint_rst_cond.xml | 12 +++++++ 6 files changed, 89 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v rename openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/{clk_arch_1clk_1rst_2layer_int_driver.xml => clk_arch_1clk_1rst_2layer_int_driver_clk.xml} (100%) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_rst_cond.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_rst_cond.xml diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v b/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v new file mode 100644 index 000000000..196eca363 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v @@ -0,0 +1,26 @@ +///////////////////////////////////////// +// Functionality: A locally generated reset signal which is to test clock network with internal drivers +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module clk_cond(rst_i, rst_cond_i, clk_i, d_i, q_o); + +input wire rst_cond_i; +input wire rst_i; +input wire clk_i; +input wire d_i; +output reg q_o; + +wire int_rst; +assign int_rst = rst_cond_i & rst_i; + +always @(posedge int_rst or posedge clk_i) begin + if (int_rst) begin + q_o <= 0; + end else begin + q_o <= d_i; + end +end + +endmodule diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml similarity index 100% rename from openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml rename to openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml new file mode 100644 index 000000000..1266725de --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_rst_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_rst_cond.xml new file mode 100644 index 000000000..55e49733f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_rst_cond.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf index 65b15b8bd..a61220518 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -32,6 +32,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40 [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v [SYNTHESIS_PARAM] # Yosys script parameters @@ -44,6 +45,12 @@ bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosy bench0_top = clk_cond bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_cond.xml bench0_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml +bench0_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml + +bench1_top = rst_cond +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_cond.xml +bench1_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_rst_cond.xml +bench1_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_rst_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_rst_cond.xml new file mode 100644 index 000000000..3c6f27aef --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_rst_cond.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + From 977283dd34e15a7d1cfc5dbd7a335769e7242c98 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 14:12:49 -0700 Subject: [PATCH 218/230] [core] typo --- openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v | 2 +- .../homo_1clock_1reset_2layer_internal_driver/config/task.conf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v b/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v index 196eca363..fba40f3a7 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v @@ -4,7 +4,7 @@ //////////////////////////////////////// `timescale 1ns / 1ps -module clk_cond(rst_i, rst_cond_i, clk_i, d_i, q_o); +module rst_cond(rst_i, rst_cond_i, clk_i, d_i, q_o); input wire rst_cond_i; input wire rst_i; diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf index a61220518..a4841a1ae 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -32,7 +32,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40 [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v [SYNTHESIS_PARAM] # Yosys script parameters From f5ba43e3922244c0b05318a29d05f27842dd259b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 14:16:24 -0700 Subject: [PATCH 219/230] [core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench --- .../verilog_preconfig_top_module_utils.cpp | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp index bca7b6709..433a05620 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp @@ -172,6 +172,27 @@ int print_verilog_preconfig_top_module_connect_global_ports( */ if ((false == pin_constraints.unconstrained_net(constrained_net_name)) && (false == pin_constraints.unmapped_net(constrained_net_name))) { + /* The clock name must be a valid primary input. Otherwise, it could be + * a signal generated by internal logics, e.g., clb */ + AtomBlockId atom_blk = atom_ctx.nlist.find_block(constrained_net_name); + if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))) { + VTR_LOG( + "Global net '%s' is not a primary input of the netlist (which " + "could a signal generated by internal logic). Will not wire it to " + "any FPGA primary input pin\n", + constrained_net_name.c_str()); + continue; + } + /* The block may be renamed as it contains special characters which + * violate Verilog syntax */ + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + VTR_LOG( + "Replace pin name '%s' with '%s' as it is renamed to comply " + "verilog syntax\n", + constrained_net_name.c_str(), + netlist_annotation.block_name(atom_blk).c_str()); + constrained_net_name = netlist_annotation.block_name(atom_blk); + } BasicPort benchmark_pin(constrained_net_name, 1); print_verilog_wire_connection(fp, module_global_pin, benchmark_pin, false); From 215de8eb9392978528a9bd50d07a8314cea8ff07 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 14:17:22 -0700 Subject: [PATCH 220/230] [core] code format --- .../src/fpga_verilog/verilog_preconfig_top_module_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp index 433a05620..0073ab46d 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp @@ -191,7 +191,7 @@ int print_verilog_preconfig_top_module_connect_global_ports( "verilog syntax\n", constrained_net_name.c_str(), netlist_annotation.block_name(atom_blk).c_str()); - constrained_net_name = netlist_annotation.block_name(atom_blk); + constrained_net_name = netlist_annotation.block_name(atom_blk); } BasicPort benchmark_pin(constrained_net_name, 1); print_verilog_wire_connection(fp, module_global_pin, benchmark_pin, From 079e6f2fcadc59ea6d88600da048fd02f641040d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 14:28:28 -0700 Subject: [PATCH 221/230] [core] add new syntax to support from_pin and to_pin for internal driver in clock network --- .../src/base/clock_network.cpp | 21 +++++++++++++------ .../src/base/clock_network.h | 11 ++++++---- 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 04dd1fab4..2d891c33f 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -360,10 +360,16 @@ ClockNetwork::spine_switch_point_internal_drivers( return spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)]; } -std::string ClockNetwork::internal_driver_port( +std::string ClockNetwork::internal_driver_from_pin( const ClockInternalDriverId& int_driver_id) const { VTR_ASSERT(valid_internal_driver_id(int_driver_id)); - return internal_driver_ports_[int_driver_id]; + return internal_driver_from_pins_[int_driver_id]; +} + +std::string ClockNetwork::internal_driver_to_pin( + const ClockInternalDriverId& int_driver_id) const { + VTR_ASSERT(valid_internal_driver_id(int_driver_id)); + return internal_driver_to_pins_[int_driver_id]; } std::vector ClockNetwork::tree_taps( @@ -523,7 +529,7 @@ std::vector ClockNetwork::tree_flatten_tap_to_ports( return flatten_taps; } -std::vector ClockNetwork::flatten_internal_driver_port( +std::vector ClockNetwork::flatten_internal_driver_from_pin( const ClockInternalDriverId& int_driver_id) const { std::vector flatten_taps; std::string tap_name = internal_driver_port(int_driver_id); @@ -765,12 +771,14 @@ ClockSwitchPointId ClockNetwork::add_spine_switch_point( ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, - const std::string& int_driver_port) { + const std::string& int_driver_from_port, + const std::string& int_driver_to_port) { VTR_ASSERT(valid_spine_id(spine_id)); VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id)); /* Find any existing id for the driver port */ for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { - if (internal_driver_ports_[int_driver_id] == int_driver_port) { + if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port + && internal_driver_to_pins_[int_driver_id] == int_driver_to_port) { spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)] .push_back(int_driver_id); return int_driver_id; @@ -780,7 +788,8 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( ClockInternalDriverId int_driver_id = ClockInternalDriverId(internal_driver_ids_.size()); internal_driver_ids_.push_back(int_driver_id); - internal_driver_ports_.push_back(int_driver_port); + internal_driver_from_pins_.push_back(int_driver_port_from_port); + internal_driver_to_pins_.push_back(int_driver_port_to_port); spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back( int_driver_id); return int_driver_id; diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index ffec611df..8be10f8bb 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -135,9 +135,11 @@ class ClockNetwork { std::vector spine_switch_point_internal_drivers( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) const; - std::string internal_driver_port( + std::string internal_driver_from_pin( const ClockInternalDriverId& int_driver_id) const; - std::vector flatten_internal_driver_port( + std::vector flatten_internal_driver_from_pin( + const ClockInternalDriverId& int_driver_id) const; + std::string internal_driver_to_pin( const ClockInternalDriverId& int_driver_id) const; /* Return the original list of tap pins that is in storage; useful for parsers @@ -222,7 +224,7 @@ class ClockNetwork { const vtr::Point& coord); ClockInternalDriverId add_spine_switch_point_internal_driver( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, - const std::string& internal_driver_port); + const std::string& internal_driver_from_port, const std::string& internal_driver_to_port); ClockTapId add_tree_tap(const ClockTreeId& tree_id, const BasicPort& from_port, const std::string& to_port); @@ -317,7 +319,8 @@ class ClockNetwork { /* Basic Information about internal drivers */ vtr::vector internal_driver_ids_; - vtr::vector internal_driver_ports_; + vtr::vector internal_driver_from_pins_; + vtr::vector internal_driver_to_pins_; /* Basic information about tap */ vtr::vector tap_ids_; vtr::vector tap_from_ports_; From b2fc47a12a09449b76cc51a4afa8e8cc3f167a29 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 14:34:54 -0700 Subject: [PATCH 222/230] [core] reworked i/o for clock network files --- .../arch/example_internal_drivers.xml | 4 ++-- .../src/io/clock_network_xml_constants.h | 4 +++- .../src/io/read_xml_clock_network.cpp | 12 +++++++++--- .../src/io/write_xml_clock_network.cpp | 7 +++++-- 4 files changed, 19 insertions(+), 8 deletions(-) diff --git a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml index 6215ba443..d6435523c 100644 --- a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml +++ b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml @@ -2,10 +2,10 @@ - + - + diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index a63141870..65e828573 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -25,7 +25,9 @@ constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = "internal_driver"; constexpr const char* - XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN = "tile_pin"; + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_FROM_PIN = "from_pin"; +constexpr const char* + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN = "to_pin"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_TAP = "tap"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X = "x"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y = "y"; diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index c56b152fd..8e7116f62 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -163,13 +163,19 @@ static void read_xml_clock_spine_switch_point_internal_driver( "Invalid id of a clock spine!\n"); } - std::string int_driver_port_name = + std::string int_driver_from_port_name = get_attribute( xml_int_driver, - XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, loc_data) + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_FROM_PIN, loc_data) + .as_string(); + std::string int_driver_to_port_name = + get_attribute( + xml_int_driver, + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN, loc_data) .as_string(); clk_ntwk.add_spine_switch_point_internal_driver(spine_id, switch_point_id, - int_driver_port_name); + int_driver_from_port_name, + int_driver_to_port_name); } /******************************************************************** diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index e36ed9ed8..8d57618a9 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -126,8 +126,11 @@ static int write_xml_clock_spine_switch_point( openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME; write_xml_attribute( - fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, - clk_ntwk.internal_driver_port(int_driver_id).c_str()); + fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_FROM_PIN, + clk_ntwk.internal_driver_from_pin(int_driver_id).c_str()); + write_xml_attribute( + fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN, + clk_ntwk.internal_driver_to_pin(int_driver_id).c_str()); fp << "/>" << "\n"; } From a4538fb25bab4b0d367c70357d74f795ece13060 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 15:01:18 -0700 Subject: [PATCH 223/230] [core] now supports to_pin in building clock network for internal driver --- .../src/base/clock_network.cpp | 30 +++++++++++++++---- .../src/base/clock_network.h | 7 +++-- .../src/io/write_xml_clock_network.cpp | 2 +- .../src/annotation/append_clock_rr_graph.cpp | 11 ++++--- 4 files changed, 36 insertions(+), 14 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 2d891c33f..db3bf0cf7 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -366,7 +366,7 @@ std::string ClockNetwork::internal_driver_from_pin( return internal_driver_from_pins_[int_driver_id]; } -std::string ClockNetwork::internal_driver_to_pin( +BasicPort ClockNetwork::internal_driver_to_pin( const ClockInternalDriverId& int_driver_id) const { VTR_ASSERT(valid_internal_driver_id(int_driver_id)); return internal_driver_to_pins_[int_driver_id]; @@ -530,9 +530,25 @@ std::vector ClockNetwork::tree_flatten_tap_to_ports( } std::vector ClockNetwork::flatten_internal_driver_from_pin( - const ClockInternalDriverId& int_driver_id) const { + const ClockInternalDriverId& int_driver_id, + const ClockTreePinId& clk_pin_id) const { std::vector flatten_taps; - std::string tap_name = internal_driver_port(int_driver_id); + BasicPort des_pin = internal_driver_to_pin(int_driver_id); + if (!des_pin.is_valid()) { + VTR_LOG_ERROR("Invalid internal driver destination port name '%s' whose index is not valid\n", + des_pin.to_verilog_string().c_str()); + exit(1); + } + if (des_pin.get_width() != 1) { + VTR_LOG_ERROR("Invalid internal driver destination port name '%s' whose width is not 1\n", + des_pin.to_verilog_string().c_str()); + exit(1); + } + if (des_pin.get_lsb() != size_t(clk_pin_id)) { + return flatten_taps; + } + + std::string tap_name = internal_driver_from_pin(int_driver_id); StringToken tokenizer(tap_name); std::vector pin_tokens = tokenizer.split("."); if (pin_tokens.size() != 2) { @@ -775,10 +791,12 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( const std::string& int_driver_to_port) { VTR_ASSERT(valid_spine_id(spine_id)); VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id)); + /* Parse ports */ + PortParser to_pin_parser(int_driver_to_port); /* Find any existing id for the driver port */ for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port - && internal_driver_to_pins_[int_driver_id] == int_driver_to_port) { + && internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) { spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)] .push_back(int_driver_id); return int_driver_id; @@ -788,8 +806,8 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( ClockInternalDriverId int_driver_id = ClockInternalDriverId(internal_driver_ids_.size()); internal_driver_ids_.push_back(int_driver_id); - internal_driver_from_pins_.push_back(int_driver_port_from_port); - internal_driver_to_pins_.push_back(int_driver_port_to_port); + internal_driver_from_pins_.push_back(int_driver_from_port); + internal_driver_to_pins_.push_back(to_pin_parser.port()); spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back( int_driver_id); return int_driver_id; diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 8be10f8bb..088a238f9 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -138,8 +138,9 @@ class ClockNetwork { std::string internal_driver_from_pin( const ClockInternalDriverId& int_driver_id) const; std::vector flatten_internal_driver_from_pin( - const ClockInternalDriverId& int_driver_id) const; - std::string internal_driver_to_pin( + const ClockInternalDriverId& int_driver_id, + const ClockTreePinId& clk_pin_id) const; + BasicPort internal_driver_to_pin( const ClockInternalDriverId& int_driver_id) const; /* Return the original list of tap pins that is in storage; useful for parsers @@ -320,7 +321,7 @@ class ClockNetwork { vtr::vector internal_driver_ids_; vtr::vector internal_driver_from_pins_; - vtr::vector internal_driver_to_pins_; + vtr::vector internal_driver_to_pins_; /* Basic information about tap */ vtr::vector tap_ids_; vtr::vector tap_from_ports_; diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 8d57618a9..d570c7607 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -130,7 +130,7 @@ static int write_xml_clock_spine_switch_point( clk_ntwk.internal_driver_from_pin(int_driver_id).c_str()); write_xml_attribute( fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN, - clk_ntwk.internal_driver_to_pin(int_driver_id).c_str()); + clk_ntwk.internal_driver_to_pin(int_driver_id).to_verilog_string().c_str()); fp << "/>" << "\n"; } diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index d051634db..a6695c678 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -590,11 +590,13 @@ static void try_find_and_add_clock_opin2track_node( std::vector& opin_nodes, const DeviceGrid& grids, const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& grid_coord, const e_side& pin_side, - const ClockNetwork& clk_ntwk, const ClockInternalDriverId& int_driver_id) { + const ClockNetwork& clk_ntwk, + const ClockTreePinId& clk_pin, + const ClockInternalDriverId& int_driver_id) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : - clk_ntwk.flatten_internal_driver_port(int_driver_id)) { + clk_ntwk.flatten_internal_driver_from_pin(int_driver_id, clk_pin)) { /* tap pin name could be 'io[5:5].a2f[0]' */ int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name); if (grid_pin_idx == grid_type->num_pins) { @@ -636,6 +638,7 @@ static std::vector find_clock_opin2track_node( const DeviceGrid& grids, const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& sb_coord, const ClockNetwork& clk_ntwk, + const ClockTreePinId& clk_pin, const std::vector& int_driver_ids) { std::vector opin_nodes; /* Find opins from @@ -660,7 +663,7 @@ static std::vector find_clock_opin2track_node( for (ClockInternalDriverId int_driver_id : int_driver_ids) { try_find_and_add_clock_opin2track_node(opin_nodes, grids, rr_graph_view, layer, grid_coord, grid_side, - clk_ntwk, int_driver_id); + clk_ntwk, clk_pin, int_driver_id); } } } @@ -709,7 +712,7 @@ static int add_rr_graph_opin2clk_edges( clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id); for (RRNodeId src_node : find_clock_opin2track_node( - grids, rr_graph_view, layer, src_coord, clk_ntwk, + grids, rr_graph_view, layer, src_coord, clk_ntwk, ipin, int_driver_ids)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); From e614ca7380f06e072e3fc3525f0d66138358f232 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 15:03:27 -0700 Subject: [PATCH 224/230] [test] use new syntax --- .../config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml | 8 ++++---- .../config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml index 38bc90f9d..481e88a60 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml @@ -2,16 +2,16 @@ - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml index 1266725de..a89b25a17 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml @@ -17,10 +17,10 @@ - + - + From a390aad0b8c01b5194594e5b38b2ccf28d37c9b6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 15:07:16 -0700 Subject: [PATCH 225/230] [doc] add new syntax --- .../manual/file_formats/clock_network.rst | 23 ++++++++++++------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index 60cd10eff..fba5c3ef2 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -28,7 +28,7 @@ The entry point of a clock tree must be at a valid connection block. - + @@ -213,19 +213,26 @@ where clock spine ``spine0`` will drive another clock spine ``spine1`` at (1, 1) For each switch point, outputs of neighbouring programmable blocks are allowed to drive the spine at next level, through syntax ``internal_driver``. -.. option:: tile_pin="" +.. option:: from_pin="" Define the pin of a programmable block as an internal driver to a clock network. The pin must be a valid pin defined in the VPR architecture description file. +.. option:: to_pin="" + + Define the source pin of a clock network. The pin must be a valid pin of the global ports defined in the tile_annotation part of OpenFPGA architecture description file. + For example, .. code-block:: xml - - - - - + + + + + + + + where the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file: @@ -298,7 +305,7 @@ For example, .. code-block:: xml - + From c96f899c53214d4adffd004a47bb46a7f8b2aae9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 15:07:26 -0700 Subject: [PATCH 226/230] [core] code format --- .../src/base/clock_network.cpp | 16 ++++++++++------ libs/libclkarchopenfpga/src/base/clock_network.h | 3 ++- .../src/io/read_xml_clock_network.cpp | 6 +++--- .../src/io/write_xml_clock_network.cpp | 4 +++- .../src/annotation/append_clock_rr_graph.cpp | 12 +++++------- 5 files changed, 23 insertions(+), 18 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index db3bf0cf7..e989e88f4 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -535,13 +535,17 @@ std::vector ClockNetwork::flatten_internal_driver_from_pin( std::vector flatten_taps; BasicPort des_pin = internal_driver_to_pin(int_driver_id); if (!des_pin.is_valid()) { - VTR_LOG_ERROR("Invalid internal driver destination port name '%s' whose index is not valid\n", - des_pin.to_verilog_string().c_str()); + VTR_LOG_ERROR( + "Invalid internal driver destination port name '%s' whose index is not " + "valid\n", + des_pin.to_verilog_string().c_str()); exit(1); } if (des_pin.get_width() != 1) { - VTR_LOG_ERROR("Invalid internal driver destination port name '%s' whose width is not 1\n", - des_pin.to_verilog_string().c_str()); + VTR_LOG_ERROR( + "Invalid internal driver destination port name '%s' whose width is not " + "1\n", + des_pin.to_verilog_string().c_str()); exit(1); } if (des_pin.get_lsb() != size_t(clk_pin_id)) { @@ -795,8 +799,8 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( PortParser to_pin_parser(int_driver_to_port); /* Find any existing id for the driver port */ for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { - if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port - && internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) { + if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port && + internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) { spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)] .push_back(int_driver_id); return int_driver_id; diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 088a238f9..2f1a09592 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -225,7 +225,8 @@ class ClockNetwork { const vtr::Point& coord); ClockInternalDriverId add_spine_switch_point_internal_driver( const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, - const std::string& internal_driver_from_port, const std::string& internal_driver_to_port); + const std::string& internal_driver_from_port, + const std::string& internal_driver_to_port); ClockTapId add_tree_tap(const ClockTreeId& tree_id, const BasicPort& from_port, const std::string& to_port); diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 8e7116f62..46f74641d 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -169,9 +169,9 @@ static void read_xml_clock_spine_switch_point_internal_driver( XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_FROM_PIN, loc_data) .as_string(); std::string int_driver_to_port_name = - get_attribute( - xml_int_driver, - XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN, loc_data) + get_attribute(xml_int_driver, + XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN, + loc_data) .as_string(); clk_ntwk.add_spine_switch_point_internal_driver(spine_id, switch_point_id, int_driver_from_port_name, diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index d570c7607..1d9937141 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -130,7 +130,9 @@ static int write_xml_clock_spine_switch_point( clk_ntwk.internal_driver_from_pin(int_driver_id).c_str()); write_xml_attribute( fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN, - clk_ntwk.internal_driver_to_pin(int_driver_id).to_verilog_string().c_str()); + clk_ntwk.internal_driver_to_pin(int_driver_id) + .to_verilog_string() + .c_str()); fp << "/>" << "\n"; } diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index a6695c678..3552cdc33 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -590,8 +590,7 @@ static void try_find_and_add_clock_opin2track_node( std::vector& opin_nodes, const DeviceGrid& grids, const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& grid_coord, const e_side& pin_side, - const ClockNetwork& clk_ntwk, - const ClockTreePinId& clk_pin, + const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin, const ClockInternalDriverId& int_driver_id) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); @@ -637,8 +636,7 @@ static void try_find_and_add_clock_opin2track_node( static std::vector find_clock_opin2track_node( const DeviceGrid& grids, const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& sb_coord, - const ClockNetwork& clk_ntwk, - const ClockTreePinId& clk_pin, + const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin, const std::vector& int_driver_ids) { std::vector opin_nodes; /* Find opins from @@ -661,9 +659,9 @@ static std::vector find_clock_opin2track_node( vtr::Point grid_coord = grid_coords[igrid]; for (e_side grid_side : grid_sides[igrid]) { for (ClockInternalDriverId int_driver_id : int_driver_ids) { - try_find_and_add_clock_opin2track_node(opin_nodes, grids, rr_graph_view, - layer, grid_coord, grid_side, - clk_ntwk, clk_pin, int_driver_id); + try_find_and_add_clock_opin2track_node( + opin_nodes, grids, rr_graph_view, layer, grid_coord, grid_side, + clk_ntwk, clk_pin, int_driver_id); } } } From 0c99fcf6f4e1a893e1b5ea6233bd560e190e7617 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 15:07:57 -0700 Subject: [PATCH 227/230] [doc] format --- .../manual/openfpga_shell/openfpga_commands/setup_commands.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 2bf9e4ccb..ab27eeceb 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -132,7 +132,7 @@ Clock signals will be auto-detected and routed based on pin constraints which ar Specify the *Pin Constraints File* (PCF) when the clock network contains multiple clock pins. For example, ``-pin_constraints_file pin_constraints.xml``. Strongly recommend for multi-clock network. See detailed file format about :ref:`file_format_pin_constraints_file`. -.. note:: If there is a global net, e.g., ``clk`` or ``reset``, which will be driven by an internal resource, it should also be defined in the PCF file. + .. note:: If there is a global net, e.g., ``clk`` or ``reset``, which will be driven by an internal resource, it should also be defined in the PCF file. .. option:: --disable_unused_trees From ab126d8cfcef60d1cd4882738c193abd71e97ccc Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 10 Jul 2024 23:57:28 +0000 Subject: [PATCH 228/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 5b5fa0de1..4213f6c90 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2480 +1.2.2516 From df0d64ddb4fea8202e80b99d8f4bc189e40a337f Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 19 Jul 2024 06:34:08 +0000 Subject: [PATCH 229/230] Bump yosys from `b08688f` to `28ebefd` Bumps [yosys](https://github.com/YosysHQ/yosys) from `b08688f` to `28ebefd`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/b08688f71197316cd44859b8ced16136cf1b3957...28ebefda4ac6f534d1e7d3f00224040df0fc5b81) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index b08688f71..28ebefda4 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit b08688f71197316cd44859b8ced16136cf1b3957 +Subproject commit 28ebefda4ac6f534d1e7d3f00224040df0fc5b81 From 9570726ab998a09849d36bfb4c32d7edb571b248 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 21 Jul 2024 03:13:52 +0000 Subject: [PATCH 230/230] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 4213f6c90..843c88771 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2516 +1.2.2520

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