From ebe66dea353e054b9a852065fbc947b622656bf5 Mon Sep 17 00:00:00 2001
From: Lalit Sharma <lsharma@quicklogic.com>
Date: Wed, 3 Feb 2021 14:30:06 +0530
Subject: [PATCH] Bumping up latest yosys changes related to adder tech mapping

---
 openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys | 6 ++++++
 yosys                                                 | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)
 create mode 100644 openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys

diff --git a/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys b/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys
new file mode 100644
index 000000000..a36608fad
--- /dev/null
+++ b/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys
@@ -0,0 +1,6 @@
+# Yosys synthesis script for ${TOP_MODULE}
+# Read verilog files
+${READ_VERILOG_FILE}
+
+synth_quicklogic -blif ${OUTPUT_BLIF} -adder -openfpga -top ${TOP_MODULE}
+
diff --git a/yosys b/yosys
index 77570b6e0..1fafc16a2 160000
--- a/yosys
+++ b/yosys
@@ -1 +1 @@
-Subproject commit 77570b6e0f97f1923ebafd51ebfc9d9224a2f4cf
+Subproject commit 1fafc16a257872ac1abbbf14181bbb853f7c8a96