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bug fixing to resolve the conflicts between explicit port map and standard cell map

This commit is contained in:
tangxifan 2019-07-12 10:38:20 -06:00
parent e461cd0b99
commit f0ecc51b51
3 changed files with 59 additions and 47 deletions
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10
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
View File

@ -736,7 +736,7 @@ t_block* search_mapped_block(int x, int y, int z) {
assert((0 < x)||(0 == x));
assert((x < (nx + 1))||(x == (nx + 1)));
assert((0 < y)||(0 == y));
assert((x < (ny + 1))||(x == (ny + 1)));
assert((y < (ny + 1))||(y == (ny + 1)));
/* Search all blocks*/
for (iblk = 0; iblk < num_blocks; iblk++) {
@ -3479,10 +3479,10 @@ int my_strlen_int(int input_int) {
boolean my_bool_to_boolean(bool my_bool) {
if(true == my_bool)
if(true == my_bool) {
return TRUE;
if(false == my_bool)
} else {
assert (false == my_bool);
return FALSE;
vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert bool to boolean. Parameter is neither true nor false.\n");
exit(1);
}
}

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -445,7 +445,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
}
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "inout",
pb_type_inout_ports[iport], dump_port_type, TRUE);
pb_type_inout_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
@ -464,7 +464,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
}
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input",
pb_type_input_ports[iport], dump_port_type, TRUE);
pb_type_input_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}
@ -482,7 +482,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
}
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "output",
pb_type_output_ports[iport], dump_port_type, TRUE);
pb_type_output_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}
@ -501,7 +501,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
}
}
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input",
pb_type_clk_ports[iport], dump_port_type, TRUE);
pb_type_clk_ports[iport], dump_port_type, dump_explicit_port_map);
/* Update the counter */
num_dumped_port++;
}

74
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -222,34 +222,41 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "`endif\n");
}
/* Explicit port map support: turn it on when there is need for the full netlist or just standard cell */
boolean subckt_require_explicit_port_map = FALSE;
if ( (TRUE == verilog_model->dump_explicit_port_map) || (true == is_explicit_mapping) ) {
subckt_require_explicit_port_map = TRUE;
}
/* Call the subckt*/
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
fprintf(fp, "\n");
/* Only dump the global ports belonging to a spice_model
* Disable recursive here !
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) {
fprintf(fp, ",\n");
}
/* assert */
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
/* print ports --> input ports */
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping));
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE,
subckt_require_explicit_port_map);
/* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) {
fprintf(fp, ",\n");
assert(1 == num_pad_port);
assert(NULL != pad_ports[0]);
/* Add explicit port mapping if required */
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".%s(",
pad_ports[0]->lib_name);
}
/* Print inout port */
fprintf(fp, "%s%s[%d]", gio_inout_prefix,
verilog_model->prefix, verilog_model->cnt);
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
@ -263,7 +270,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
case SPICE_SRAM_SCAN_CHAIN:
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (true == is_explicit_mapping)) {
&& (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -273,7 +280,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
0, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (true == is_explicit_mapping)) {
&& (true == subckt_require_explicit_port_map)) {
fprintf(fp, ")");
}
@ -284,7 +291,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ", ");
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (true == is_explicit_mapping)) {
&& (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -294,14 +301,14 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
1, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (true == is_explicit_mapping)) {
&& (TRUE == verilog_model->dump_explicit_port_map || is_explicit_mapping)) {
fprintf(fp, ")");
}
break;
case SPICE_SRAM_MEMORY_BANK:
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (true == is_explicit_mapping)) {
&& (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -311,7 +318,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
0, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (true == is_explicit_mapping)) {
&& (TRUE == subckt_require_explicit_port_map)) {
fprintf(fp, ")");
}
/* Check if we have an inverterd prefix */
@ -321,7 +328,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ", ");
/* Add explicit port mapping if required */
if ( (0 < num_sram)
&& (true == is_explicit_mapping)) {
&& (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
@ -331,7 +338,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
1, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (true == is_explicit_mapping)) {
&& (TRUE == subckt_require_explicit_port_map)) {
fprintf(fp, ")");
}
break;
@ -594,6 +601,11 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
/* Explicit port map support: turn it on when there is need for the full netlist or just standard cell */
boolean subckt_require_explicit_port_map = FALSE;
if ( (TRUE == verilog_model->dump_explicit_port_map) || (true == is_explicit_mapping) ) {
subckt_require_explicit_port_map = TRUE;
}
/* Call LUT subckt*/
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
fprintf(fp, "\n");
@ -602,13 +614,13 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
* Only dump the global ports belonging to a spice_model
* DISABLE recursive here !
*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) {
fprintf(fp, ",\n");
}
/* Connect inputs*/
/* Connect outputs*/
fprintf(fp, "//----- Input and output ports -----\n");
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping));
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, subckt_require_explicit_port_map);
fprintf(fp, "\n//----- SRAM ports -----\n");
/* check */
@ -620,88 +632,88 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
case SPICE_SRAM_STANDALONE:
break;
case SPICE_SRAM_SCAN_CHAIN:
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".sram_out( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".sram_outb( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
if (0 < num_mode_sram) {
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
}
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_out( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_outb( ");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
}
break;
case SPICE_SRAM_MEMORY_BANK:
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".sram_out( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".sram_outb( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_lut_sram - 1,
1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
if (0 < num_mode_sram) {
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_out( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".mode_outb( ");
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
1, VERILOG_PORT_CONKT);
}
if (true == is_explicit_mapping) {
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ")");
}
break;