diff --git a/libs/libnamemanager/src/base/module_name_map.cpp b/libs/libnamemanager/src/base/module_name_map.cpp index 2a163191c..d0024b346 100644 --- a/libs/libnamemanager/src/base/module_name_map.cpp +++ b/libs/libnamemanager/src/base/module_name_map.cpp @@ -27,6 +27,11 @@ std::string ModuleNameMap::name(const std::string& tag) const { return result->second; } +bool ModuleNameMap::name_exist(const std::string& tag) const { + auto result = tag2names_.find(tag); + return result != tag2names_.end(); +} + std::vector ModuleNameMap::tags() const { std::vector keys; for (auto const& element : tag2names_) { diff --git a/libs/libnamemanager/src/base/module_name_map.h b/libs/libnamemanager/src/base/module_name_map.h index e18359f0e..291098a24 100644 --- a/libs/libnamemanager/src/base/module_name_map.h +++ b/libs/libnamemanager/src/base/module_name_map.h @@ -19,6 +19,8 @@ class ModuleNameMap { public: /* Public accessors */ /** @brief Get customized name with a given tag */ std::string name(const std::string& tag) const; + /** @brief Check if a name does exist with a given tag. Return true if there is a tag-to-name mapping */ + bool name_exist(const std::string& tag) const; /** @brief return a list of all the current keys */ std::vector tags() const; diff --git a/openfpga/src/base/openfpga_bitstream_template.h b/openfpga/src/base/openfpga_bitstream_template.h index 6874a04b3..85edafd9c 100644 --- a/openfpga/src/base/openfpga_bitstream_template.h +++ b/openfpga/src/base/openfpga_bitstream_template.h @@ -73,8 +73,8 @@ int build_fabric_bitstream_template(T& openfpga_ctx, const Command& cmd, /* Build fabric bitstream here */ openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream( openfpga_ctx.bitstream_manager(), openfpga_ctx.module_graph(), - openfpga_ctx.module_name_map(), - openfpga_ctx.arch().circuit_lib, openfpga_ctx.arch().config_protocol, + openfpga_ctx.module_name_map(), openfpga_ctx.arch().circuit_lib, + openfpga_ctx.arch().config_protocol, cmd_context.option_enable(cmd, opt_verbose)); /* TODO: should identify the error code from internal function execution */ diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 21fa7497d..81b48b18c 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -285,8 +285,8 @@ int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd, /* Write hierarchy to a file */ return write_fabric_hierarchy_to_text_file( - openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), hie_file_name, size_t(depth), - cmd_context.option_enable(cmd, opt_verbose)); + openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), hie_file_name, + size_t(depth), cmd_context.option_enable(cmd, opt_verbose)); } /******************************************************************** diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index e90d41389..e3c84e5da 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -335,7 +335,7 @@ int write_preconfigured_testbench_template(const T& openfpga_ctx, } return fpga_verilog_preconfigured_testbench( - openfpga_ctx.module_graph(), g_vpr_ctx.atom(), pin_constraints, bus_group, + openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), g_vpr_ctx.atom(), pin_constraints, bus_group, openfpga_ctx.fabric_global_port_info(), openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.simulation_setting(), options); diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.cpp b/openfpga/src/fabric/fabric_hierarchy_writer.cpp index 86f4065e7..46daae954 100644 --- a/openfpga/src/fabric/fabric_hierarchy_writer.cpp +++ b/openfpga/src/fabric/fabric_hierarchy_writer.cpp @@ -112,7 +112,8 @@ int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager, check_file_stream(fname.c_str(), fp); /* Find top-level module */ - std::string top_module_name = module_name_map.name(generate_fpga_top_module_name()); + std::string top_module_name = + module_name_map.name(generate_fpga_top_module_name()); ModuleId top_module = module_manager.find_module(top_module_name); if (true != module_manager.valid_module_id(top_module)) { VTR_LOGV_ERROR(verbose, "Unable to find the top-level module '%s'!\n", diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index 5d3181318..69482ec52 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -161,14 +161,16 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, /* Create the top-level block for bitstream * This is related to the top-level module of fpga */ - std::string top_block_name = openfpga_ctx.module_name_map().name(generate_fpga_top_module_name()); + std::string top_block_name = + openfpga_ctx.module_name_map().name(generate_fpga_top_module_name()); ConfigBlockId top_block = bitstream_manager.add_block(top_block_name); ModuleId top_module = openfpga_ctx.module_graph().find_module(top_block_name); VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module)); /* Create the core block when the fpga_core is added */ size_t num_blocks_to_reserve = 0; - std::string core_block_name = openfpga_ctx.module_name_map().name(generate_fpga_core_module_name()); + std::string core_block_name = + openfpga_ctx.module_name_map().name(generate_fpga_core_module_name()); const ModuleId& core_module = openfpga_ctx.module_graph().find_module(core_block_name); if (openfpga_ctx.module_graph().valid_module_id(core_module)) { diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp index d674fdf2e..c9908af0d 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp @@ -773,14 +773,15 @@ static void build_module_fabric_dependent_bitstream( FabricBitstream build_fabric_dependent_bitstream( const BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const ConfigProtocol& config_protocol, const bool& verbose) { + const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, + const bool& verbose) { FabricBitstream fabric_bitstream; vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n"); /* Get the top module name in module manager, which is our starting point */ - std::string top_module_name = module_name_map.name(generate_fpga_top_module_name()); + std::string top_module_name = + module_name_map.name(generate_fpga_top_module_name()); ModuleId top_module = module_manager.find_module(top_module_name); VTR_ASSERT(true == module_manager.valid_module_id(top_module)); @@ -794,7 +795,8 @@ FabricBitstream build_fabric_dependent_bitstream( ConfigBlockId top_block = top_blocks[0]; /* Create the core block when the fpga_core is added */ - std::string core_block_name = module_name_map.name(generate_fpga_core_module_name()); + std::string core_block_name = + module_name_map.name(generate_fpga_core_module_name()); const ModuleId& core_module = module_manager.find_module(core_block_name); if (module_manager.valid_module_id(core_module)) { /* Now we use the core_block as the top-level block for the remaining diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.h b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h index 6f86e896e..8c52742d0 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h @@ -22,10 +22,9 @@ namespace openfpga { FabricBitstream build_fabric_dependent_bitstream( const BitstreamManager& bitstream_manager, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const ConfigProtocol& config_protocol, const bool& verbose); + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index 7eb646749..7104923be 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -319,7 +319,9 @@ int fpga_verilog_mock_fpga_wrapper( *verification and formal verification purpose. ********************************************************************/ int fpga_verilog_preconfigured_testbench( - const ModuleManager &module_manager, const AtomContext &atom_ctx, + const ModuleManager &module_manager, + const ModuleNameMap &module_name_map, + const AtomContext &atom_ctx, const PinConstraints &pin_constraints, const BusGroup &bus_group, const FabricGlobalPortInfo &fabric_global_port_info, const VprNetlistAnnotation &netlist_annotation, @@ -343,7 +345,7 @@ int fpga_verilog_preconfigured_testbench( std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); print_verilog_random_top_testbench( netlist_name, random_top_testbench_file_path, atom_ctx, netlist_annotation, - module_manager, fabric_global_port_info, pin_constraints, bus_group, + module_manager, module_name_map, fabric_global_port_info, pin_constraints, bus_group, simulation_setting, options); /* Generate a Verilog file including all the netlists that have been generated diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h index b8eb9a89a..1ba84cf29 100644 --- a/openfpga/src/fpga_verilog/verilog_api.h +++ b/openfpga/src/fpga_verilog/verilog_api.h @@ -84,7 +84,9 @@ int fpga_verilog_mock_fpga_wrapper( const VerilogTestbenchOption& options); int fpga_verilog_preconfigured_testbench( - const ModuleManager& module_manager, const AtomContext& atom_ctx, + const ModuleManager& module_manager, + const ModuleNameMap &module_name_map, + const AtomContext& atom_ctx, const PinConstraints& pin_constraints, const BusGroup& bus_group, const FabricGlobalPortInfo& fabric_global_port_info, const VprNetlistAnnotation& netlist_annotation, diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 045a69024..3fc00ccd2 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -52,6 +52,7 @@ constexpr const char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start"; *******************************************************************/ static void print_verilog_top_random_testbench_ports( std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, const std::string& circuit_name, const std::vector& clock_port_names, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, @@ -82,7 +83,7 @@ static void print_verilog_top_random_testbench_ports( fp << std::endl; print_verilog_testbench_shared_ports( - fp, module_manager, FabricGlobalPortInfo(), PinConstraints(), atom_ctx, + fp, module_manager, module_name_map, FabricGlobalPortInfo(), PinConstraints(), atom_ctx, netlist_annotation, clock_port_names, std::string(), std::string(BENCHMARK_PORT_POSTFIX), std::string(FPGA_PORT_POSTFIX), std::string(CHECKFLAG_PORT_POSTFIX), options.no_self_checking()); @@ -168,7 +169,9 @@ static void print_verilog_random_testbench_fpga_instance( static void print_verilog_random_testbench_reset_stimuli( std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const std::vector& clock_port_names, const BasicPort& clock_port) { @@ -200,7 +203,7 @@ static void print_verilog_random_testbench_reset_stimuli( * fabric because their stimulus cannot be random */ if (false == - port_is_fabric_global_reset_port(global_ports, module_manager, + port_is_fabric_global_reset_port(global_ports, module_manager, module_name_map, pin_constraints.net_pin(block_name))) { continue; } @@ -210,7 +213,7 @@ static void print_verilog_random_testbench_reset_stimuli( size_t initial_value = 1; if (1 == global_ports.global_port_default_value(find_fabric_global_port( - global_ports, module_manager, pin_constraints.net_pin(block_name)))) { + global_ports, module_manager, module_name_map, pin_constraints.net_pin(block_name)))) { initial_value = 0; } @@ -270,7 +273,9 @@ static void print_verilog_random_testbench_reset_stimuli( void print_verilog_random_top_testbench( const std::string& circuit_name, const std::string& verilog_fname, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const BusGroup& bus_group, const SimulationSetting& simulation_parameters, const VerilogTestbenchOption& options) { @@ -301,7 +306,7 @@ void print_verilog_random_top_testbench( find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); /* Start of testbench */ - print_verilog_top_random_testbench_ports(fp, module_manager, circuit_name, + print_verilog_top_random_testbench_ports(fp, module_manager, module_name_map, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options); @@ -329,11 +334,11 @@ void print_verilog_random_top_testbench( * limitation should be removed! */ print_verilog_random_testbench_reset_stimuli( - fp, atom_ctx, netlist_annotation, module_manager, global_ports, + fp, atom_ctx, netlist_annotation, module_manager, module_name_map, global_ports, pin_constraints, clock_port_names, clock_ports[0]); print_verilog_testbench_random_stimuli( - fp, atom_ctx, netlist_annotation, module_manager, global_ports, + fp, atom_ctx, netlist_annotation, module_manager, module_name_map, global_ports, pin_constraints, clock_port_names, std::string(), std::string(CHECKFLAG_PORT_POSTFIX), clock_ports, options.no_self_checking()); diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h index 0e26165e6..f281e5fdf 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h @@ -9,6 +9,7 @@ #include "bus_group.h" #include "fabric_global_port_info.h" #include "module_manager.h" +#include "module_name_map.h" #include "pin_constraints.h" #include "simulation_setting.h" #include "verilog_testbench_options.h" @@ -25,7 +26,9 @@ namespace openfpga { void print_verilog_random_top_testbench( const std::string& circuit_name, const std::string& verilog_fname, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const BusGroup& bus_group, const SimulationSetting& simulation_parameters, const VerilogTestbenchOption& options); diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 5d1ca1828..8c56e5e8e 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -72,7 +72,9 @@ static void print_verilog_mux_memory_module( find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX)); - feedthru_module_name = module_name_map.name(feedthru_module_name); + if (module_name_map.name_exist(feedthru_module_name)) { + feedthru_module_name = module_name_map.name(feedthru_module_name); + } ModuleId feedthru_mem_module = module_manager.find_module(feedthru_module_name); if (module_manager.valid_module_id(feedthru_mem_module)) { @@ -215,7 +217,9 @@ void print_verilog_submodule_memories( std::string feedthru_module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX), true); - feedthru_module_name = module_name_map.name(feedthru_module_name); + if (module_name_map.name_exist(feedthru_module_name)) { + feedthru_module_name = module_name_map.name(feedthru_module_name); + } ModuleId feedthru_mem_module = module_manager.find_module(feedthru_module_name); diff --git a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp index a46fb72e1..0c8b7cfe3 100644 --- a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp +++ b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp @@ -44,7 +44,7 @@ static void print_verilog_mock_fpga_wrapper_connect_ios( std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, const AtomContext& atom_ctx, const PlacementContext& place_ctx, const IoLocationMap& io_location_map, - const IoNameMap& io_name_map, const PinConstraints& pin_constraints, + const IoNameMap& io_name_map, const ModuleNameMap& module_name_map, const PinConstraints& pin_constraints, const FabricGlobalPortInfo& global_ports, const VprNetlistAnnotation& netlist_annotation, const std::string& net_name_postfix, @@ -190,7 +190,7 @@ static void print_verilog_mock_fpga_wrapper_connect_ios( /* For global ports, use wires; otherwise, use registers*/ if (true == port_is_fabric_global_reset_port( global_ports, module_manager, - pin_constraints.net_pin(block_name))) { + module_name_map, pin_constraints.net_pin(block_name))) { continue; } @@ -516,7 +516,7 @@ int print_verilog_mock_fpga_wrapper( /* Print local wires */ print_verilog_testbench_shared_input_ports( - fp, module_manager, global_ports, pin_constraints, atom_ctx, + fp, module_manager, module_name_map, global_ports, pin_constraints, atom_ctx, netlist_annotation, benchmark_clock_port_names, true, std::string(APPINST_PORT_POSTFIX), false); @@ -543,7 +543,7 @@ int print_verilog_mock_fpga_wrapper( /* Connect I/Os to benchmark I/Os or constant driver */ print_verilog_mock_fpga_wrapper_connect_ios( fp, module_manager, core_module, atom_ctx, place_ctx, io_location_map, - require_io_naming ? io_name_map : IoNameMap(), pin_constraints, + require_io_naming ? io_name_map : IoNameMap(), module_name_map, pin_constraints, global_ports, netlist_annotation, std::string(), std::string(APPINST_PORT_POSTFIX), std::string(APPINST_PORT_POSTFIX), benchmark_clock_port_names, (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index c56d0c4a0..b491923a3 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -631,10 +631,10 @@ int print_verilog_preconfig_top_module( /* If we do have the core module, and the dut is specified as core module, the * hierarchy path when adding should be the instance name of the core module */ - std::string inst_name = generate_fpga_top_module_name(); + std::string inst_name = module_name_map.name(generate_fpga_top_module_name()); if (options.dut_module() == generate_fpga_core_module_name()) { ModuleId parent_module = - module_manager.find_module(generate_fpga_top_module_name()); + module_manager.find_module(module_name_map.name(generate_fpga_top_module_name())); inst_name = module_manager.instance_name(parent_module, core_module, 0); } diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index e3895c28d..aa1f2cb9c 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -818,7 +818,9 @@ void print_verilog_testbench_clock_stimuli( void print_verilog_testbench_random_stimuli( std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const std::vector& clock_port_names, const std::string& input_port_postfix, @@ -860,7 +862,7 @@ void print_verilog_testbench_random_stimuli( */ if (true == port_is_fabric_global_reset_port(global_ports, module_manager, - pin_constraints.net_pin(block_name))) { + module_name_map, pin_constraints.net_pin(block_name))) { continue; } @@ -943,7 +945,7 @@ void print_verilog_testbench_random_stimuli( * fabric because their stimulus cannot be random */ if (true == - port_is_fabric_global_reset_port(global_ports, module_manager, + port_is_fabric_global_reset_port(global_ports, module_manager, module_name_map, pin_constraints.net_pin(block_name))) { continue; } @@ -970,6 +972,7 @@ void print_verilog_testbench_random_stimuli( *******************************************************************/ void print_verilog_testbench_shared_input_ports( std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, @@ -1008,7 +1011,7 @@ void print_verilog_testbench_shared_input_ports( /* For global ports, use wires; otherwise, use registers*/ if (false == port_is_fabric_global_reset_port(global_ports, module_manager, - pin_constraints.net_pin(block_name))) { + module_name_map, pin_constraints.net_pin(block_name))) { if (use_reg_port) { fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; @@ -1159,6 +1162,7 @@ void print_verilog_testbench_shared_check_flags( *******************************************************************/ void print_verilog_testbench_shared_ports( std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, @@ -1168,7 +1172,7 @@ void print_verilog_testbench_shared_ports( const std::string& fpga_output_port_postfix, const std::string& check_flag_port_postfix, const bool& no_self_checking) { print_verilog_testbench_shared_input_ports( - fp, module_manager, global_ports, pin_constraints, atom_ctx, + fp, module_manager, module_name_map, global_ports, pin_constraints, atom_ctx, netlist_annotation, clock_port_names, false, shared_input_port_postfix, true); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 87059645f..495fe0c6e 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -13,6 +13,7 @@ #include "fabric_global_port_info.h" #include "io_location_map.h" #include "io_name_map.h" +#include "module_name_map.h" #include "module_manager.h" #include "pin_constraints.h" #include "simulation_setting.h" @@ -84,7 +85,9 @@ void print_verilog_testbench_clock_stimuli( void print_verilog_testbench_random_stimuli( std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const std::vector& clock_port_names, const std::string& input_port_postfix, @@ -93,6 +96,7 @@ void print_verilog_testbench_random_stimuli( void print_verilog_testbench_shared_input_ports( std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, @@ -117,6 +121,7 @@ void print_verilog_testbench_shared_check_flags( void print_verilog_testbench_shared_ports( std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index b2bfaa884..a1287aef7 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -801,6 +801,7 @@ static void print_verilog_top_testbench_benchmark_clock_ports( *******************************************************************/ static void print_verilog_top_testbench_ports( std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, const ModuleId& top_module, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const std::vector& clock_port_names, @@ -950,7 +951,7 @@ static void print_verilog_top_testbench_ports( std::vector global_port_names; print_verilog_testbench_shared_ports( - fp, module_manager, global_ports, pin_constraints, atom_ctx, + fp, module_manager, module_name_map, global_ports, pin_constraints, atom_ctx, netlist_annotation, clock_port_names, std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), @@ -2336,7 +2337,9 @@ static void print_verilog_full_testbench_bitstream( static void print_verilog_top_testbench_reset_stimuli( std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const std::string& port_name_postfix, const std::vector& clock_port_names) { valid_file_stream(fp); @@ -2368,13 +2371,13 @@ static void print_verilog_top_testbench_reset_stimuli( */ if (false == port_is_fabric_global_reset_port(global_ports, module_manager, - pin_constraints.net_pin(block_name))) { + module_name_map, pin_constraints.net_pin(block_name))) { continue; } size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port( - global_ports, module_manager, pin_constraints.net_pin(block_name))); + global_ports, module_manager, module_name_map, pin_constraints.net_pin(block_name))); /* Connect stimuli to greset with an optional inversion, depending on the * default value */ @@ -2518,7 +2521,7 @@ int print_verilog_full_testbench( /* Start of testbench */ print_verilog_top_testbench_ports( - fp, module_manager, core_module, atom_ctx, netlist_annotation, + fp, module_manager, module_name_map, core_module, atom_ctx, netlist_annotation, clock_port_names, global_ports, pin_constraints, simulation_parameters, config_protocol, circuit_name, options); @@ -2626,11 +2629,11 @@ int print_verilog_full_testbench( /* Add stimuli for reset, set, clock and iopad signals */ print_verilog_top_testbench_reset_stimuli( - fp, atom_ctx, netlist_annotation, module_manager, global_ports, + fp, atom_ctx, netlist_annotation, module_manager, module_name_map, global_ports, pin_constraints, std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), clock_port_names); print_verilog_testbench_random_stimuli( - fp, atom_ctx, netlist_annotation, module_manager, global_ports, + fp, atom_ctx, netlist_annotation, module_manager, module_name_map, global_ports, pin_constraints, clock_port_names, std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), diff --git a/openfpga/src/utils/fabric_global_port_info_utils.cpp b/openfpga/src/utils/fabric_global_port_info_utils.cpp index aaba4b123..8b06c8685 100644 --- a/openfpga/src/utils/fabric_global_port_info_utils.cpp +++ b/openfpga/src/utils/fabric_global_port_info_utils.cpp @@ -72,15 +72,15 @@ std::vector find_fabric_global_programming_set_ports( *******************************************************************/ bool port_is_fabric_global_reset_port( const FabricGlobalPortInfo& fabric_global_port_info, - const ModuleManager& module_manager, const BasicPort& port) { + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, const BasicPort& port) { /* Find the top_module: the fabric global ports are always part of the ports * of the top/core module. If there is a core module, we should consider core * only */ ModuleId top_module = - module_manager.find_module(generate_fpga_top_module_name()); + module_manager.find_module(module_name_map.name(generate_fpga_top_module_name())); VTR_ASSERT(true == module_manager.valid_module_id(top_module)); ModuleId core_module = - module_manager.find_module(generate_fpga_core_module_name()); + module_manager.find_module(module_name_map.name(generate_fpga_core_module_name())); if (module_manager.valid_module_id(core_module)) { top_module = core_module; } @@ -111,15 +111,17 @@ bool port_is_fabric_global_reset_port( *******************************************************************/ FabricGlobalPortId find_fabric_global_port( const FabricGlobalPortInfo& fabric_global_port_info, - const ModuleManager& module_manager, const BasicPort& port) { + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const BasicPort& port) { /* Find the top_module: the fabric global ports are always part of the ports * of the top/core module. If there is a core module, we should consider core * only */ ModuleId top_module = - module_manager.find_module(generate_fpga_top_module_name()); + module_manager.find_module(module_name_map.name(generate_fpga_top_module_name())); VTR_ASSERT(true == module_manager.valid_module_id(top_module)); ModuleId core_module = - module_manager.find_module(generate_fpga_core_module_name()); + module_manager.find_module(module_name_map.name(generate_fpga_core_module_name())); if (module_manager.valid_module_id(core_module)) { top_module = core_module; } diff --git a/openfpga/src/utils/fabric_global_port_info_utils.h b/openfpga/src/utils/fabric_global_port_info_utils.h index 5fd300337..298d67e74 100644 --- a/openfpga/src/utils/fabric_global_port_info_utils.h +++ b/openfpga/src/utils/fabric_global_port_info_utils.h @@ -8,6 +8,7 @@ #include "fabric_global_port_info.h" #include "module_manager.h" +#include "module_name_map.h" /******************************************************************** * Function declaration @@ -24,11 +25,14 @@ std::vector find_fabric_global_programming_set_ports( bool port_is_fabric_global_reset_port( const FabricGlobalPortInfo& fabric_global_port_info, - const ModuleManager& module_manager, const BasicPort& port); + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const BasicPort& port); FabricGlobalPortId find_fabric_global_port( const FabricGlobalPortInfo& fabric_global_port_info, - const ModuleManager& module_manager, const BasicPort& port); + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const BasicPort& port); } /* end namespace openfpga */