From ef78eac87b6b959a0f8dd3c1a1baa066f16864e9 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sun, 23 Oct 2022 16:10:52 -0600
Subject: [PATCH] Adding test case

---
 ...k4_N4_40nm_subtile_annotation_openfpga.xml | 204 ++++++++++++++++
 .../global_tile_subtile/config/task.conf      |  37 +++
 .../vpr_arch/k4_N4_io_subtiles_40nm.xml       | 230 ++++++++++++++++++
 3 files changed, 471 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_subtile/config/task.conf
 create mode 100644 openfpga_flow/vpr_arch/k4_N4_io_subtiles_40nm.xml

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml
new file mode 100644
index 000000000..429b48947
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml
@@ -0,0 +1,204 @@
+<?xml version="1.0"?>
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
+      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
+      <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+      <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+      <port type="output" prefix="Q" size="1"/>
+      <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="output" prefix="Q" size="1"/>
+      <port type="output" prefix="QN" size="1"/>
+      <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFF" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="DFF"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_tree_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <tile_annotations>
+    <global_port name="clk" is_clock="true" default_val="0">
+      <tile name="clb" port="clk" x="-1" y="-1"/>
+    </global_port>
+  </tile_annotations>
+  <pb_type_annotations>
+    <!-- fpga_input pb_type annoptation  -->
+    <pb_type name="fpga_input" physical_mode_name="physical"/>
+    <pb_type name="fpga_output" physical_mode_name="physical"/>
+
+    <pb_type name="fpga_input[physical].iopad" circuit_model_name="GPIO" mode_bits="0">
+      <port name="inpad" physical_mode_port="inpad"/>
+    </pb_type>
+    <pb_type name="fpga_output[physical].iopad" circuit_model_name="GPIO" mode_bits="0">
+      <port name="outpad" physical_mode_port="outpad"/>
+    </pb_type>
+
+    <pb_type name="fpga_input[inpad].inpad" physical_pb_type_name="fpga_input[physical].iopad" mode_bits="1"/>
+    <pb_type name="fpga_output[outpad].outpad" physical_pb_type_name="fpga_output[physical].iopad" mode_bits="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_subtile/config/task.conf
new file mode 100644
index 000000000..b8fa2ec7e
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_subtile/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_io_subtiles_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
diff --git a/openfpga_flow/vpr_arch/k4_N4_io_subtiles_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_io_subtiles_40nm.xml
new file mode 100644
index 000000000..58204198e
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_N4_io_subtiles_40nm.xml
@@ -0,0 +1,230 @@
+<?xml version="1.0"?>
+<!--
+  Architecture with no fracturable LUTs
+
+  - 40 nm technology
+  - General purpose logic block:
+    K = 4, N = 4
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+    <models>
+        <!-- A virtual model for I/O to be used in the physical mode of io block -->
+        <model name="io_inpad">
+            <output_ports>
+                <port name="inpad"/>
+            </output_ports>
+        </model>
+        <model name="io_outpad">
+            <input_ports>
+                <port name="outpad"/>
+            </input_ports>
+        </model>
+    </models>
+    <tiles>
+        <tile name="hybrid_io_tile" area="0">
+            <sub_tile name="fpga_input" capacity="8">
+                <equivalent_sites>
+                    <site pb_type="fpga_input"/>
+                </equivalent_sites>
+                <output name="inpad" num_pins="1"/>
+                <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+                <pinlocations pattern="custom">
+                    <loc side="left"> fpga_input.inpad</loc>
+                    <loc side="top"> fpga_input.inpad</loc>
+                    <loc side="right"> fpga_input.inpad</loc>
+                    <loc side="bottom"> fpga_input.inpad</loc>
+                </pinlocations>
+            </sub_tile>
+            <sub_tile name="fpga_output" capacity="8">
+                <equivalent_sites>
+                    <site pb_type="fpga_output"/>
+                </equivalent_sites>
+                <input name="outpad" num_pins="1"/>
+                <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+                <pinlocations pattern="custom">
+                    <loc side="left"> fpga_output.outpad</loc>
+                    <loc side="top"> fpga_output.outpad</loc>
+                    <loc side="right"> fpga_output.outpad</loc>
+                    <loc side="bottom"> fpga_output.outpad</loc>
+                </pinlocations>
+            </sub_tile>
+        </tile>
+        <tile name="clb" area="53894">
+            <sub_tile name="clb">
+                <equivalent_sites>
+                    <site pb_type="clb"/>
+                </equivalent_sites>
+                <input name="I" num_pins="10" equivalent="full"/>
+                <output name="O" num_pins="4" equivalent="none"/>
+                <clock name="clk" num_pins="1"/>
+                <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+                    <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
+                </fc>
+                <pinlocations pattern="spread"/>
+            </sub_tile>
+        </tile>
+    </tiles>
+    <!-- ODIN II specific config ends -->
+    <!-- Physical descriptions begin -->
+    <layout tileable="true">
+        <auto_layout aspect_ratio="1.0">
+            <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+            <perimeter type="io" priority="100"/>
+            <corners type="EMPTY" priority="101"/>
+            <!--Fill with 'clb'-->
+            <fill type="clb" priority="10"/>
+        </auto_layout>
+        <fixed_layout name="2x2" width="10" height="10">
+            <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+            <perimeter type="hybrid_io_tile" priority="100"/>
+            <corners type="EMPTY" priority="101"/>
+            <!--Fill with 'clb'-->
+            <fill type="clb" priority="10"/>
+        </fixed_layout>
+    </layout>
+    <device>
+        <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+        <area grid_logic_tile_area="0"/>
+        <chan_width_distr>
+            <x distr="uniform" peak="1.000000"/>
+            <y distr="uniform" peak="1.000000"/>
+        </chan_width_distr>
+        <switch_block type="wilton" fs="3"/>
+        <connection_block input_switch_name="ipin_cblock"/>
+    </device>
+    <switchlist>
+
+        <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+        <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+    </switchlist>
+    <segmentlist>
+        <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+            <mux name="0"/>
+            <sb type="pattern">1 1 1 1 1</sb>
+            <cb type="pattern">1 1 1 1</cb>
+        </segment>
+    </segmentlist>
+    <complexblocklist>
+
+        <pb_type name="fpga_input">
+            <output name="inpad" num_pins="1"/>
+            <mode name="physical" disable_packing="true">
+                <pb_type name="iopad" blif_model=".subckt io_inpad" num_pb="1">
+                    <output name="inpad" num_pins="1"/>
+                </pb_type>
+                <interconnect>
+                    <direct name="inpad" input="iopad.inpad" output="fpga_input.inpad"/>
+                </interconnect>
+            </mode>
+            <mode name="inpad">
+                <pb_type name="inpad" blif_model=".input" num_pb="1">
+                    <output name="inpad" num_pins="1"/>
+                </pb_type>
+                <interconnect>
+                    <direct name="inpad" input="inpad.inpad" output="fpga_input.inpad">
+                        <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="fpga_input.inpad"/>
+                    </direct>
+                </interconnect>
+            </mode>
+        </pb_type>
+
+        <pb_type name="fpga_output">
+            <input name="outpad" num_pins="1"/>
+
+            <mode name="physical" disable_packing="true">
+                <pb_type name="iopad" blif_model=".subckt io_outpad" num_pb="1">
+                    <input name="outpad" num_pins="1"/>
+                </pb_type>
+                <interconnect>
+                    <direct name="outpad" input="fpga_output.outpad" output="iopad.outpad"/>
+                </interconnect>
+            </mode>
+
+            <mode name="outpad">
+                <pb_type name="outpad" blif_model=".output" num_pb="1">
+                    <input name="outpad" num_pins="1"/>
+                </pb_type>
+                <interconnect>
+                    <direct name="outpad" input="fpga_output.outpad" output="outpad.outpad"/>
+                </interconnect>
+            </mode>
+
+        </pb_type>
+
+        <pb_type name="clb">
+            <input name="I" num_pins="10" equivalent="full"/>
+            <output name="O" num_pins="4" equivalent="none"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="fle" num_pb="4">
+                <input name="in" num_pins="4"/>
+                <output name="out" num_pins="1"/>
+                <clock name="clk" num_pins="1"/>
+                <!-- 4-LUT mode definition begin -->
+                <mode name="n1_lut4">
+                    <!-- Define 4-LUT mode -->
+                    <pb_type name="ble4" num_pb="1">
+                        <input name="in" num_pins="4"/>
+                        <output name="out" num_pins="1"/>
+                        <clock name="clk" num_pins="1"/>
+                        <!-- Define LUT -->
+                        <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+                            <input name="in" num_pins="4" port_class="lut_in"/>
+                            <output name="out" num_pins="1" port_class="lut_out"/>
+                            <!-- LUT timing using delay matrix -->
+                            <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                                261e-12
+                                261e-12
+                                261e-12
+                                261e-12
+                            </delay_matrix>
+                        </pb_type>
+                        <!-- Define flip-flop -->
+                        <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                            <input name="D" num_pins="1" port_class="D"/>
+                            <output name="Q" num_pins="1" port_class="Q"/>
+                            <clock name="clk" num_pins="1" port_class="clock"/>
+                            <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                            <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                        </pb_type>
+                        <interconnect>
+                            <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+                            <direct name="direct2" input="lut4.out" output="ff.D">
+                                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+                            </direct>
+                            <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+                            <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+                            </mux>
+                        </interconnect>
+                    </pb_type>
+                    <interconnect>
+                        <direct name="direct1" input="fle.in" output="ble4.in"/>
+                        <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+                        <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+                    </interconnect>
+                </mode>
+            </pb_type>
+            <interconnect>
+                <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+                    <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+                    <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+                </complete>
+                <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+                </complete>
+
+                <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
+            </interconnect>
+        </pb_type>
+    </complexblocklist>
+</architecture>