diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml
new file mode 100644
index 000000000..429b48947
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml
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+
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12 5e-12 5e-12
+
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+ 10e-12 5e-12 5e-12
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diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_subtile/config/task.conf
new file mode 100644
index 000000000..b8fa2ec7e
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_subtile/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_subtile_annotation_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_io_subtiles_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
diff --git a/openfpga_flow/vpr_arch/k4_N4_io_subtiles_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_io_subtiles_40nm.xml
new file mode 100644
index 000000000..58204198e
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_N4_io_subtiles_40nm.xml
@@ -0,0 +1,230 @@
+
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+ fpga_input.inpad
+ fpga_input.inpad
+ fpga_input.inpad
+ fpga_input.inpad
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+ fpga_output.outpad
+ fpga_output.outpad
+ fpga_output.outpad
+ fpga_output.outpad
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+ 1 1 1 1 1
+ 1 1 1 1
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+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
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