diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 717efb21b..42bb7886f 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -363,6 +363,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, std::string(BENCHMARK_PORT_POSTFIX), std::string(FPGA_PORT_POSTFIX), std::string(CHECKFLAG_PORT_POSTFIX), + std::string(), std::string(ERROR_COUNTER), atom_ctx, netlist_annotation, diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 78854ebc3..899d6b014 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -433,6 +433,7 @@ void print_verilog_testbench_check(std::fstream& fp, const std::string& benchmark_port_postfix, const std::string& fpga_port_postfix, const std::string& check_flag_port_postfix, + const std::string& config_done_name, const std::string& error_counter_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, @@ -465,7 +466,12 @@ void print_verilog_testbench_check(std::fstream& fp, fp << "\t\tif (1'b1 == " << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << ") begin" << std::endl; fp << "\t\t"; print_verilog_register_connection(fp, sim_start_port, sim_start_port, true); - fp << "\t\tend else begin" << std::endl; + fp << "\t\tend else " << std::endl; + /* If there is a config done signal specified, consider it as a trigger on checking */ + if (!config_done_name.empty()) { + fp << "if (1'b1 == " << config_done_name << ") "; + } + fp << "begin" << std::endl; for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { /* Bypass non-I/O atom blocks ! */ diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 3406b89b9..44816e85b 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -76,6 +76,7 @@ void print_verilog_testbench_check(std::fstream& fp, const std::string& benchmark_port_postfix, const std::string& fpga_port_postfix, const std::string& check_flag_port_postfix, + const std::string& config_done_name, const std::string& error_counter_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index d644c6a2b..d668cb997 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -2131,6 +2131,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), + std::string(TOP_TB_CONFIG_DONE_PORT_NAME), std::string(TOP_TESTBENCH_ERROR_COUNTER), atom_ctx, netlist_annotation, diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v index 4a3542eec..ead38700f 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v @@ -15,6 +15,10 @@ module counter ( reg [127:0] result; + initial begin + result <= 0; + end + always @(posedge clk or posedge reset) begin if (reset) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v index 628ec4c08..fda46b891 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v @@ -15,6 +15,10 @@ module counter ( reg [127:0] result; + initial begin + result <= 0; + end + always @(posedge clk or negedge resetb) begin if (~resetb) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v index c1b5f2ee6..5bad03ced 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v @@ -1,18 +1,22 @@ -module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); +module counter_4bit_2clock(clk0, rst, clk1, q0, q1); input clk0; - input rst0; + input rst; output [3:0] q0; reg [3:0] q0; input clk1; - input rst1; output [3:0] q1; reg [3:0] q1; + initial begin + q0 <= 0; + q1 <= 0; + end + always @ (posedge clk0) begin - if(rst0) + if(rst) q0 <= 4'b0000; else q0 <= q0 + 1; @@ -20,7 +24,7 @@ module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); always @ (posedge clk1) begin - if(rst1) + if(rst) q1 <= 4'b0000; else q1 <= q1 + 1; diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v index 685b77577..0997e1b63 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v @@ -15,6 +15,10 @@ module counter ( reg [7:0] result; + initial begin + result <= 0; + end + always @(posedge clk or posedge reset) begin if (reset) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v index 3d929091d..3d7869948 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v @@ -15,6 +15,10 @@ module counter ( reg [7:0] result; + initial begin + result <= 0; + end + always @(posedge clk or negedge resetb) begin if (!resetb) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v index 216053285..10f0e1c4b 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v @@ -5,6 +5,10 @@ module counter(clk_counter, q_counter, rst_counter); output [7:0] q_counter; reg [7:0] q_counter; + initial begin + q_counter <= 0; + end + always @ (posedge clk_counter) begin if(rst_counter) diff --git a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga index 6d623e138..698b25ec3 100644 --- a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga @@ -55,9 +55,9 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/and2_latch_pin_constraints.xml similarity index 100% rename from openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml rename to openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/and2_latch_pin_constraints.xml diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/counter_2clock_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/counter_2clock_pin_constraints.xml new file mode 100644 index 000000000..60a8c9ae1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/counter_2clock_pin_constraints.xml @@ -0,0 +1,12 @@ + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf index e61b9e49f..b6181c190 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf @@ -19,7 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml -openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml +openfpga_repack_design_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml @@ -31,9 +31,9 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch [SYNTHESIS_PARAM] bench_read_verilog_options_common = -nolatches bench0_top = counter_4bit_2clock -bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml +bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/counter_2clock_pin_constraints.xml bench1_top = and2_latch_2clock -bench1_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml +bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/and2_latch_pin_constraints.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/pin_constraints_reset.xml b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/pin_constraints_reset.xml new file mode 100644 index 000000000..5b4f76fe3 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf index fbe19333c..df489b240 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf @@ -19,7 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -openfpga_verilog_default_net_type=none +openfpga_default_net_type=none [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml @@ -30,7 +30,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/c [SYNTHESIS_PARAM] bench_read_verilog_options_common = -nolatches bench0_top = counter -bench0_chan_width = 300 +bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/pin_constraints_reset.xml b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/pin_constraints_reset.xml new file mode 100644 index 000000000..5b4f76fe3 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf index e298e0cc2..958282c02 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf @@ -19,7 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -openfpga_verilog_default_net_type=wire +openfpga_default_net_type=wire [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml @@ -30,7 +30,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/c [SYNTHESIS_PARAM] bench_read_verilog_options_common = -nolatches bench0_top = counter -bench0_chan_width = 300 +bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=