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Merge pull request #488 from lnis-uofu/issue-483 

Read HDL files as a single compilation unit in yosys_vpr flow for Verific mode.
This commit is contained in:
tangxifan 2022-01-19 10:35:58 -08:00 committed by GitHub
parent ff67966356 397f2e71f1
commit eebf40d9c3
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GPG Key ID: 4AEE18F83AFDEB23
106 changed files with 197 additions and 32 deletions
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2
docs/source/manual/openfpga_flow/run_fpga_flow.rst
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@ -109,7 +109,7 @@ General Arguments
.. option:: --yosys_tmpl <yosys_template_file>
This option allows the user to provide a custom Yosys template while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Alternately, user can create a copy and modify according to their need. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables. In case if ``--verific`` option is provided then ``ADD_INCLUDE_DIR``, ``ADD_LIBRARY_DIR``, ``ADD_BLACKBOX_MODULES``, ``READ_HDL_FILE`` (should be used instead of ``READ_VERILOG_FILE``) and ``READ_LIBRARY`` additional varialbes are supported. The variables can be used as ``${var_name}``.
This option allows the user to provide a custom Yosys template while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Alternately, user can create a copy and modify according to their need. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_OPTIONS`` ``VERILOG_FILES`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables. In case if ``--verific`` option is provided then ``ADD_INCLUDE_DIR``, ``ADD_LIBRARY_DIR``, ``ADD_BLACKBOX_MODULES``, ``READ_HDL_FILE`` (should be used instead of ``READ_VERILOG_OPTIONS`` and ``VERILOG_FILES``) and ``READ_LIBRARY`` additional varialbes are supported. The variables can be used as ``${var_name}``.
.. option:: --ys_rewrite_tmpl <yosys_rewrite_template_file>

18
docs/source/manual/openfpga_flow/run_fpga_task.rst
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@ -157,13 +157,15 @@ OpenFPGA_SHELL Sections
The option specifies VHDL language standard to be used while reading the VHDL files.
.. option:: verific_read_lib_name=<lib_name>
.. option:: verific_read_lib_name<lib_label>=<lib_name>
The option specifies library name where Verilog/SystemVerilog/VHDL files specified by ``verific_read_lib_src`` option will be loaded. This option should be used only with ``verific_read_lib_src`` option.
The ``lib_label`` variable can be any number of string without
white-spaces. The option specifies library name where Verilog/SystemVerilog/VHDL files specified by ``verific_read_lib_src<lib_label>`` option will be loaded. This option should be used only with ``verific_read_lib_src<lib_label>`` option.
.. option:: verific_read_lib_src=<library_src_files>
.. option:: verific_read_lib_src<lib_label>=<library_src_files>
The option specifies Verilog/SystemVerilog/VHDL files to be loaded into library specified by ``verific_read_lib_name`` option. The ``library_src_files`` should be the source files names separated by commas. This option should be used only with ``verific_read_lib_name`` option.
The ``lib_label`` variable can be any number of string without
white-spaces. The option specifies Verilog/SystemVerilog/VHDL files to be loaded into library specified by ``verific_read_lib_name<lib_label>`` option. The ``library_src_files`` should be the source files names separated by commas. This option should be used only with ``verific_read_lib_name<lib_label>`` option.
.. option:: verific_search_lib=<lib_name>
@ -210,8 +212,7 @@ Benchmarks Sections
.. option:: bench<bench_label>=<list_of_files_in_benchmark>
The ``bench_label`` variable can be any number of string without
white-spaces. ``xml_architecture_file_path`` is path to the actual XML
architecture file
white-spaces. ``list_of_files_in_benchmark`` is a list of benchmark HDL files paths.
For Example following code shows how to define a benchmarks,
with a single file, multiple files and files added from a specific directory.
@ -263,6 +264,11 @@ Synthesis Parameter Sections
the source Verilog design for ``bench_label`` benchmark to be used
while verification.
.. option:: bench<bench_label>_read_verilog_options=<Options>
This option defines the ``read_verilog`` command options for ``bench_label`` benchmark.
If all benchmarks share the same options then ``bench_read_verilog_options_common`` can be used to define common options.
Script Parameter Sections
^^^^^^^^^^^^^^^^^^^^^^^^^
The script parameter section lists set of commnad line pararmeters to be passed to :ref:`run_fpga_flow` script. The section name is defines as ``SCRIPT_PARAM_<parameter_set_label>`` where `parameter_set_label` can be any word without white spaces.

2
openfpga_flow/misc/qlf_yosys.ys
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@ -3,7 +3,7 @@
plugin -i ql-qlf
# Read verilog files
${READ_VERILOG_FILE}
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
synth_ql -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}

2
openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
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@ -4,7 +4,7 @@
# Parse input files
#########################
# Read verilog files
${READ_VERILOG_FILE}
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Read technology library
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}

2
openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
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@ -4,7 +4,7 @@
# Parse input files
#########################
# Read verilog files
${READ_VERILOG_FILE}
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Read technology library
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}

2
openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
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@ -4,7 +4,7 @@
# Parse input files
#########################
# Read verilog files
${READ_VERILOG_FILE}
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Read technology library
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}

2
openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
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@ -1,6 +1,6 @@
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Read technology library
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}

2
openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
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@ -4,7 +4,7 @@
# Parse input files
#########################
# Read verilog files
${READ_VERILOG_FILE}
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Read technology library
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}

2
openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
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@ -1,6 +1,6 @@
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Technology mapping
hierarchy -top ${TOP_MODULE}

2
openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
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@ -1,6 +1,6 @@
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
# Technology mapping
hierarchy -top ${TOP_MODULE}

3
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -140,6 +140,9 @@ run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_
echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific";
run-task basic_tests/verific_test --debug --show_thread_logs
echo -e "Testing explicit multi verilog files";
run-task basic_tests/explicit_multi_verilog_files --debug --show_thread_logs
# Repgression test to test multi-user enviroment
cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/
cd /tmp/ && run-task configuration_chain --debug --show_thread_logs

40
openfpga_flow/scripts/run_fpga_flow.py
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@ -497,9 +497,10 @@ def create_yosys_params():
ys_params[tmpVar] = OpenFPGAArgs[indx+1]
if not args.verific:
ys_params["READ_VERILOG_FILE"] = " \n".join([
"read_verilog -nolatches " + shlex.quote(eachfile)
for eachfile in args.benchmark_files])
ys_params["VERILOG_FILES"] = " ".join([
shlex.quote(eachfile) for eachfile in args.benchmark_files])
if not "READ_VERILOG_OPTIONS" in ys_params:
ys_params["READ_VERILOG_OPTIONS"] = ""
else:
if "ADD_INCLUDE_DIR" not in ys_params:
ys_params["ADD_INCLUDE_DIR"] = ""
@ -538,26 +539,37 @@ def create_yosys_params():
ys_params["ADD_LIBRARY_DIR"] = "\n".join(["verific -vlog-libdir " +
shlex.quote(eachdir) for eachdir in ys_params["VERIFIC_LIBRARY_DIR"].split(",")])
try:
if "VERIFIC_READ_LIB_NAME" in ys_params and "VERIFIC_READ_LIB_SRC" in ys_params:
for name in ys_params["VERIFIC_READ_LIB_SRC"].split(","):
for param, value in ys_params.items():
if param.startswith("VERIFIC_READ_LIB_NAME"):
index = param[len("VERIFIC_READ_LIB_NAME"):]
src_param = "VERIFIC_READ_LIB_SRC" + index
if src_param in ys_params:
src_files = []
for name in ys_params[src_param].split(","):
for eachfile in args.benchmark_files:
if name in eachfile:
lib_files.append(eachfile)
if name.strip() in eachfile:
src_files.append(eachfile)
break
if not lib_files:
if not src_files:
clean_up_and_exit("Failed to locate verific library files")
filename, file_extension = os.path.splitext(lib_files[0])
ys_params["READ_LIBRARY"] = " ".join(["verific -work",
ys_params["VERIFIC_READ_LIB_NAME"], ext_to_standard_map[file_extension]] +
[shlex.quote(eachfile) for eachfile in lib_files])
lib_files.extend(src_files)
filename, file_extension = os.path.splitext(src_files[0])
ys_params["READ_LIBRARY"] += " ".join(["verific -work",
ys_params[param], ext_to_standard_map[file_extension]] +
[shlex.quote(eachfile) for eachfile in src_files] + ["\n"])
standard_to_sources = {}
for eachfile in args.benchmark_files:
if eachfile in lib_files:
continue
filename, file_extension = os.path.splitext(eachfile)
if ext_to_standard_map[file_extension] in standard_to_sources:
standard_to_sources[ext_to_standard_map[file_extension]].append(eachfile)
else:
standard_to_sources[ext_to_standard_map[file_extension]] = [eachfile]
for standard, sources in standard_to_sources.items():
ys_params["READ_HDL_FILE"] += " ".join(["verific",
"-L " + ys_params["VERIFIC_SEARCH_LIB"] if "VERIFIC_SEARCH_LIB" in ys_params else "",
ext_to_standard_map[file_extension],
shlex.quote(eachfile), "\n"])
standard, " ".join([shlex.quote(src) for src in sources]), "\n"])
except:
logger.exception("Failed to determine design file type")
clean_up_and_exit("")

7
openfpga_flow/scripts/run_fpga_task.py
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@ -264,9 +264,11 @@ def generate_each_task_actions(taskname):
# - All the benchmarks may share the same yosys synthesis template script
# - All the benchmarks may share the same rewrite yosys template script, which converts post-synthesis .v netlist to be compatible with .blif port definition. This is required for correct verification at the end of flows
# - All the benchmarks may share the same routing channel width in VPR runs. This is designed to enable architecture evaluations for a fixed device model
# - All the benchmarks may share the same options for reading verilog files
ys_for_task_common = SynthSection.get("bench_yosys_common")
ys_rewrite_for_task_common = SynthSection.get("bench_yosys_rewrite_common")
chan_width_common = SynthSection.get("bench_chan_width_common")
read_verilog_options_common = SynthSection.get("bench_read_verilog_options_common")
# Individual benchmark configuration
CurrBenchPara["files"] = bench_files
@ -284,6 +286,11 @@ def generate_each_task_actions(taskname):
eachKey = eachKey.replace(bech_name+"_", "").upper()
CurrBenchPara["benchVariable"] += [f"--{eachKey}", eachValue]
if not "read_verilog_options".upper() in CurrBenchPara["benchVariable"]:
if read_verilog_options_common:
CurrBenchPara["benchVariable"] += ["--read_verilog_options".upper(),
read_verilog_options_common]
if GeneralSection.get("fpga_flow") == "vpr_blif":
# Check if activity file exist
if not SynthSection.get(bech_name+"_act"):

45
openfpga_flow/tasks/basic_tests/explicit_multi_verilog_files/config/task.conf Normal file
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@ -0,0 +1,45 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
# Yosys script parameters
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
# VPR parameters
# Use a fixed routing channel width to save runtime
vpr_route_chan_width=300
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
[BENCHMARKS]
# RTL netlists from IWLS 2005 benchmark release
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_clockgen.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_crc.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_defines.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_fifo.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_maccontrol.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_macstatus.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_miim.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_outputcontrol.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_random.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_receivecontrol.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_register.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_registers.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxaddrcheck.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxcounters.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxethmac.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxstatem.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_shiftreg.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_spram_256x32.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_top.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_transmitcontrol.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txcounters.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txethmac.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txstatem.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_wishbone.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/timescale.v
[SYNTHESIS_PARAM]
bench0_read_verilog_options = -nolatches
bench0_yosys = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
bench0_top = eth_top
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq/config/task.conf
View File

@ -30,6 +30,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_config_enable_scff/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf
View File

@ -32,6 +32,7 @@ bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/blinking/blinking.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/full_testbench_without_self_checking/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2_latch
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_frame/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/multi_region_ql_memory_bank/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_shift_register/config/task.conf
View File

@ -32,6 +32,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain/config/task.conf
View File

@ -32,6 +32,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr/config/task.conf
View File

@ -32,6 +32,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_use_wlr/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_frame/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf
View File

@ -32,6 +32,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf
View File

@ -29,6 +29,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/c
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = counter_4bit_2clock
bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml
bench1_top = and2_latch_2clock

1
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf
View File

@ -30,6 +30,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf
View File

@ -28,6 +28,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf
View File

@ -32,6 +32,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_cha
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
bench0_top = and2

1
openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf
View File

@ -31,6 +31,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/c
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys

1
openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf
View File

@ -29,6 +29,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf
View File

@ -29,6 +29,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf
View File

@ -29,6 +29,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf
View File

@ -29,6 +29,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking/config/task.conf
View File

@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2_latch
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/tile_organization/bottom_right_custom_pins/config/task.conf
View File

@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40n
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = or2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/tile_organization/tileable_io/config/task.conf
View File

@ -28,6 +28,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = or2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/tile_organization/top_left_custom_pins/config/task.conf
View File

@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40n
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = or2
bench0_chan_width = 300

1
openfpga_flow/tasks/basic_tests/tile_organization/top_right_custom_pins/config/task.conf
View File

@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40n
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = or2
bench0_chan_width = 300

1
openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf
View File

@ -40,6 +40,7 @@ bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/c
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
#bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys

1
openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf
View File

@ -67,6 +67,7 @@ bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/*.v
bench22=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/*.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
bench0_top = ac97_top
bench1_top = eth_top

1
openfpga_flow/tasks/benchmark_sweep/mac_units/config/task.conf
View File

@ -48,6 +48,7 @@ bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_3
bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
bench0_top = mac_2
bench1_top = mac_4

1
openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = clock_divider
bench0_chan_width = 300

1
openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf
View File

@ -65,6 +65,7 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovisio
#bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
# Benchmark ch_intrinsics
bench0_top = bgm

1
openfpga_flow/tasks/ci_tests/config/task.conf
View File

@ -32,6 +32,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
bench0=${PATH:DESIGN_PATH}
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top =${PATH:DESIGN_TOP}
#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v

1
openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_flatten/config/task.conf
View File

@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register/config/task.conf
View File

@ -32,6 +32,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

1
openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf
View File

@ -38,6 +38,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_ch
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/*
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
bench0_top = SAPone

1
openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf
View File

@ -30,6 +30,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_re
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/*.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = RISC_core_top
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_auto/config/task.conf
View File

@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/fpga_bitstream/overload_mux_default_path/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2_pipelined
bench0_chan_width = 300

1
openfpga_flow/tasks/fpga_bitstream/report_bitstream_distribution/custom_depth/config/task.conf
View File

@ -28,6 +28,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/fpga_bitstream/report_bitstream_distribution/default_depth/config/task.conf
View File

@ -28,6 +28,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/fpga_bitstream/write_io_mapping/config/task.conf
View File

@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/fpga_verilog/bram/dpram1k/config/task.conf
View File

@ -33,6 +33,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_ch
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_1k/dual_port_ram_1k.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = dual_port_ram_1k

1
openfpga_flow/tasks/fpga_verilog/bram/wide_dpram1k/config/task.conf
View File

@ -33,6 +33,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_ch
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_1k/dual_port_ram_1k.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = dual_port_ram_1k

1
openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/task.conf
View File

@ -36,6 +36,7 @@ bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_12
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys

1
openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf
View File

@ -36,6 +36,7 @@ bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys

1
openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8_reg/config/task.conf
View File

@ -33,6 +33,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.x
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult_2_pipelined/mult_2_pipelined.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys

1
openfpga_flow/tasks/fpga_verilog/dsp/wide_multi_mode_mult_16x16/config/task.conf
View File

@ -34,6 +34,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys

1
openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf
View File

@ -28,6 +28,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2_pipelined
bench0_chan_width = 300

1
openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf
View File

@ -29,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
bench0_chan_width = 300

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