diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index 69482ec52..f74c35acc 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -209,7 +209,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, /* Create bitstream from grids */ VTR_LOGV(verbose, "Building grid bitstream...\n"); build_grid_bitstream(bitstream_manager, top_block, - openfpga_ctx.module_graph(), openfpga_ctx.fabric_tile(), + openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), openfpga_ctx.fabric_tile(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), vpr_ctx.device().grid, 0, vpr_ctx.atom(), openfpga_ctx.vpr_device_annotation(), diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index df3f070aa..2440a38ef 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -180,7 +180,9 @@ static void build_physical_block_pin_interc_bitstream( BitstreamManager& bitstream_manager, std::map& grouped_mem_inst_scoreboard, const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprBitstreamAnnotation& bitstream_annotation, @@ -290,6 +292,7 @@ static void build_physical_block_pin_interc_bitstream( std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); + mem_module_name = module_name_map.name(mem_module_name); ModuleId mux_mem_module = module_manager.find_module(mem_module_name); VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module)); ModulePortId mux_mem_out_port_id = module_manager.find_module_port( @@ -302,6 +305,9 @@ static void build_physical_block_pin_interc_bitstream( std::string feedthru_mem_block_name = generate_mux_subckt_name( circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX)); + if (module_name_map.name_exist(feedthru_mem_block_name)) { + feedthru_mem_block_name = module_name_map.name(feedthru_mem_block_name); + } ModuleId feedthru_mem_module = module_manager.find_module(feedthru_mem_block_name); if (module_manager.valid_module_id(feedthru_mem_module)) { @@ -375,7 +381,9 @@ static void build_physical_block_interc_port_bitstream( BitstreamManager& bitstream_manager, std::map& grouped_mem_inst_scoreboard, const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprBitstreamAnnotation& bitstream_annotation, @@ -390,7 +398,7 @@ static void build_physical_block_interc_port_bitstream( ++ipin) { build_physical_block_pin_interc_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, circuit_lib, mux_lib, + parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, physical_pb, &(physical_pb_graph_node->input_pins[iport][ipin]), physical_mode, verbose); @@ -404,7 +412,7 @@ static void build_physical_block_interc_port_bitstream( ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { build_physical_block_pin_interc_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, circuit_lib, mux_lib, + parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, physical_pb, &(physical_pb_graph_node->output_pins[iport][ipin]), physical_mode, verbose); @@ -418,7 +426,7 @@ static void build_physical_block_interc_port_bitstream( ++ipin) { build_physical_block_pin_interc_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, circuit_lib, mux_lib, + parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, physical_pb, &(physical_pb_graph_node->clock_pins[iport][ipin]), physical_mode, verbose); @@ -439,7 +447,9 @@ static void build_physical_block_interc_bitstream( BitstreamManager& bitstream_manager, std::map& grouped_mem_inst_scoreboard, const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprBitstreamAnnotation& bitstream_annotation, @@ -463,7 +473,7 @@ static void build_physical_block_interc_bitstream( */ build_physical_block_interc_port_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, - module_manager, circuit_lib, mux_lib, atom_ctx, device_annotation, + module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, physical_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode, verbose); @@ -486,13 +496,13 @@ static void build_physical_block_interc_bitstream( /* For each child_pb_graph_node input pins*/ build_physical_block_interc_port_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, circuit_lib, mux_lib, + parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode, verbose); /* For clock pins, we should do the same work */ build_physical_block_interc_port_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, circuit_lib, mux_lib, + parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode, verbose); } @@ -697,7 +707,9 @@ static void rec_build_physical_block_bitstream( BitstreamManager& bitstream_manager, std::map& grouped_mem_inst_scoreboard, const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprBitstreamAnnotation& bitstream_annotation, const e_side& border_side, @@ -713,6 +725,7 @@ static void rec_build_physical_block_bitstream( /* Early exit if this parent module has no configurable child modules */ std::string pb_module_name = generate_physical_block_module_name(physical_pb_type); + pb_module_name = module_name_map.name(pb_module_name); ModuleId pb_module = module_manager.find_module(pb_module_name); VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); @@ -758,7 +771,7 @@ static void rec_build_physical_block_bitstream( /* Go recursively */ rec_build_physical_block_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, - module_manager, circuit_lib, mux_lib, atom_ctx, device_annotation, + module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, border_side, physical_pb, child_pb, &(physical_pb_graph_node ->child_pb_graph_nodes[physical_mode->index][ipb][jpb]), @@ -804,7 +817,7 @@ static void rec_build_physical_block_bitstream( /* Generate the bitstream for the interconnection in this physical block */ build_physical_block_interc_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, - module_manager, circuit_lib, mux_lib, atom_ctx, device_annotation, + module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, physical_pb_graph_node, physical_pb, physical_mode, verbose); } @@ -817,7 +830,9 @@ static void rec_build_physical_block_bitstream( *******************************************************************/ static void build_physical_block_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, - const ModuleManager& module_manager, const FabricTile& fabric_tile, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricTile& fabric_tile, const FabricTileId& curr_tile, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, @@ -835,6 +850,7 @@ static void build_physical_block_bitstream( std::string grid_module_name = generate_grid_block_module_name( grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), border_side); + grid_module_name = module_name_map.name(grid_module_name); ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); @@ -916,7 +932,7 @@ static void build_physical_block_bitstream( /* Recursively traverse the pb_graph and generate bitstream */ rec_build_physical_block_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - grid_configurable_block, module_manager, circuit_lib, mux_lib, + grid_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, border_side, PhysicalPb(), PhysicalPbId::INVALID(), lb_type->pb_graph_head, z, verbose); @@ -932,7 +948,7 @@ static void build_physical_block_bitstream( /* Recursively traverse the pb_graph and generate bitstream */ rec_build_physical_block_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - grid_configurable_block, module_manager, circuit_lib, mux_lib, + grid_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, bitstream_annotation, border_side, phy_pb, top_pb_id, pb_graph_head, z, verbose); } @@ -948,7 +964,9 @@ static void build_physical_block_bitstream( *******************************************************************/ void build_grid_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, - const ModuleManager& module_manager, const FabricTile& fabric_tile, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, @@ -992,7 +1010,7 @@ void build_grid_bitstream( } build_physical_block_bitstream( - bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile, + bitstream_manager, parent_block, module_manager, module_name_map, fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, place_annotation, bitstream_annotation, grids, layer, grid_coord, NUM_SIDES, verbose); @@ -1040,7 +1058,7 @@ void build_grid_bitstream( } build_physical_block_bitstream( - bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile, + bitstream_manager, parent_block, module_manager, module_name_map, fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, place_annotation, bitstream_annotation, grids, layer, io_coordinate, io_side, verbose); diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.h b/openfpga/src/fpga_bitstream/build_grid_bitstream.h index a3f4f2603..c4b315253 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.h @@ -11,6 +11,7 @@ #include "device_grid.h" #include "fabric_tile.h" #include "module_manager.h" +#include "module_name_map.h" #include "mux_library.h" #include "vpr_bitstream_annotation.h" #include "vpr_clustering_annotation.h" @@ -27,7 +28,9 @@ namespace openfpga { void build_grid_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, - const ModuleManager& module_manager, const FabricTile& fabric_tile, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index 2daf50108..dadeddb97 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -33,7 +33,9 @@ namespace openfpga { *******************************************************************/ static void build_switch_block_mux_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& mux_mem_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const RRGraphView& rr_graph, const RRNodeId& cur_rr_node, const std::vector& drive_rr_nodes, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, @@ -94,6 +96,7 @@ static void build_switch_block_mux_bitstream( std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); + mem_module_name = module_name_map.name(mem_module_name); ModuleId mux_mem_module = module_manager.find_module(mem_module_name); VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module)); ModulePortId mux_mem_out_port_id = module_manager.find_module_port( @@ -152,7 +155,9 @@ static void build_switch_block_mux_bitstream( static void build_switch_block_interc_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& sb_configurable_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const RRGraphView& rr_graph, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGSB& rr_gsb, @@ -190,7 +195,7 @@ static void build_switch_block_interc_bitstream( bitstream_manager.block_name(sb_configurable_block).c_str()); /* This is a routing multiplexer! Generate bitstream */ build_switch_block_mux_bitstream( - bitstream_manager, mux_mem_block, module_manager, circuit_lib, mux_lib, + bitstream_manager, mux_mem_block, module_manager, module_name_map, circuit_lib, mux_lib, rr_graph, cur_rr_node, driver_rr_nodes, atom_ctx, device_annotation, routing_annotation, verbose); } /*Nothing should be done else*/ @@ -209,7 +214,8 @@ static void build_switch_block_interc_bitstream( *******************************************************************/ static void build_switch_block_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& sb_config_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, @@ -229,7 +235,7 @@ static void build_switch_block_bitstream( continue; } build_switch_block_interc_bitstream( - bitstream_manager, sb_config_block, module_manager, circuit_lib, + bitstream_manager, sb_config_block, module_manager, module_name_map, circuit_lib, mux_lib, rr_graph, atom_ctx, device_annotation, routing_annotation, rr_gsb, side_manager.get_side(), itrack, verbose); } @@ -245,7 +251,9 @@ static void build_switch_block_bitstream( *******************************************************************/ static void build_connection_block_mux_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& mux_mem_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, @@ -310,6 +318,7 @@ static void build_connection_block_mux_bitstream( std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); + mem_module_name = module_name_map.name(mem_module_name); ModuleId mux_mem_module = module_manager.find_module(mem_module_name); VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module)); ModulePortId mux_mem_out_port_id = module_manager.find_module_port( @@ -368,7 +377,9 @@ static void build_connection_block_mux_bitstream( static void build_connection_block_interc_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& cb_configurable_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, @@ -402,7 +413,7 @@ static void build_connection_block_interc_bitstream( bitstream_manager.block_name(cb_configurable_block).c_str()); /* This is a routing multiplexer! Generate bitstream */ build_connection_block_mux_bitstream( - bitstream_manager, mux_mem_block, module_manager, circuit_lib, mux_lib, + bitstream_manager, mux_mem_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph, rr_gsb, cb_ipin_side, ipin_index, verbose); } /*Nothing should be done else*/ @@ -422,7 +433,9 @@ static void build_connection_block_interc_bitstream( static void build_connection_block_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& cb_configurable_block, - const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, @@ -439,7 +452,7 @@ static void build_connection_block_bitstream( VTR_LOGV(verbose, "\tGenerating bitstream for IPIN at '%s' side\n", side_manager.to_string().c_str()); build_connection_block_interc_bitstream( - bitstream_manager, cb_configurable_block, module_manager, circuit_lib, + bitstream_manager, cb_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph, rr_gsb, cb_ipin_side, inode, verbose); } @@ -580,7 +593,7 @@ static void build_connection_block_bitstreams( } build_connection_block_bitstream( - bitstream_manager, cb_configurable_block, module_manager, circuit_lib, + bitstream_manager, cb_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph, rr_gsb, cb_type, verbose); @@ -712,7 +725,7 @@ void build_routing_bitstream( } build_switch_block_bitstream( - bitstream_manager, sb_configurable_block, module_manager, circuit_lib, + bitstream_manager, sb_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph, rr_gsb, verbose); diff --git a/openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/module_names.xml b/openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/module_names.xml index 8729ed878..0345c1252 100644 --- a/openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/module_names.xml +++ b/openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/module_names.xml @@ -1,4 +1,10 @@ + + + + + +