From ee59bdb675d02220ee02e3daff20e9df73108557 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Jun 2023 18:55:34 -0700 Subject: [PATCH] [core] code format --- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 9 ++- .../fabric/build_fabric_io_location_map.cpp | 3 +- .../src/fabric/build_routing_module_utils.cpp | 8 +- openfpga/src/fabric/build_top_module.cpp | 25 ++++--- .../fabric/build_top_module_connection.cpp | 19 ++--- .../src/fabric/build_top_module_utils.cpp | 7 +- .../fpga_bitstream/build_grid_bitstream.cpp | 4 +- .../src/tile_direct/build_tile_direct.cpp | 74 +++++++++++-------- .../utils/openfpga_physical_tile_utils.cpp | 3 +- 9 files changed, 87 insertions(+), 65 deletions(-) diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 949b3dd9c..952a495d1 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -39,7 +39,8 @@ static void update_cluster_pin_with_post_routing_results( const e_side& border_side, const size_t& z, const bool& verbose) { /* Handle each pin */ auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id); - auto physical_tile = device_ctx.grid.get_physical_type(grid_coord.x(), grid_coord.y()); + auto physical_tile = + device_ctx.grid.get_physical_type(grid_coord.x(), grid_coord.y()); for (int j = 0; j < logical_block->pb_type->num_pins; j++) { /* Get the ptc num for the pin in rr_graph, we need t consider the z offset @@ -222,10 +223,10 @@ void update_pb_pin_with_post_routing_results( for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coord : io_coordinates[io_side]) { - t_physical_tile_type_ptr phy_tile_type = device_ctx.grid.get_physical_type(io_coord.x(), io_coord.y()); + t_physical_tile_type_ptr phy_tile_type = + device_ctx.grid.get_physical_type(io_coord.x(), io_coord.y()); /* Bypass EMPTY grid */ - if (true == - is_empty_type(phy_tile_type)) { + if (true == is_empty_type(phy_tile_type)) { continue; } /* Get the mapped blocks to this grid */ diff --git a/openfpga/src/fabric/build_fabric_io_location_map.cpp b/openfpga/src/fabric/build_fabric_io_location_map.cpp index b84fd333a..f099e546c 100644 --- a/openfpga/src/fabric/build_fabric_io_location_map.cpp +++ b/openfpga/src/fabric/build_fabric_io_location_map.cpp @@ -50,7 +50,8 @@ IoLocationMap build_fabric_io_location_map(const ModuleManager& module_manager, ModuleId child = module_manager.io_children(top_module)[ichild]; vtr::Point coord = module_manager.io_child_coordinates(top_module)[ichild]; - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(coord.x(), coord.y()); + t_physical_tile_type_ptr phy_tile_type = + grids.get_physical_type(coord.x(), coord.y()); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp index 83b167a73..64a1472ea 100644 --- a/openfpga/src/fabric/build_routing_module_utils.cpp +++ b/openfpga/src/fabric/build_routing_module_utils.cpp @@ -76,8 +76,8 @@ std::string generate_sb_module_grid_port_name( /* Collect the attributes of the rr_node required to generate the port name */ int pin_id = rr_graph.node_pin_num(rr_node); e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node); - t_physical_tile_type_ptr physical_tile = - vpr_device_grid.get_physical_type(rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node)); + t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type( + rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node)); int pin_width_offset = physical_tile->pin_width_offset[pin_id]; int pin_height_offset = physical_tile->pin_height_offset[pin_id]; BasicPort pin_info = @@ -110,8 +110,8 @@ std::string generate_cb_module_grid_port_name( /* Collect the attributes of the rr_node required to generate the port name */ int pin_id = rr_graph.node_pin_num(rr_node); e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node); - t_physical_tile_type_ptr physical_tile = - vpr_device_grid.get_physical_type(rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node)); + t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type( + rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node)); int pin_width_offset = physical_tile->pin_width_offset[pin_id]; int pin_height_offset = physical_tile->pin_height_offset[pin_id]; BasicPort pin_info = diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index cfe9ac7c9..395ca26f2 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -108,15 +108,15 @@ static vtr::Matrix add_top_module_grid_instances( for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(io_coordinate.x(), io_coordinate.y()); + t_physical_tile_type_ptr phy_tile_type = + grids.get_physical_type(io_coordinate.x(), io_coordinate.y()); /* Bypass EMPTY grid */ - if (true == - is_empty_type(phy_tile_type)) { + if (true == is_empty_type(phy_tile_type)) { continue; } /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ if ((0 < grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) || - (0 < grids.get_height_offset(io_coordinate.x(),io_coordinate.y()))) { + (0 < grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) { /* Find the root of this grid, the instance id should be valid. * We just copy it here */ @@ -134,10 +134,8 @@ static vtr::Matrix add_top_module_grid_instances( /* Add a grid module to top_module*/ grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = - add_top_module_grid_instance( - module_manager, top_module, - phy_tile_type, io_side, - io_coordinate); + add_top_module_grid_instance(module_manager, top_module, phy_tile_type, + io_side, io_coordinate); } } @@ -160,8 +158,9 @@ static vtr::Matrix add_top_module_grid_instances( /* Find the root of this grid, the instance id should be valid. * We just copy it here */ - vtr::Point root_grid_coord(ix - grids.get_width_offset(ix, iy), - iy - grids.get_height_offset(ix, iy)); + vtr::Point root_grid_coord( + ix - grids.get_width_offset(ix, iy), + iy - grids.get_height_offset(ix, iy)); VTR_ASSERT(size_t(-1) != grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]); grid_instance_ids[ix][iy] = @@ -326,7 +325,8 @@ static void add_top_module_io_children( for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coord : io_coordinates[io_side]) { - t_physical_tile_type_ptr grid_type = grids.get_physical_type(io_coord.x(), io_coord.y()); + t_physical_tile_type_ptr grid_type = + grids.get_physical_type(io_coord.x(), io_coord.y()); /* Bypass EMPTY grid */ if (true == is_empty_type(grid_type)) { continue; @@ -394,7 +394,8 @@ static void add_top_module_io_children( /* Now walk through the coordinates */ for (vtr::Point coord : coords) { - t_physical_tile_type_ptr grid_type = grids.get_physical_type(coord.x(), coord.y()); + t_physical_tile_type_ptr grid_type = + grids.get_physical_type(coord.x(), coord.y()); /* Bypass EMPTY grid */ if (true == is_empty_type(grid_type)) { continue; diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 15dbd04f3..de4402c51 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1038,7 +1038,8 @@ static int build_top_module_global_net_from_grid_modules( /* Spot the port from child modules from core grids */ for (size_t ix = start_coord.x(); ix < end_coord.x(); ++ix) { for (size_t iy = start_coord.y(); iy < end_coord.y(); ++iy) { - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(ix, iy); + t_physical_tile_type_ptr phy_tile_type = + grids.get_physical_type(ix, iy); /* Bypass EMPTY tiles */ if (true == is_empty_type(phy_tile_type)) { continue; @@ -1068,23 +1069,23 @@ static int build_top_module_global_net_from_grid_modules( /* Walk through all the grids on the perimeter, which are I/O grids */ for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(io_coordinate.x(), io_coordinate.y()); + t_physical_tile_type_ptr phy_tile_type = + grids.get_physical_type(io_coordinate.x(), io_coordinate.y()); /* Bypass EMPTY grid */ - if (true == - is_empty_type(phy_tile_type)) { + if (true == is_empty_type(phy_tile_type)) { continue; } /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) || - (0 < grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) { + if ((0 < + grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) || + (0 < + grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) { continue; } /* Bypass the tiles whose names do not match */ - if (std::string( - phy_tile_type->name) != - tile_name) { + if (std::string(phy_tile_type->name) != tile_name) { continue; } diff --git a/openfpga/src/fabric/build_top_module_utils.cpp b/openfpga/src/fabric/build_top_module_utils.cpp index f9c4f53ac..b75c2bafc 100644 --- a/openfpga/src/fabric/build_top_module_utils.cpp +++ b/openfpga/src/fabric/build_top_module_utils.cpp @@ -28,11 +28,12 @@ std::string generate_grid_block_module_name_in_top_module( /* Determine if the grid locates at the border */ vtr::Point device_size(grids.width(), grids.height()); e_side border_side = find_grid_border_side(device_size, grid_coord); - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coord.x(), grid_coord.y()); + t_physical_tile_type_ptr phy_tile_type = + grids.get_physical_type(grid_coord.x(), grid_coord.y()); return generate_grid_block_module_name( - prefix, std::string(phy_tile_type->name), - is_io_type(phy_tile_type), border_side); + prefix, std::string(phy_tile_type->name), is_io_type(phy_tile_type), + border_side); } /******************************************************************** diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index 4a3945c00..35a6556dc 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -859,8 +859,8 @@ void build_grid_bitstream( for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { /* Bypass EMPTY grid */ - if (true == - is_empty_type(grids.get_physical_type(io_coordinate.x(), io_coordinate.y()))) { + if (true == is_empty_type(grids.get_physical_type(io_coordinate.x(), + io_coordinate.y()))) { continue; } /* Skip height > 1 tiles (mostly heterogeneous blocks) */ diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp index c3dd24c36..e2c46cf12 100644 --- a/openfpga/src/tile_direct/build_tile_direct.cpp +++ b/openfpga/src/tile_direct/build_tile_direct.cpp @@ -401,7 +401,8 @@ static void build_inner_column_row_tile_direct( /* Walk through the device fabric and find the grid that fit the source */ for (size_t x = 0; x < device_ctx.grid.width(); ++x) { for (size_t y = 0; y < device_ctx.grid.height(); ++y) { - t_physical_tile_type_ptr from_phy_tile_type = device_ctx.grid.get_physical_type(x, y); + t_physical_tile_type_ptr from_phy_tile_type = + device_ctx.grid.get_physical_type(x, y); /* Bypass empty grid */ if (true == is_empty_type(from_phy_tile_type)) { continue; @@ -436,10 +437,11 @@ static void build_inner_column_row_tile_direct( continue; } - t_physical_tile_type_ptr to_phy_tile_type = device_ctx.grid.get_physical_type(to_grid_coord.x(), to_grid_coord.y()); + t_physical_tile_type_ptr to_phy_tile_type = + device_ctx.grid.get_physical_type(to_grid_coord.x(), + to_grid_coord.y()); /* Bypass the grid that does not fit the from_tile name */ - if (to_tile_name != - std::string(to_phy_tile_type->name)) { + if (to_tile_name != std::string(to_phy_tile_type->name)) { continue; } @@ -449,11 +451,13 @@ static void build_inner_column_row_tile_direct( */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - std::vector to_pins = find_physical_tile_pin_id( - to_phy_tile_type, - device_ctx.grid.get_width_offset(to_grid_coord.x(), to_grid_coord.y()), - device_ctx.grid.get_height_offset(to_grid_coord.x(), to_grid_coord.y()), - to_tile_port, to_side); + std::vector to_pins = + find_physical_tile_pin_id(to_phy_tile_type, + device_ctx.grid.get_width_offset( + to_grid_coord.x(), to_grid_coord.y()), + device_ctx.grid.get_height_offset( + to_grid_coord.x(), to_grid_coord.y()), + to_tile_port, to_side); /* If nothing found, we can continue */ if (0 == to_pins.size()) { continue; @@ -590,11 +594,14 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - std::vector from_pins = find_physical_tile_pin_id( - device_ctx.grid.get_physical_type(from_grid_coord.x(), from_grid_coord.y()), - device_ctx.grid.get_width_offset(from_grid_coord.x(), from_grid_coord.y()), - device_ctx.grid.get_height_offset(from_grid_coord.x(), from_grid_coord.y()), - from_tile_port, from_side); + std::vector from_pins = + find_physical_tile_pin_id(device_ctx.grid.get_physical_type( + from_grid_coord.x(), from_grid_coord.y()), + device_ctx.grid.get_width_offset( + from_grid_coord.x(), from_grid_coord.y()), + device_ctx.grid.get_height_offset( + from_grid_coord.x(), from_grid_coord.y()), + from_tile_port, from_side); /* If nothing found, we can continue */ if (0 == from_pins.size()) { continue; @@ -618,11 +625,14 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - std::vector to_pins = find_physical_tile_pin_id( - device_ctx.grid.get_physical_type(to_grid_coord.x(), to_grid_coord.y()), - device_ctx.grid.get_width_offset(to_grid_coord.x(), to_grid_coord.y()), - device_ctx.grid.get_height_offset(to_grid_coord.x(), to_grid_coord.y()), - to_tile_port, to_side); + std::vector to_pins = + find_physical_tile_pin_id(device_ctx.grid.get_physical_type( + to_grid_coord.x(), to_grid_coord.y()), + device_ctx.grid.get_width_offset( + to_grid_coord.x(), to_grid_coord.y()), + device_ctx.grid.get_height_offset( + to_grid_coord.x(), to_grid_coord.y()), + to_tile_port, to_side); /* If nothing found, we can continue */ if (0 == to_pins.size()) { continue; @@ -697,11 +707,14 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - std::vector from_pins = find_physical_tile_pin_id( - device_ctx.grid.get_physical_type(from_grid_coord.x(), from_grid_coord.y()), - device_ctx.grid.get_width_offset(from_grid_coord.x(), from_grid_coord.y()), - device_ctx.grid.get_height_offset(from_grid_coord.x(), from_grid_coord.y()), - from_tile_port, from_side); + std::vector from_pins = + find_physical_tile_pin_id(device_ctx.grid.get_physical_type( + from_grid_coord.x(), from_grid_coord.y()), + device_ctx.grid.get_width_offset( + from_grid_coord.x(), from_grid_coord.y()), + device_ctx.grid.get_height_offset( + from_grid_coord.x(), from_grid_coord.y()), + from_tile_port, from_side); /* If nothing found, we can continue */ if (0 == from_pins.size()) { continue; @@ -725,11 +738,14 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - std::vector to_pins = find_physical_tile_pin_id( - device_ctx.grid.get_physical_type(to_grid_coord.x(), to_grid_coord.y()), - device_ctx.grid.get_width_offset(to_grid_coord.x(), to_grid_coord.y()), - device_ctx.grid.get_height_offset(to_grid_coord.x(), to_grid_coord.y()), - to_tile_port, to_side); + std::vector to_pins = + find_physical_tile_pin_id(device_ctx.grid.get_physical_type( + to_grid_coord.x(), to_grid_coord.y()), + device_ctx.grid.get_width_offset( + to_grid_coord.x(), to_grid_coord.y()), + device_ctx.grid.get_height_offset( + to_grid_coord.x(), to_grid_coord.y()), + to_tile_port, to_side); /* If nothing found, we can continue */ if (0 == to_pins.size()) { continue; diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 7ab62538a..2e599eb1b 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -108,7 +108,8 @@ std::set find_physical_io_tile_located_sides( for (const e_side& fpga_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[fpga_side]) { /* If located in center, we add a NUM_SIDES and finish */ - if (physical_tile == grids.get_physical_type(io_coordinate.x(), io_coordinate.y())) { + if (physical_tile == + grids.get_physical_type(io_coordinate.x(), io_coordinate.y())) { io_sides.insert(fpga_side); break; }