From 9bbf2144568e35e2bf99ed86041bf58eb9cb3078 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 29 Jan 2021 17:00:17 -0700 Subject: [PATCH 01/40] [Arch] Update the caravel architecture --- ...ister_scan_chain_nonLR_caravel_io_skywater130nm.xml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 07c6ba848..b7c308935 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -437,10 +437,12 @@ - - - - + + + + + + From 6ede799c1643b76516bb6a0da2ef20aea42b4617 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 10:15:35 -0700 Subject: [PATCH 02/40] [Arch] Add openfpga architecture for the QLSOFA --- ...avel_io_skywater130nm_fdhd_cc_openfpga.xml | 272 ++++++++++++++++++ 1 file changed, 272 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml new file mode 100644 index 000000000..18ff863d6 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -0,0 +1,272 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 39543f794517aa50e64c26025e60c33ef1fd9659 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 10:23:46 -0700 Subject: [PATCH 03/40] [HDL] Add carry mux2 to cell library --- .../openfpga_cell_library/verilog/mux2.v | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/openfpga_flow/openfpga_cell_library/verilog/mux2.v b/openfpga_flow/openfpga_cell_library/verilog/mux2.v index 66d204a99..297baedb6 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/mux2.v +++ b/openfpga_flow/openfpga_cell_library/verilog/mux2.v @@ -53,3 +53,28 @@ module MUX2( `endif endmodule + +//----------------------------------------------------- +// Design Name : CARRY_MUX2 +// File Name : mux2.v +// Function : Standard cell (static gate) implementation +// of 2-input multiplexers to be used by carry logic +// Coder : Xifan Tang +//----------------------------------------------------- + +module CARRY_MUX2( + // iVerilog is buggy on the 'input A' declaration when deposit initial + // values + input [0:0] A, // Data input 0 + input [0:0] B, // Data input 1 + input [0:0] S0, // Select port + output [0:0] Y // Data output + ); + + assign Y = S0 ? B : A; + +// Note: +// MUX2 appears in the datapath logic driven by carry-in and LUT outputs +// where initial values and signal deposit are not required + +endmodule From e0e2506e32207bcc7d92856d0f8e7c6aa3bd1c45 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 10:33:08 -0700 Subject: [PATCH 04/40] [HDL] Remove redundant comments --- openfpga_flow/openfpga_cell_library/verilog/mux2.v | 2 -- 1 file changed, 2 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/mux2.v b/openfpga_flow/openfpga_cell_library/verilog/mux2.v index 297baedb6..bfa527959 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/mux2.v +++ b/openfpga_flow/openfpga_cell_library/verilog/mux2.v @@ -63,8 +63,6 @@ endmodule //----------------------------------------------------- module CARRY_MUX2( - // iVerilog is buggy on the 'input A' declaration when deposit initial - // values input [0:0] A, // Data input 0 input [0:0] B, // Data input 1 input [0:0] S0, // Select port From 0eb949b85aaf4945ad1895c92701b3c6d161e1ad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 10:34:32 -0700 Subject: [PATCH 05/40] [Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA --- ...scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 18ff863d6..0e26f8a37 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -196,7 +196,7 @@ - + @@ -204,7 +204,7 @@ - + @@ -249,7 +249,7 @@ - + From 9cce411eda09f52eff92e6821685ef9abfd31c79 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 10:42:24 -0700 Subject: [PATCH 06/40] [Test] Add adder test cases --- .../adder/hard_adder/config/task.conf | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf new file mode 100644 index 000000000..0764beeb3 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From af630dab1e32527d8f5dec335d399b05208e7101 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 10:53:38 -0700 Subject: [PATCH 07/40] [Test] Add soft adder test case. This is placeholder. Test arch will be elaborated --- .../adder/soft_adder/config/task.conf | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf new file mode 100644 index 000000000..6b7b431bc --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +external_fabric_key_file= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From a80acfb5473de818dc22632c7dc91ed9c85d2d83 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 11:16:12 -0700 Subject: [PATCH 08/40] [Test] Add new test case to CI script --- .github/workflows/fpga_verilog_reg_test.sh | 5 ++- .../fpga_verilog/hard_adder/config/task.conf | 38 ------------------- 2 files changed, 4 insertions(+), 39 deletions(-) delete mode 100644 openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/.github/workflows/fpga_verilog_reg_test.sh index b7a47508e..7b7aad6b0 100755 --- a/.github/workflows/fpga_verilog_reg_test.sh +++ b/.github/workflows/fpga_verilog_reg_test.sh @@ -30,7 +30,10 @@ echo -e "Testing Verilog generation with VPR's untileable routing architecture " run-task fpga_verilog/untileable --debug --show_thread_logs echo -e "Testing Verilog generation with hard adder chain in CLBs "; -run-task fpga_verilog/hard_adder --debug --show_thread_logs +run-task fpga_verilog/adder/hard_adder --debug --show_thread_logs + +echo -e "Testing Verilog generation with soft adder chain in CLBs "; +run-task fpga_verilog/adder/soft_adder --debug --show_thread_logs echo -e "Testing Verilog generation with 16k block RAMs "; run-task fpga_verilog/bram/dpram16k --debug --show_thread_logs diff --git a/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf deleted file mode 100644 index 0764beeb3..000000000 --- a/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf +++ /dev/null @@ -1,38 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif - -[SYNTHESIS_PARAM] -bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v -bench0_chan_width = 300 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= -vpr_fpga_verilog_formal_verification_top_netlist= From 940dce469a629edd019e7659fb5a357ba6805c98 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 11:19:47 -0700 Subject: [PATCH 09/40] [Test] Bug fix for test case configuration --- .../tasks/fpga_verilog/adder/soft_adder/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index 6b7b431bc..98c283a53 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=vpr_blif [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml external_fabric_key_file= From fb05e1a938b2bcb9fd43bbd56b4e89a3ddf7ccca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 11:27:21 -0700 Subject: [PATCH 10/40] [Arch] bug fix due to using openfpga cell library --- ...ter_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 0e26f8a37..0b2b99a8b 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -172,7 +172,7 @@ - + From e4abe263c328c7afd7fe10bff86ded1d7d52b3a8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 11:29:27 -0700 Subject: [PATCH 11/40] [Arch] Bug fix --- ...ter_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 0b2b99a8b..8dbf6a29a 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -196,7 +196,7 @@ - + From b215b868c10c35b60b06ae6526a263631862304c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 11:35:25 -0700 Subject: [PATCH 12/40] [HDL] Bug fix in HDL netlist due to port name mismatching --- openfpga_flow/openfpga_cell_library/verilog/mux2.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/mux2.v b/openfpga_flow/openfpga_cell_library/verilog/mux2.v index bfa527959..fed7858ba 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/mux2.v +++ b/openfpga_flow/openfpga_cell_library/verilog/mux2.v @@ -63,13 +63,13 @@ endmodule //----------------------------------------------------- module CARRY_MUX2( - input [0:0] A, // Data input 0 - input [0:0] B, // Data input 1 - input [0:0] S0, // Select port + input [0:0] A0, // Data input 0 + input [0:0] A1, // Data input 1 + input [0:0] S, // Select port output [0:0] Y // Data output ); - assign Y = S0 ? B : A; + assign Y = S ? A1 : A0; // Note: // MUX2 appears in the datapath logic driven by carry-in and LUT outputs From 7f0f7a1c70bd3dac635a0ea8dacc83ebbd6f7427 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 12:05:04 -0700 Subject: [PATCH 13/40] [Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script --- .../micro_benchmark/adder_8/adder_8.blif | 39 +++++ .../micro_benchmark/adder_8/adder_8.v | 21 +++ .../micro_benchmark/adder_8/adder_8_out.v | 144 ++++++++++++++++++ 3 files changed, 204 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif new file mode 100644 index 000000000..5e984d0ec --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif @@ -0,0 +1,39 @@ +# Generated by Yosys 0.9+2406 (git sha1 e6ff764e, clang 12.0.0 -fPIC -Os) + +.model adder_8 +.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] cin +.outputs cout sum[0] sum[1] sum[2] sum[3] sum[4] sum[5] sum[6] sum[7] +.names $false +.names $true +1 +.names $undef +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7] in[1]=$false in[0]=$false lut2_out[1]=cout_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=cout_frac_lut4_lut4_out_lut2_out[0] lut4_out=cout +.param LUT 0110100101100001 +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] in[1]=a[7] in[0]=b[7] lut2_out[1]=sum_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_lut2_out[0] lut4_out=sum[7] +.param LUT 0110100101100001 +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] in[1]=a[6] in[0]=b[6] lut2_out[1]=sum_frac_lut4_lut4_out_1_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_1_lut2_out[0] lut4_out=sum[6] +.param LUT 0110100101100001 +.subckt carry_follower a=sum_frac_lut4_lut4_out_1_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] cin=sum_frac_lut4_lut4_out_1_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] in[1]=a[5] in[0]=b[5] lut2_out[1]=sum_frac_lut4_lut4_out_2_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_2_lut2_out[0] lut4_out=sum[5] +.param LUT 0110100101100001 +.subckt carry_follower a=sum_frac_lut4_lut4_out_2_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] cin=sum_frac_lut4_lut4_out_2_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] in[1]=a[4] in[0]=b[4] lut2_out[1]=sum_frac_lut4_lut4_out_3_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_3_lut2_out[0] lut4_out=sum[4] +.param LUT 0110100101100001 +.subckt carry_follower a=sum_frac_lut4_lut4_out_3_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] cin=sum_frac_lut4_lut4_out_3_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] in[1]=a[3] in[0]=b[3] lut2_out[1]=sum_frac_lut4_lut4_out_4_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_4_lut2_out[0] lut4_out=sum[3] +.param LUT 0110100101100001 +.subckt carry_follower a=sum_frac_lut4_lut4_out_4_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] cin=sum_frac_lut4_lut4_out_4_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] in[1]=a[2] in[0]=b[2] lut2_out[1]=sum_frac_lut4_lut4_out_5_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_5_lut2_out[0] lut4_out=sum[2] +.param LUT 0110100101100001 +.subckt carry_follower a=sum_frac_lut4_lut4_out_5_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] cin=sum_frac_lut4_lut4_out_5_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] in[1]=a[1] in[0]=b[1] lut2_out[1]=sum_frac_lut4_lut4_out_6_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_6_lut2_out[0] lut4_out=sum[1] +.param LUT 0110100101100001 +.subckt carry_follower a=sum_frac_lut4_lut4_out_6_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] cin=sum_frac_lut4_lut4_out_6_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_7_in in[1]=a[0] in[0]=b[0] lut2_out[1]=sum_frac_lut4_lut4_out_7_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_7_lut2_out[0] lut4_out=sum[0] +.param LUT 0110100101100001 +.subckt carry_follower a=sum_frac_lut4_lut4_out_7_lut2_out[1] cin=sum_frac_lut4_lut4_out_7_lut2_out[0] cout=sum_frac_lut4_lut4_out_7_in +.subckt adder_lut4 in[3]=$undef in[2]=$undef in[1]=cin in[0]=$undef lut2_out[1]=sum_frac_lut4_lut4_out_7_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_7_lut2_out[0] +.param LUT 1100000000000011 +.subckt carry_follower a=sum_frac_lut4_lut4_out_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] cin=sum_frac_lut4_lut4_out_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7] +.subckt carry_follower a=sum_frac_lut4_lut4_out_7_lut2_out[1] b=sum_frac_lut4_lut4_out_7_in cin=sum_frac_lut4_lut4_out_7_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] +.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v new file mode 100644 index 000000000..98a625263 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_8(cout, sum, a, b, cin); +parameter size = 8; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v new file mode 100644 index 000000000..810bca094 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v @@ -0,0 +1,144 @@ +/* Generated by Yosys 0.9+2406 (git sha1 e6ff764e, clang 12.0.0 -fPIC -Os) */ + +module adder_8(cout, sum, a, b, cin); + input [7:0] a; + input [7:0] b; + input cin; + output cout; + wire [0:1] cout_frac_lut4_lut4_out_lut2_out; + output [7:0] sum; + wire [0:1] sum_frac_lut4_lut4_out_1_lut2_out; + wire [0:1] sum_frac_lut4_lut4_out_2_lut2_out; + wire [0:1] sum_frac_lut4_lut4_out_3_lut2_out; + wire [0:1] sum_frac_lut4_lut4_out_4_lut2_out; + wire [0:1] sum_frac_lut4_lut4_out_5_lut2_out; + wire [0:1] sum_frac_lut4_lut4_out_6_lut2_out; + wire sum_frac_lut4_lut4_out_7_in; + wire [0:1] sum_frac_lut4_lut4_out_7_lut2_out; + wire [0:1] sum_frac_lut4_lut4_out_lut2_out; + wire [8:0] sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout; + frac_lut4 #( + .LUT(16'b0110100101100001) + ) cout_frac_lut4_lut4_out ( + .in({ 2'b00, sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7], 1'b0 }), + .lut2_out(cout_frac_lut4_lut4_out_lut2_out), + .lut4_out(cout) + ); + frac_lut4 #( + .LUT(16'b0110100101100001) + ) sum_frac_lut4_lut4_out ( + .in({ b[7], a[7], sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6], 1'b0 }), + .lut2_out(sum_frac_lut4_lut4_out_lut2_out), + .lut4_out(sum[7]) + ); + frac_lut4 #( + .LUT(16'b0110100101100001) + ) sum_frac_lut4_lut4_out_1 ( + .in({ b[6], a[6], sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5], 1'b0 }), + .lut2_out(sum_frac_lut4_lut4_out_1_lut2_out), + .lut4_out(sum[6]) + ); + carry_follower sum_frac_lut4_lut4_out_1_lut2_out_carry_follower_a ( + .a(sum_frac_lut4_lut4_out_1_lut2_out[1]), + .b(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5]), + .cin(sum_frac_lut4_lut4_out_1_lut2_out[0]), + .cout(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6]) + ); + frac_lut4 #( + .LUT(16'b0110100101100001) + ) sum_frac_lut4_lut4_out_2 ( + .in({ b[5], a[5], sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4], 1'b0 }), + .lut2_out(sum_frac_lut4_lut4_out_2_lut2_out), + .lut4_out(sum[5]) + ); + carry_follower sum_frac_lut4_lut4_out_2_lut2_out_carry_follower_a ( + .a(sum_frac_lut4_lut4_out_2_lut2_out[1]), + .b(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4]), + .cin(sum_frac_lut4_lut4_out_2_lut2_out[0]), + .cout(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5]) + ); + frac_lut4 #( + .LUT(16'b0110100101100001) + ) sum_frac_lut4_lut4_out_3 ( + .in({ b[4], a[4], sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3], 1'b0 }), + .lut2_out(sum_frac_lut4_lut4_out_3_lut2_out), + .lut4_out(sum[4]) + ); + carry_follower sum_frac_lut4_lut4_out_3_lut2_out_carry_follower_a ( + .a(sum_frac_lut4_lut4_out_3_lut2_out[1]), + .b(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3]), + .cin(sum_frac_lut4_lut4_out_3_lut2_out[0]), + .cout(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4]) + ); + frac_lut4 #( + .LUT(16'b0110100101100001) + ) sum_frac_lut4_lut4_out_4 ( + .in({ b[3], a[3], sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2], 1'b0 }), + .lut2_out(sum_frac_lut4_lut4_out_4_lut2_out), + .lut4_out(sum[3]) + ); + carry_follower sum_frac_lut4_lut4_out_4_lut2_out_carry_follower_a ( + .a(sum_frac_lut4_lut4_out_4_lut2_out[1]), + .b(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2]), + .cin(sum_frac_lut4_lut4_out_4_lut2_out[0]), + .cout(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3]) + ); + frac_lut4 #( + .LUT(16'b0110100101100001) + ) sum_frac_lut4_lut4_out_5 ( + .in({ b[2], a[2], sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1], 1'b0 }), + .lut2_out(sum_frac_lut4_lut4_out_5_lut2_out), + .lut4_out(sum[2]) + ); + carry_follower sum_frac_lut4_lut4_out_5_lut2_out_carry_follower_a ( + .a(sum_frac_lut4_lut4_out_5_lut2_out[1]), + .b(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1]), + .cin(sum_frac_lut4_lut4_out_5_lut2_out[0]), + .cout(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2]) + ); + frac_lut4 #( + .LUT(16'b0110100101100001) + ) sum_frac_lut4_lut4_out_6 ( + .in({ b[1], a[1], sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0], 1'b0 }), + .lut2_out(sum_frac_lut4_lut4_out_6_lut2_out), + .lut4_out(sum[1]) + ); + carry_follower sum_frac_lut4_lut4_out_6_lut2_out_carry_follower_a ( + .a(sum_frac_lut4_lut4_out_6_lut2_out[1]), + .b(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0]), + .cin(sum_frac_lut4_lut4_out_6_lut2_out[0]), + .cout(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1]) + ); + frac_lut4 #( + .LUT(16'b0110100101100001) + ) sum_frac_lut4_lut4_out_7 ( + .in({ b[0], a[0], sum_frac_lut4_lut4_out_7_in, 1'b0 }), + .lut2_out(sum_frac_lut4_lut4_out_7_lut2_out), + .lut4_out(sum[0]) + ); + carry_follower sum_frac_lut4_lut4_out_7_in_carry_follower_cout ( + .a(sum_frac_lut4_lut4_out_7_lut2_out[1]), + .b(), + .cin(sum_frac_lut4_lut4_out_7_lut2_out[0]), + .cout(sum_frac_lut4_lut4_out_7_in) + ); + frac_lut4 #( + .LUT(16'b1100000000000011) + ) sum_frac_lut4_lut4_out_7_lut2_out_frac_lut4_lut2_out ( + .in({ 1'bx, cin, 2'bxx }), + .lut2_out(sum_frac_lut4_lut4_out_7_lut2_out), + .lut4_out() + ); + carry_follower sum_frac_lut4_lut4_out_lut2_out_carry_follower_a ( + .a(sum_frac_lut4_lut4_out_lut2_out[1]), + .b(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6]), + .cin(sum_frac_lut4_lut4_out_lut2_out[0]), + .cout(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7]) + ); + carry_follower sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout_carry_follower_cout ( + .a(sum_frac_lut4_lut4_out_7_lut2_out[1]), + .b(sum_frac_lut4_lut4_out_7_in), + .cin(sum_frac_lut4_lut4_out_7_lut2_out[0]), + .cout(sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0]) + ); +endmodule From d8927e12e8cdec12e7a9a7ddafd5dc6dea74ea49 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 12:25:37 -0700 Subject: [PATCH 14/40] [Arch] Add soft adder operating mode to test architecture --- ...avel_io_skywater130nm_fdhd_cc_openfpga.xml | 6 ++ ...n_chain_nonLR_caravel_io_skywater130nm.xml | 63 ++++++++++++++++++- 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 8dbf6a29a..6a4a69e68 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -252,6 +252,12 @@ + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index b7c308935..89104d53b 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -33,7 +33,15 @@ - + + + + + + + + + @@ -479,6 +487,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 10302752a7e9ae0a8ad8896827a7ce8589bca461 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 13:43:39 -0700 Subject: [PATCH 15/40] [Arch] Bug fix in architecture. Now soft adder modes are accepted --- ...der_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 89104d53b..61d15c8af 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -488,7 +488,7 @@ - + @@ -523,7 +523,7 @@ - + From df88e2adc0329c609c15f5de804fe16d969ffa85 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 14:26:11 -0700 Subject: [PATCH 16/40] [Arch] Add an example definition of external bitstream to openfpga arch with soft adder --- ...ster_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 6a4a69e68..9ca1a90b4 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -254,6 +254,7 @@ + From a6354fab7c5bd67c2018be53ac51656eca7757ca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 15:57:44 -0700 Subject: [PATCH 17/40] [Arch] Decide to move external bitstream definition to a separated XML file --- ...r_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 9ca1a90b4..11d7bbf34 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -253,9 +253,7 @@ - - - + From 280c9620aae994c2f16e8cc42ac991f6bad40f0a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 16:01:21 -0700 Subject: [PATCH 18/40] [Test] Add an example bitstream annotation file --- .../adder/soft_adder/config/bitstream_annotation.xml | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml new file mode 100644 index 000000000..efbfcae62 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml @@ -0,0 +1,3 @@ + + + From 04594cb7abdd94290c2e0be46670fee20767a500 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 17:38:36 -0700 Subject: [PATCH 19/40] [Test] Adapt bitstream annotatin file to parser's requirement --- .../adder/soft_adder/config/bitstream_annotation.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml index efbfcae62..735d45c23 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml @@ -1,3 +1,3 @@ - + - + From f102e84497365c2e433f829e9b3e2c9641e459ff Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 17:43:46 -0700 Subject: [PATCH 20/40] [Tool] Add bitstream setting file to openfpga library --- .../libarchopenfpga/src/bitstream_setting.cpp | 80 ++++++++++++++++++ .../libarchopenfpga/src/bitstream_setting.h | 61 ++++++++++++++ .../src/bitstream_setting_fwd.h | 22 +++++ .../libarchopenfpga/src/openfpga_arch.h | 1 - .../src/read_xml_bitstream_setting.cpp | 65 ++++++++++++++ .../src/read_xml_bitstream_setting.h | 18 ++++ .../src/read_xml_openfpga_arch.cpp | 32 +++++++ .../src/read_xml_openfpga_arch.h | 4 + .../src/write_xml_bitstream_setting.cpp | 84 +++++++++++++++++++ .../src/write_xml_bitstream_setting.h | 17 ++++ .../test/read_bitstream_setting_openfpga.cpp | 31 +++++++ openfpga/src/base/openfpga_context.h | 1 + 12 files changed, 415 insertions(+), 1 deletion(-) create mode 100644 libopenfpga/libarchopenfpga/src/bitstream_setting.cpp create mode 100644 libopenfpga/libarchopenfpga/src/bitstream_setting.h create mode 100644 libopenfpga/libarchopenfpga/src/bitstream_setting_fwd.h create mode 100644 libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.cpp create mode 100644 libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.h create mode 100644 libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp create mode 100644 libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.h create mode 100644 libopenfpga/libarchopenfpga/test/read_bitstream_setting_openfpga.cpp diff --git a/libopenfpga/libarchopenfpga/src/bitstream_setting.cpp b/libopenfpga/libarchopenfpga/src/bitstream_setting.cpp new file mode 100644 index 000000000..924e96c0e --- /dev/null +++ b/libopenfpga/libarchopenfpga/src/bitstream_setting.cpp @@ -0,0 +1,80 @@ +#include "vtr_assert.h" + +#include "bitstream_setting.h" + +/* namespace openfpga begins */ +namespace openfpga { + +/************************************************************************ + * Member functions for class BitstreamSetting + ***********************************************************************/ + +/************************************************************************ + * Public Accessors : aggregates + ***********************************************************************/ +BitstreamSetting::bitstream_pb_type_setting_range BitstreamSetting::pb_type_settings() const { + return vtr::make_range(pb_type_setting_ids_.begin(), pb_type_setting_ids_.end()); +} + +/************************************************************************ + * Constructors + ***********************************************************************/ +BitstreamSetting::BitstreamSetting() { + return; +} + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +std::string BitstreamSetting::pb_type_name(const BitstreamPbTypeSettingId& pb_type_setting_id) const { + VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id)); + return pb_type_names_[pb_type_setting_id]; +} + +std::vector BitstreamSetting::parent_pb_type_names(const BitstreamPbTypeSettingId& pb_type_setting_id) const { + VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id)); + return parent_pb_type_names_[pb_type_setting_id]; +} + +std::vector BitstreamSetting::parent_mode_names(const BitstreamPbTypeSettingId& pb_type_setting_id) const { + VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id)); + return parent_mode_names_[pb_type_setting_id]; +} + +std::string BitstreamSetting::pb_type_bitstream_source(const BitstreamPbTypeSettingId& pb_type_setting_id) const { + VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id)); + return pb_type_bitstream_sources_[pb_type_setting_id]; +} + +std::string BitstreamSetting::pb_type_bitstream_content(const BitstreamPbTypeSettingId& pb_type_setting_id) const { + VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id)); + return pb_type_bitstream_contents_[pb_type_setting_id]; +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +BitstreamPbTypeSettingId BitstreamSetting::add_bitstream_pb_type_setting(const std::string& pb_type_name, + const std::vector& parent_pb_type_names, + const std::vector& parent_mode_names, + const std::string& bitstream_source, + const std::string& bitstream_content) { + BitstreamPbTypeSettingId pb_type_setting_id = BitstreamPbTypeSettingId(pb_type_setting_ids_.size()); + pb_type_setting_ids_.push_back(pb_type_setting_id); + pb_type_names_.push_back(pb_type_name); + parent_pb_type_names_.push_back(parent_pb_type_names); + parent_mode_names_.push_back(parent_mode_names); + pb_type_bitstream_sources_.push_back(bitstream_source); + pb_type_bitstream_contents_.push_back(bitstream_content); + + return pb_type_setting_id; +} + +/************************************************************************ + * Public Validators + ***********************************************************************/ +bool BitstreamSetting::valid_bitstream_pb_type_setting_id(const BitstreamPbTypeSettingId& pb_type_setting_id) const { + return ( size_t(pb_type_setting_id) < pb_type_setting_ids_.size() ) && ( pb_type_setting_id == pb_type_setting_ids_[pb_type_setting_id] ); +} + +} /* namespace openfpga ends */ diff --git a/libopenfpga/libarchopenfpga/src/bitstream_setting.h b/libopenfpga/libarchopenfpga/src/bitstream_setting.h new file mode 100644 index 000000000..d42ebe430 --- /dev/null +++ b/libopenfpga/libarchopenfpga/src/bitstream_setting.h @@ -0,0 +1,61 @@ +#ifndef BITSTREAM_SETTING_H +#define BITSTREAM_SETTING_H + +/******************************************************************** + * This file include the declaration of simulation settings + * which are used by OpenFPGA + *******************************************************************/ +#include + +#include "vtr_vector.h" + +#include "bitstream_setting_fwd.h" + +/* namespace openfpga begins */ +namespace openfpga { + +/******************************************************************** + * A data structure to describe bitstream settings + * + * Typical usage: + * -------------- + * // Create an empty bitstream setting + * BitstreamSetting bitstream_setting; + * // call your builder for bitstream_setting + * + *******************************************************************/ +class BitstreamSetting { + public: /* Types */ + typedef vtr::vector::const_iterator bitstream_pb_type_setting_iterator; + /* Create range */ + typedef vtr::Range bitstream_pb_type_setting_range; + public: /* Constructors */ + BitstreamSetting(); + public: /* Accessors: aggregates */ + bitstream_pb_type_setting_range pb_type_settings() const; + public: /* Public Accessors */ + std::string pb_type_name(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + std::vector parent_pb_type_names(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + std::vector parent_mode_names(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + std::string pb_type_bitstream_source(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + std::string pb_type_bitstream_content(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + public: /* Public Mutators */ + BitstreamPbTypeSettingId add_bitstream_pb_type_setting(const std::string& pb_type_name, + const std::vector& parent_pb_type_names, + const std::vector& parent_mode_names, + const std::string& bitstream_source, + const std::string& bitstream_content); + public: /* Public Validators */ + bool valid_bitstream_pb_type_setting_id(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + private: /* Internal data */ + vtr::vector pb_type_setting_ids_; + vtr::vector pb_type_names_; + vtr::vector> parent_pb_type_names_; + vtr::vector> parent_mode_names_; + vtr::vector pb_type_bitstream_sources_; + vtr::vector pb_type_bitstream_contents_; +}; + +} /* namespace openfpga ends */ + +#endif diff --git a/libopenfpga/libarchopenfpga/src/bitstream_setting_fwd.h b/libopenfpga/libarchopenfpga/src/bitstream_setting_fwd.h new file mode 100644 index 000000000..009bcbfed --- /dev/null +++ b/libopenfpga/libarchopenfpga/src/bitstream_setting_fwd.h @@ -0,0 +1,22 @@ +/************************************************************************ + * A header file for BitstreamSetting class, including critical data declaration + * Please include this file only for using any BitstreamSetting data structure + * Refer to bitstream_setting.h for more details + ***********************************************************************/ + +/************************************************************************ + * Create strong id for the pb_type annotation in Bitstream setting to avoid illegal type casting + ***********************************************************************/ +#ifndef BITSTREAM_SETTING_FWD_H +#define BITSTREAM_SETTING_FWD_H + +#include "vtr_strong_id.h" + +struct bitstream_pb_type_setting_id_tag; + +typedef vtr::StrongId BitstreamPbTypeSettingId; + +/* Short declaration of class */ +class BitstreamSetting; + +#endif diff --git a/libopenfpga/libarchopenfpga/src/openfpga_arch.h b/libopenfpga/libarchopenfpga/src/openfpga_arch.h index 38d920c6e..6867a4bb4 100644 --- a/libopenfpga/libarchopenfpga/src/openfpga_arch.h +++ b/libopenfpga/libarchopenfpga/src/openfpga_arch.h @@ -6,7 +6,6 @@ #include "circuit_library.h" #include "technology_library.h" -#include "simulation_setting.h" #include "config_protocol.h" #include "arch_direct.h" #include "tile_annotation.h" diff --git a/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.cpp b/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.cpp new file mode 100644 index 000000000..02f257ffe --- /dev/null +++ b/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.cpp @@ -0,0 +1,65 @@ +/******************************************************************** + * This file includes the top-level function of this library + * which reads an XML modeling OpenFPGA architecture to the associated + * data structures + *******************************************************************/ +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" + +/* Headers from openfpga util library */ +#include "openfpga_pb_parser.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "read_xml_util.h" + +#include "read_xml_bitstream_setting.h" + +/******************************************************************** + * Parse XML description for a pb_type annotation under a XML node + *******************************************************************/ +static +void read_xml_bitstream_pb_type_setting(pugi::xml_node& xml_pb_type, + const pugiutil::loc_data& loc_data, + openfpga::BitstreamSetting& bitstream_setting) { + const std::string& name_attr = get_attribute(xml_pb_type, "name", loc_data).as_string(); + const std::string& source_attr = get_attribute(xml_pb_type, "source", loc_data).as_string(); + const std::string& content_attr = get_attribute(xml_pb_type, "content", loc_data).as_string(); + + /* Parse the attributes for operating pb_type */ + openfpga::PbParser operating_pb_parser(name_attr); + + /* Add to bitstream setting */ + bitstream_setting.add_bitstream_pb_type_setting(operating_pb_parser.leaf(), + operating_pb_parser.parents(), + operating_pb_parser.modes(), + source_attr, + content_attr); +} + +/******************************************************************** + * Parse XML codes about to an object + *******************************************************************/ +openfpga::BitstreamSetting read_xml_bitstream_setting(pugi::xml_node& Node, + const pugiutil::loc_data& loc_data) { + openfpga::BitstreamSetting bitstream_setting; + + /* Iterate over the children under this node, + * each child should be named after + */ + for (pugi::xml_node xml_pb_type : Node.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_pb_type.name() != std::string("pb_type")) { + bad_tag(xml_pb_type, loc_data, Node, {"pb_type"}); + } + read_xml_bitstream_pb_type_setting(xml_pb_type, loc_data, bitstream_setting); + } + + return bitstream_setting; +} diff --git a/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.h b/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.h new file mode 100644 index 000000000..d3b16ec82 --- /dev/null +++ b/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.h @@ -0,0 +1,18 @@ +#ifndef READ_XML_BITSTREAM_SETTING_H +#define READ_XML_BITSTREAM_SETTING_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "pugixml_util.hpp" +#include "pugixml.hpp" +#include "bitstream_setting.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +openfpga::BitstreamSetting read_xml_bitstream_setting(pugi::xml_node& Node, + const pugiutil::loc_data& loc_data); + +#endif diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp index bbeb893c0..ad0c88b4d 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp @@ -23,6 +23,7 @@ #include "read_xml_routing_circuit.h" #include "read_xml_tile_annotation.h" #include "read_xml_pb_type_annotation.h" +#include "read_xml_bitstream_setting.h" #include "read_xml_openfpga_arch.h" #include "openfpga_arch_linker.h" @@ -149,3 +150,34 @@ openfpga::SimulationSetting read_xml_openfpga_simulation_settings(const char* si return openfpga_sim_setting; } +/******************************************************************** + * Top-level function to parse an XML file and load data to bitstream settings + *******************************************************************/ +openfpga::BitstreamSetting read_xml_openfpga_bitstream_settings(const char* bitstream_setting_file_name) { + vtr::ScopedStartFinishTimer timer("Read OpenFPGA bitstream settings"); + + openfpga::BitstreamSetting openfpga_bitstream_setting; + + pugi::xml_node Next; + + /* Parse the file */ + pugi::xml_document doc; + pugiutil::loc_data loc_data; + + try { + loc_data = pugiutil::load_xml(doc, bitstream_setting_file_name); + + /* Second node should be */ + auto xml_bitstream_settings = get_single_child(doc, "openfpga_bitstream_setting", loc_data); + + /* Parse simulation settings to data structure */ + openfpga_bitstream_setting = read_xml_bitstream_setting(xml_bitstream_settings, loc_data); + + } catch (pugiutil::XmlError& e) { + archfpga_throw(bitstream_setting_file_name, e.line(), + "%s", e.what()); + } + + return openfpga_bitstream_setting; +} + diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.h b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.h index 660baeec0..920ba20e1 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.h +++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.h @@ -6,6 +6,8 @@ *******************************************************************/ #include #include "openfpga_arch.h" +#include "simulation_setting.h" +#include "bitstream_setting.h" /******************************************************************** * Function declaration @@ -14,4 +16,6 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name); openfpga::SimulationSetting read_xml_openfpga_simulation_settings(const char* sim_setting_file_name); +openfpga::BitstreamSetting read_xml_openfpga_bitstream_settings(const char* bitstream_setting_file_name); + #endif diff --git a/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp b/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp new file mode 100644 index 000000000..8256573dd --- /dev/null +++ b/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp @@ -0,0 +1,84 @@ +/******************************************************************** + * This file includes functions that outputs a bitstream setting to XML format + *******************************************************************/ +/* Headers from system goes first */ +#include +#include + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "openfpga_digest.h" + +/* Headers from readarchopenfpga library */ +#include "write_xml_utils.h" +#include "write_xml_bitstream_setting.h" + +/******************************************************************** + * Generate the full hierarchy name for a pb_type in bitstream setting + *******************************************************************/ +static +std::string generate_bitstream_setting_pb_type_hierarchy_name(const openfpga::BitstreamSetting& bitstream_setting, + const BitstreamPbTypeSettingId& bitstream_pb_type_setting_id) { + /* Iterate over the parent_pb_type and modes names, they should well match */ + VTR_ASSERT_SAFE(bitstream_setting.parent_pb_type_names(bitstream_pb_type_setting_id).size() == bitstream_setting.parent_mode_names(bitstream_pb_type_setting_id).size()); + + std::string hie_name; + + for (size_t i = 0 ; i < bitstream_setting.parent_pb_type_names(bitstream_pb_type_setting_id).size(); ++i) { + hie_name += bitstream_setting.parent_pb_type_names(bitstream_pb_type_setting_id)[i]; + hie_name += std::string("["); + hie_name += bitstream_setting.parent_mode_names(bitstream_pb_type_setting_id)[i]; + hie_name += std::string("]"); + hie_name += std::string("."); + } + + /* Add the leaf pb_type */ + hie_name += bitstream_setting.pb_type_name(bitstream_pb_type_setting_id); + + return hie_name; +} + +/******************************************************************** + * A writer to output a bitstream pb_type setting to XML format + *******************************************************************/ +static +void write_xml_bitstream_pb_type_setting(std::fstream& fp, + const char* fname, + const openfpga::BitstreamSetting& bitstream_setting, + const BitstreamPbTypeSettingId& bitstream_pb_type_setting_id) { + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + fp << "\t\t" << "" << "\n"; +} + +/******************************************************************** + * A writer to output a bitstream setting to XML format + *******************************************************************/ +void write_xml_bitstream_setting(std::fstream& fp, + const char* fname, + const openfpga::BitstreamSetting& bitstream_setting) { + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + /* Write the root node + */ + fp << "" << "\n"; + + /* Write clock settings */ + for (const auto& bitstream_pb_type_setting_id : bitstream_setting.pb_type_settings()) { + write_xml_bitstream_pb_type_setting(fp, fname, bitstream_setting, bitstream_pb_type_setting_id); + } + + /* Write the root node */ + fp << "" << "\n"; +} diff --git a/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.h b/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.h new file mode 100644 index 000000000..b4eea0d10 --- /dev/null +++ b/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.h @@ -0,0 +1,17 @@ +#ifndef WRITE_XML_BITSTREAM_SETTING_H +#define WRITE_XML_BITSTREAM_SETTING_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include "bitstream_setting.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ +void write_xml_bitstream_setting(std::fstream& fp, + const char* fname, + const openfpga::BitstreamSetting& bitstream_setting); + +#endif diff --git a/libopenfpga/libarchopenfpga/test/read_bitstream_setting_openfpga.cpp b/libopenfpga/libarchopenfpga/test/read_bitstream_setting_openfpga.cpp new file mode 100644 index 000000000..d805eb7f4 --- /dev/null +++ b/libopenfpga/libarchopenfpga/test/read_bitstream_setting_openfpga.cpp @@ -0,0 +1,31 @@ +/******************************************************************** + * Unit test functions to validate the correctness of + * 1. parser of data structures + * 2. writer of data structures + *******************************************************************/ +/* Headers from vtrutils */ +#include "vtr_assert.h" +#include "vtr_log.h" + +/* Headers from readarchopenfpga */ +#include "read_xml_openfpga_arch.h" +#include "write_xml_openfpga_arch.h" + +int main(int argc, const char** argv) { + /* Ensure we have only one or two argument */ + VTR_ASSERT((2 == argc) || (3 == argc)); + + /* Parse the simulation settings from an XML file */ + const openfpga::BitstreamSetting& openfpga_sim_setting = read_xml_openfpga_bitstream_settings(argv[1]); + VTR_LOG("Parsed bitstream settings from XML %s.\n", + argv[1]); + + /* Output the simulation settings to an XML file + * This is optional only used when there is a second argument + */ + if (3 <= argc) { + write_xml_openfpga_bitstream_settings(argv[2], openfpga_bitstream_setting); + VTR_LOG("Echo the OpenFPGA bitstream settings to an XML file: %s.\n", + argv[2]); + } +} diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h index a6ea28ace..0bff4448e 100644 --- a/openfpga/src/base/openfpga_context.h +++ b/openfpga/src/base/openfpga_context.h @@ -4,6 +4,7 @@ #include #include "vpr_context.h" #include "openfpga_arch.h" +#include "simulation_setting.h" #include "vpr_netlist_annotation.h" #include "vpr_device_annotation.h" #include "vpr_clustering_annotation.h" From d5b1cc5ec7c94acc412398f5fd26703b75ee3de1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 18:01:42 -0700 Subject: [PATCH 21/40] [Tool] Bug fix in parser for bitstream settings --- .../src/write_xml_openfpga_arch.cpp | 23 +++++++++++++++++++ .../src/write_xml_openfpga_arch.h | 3 +++ .../test/read_bitstream_setting_openfpga.cpp | 2 +- 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp index f64e1970e..a97c3f002 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp @@ -14,6 +14,7 @@ #include "write_xml_circuit_library.h" #include "write_xml_technology_library.h" #include "write_xml_simulation_setting.h" +#include "write_xml_bitstream_setting.h" #include "write_xml_config_protocol.h" #include "write_xml_routing_circuit.h" #include "write_xml_tile_annotation.h" @@ -92,3 +93,25 @@ void write_xml_openfpga_simulation_settings(const char* fname, /* Close the file stream */ fp.close(); } + +/******************************************************************** + * A writer to output an OpenFPGA bitstream setting database to XML format + *******************************************************************/ +void write_xml_openfpga_bitstream_settings(const char* fname, + const openfpga::BitstreamSetting& openfpga_bitstream_setting) { + vtr::ScopedStartFinishTimer timer("Write OpenFPGA bitstream settings"); + + /* Create a file handler */ + std::fstream fp; + /* Open the file stream */ + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + /* Write the simulation */ + write_xml_bitstream_setting(fp, fname, openfpga_bitstream_setting); + + /* Close the file stream */ + fp.close(); +} diff --git a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.h b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.h index 68611493f..3ea251b49 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.h +++ b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.h @@ -16,5 +16,8 @@ void write_xml_openfpga_arch(const char* xml_fname, void write_xml_openfpga_simulation_settings(const char* xml_fname, const openfpga::SimulationSetting& openfpga_sim_setting); +void write_xml_openfpga_bitstream_settings(const char* fname, + const openfpga::BitstreamSetting& openfpga_bitstream_setting); + #endif diff --git a/libopenfpga/libarchopenfpga/test/read_bitstream_setting_openfpga.cpp b/libopenfpga/libarchopenfpga/test/read_bitstream_setting_openfpga.cpp index d805eb7f4..9447f2f0f 100644 --- a/libopenfpga/libarchopenfpga/test/read_bitstream_setting_openfpga.cpp +++ b/libopenfpga/libarchopenfpga/test/read_bitstream_setting_openfpga.cpp @@ -16,7 +16,7 @@ int main(int argc, const char** argv) { VTR_ASSERT((2 == argc) || (3 == argc)); /* Parse the simulation settings from an XML file */ - const openfpga::BitstreamSetting& openfpga_sim_setting = read_xml_openfpga_bitstream_settings(argv[1]); + const openfpga::BitstreamSetting& openfpga_bitstream_setting = read_xml_openfpga_bitstream_settings(argv[1]); VTR_LOG("Parsed bitstream settings from XML %s.\n", argv[1]); From faabdab815b262351eb087ddb8669700590d57f6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 18:04:21 -0700 Subject: [PATCH 22/40] [Tool] Remove redundant tab in bitstream setting writer --- libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp b/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp index 8256573dd..1273f083a 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp @@ -50,7 +50,7 @@ void write_xml_bitstream_pb_type_setting(std::fstream& fp, /* Validate the file stream */ openfpga::check_file_stream(fname, fp); - fp << "\t\t" << " Date: Mon, 1 Feb 2021 20:49:36 -0700 Subject: [PATCH 23/40] [Tool] Add bitstream annotation support --- .../annotation/annotate_bitstream_setting.cpp | 85 +++++++++++++++++++ .../annotation/annotate_bitstream_setting.h | 23 +++++ .../annotation/vpr_bitstream_annotation.cpp | 54 ++++++++++++ .../src/annotation/vpr_bitstream_annotation.h | 50 +++++++++++ openfpga/src/base/openfpga_context.h | 10 +++ openfpga/src/base/openfpga_link_arch.cpp | 9 ++ openfpga/src/base/openfpga_read_arch.cpp | 54 ++++++++++++ openfpga/src/base/openfpga_read_arch.h | 7 ++ openfpga/src/base/openfpga_repack.cpp | 1 + openfpga/src/base/openfpga_setup_command.cpp | 65 ++++++++++++++ .../fpga_bitstream/build_grid_bitstream.cpp | 17 ++++ .../src/repack/build_physical_truth_table.h | 1 + openfpga/src/repack/physical_pb.cpp | 12 +++ openfpga/src/repack/physical_pb.h | 5 ++ openfpga/src/repack/repack.cpp | 9 +- openfpga/src/repack/repack.h | 2 + openfpga/src/utils/physical_pb_utils.cpp | 28 ++++++ openfpga/src/utils/physical_pb_utils.h | 2 + 18 files changed, 433 insertions(+), 1 deletion(-) create mode 100644 openfpga/src/annotation/annotate_bitstream_setting.cpp create mode 100644 openfpga/src/annotation/annotate_bitstream_setting.h create mode 100644 openfpga/src/annotation/vpr_bitstream_annotation.cpp create mode 100644 openfpga/src/annotation/vpr_bitstream_annotation.h diff --git a/openfpga/src/annotation/annotate_bitstream_setting.cpp b/openfpga/src/annotation/annotate_bitstream_setting.cpp new file mode 100644 index 000000000..fbcb92cf0 --- /dev/null +++ b/openfpga/src/annotation/annotate_bitstream_setting.cpp @@ -0,0 +1,85 @@ +/******************************************************************** + * This file includes functions that are used to annotate pb_type + * from VPR to OpenFPGA + *******************************************************************/ +#include +#include + +/* Headers from openfpgashell library */ +#include "command_exit_codes.h" + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "pb_type_utils.h" +#include "annotate_bitstream_setting.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Annotate bitstream setting based on VPR device information + * - Find the pb_type and link to the bitstream source + * - Find the pb_type and link to the bitstream content + *******************************************************************/ +int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting, + const DeviceContext& vpr_device_ctx, + VprBitstreamAnnotation& vpr_bitstream_annotation) { + + for (const auto& bitstream_pb_type_setting_id : bitstream_setting.pb_type_settings()) { + /* Get the full name of pb_type */ + std::vector target_pb_type_names; + std::vector target_pb_mode_names; + + target_pb_type_names = bitstream_setting.parent_pb_type_names(bitstream_pb_type_setting_id); + target_pb_type_names.push_back(bitstream_setting.pb_type_name(bitstream_pb_type_setting_id)); + target_pb_mode_names = bitstream_setting.parent_mode_names(bitstream_pb_type_setting_id); + + /* Pb type information are located at the logic_block_types in the device context of VPR + * We iterate over the vectors and find the pb_type matches the parent_pb_type_name + */ + bool link_success = false; + + for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) { + /* By pass nullptr for pb_type head */ + if (nullptr == lb_type.pb_type) { + continue; + } + /* Check the name of the top-level pb_type, if it does not match, we can bypass */ + if (target_pb_type_names[0] != std::string(lb_type.pb_type->name)) { + continue; + } + /* Match the name in the top-level, we go further to search the pb_type in the graph */ + t_pb_type* target_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_pb_type_names, + target_pb_mode_names); + if (nullptr == target_pb_type) { + continue; + } + /* Found one, build annotation */ + if (std::string("eblif") == bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id)) { + vpr_bitstream_annotation.set_pb_type_bitstream_source(target_pb_type, VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF); + } else { + /* Invalid source, error out! */ + VTR_LOG_ERROR("Invalid bitstream source '%s' for pb_type '%s' which is defined in bitstream setting\n", + bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id).c_str(), + target_pb_type_names[0].c_str()); + return CMD_EXEC_FATAL_ERROR; + } + vpr_bitstream_annotation.set_pb_type_bitstream_content(target_pb_type, bitstream_setting.pb_type_bitstream_content(bitstream_pb_type_setting_id)); + + link_success = true; + } + + /* If fail to link bitstream setting to architecture, error out immediately */ + if (false == link_success) { + VTR_LOG_ERROR("Fail to find a pb_type '%s' which is defined in bitstream setting from VPR architecture description\n", + target_pb_type_names[0].c_str()); + return CMD_EXEC_FATAL_ERROR; + } + } + + return CMD_EXEC_SUCCESS; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/annotation/annotate_bitstream_setting.h b/openfpga/src/annotation/annotate_bitstream_setting.h new file mode 100644 index 000000000..053ca2fbe --- /dev/null +++ b/openfpga/src/annotation/annotate_bitstream_setting.h @@ -0,0 +1,23 @@ +#ifndef ANNOTATE_BITSTREAM_SETTING_H +#define ANNOTATE_BITSTREAM_SETTING_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "vpr_context.h" +#include "openfpga_context.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting, + const DeviceContext& vpr_device_ctx, + VprBitstreamAnnotation& vpr_bitstream_annotation); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/annotation/vpr_bitstream_annotation.cpp b/openfpga/src/annotation/vpr_bitstream_annotation.cpp new file mode 100644 index 000000000..fdb66048c --- /dev/null +++ b/openfpga/src/annotation/vpr_bitstream_annotation.cpp @@ -0,0 +1,54 @@ +/************************************************************************ + * Member functions for class VprBitstreamAnnotation + ***********************************************************************/ +#include "vtr_log.h" +#include "vtr_assert.h" +#include "vpr_bitstream_annotation.h" + +/* namespace openfpga begins */ +namespace openfpga { + +/************************************************************************ + * Constructors + ***********************************************************************/ +VprBitstreamAnnotation::VprBitstreamAnnotation() { + return; +} + +/************************************************************************ + * Public accessors + ***********************************************************************/ +VprBitstreamAnnotation::e_bitstream_source_type VprBitstreamAnnotation::pb_type_bitstream_source(t_pb_type* pb_type) const { + auto result = bitstream_sources_.find(pb_type); + if (result != bitstream_sources_.end()) { + return result->second; + } + + /* Not found, return an invalid type*/ + return NUM_BITSTREAM_SOURCE_TYPES; +} + +std::string VprBitstreamAnnotation::pb_type_bitstream_content(t_pb_type* pb_type) const { + auto result = bitstream_contents_.find(pb_type); + if (result != bitstream_contents_.end()) { + return result->second; + } + + /* Not found, return an invalid type */ + return std::string(); +} + +/************************************************************************ + * Public mutators + ***********************************************************************/ +void VprBitstreamAnnotation::set_pb_type_bitstream_source(t_pb_type* pb_type, + const e_bitstream_source_type& bitstream_source) { + bitstream_sources_[pb_type] = bitstream_source; +} +void VprBitstreamAnnotation::set_pb_type_bitstream_content(t_pb_type* pb_type, + const std::string& bitstream_content) { + bitstream_contents_[pb_type] = bitstream_content; +} + + +} /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/vpr_bitstream_annotation.h b/openfpga/src/annotation/vpr_bitstream_annotation.h new file mode 100644 index 000000000..c8d4102a0 --- /dev/null +++ b/openfpga/src/annotation/vpr_bitstream_annotation.h @@ -0,0 +1,50 @@ +#ifndef VPR_BITSTREAM_ANNOTATION_H +#define VPR_BITSTREAM_ANNOTATION_H + +/******************************************************************** + * Include header files required by the data structure definition + *******************************************************************/ +#include +#include + +/* Header from vpr library */ +#include "vpr_context.h" + +/* Begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * This is the critical data structure to link the pb_type in VPR + * to openfpga annotations + * With a given pb_type pointer, it aims to identify: + * 1. if the pb_type requires another bitstream source than .blif file + * which may be .eblif file + * 2. if the pb_type requires a fixed bitstream value + * or an attribute line in the .eblif file + *******************************************************************/ +class VprBitstreamAnnotation { + public: /* Type */ + enum e_bitstream_source_type { + BITSTREAM_SOURCE_EBLIF, + NUM_BITSTREAM_SOURCE_TYPES + }; + public: /* Constructor */ + VprBitstreamAnnotation(); + public: /* Public accessors */ + e_bitstream_source_type pb_type_bitstream_source(t_pb_type* pb_type) const; + std::string pb_type_bitstream_content(t_pb_type* pb_type) const; + public: /* Public mutators */ + void set_pb_type_bitstream_source(t_pb_type* pb_type, + const e_bitstream_source_type& bitstream_source); + void set_pb_type_bitstream_content(t_pb_type* pb_type, + const std::string& bitstream_content); + private: /* Internal data */ + /* A look up for pb type to find bitstream source type */ + std::map bitstream_sources_; + /* Binding from pb type to bitstream content */ + std::map bitstream_contents_; +}; + +} /* End namespace openfpga*/ + +#endif diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h index 0bff4448e..c85bf8607 100644 --- a/openfpga/src/base/openfpga_context.h +++ b/openfpga/src/base/openfpga_context.h @@ -5,11 +5,13 @@ #include "vpr_context.h" #include "openfpga_arch.h" #include "simulation_setting.h" +#include "bitstream_setting.h" #include "vpr_netlist_annotation.h" #include "vpr_device_annotation.h" #include "vpr_clustering_annotation.h" #include "vpr_placement_annotation.h" #include "vpr_routing_annotation.h" +#include "vpr_bitstream_annotation.h" #include "mux_library.h" #include "decoder_library.h" #include "tile_direct.h" @@ -53,11 +55,13 @@ class OpenfpgaContext : public Context { public: /* Public accessors */ const openfpga::Arch& arch() const { return arch_; } const openfpga::SimulationSetting& simulation_setting() const { return sim_setting_; } + const openfpga::BitstreamSetting& bitstream_setting() const { return bitstream_setting_; } const openfpga::VprDeviceAnnotation& vpr_device_annotation() const { return vpr_device_annotation_; } const openfpga::VprNetlistAnnotation& vpr_netlist_annotation() const { return vpr_netlist_annotation_; } const openfpga::VprClusteringAnnotation& vpr_clustering_annotation() const { return vpr_clustering_annotation_; } const openfpga::VprPlacementAnnotation& vpr_placement_annotation() const { return vpr_placement_annotation_; } const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; } + const openfpga::VprBitstreamAnnotation& vpr_bitstream_annotation() const { return vpr_bitstream_annotation_; } const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; } const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; } const openfpga::DecoderLibrary& decoder_lib() const { return decoder_lib_; } @@ -73,11 +77,13 @@ class OpenfpgaContext : public Context { public: /* Public mutators */ openfpga::Arch& mutable_arch() { return arch_; } openfpga::SimulationSetting& mutable_simulation_setting() { return sim_setting_; } + openfpga::BitstreamSetting& mutable_bitstream_setting() { return bitstream_setting_; } openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; } openfpga::VprNetlistAnnotation& mutable_vpr_netlist_annotation() { return vpr_netlist_annotation_; } openfpga::VprClusteringAnnotation& mutable_vpr_clustering_annotation() { return vpr_clustering_annotation_; } openfpga::VprPlacementAnnotation& mutable_vpr_placement_annotation() { return vpr_placement_annotation_; } openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; } + openfpga::VprBitstreamAnnotation& mutable_vpr_bitstream_annotation() { return vpr_bitstream_annotation_; } openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; } openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; } openfpga::DecoderLibrary& mutable_decoder_lib() { return decoder_lib_; } @@ -94,6 +100,7 @@ class OpenfpgaContext : public Context { /* Data structure to store information from read_openfpga_arch library */ openfpga::Arch arch_; openfpga::SimulationSetting sim_setting_; + openfpga::BitstreamSetting bitstream_setting_; /* Annotation to pb_type of VPR */ openfpga::VprDeviceAnnotation vpr_device_annotation_; @@ -110,6 +117,9 @@ class OpenfpgaContext : public Context { /* Routing results annotation */ openfpga::VprRoutingAnnotation vpr_routing_annotation_; + /* Annotation to pb_type of VPR */ + openfpga::VprBitstreamAnnotation vpr_bitstream_annotation_; + /* Device-level annotation */ openfpga::DeviceRRGSB device_rr_gsb_; diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp index efedf9584..f33a292c6 100644 --- a/openfpga/src/base/openfpga_link_arch.cpp +++ b/openfpga/src/base/openfpga_link_arch.cpp @@ -21,6 +21,7 @@ #include "annotate_routing.h" #include "annotate_rr_graph.h" #include "annotate_simulation_setting.h" +#include "annotate_bitstream_setting.h" #include "mux_library_builder.h" #include "build_tile_direct.h" #include "annotate_placement.h" @@ -168,6 +169,14 @@ int link_arch(OpenfpgaContext& openfpga_ctx, return CMD_EXEC_FATAL_ERROR; } + /* Build bitstream annotation based on bitstream settings */ + if (CMD_EXEC_FATAL_ERROR == annotate_bitstream_setting(openfpga_ctx.bitstream_setting(), + g_vpr_ctx.device(), + openfpga_ctx.mutable_vpr_bitstream_annotation())) { + return CMD_EXEC_FATAL_ERROR; + } + + /* TODO: should identify the error code from internal function execution */ return CMD_EXEC_SUCCESS; } diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch.cpp index 1e58ec373..25bfc3831 100644 --- a/openfpga/src/base/openfpga_read_arch.cpp +++ b/openfpga/src/base/openfpga_read_arch.cpp @@ -152,5 +152,59 @@ int write_simulation_setting(const OpenfpgaContext& openfpga_context, return CMD_EXEC_SUCCESS; } +/******************************************************************** + * Top-level function to read an OpenFPGA bitstream setting file + * we use the APIs from the libarchopenfpga library + * + * The command will accept an option '--file' which is the bitstream setting + * file provided by users + *******************************************************************/ +int read_bitstream_setting(OpenfpgaContext& openfpga_context, + const Command& cmd, const CommandContext& cmd_context) { + /* Check the option '--file' is enabled or not + * Actually, it must be enabled as the shell interface will check + * before reaching this fuction + */ + CommandOptionId opt_file = cmd.option("file"); + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + + std::string arch_file_name = cmd_context.option_value(cmd, opt_file); + + VTR_LOG("Reading XML bitstream setting '%s'...\n", + arch_file_name.c_str()); + openfpga_context.mutable_bitstream_setting() = read_xml_openfpga_bitstream_settings(arch_file_name.c_str()); + + /* TODO: should identify the error code from internal function execution */ + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * A function to write an OpenFPGA bitstream setting file + * we use the APIs from the libarchopenfpga library + * + * The command will accept an option '--file' which is the simulation setting + * file provided by users + *******************************************************************/ +int write_bitstream_setting(const OpenfpgaContext& openfpga_context, + const Command& cmd, const CommandContext& cmd_context) { + /* Check the option '--file' is enabled or not + * Actually, it must be enabled as the shell interface will check + * before reaching this fuction + */ + CommandOptionId opt_file = cmd.option("file"); + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + + std::string arch_file_name = cmd_context.option_value(cmd, opt_file); + + VTR_LOG("Writing XML bitstream setting to '%s'...\n", + arch_file_name.c_str()); + write_xml_openfpga_bitstream_settings(arch_file_name.c_str(), openfpga_context.bitstream_setting()); + + /* TODO: should identify the error code from internal function execution */ + return CMD_EXEC_SUCCESS; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_read_arch.h b/openfpga/src/base/openfpga_read_arch.h index d5502db56..9ffc0d3cb 100644 --- a/openfpga/src/base/openfpga_read_arch.h +++ b/openfpga/src/base/openfpga_read_arch.h @@ -27,6 +27,13 @@ int read_simulation_setting(OpenfpgaContext& openfpga_context, int write_simulation_setting(const OpenfpgaContext& openfpga_context, const Command& cmd, const CommandContext& cmd_context); +int read_bitstream_setting(OpenfpgaContext& openfpga_context, + const Command& cmd, const CommandContext& cmd_context); + +int write_bitstream_setting(const OpenfpgaContext& openfpga_context, + const Command& cmd, const CommandContext& cmd_context); + + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp index 872de054c..8e8a79141 100644 --- a/openfpga/src/base/openfpga_repack.cpp +++ b/openfpga/src/base/openfpga_repack.cpp @@ -45,6 +45,7 @@ int repack(OpenfpgaContext& openfpga_ctx, g_vpr_ctx.clustering(), openfpga_ctx.mutable_vpr_device_annotation(), openfpga_ctx.mutable_vpr_clustering_annotation(), + openfpga_ctx.vpr_bitstream_annotation(), repack_design_constraints, cmd_context.option_enable(cmd, opt_verbose)); diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index 7e484731d..517ed364a 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -113,6 +113,55 @@ ShellCommandId add_openfpga_write_simulation_setting_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id) { + Command shell_cmd("read_openfpga_bitstream_setting"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to the bitstream setting XML"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add command 'read_openfpga_bitstream_setting' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "read OpenFPGA bitstream setting file"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, read_bitstream_setting); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_openfpga_bitstream_setting + * - Add associated options + * - Add command dependency + *******************************************************************/ +static +ShellCommandId add_openfpga_write_bitstream_setting_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_openfpga_bitstream_setting"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to the bitstream setting XML"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add command 'write_openfpga_bitstream_setting' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "write OpenFPGA bitstream setting file"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function(shell_cmd_id, write_bitstream_setting); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + /******************************************************************** * - Add a command to Shell environment: link_openfpga_arch * - Add associated options @@ -373,6 +422,22 @@ void add_openfpga_setup_commands(openfpga::Shell& shell) { openfpga_setup_cmd_class, write_sim_setting_dependent_cmds); + /******************************** + * Command 'read_openfpga_bitstream_setting' + */ + ShellCommandId read_bitstream_setting_cmd_id = add_openfpga_read_bitstream_setting_command(shell, + openfpga_setup_cmd_class); + + /******************************** + * Command 'write_openfpga_bitstream_setting' + */ + /* The 'write_openfpga_bitstream_setting' command should NOT be executed before 'read_openfpga_bitstream_setting' */ + std::vector write_bitstream_setting_dependent_cmds(1, read_bitstream_setting_cmd_id); + add_openfpga_write_bitstream_setting_command(shell, + openfpga_setup_cmd_class, + write_bitstream_setting_dependent_cmds); + + /******************************** * Command 'link_openfpga_arch' */ diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index 3397be4b8..3062c126f 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -445,6 +445,23 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager, device_annotation, physical_pb.truth_tables(lut_pb_id), circuit_lib.port_default_value(lut_regular_sram_ports[0])); + /* If the physical pb contains fixed bitstream, overload here */ + if (false == physical_pb.fixed_bitstream(lut_pb_id).empty()) { + std::string fixed_bitstream = physical_pb.fixed_bitstream(lut_pb_id); + /* Ensure the length matches!!! */ + if (lut_bitstream.size() != fixed_bitstream.size()) { + VTR_LOG_ERROR("Unmatched length of fixed bitstream %s!Expected to be %ld bits\n", + fixed_bitstream.c_str(), + lut_bitstream.size()); + exit(1); + } + /* Overload here */ + lut_bitstream.clear(); + for (const char& fixed_bit : fixed_bitstream) { + VTR_ASSERT('0' == fixed_bit || '1' == fixed_bit); + lut_bitstream.push_back('1' == fixed_bit); + } + } } /* Generate bitstream for mode-select ports */ diff --git a/openfpga/src/repack/build_physical_truth_table.h b/openfpga/src/repack/build_physical_truth_table.h index 3c0c8ebf3..ecd4daad5 100644 --- a/openfpga/src/repack/build_physical_truth_table.h +++ b/openfpga/src/repack/build_physical_truth_table.h @@ -7,6 +7,7 @@ #include "vpr_context.h" #include "vpr_device_annotation.h" #include "vpr_clustering_annotation.h" +#include "vpr_bitstream_annotation.h" #include "circuit_library.h" /******************************************************************** diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp index 4650d7d0d..c64f05f07 100644 --- a/openfpga/src/repack/physical_pb.cpp +++ b/openfpga/src/repack/physical_pb.cpp @@ -102,6 +102,11 @@ std::vector PhysicalPb::mode_bits(const PhysicalPbId& pb) const { return mode_bits_[pb]; } +std::string PhysicalPb::fixed_bitstream(const PhysicalPbId& pb) const { + VTR_ASSERT(true == valid_pb_id(pb)); + return fixed_bitstreams_[pb]; +} + /****************************************************************************** * Private Mutators ******************************************************************************/ @@ -128,6 +133,7 @@ PhysicalPbId PhysicalPb::create_pb(const t_pb_graph_node* pb_graph_node) { truth_tables_.emplace_back(); mode_bits_.emplace_back(); + fixed_bitstreams_.emplace_back(); /* Register in the name2id map */ type2id_map_[pb_graph_node] = pb; @@ -206,6 +212,12 @@ void PhysicalPb::set_wire_lut_output(const PhysicalPbId& pb, wire_lut_outputs_[pb][pb_graph_pin] = wire_lut_output; } +void PhysicalPb::set_fixed_bitstream(const PhysicalPbId& pb, + const std::string& fixed_bitstream) { + VTR_ASSERT(true == valid_pb_id(pb)); + fixed_bitstreams_[pb] = fixed_bitstream; +} + /****************************************************************************** * Private validators/invalidators ******************************************************************************/ diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h index 6d8d2ba3b..078cc6bc9 100644 --- a/openfpga/src/repack/physical_pb.h +++ b/openfpga/src/repack/physical_pb.h @@ -54,6 +54,7 @@ class PhysicalPb { const t_pb_graph_pin* pb_graph_pin) const; std::map truth_tables(const PhysicalPbId& pb) const; std::vector mode_bits(const PhysicalPbId& pb) const; + std::string fixed_bitstream(const PhysicalPbId& pb) const; public: /* Public mutators */ PhysicalPbId create_pb(const t_pb_graph_node* pb_graph_node); void add_child(const PhysicalPbId& parent, @@ -72,6 +73,8 @@ class PhysicalPb { void set_wire_lut_output(const PhysicalPbId& pb, const t_pb_graph_pin* pb_graph_pin, const bool& wire_lut_output); + void set_fixed_bitstream(const PhysicalPbId& pb, + const std::string& fixed_bitstream); public: /* Public validators/invalidators */ bool valid_pb_id(const PhysicalPbId& pb_id) const; bool empty() const; @@ -94,6 +97,8 @@ class PhysicalPb { vtr::vector> mode_bits_; + vtr::vector fixed_bitstreams_; + /* Fast lookup */ std::map type2id_map_; }; diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 7869448be..e737991b8 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -611,6 +611,7 @@ void repack_cluster(const AtomContext& atom_ctx, const ClusteringContext& clustering_ctx, const VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const RepackDesignConstraints& design_constraints, const ClusterBlockId& block_id, const bool& verbose) { @@ -659,6 +660,7 @@ void repack_cluster(const AtomContext& atom_ctx, clustering_ctx.clb_nlist.block_pb(block_id)->pb_route, atom_ctx, device_annotation, + bitstream_annotation, verbose); /* Save routing results */ save_lb_router_results_to_physical_pb(phy_pb, lb_router, lb_rr_graph); @@ -678,6 +680,7 @@ void repack_clusters(const AtomContext& atom_ctx, const ClusteringContext& clustering_ctx, const VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const RepackDesignConstraints& design_constraints, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Repack clustered blocks to physical implementation of logical tile"); @@ -686,6 +689,7 @@ void repack_clusters(const AtomContext& atom_ctx, repack_cluster(atom_ctx, clustering_ctx, device_annotation, clustering_annotation, + bitstream_annotation, design_constraints, blk_id, verbose); } @@ -706,6 +710,7 @@ void pack_physical_pbs(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const RepackDesignConstraints& design_constraints, const bool& verbose) { @@ -716,7 +721,9 @@ void pack_physical_pbs(const DeviceContext& device_ctx, /* Call the LbRouter to re-pack each clustered block to physical implementation */ repack_clusters(atom_ctx, clustering_ctx, - const_cast(device_annotation), clustering_annotation, + const_cast(device_annotation), + clustering_annotation, + bitstream_annotation, design_constraints, verbose); } diff --git a/openfpga/src/repack/repack.h b/openfpga/src/repack/repack.h index 3ca3a613f..feb48a578 100644 --- a/openfpga/src/repack/repack.h +++ b/openfpga/src/repack/repack.h @@ -8,6 +8,7 @@ #include "vpr_device_annotation.h" #include "vpr_clustering_annotation.h" #include "vpr_routing_annotation.h" +#include "vpr_bitstream_annotation.h" #include "repack_design_constraints.h" /******************************************************************** @@ -22,6 +23,7 @@ void pack_physical_pbs(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const RepackDesignConstraints& design_constraints, const bool& verbose); diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp index 129784575..9f3cbf087 100644 --- a/openfpga/src/utils/physical_pb_utils.cpp +++ b/openfpga/src/utils/physical_pb_utils.cpp @@ -6,6 +6,9 @@ #include "vtr_assert.h" #include "vtr_log.h" +/* Headers from openfpgautil library */ +#include "openfpga_tokenizer.h" + #include "openfpga_naming.h" #include "pb_type_utils.h" #include "physical_pb_utils.h" @@ -278,6 +281,7 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, const t_pb_routes& pb_route, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose) { t_pb_graph_node* pb_graph_node = op_pb->pb_graph_node; t_pb_type* pb_type = pb_graph_node->pb_type; @@ -297,6 +301,29 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, VTR_ASSERT(atom_blk); phy_pb.add_atom_block(physical_pb, atom_blk); + + /* if the operating pb type has bitstream annotation, + * bind the bitstream value from atom block to the physical pb + */ + if (VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF == bitstream_annotation.pb_type_bitstream_source(pb_type)) { + StringToken tokenizer = bitstream_annotation.pb_type_bitstream_content(pb_type); + std::vector tokens = tokenizer.split(" "); + /* FIXME: The token-level check should be done much earlier!!! */ + VTR_ASSERT(2 == tokens.size()); + if (std::string(".param") == tokens[0]) { + for (const auto& param_search : atom_ctx.nlist.block_params(atom_blk)) { + if (param_search.first == tokens[1]) { + phy_pb.set_fixed_bitstream(physical_pb, param_search.second); + } + } + } else if (std::string(".attr") == tokens[0]) { + for (const auto& attr_search : atom_ctx.nlist.block_attrs(atom_blk)) { + if (attr_search.first == tokens[1]) { + phy_pb.set_fixed_bitstream(physical_pb, attr_search.second); + } + } + } + } /* Iterate over ports and annotate the atom pins */ synchronize_primitive_physical_pb_atom_nets(phy_pb, physical_pb, @@ -318,6 +345,7 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, pb_route, atom_ctx, device_annotation, + bitstream_annotation, verbose); } else { /* Some pb may be used just in routing purpose, find out the output nets */ diff --git a/openfpga/src/utils/physical_pb_utils.h b/openfpga/src/utils/physical_pb_utils.h index 227feec6c..faa18bc91 100644 --- a/openfpga/src/utils/physical_pb_utils.h +++ b/openfpga/src/utils/physical_pb_utils.h @@ -10,6 +10,7 @@ #include #include "physical_types.h" #include "vpr_device_annotation.h" +#include "vpr_bitstream_annotation.h" #include "vpr_context.h" #include "physical_pb.h" @@ -29,6 +30,7 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, const t_pb_routes& pb_route, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose); } /* end namespace openfpga */ From d83158654cec57581c74c23d4cf527a901fca266 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 22:33:17 -0700 Subject: [PATCH 24/40] [Doc] Add a draft documentation about the bitstream setting --- .../manual/file_formats/bitstream_setting.rst | 27 +++++++++++++++++++ docs/source/manual/file_formats/index.rst | 2 ++ .../openfpga_commands/setup_commands.rst | 27 +++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 docs/source/manual/file_formats/bitstream_setting.rst diff --git a/docs/source/manual/file_formats/bitstream_setting.rst b/docs/source/manual/file_formats/bitstream_setting.rst new file mode 100644 index 000000000..b21bd0c25 --- /dev/null +++ b/docs/source/manual/file_formats/bitstream_setting.rst @@ -0,0 +1,27 @@ +.. _file_formats_bitstream_setting: + +Bitstream Setting (.xml) +------------------------ + +An example of bitstream settings is shown as follows. +This can define a hard-coded bitstream for a reconfigurable resource in FPGA fabrics. + +.. code-block:: xml + + + + + +.. option:: pb_type="" + + The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example, ``pb_type="clb.fle[arithmetic].soft_adder.adder_lut4"`` + +.. option:: source="" + + The source of the ``pb_type`` bitstream, which could be from a ``.eblif`` file. For example, ``source="eblif"``. + +.. option:: content="" + + The content of the ``pb_type`` bitstream, which could be a keyword in a ``.eblif`` file. For example, ``content=".attr LUT"`` means that the bitstream will be extracted from the ``.attr LUT`` line which is defined under the ``.blif model`` (that is defined under the ``pb_type`` in VPR architecture file). + +.. warning:: Bitstream is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users's responsibility to ensure correct bitstream. diff --git a/docs/source/manual/file_formats/index.rst b/docs/source/manual/file_formats/index.rst index 698bf2253..f02218cd3 100644 --- a/docs/source/manual/file_formats/index.rst +++ b/docs/source/manual/file_formats/index.rst @@ -18,4 +18,6 @@ OpenFPGA widely uses XML format for interchangable files fabric_bitstream + bitstream_setting + fabric_key diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 9430483ee..9bc9c6334 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -56,6 +56,33 @@ write_openfpga_simulation_setting Show verbose log +read_openfpga_bitstream_setting +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Read the XML file about bitstream settings (see details in :ref:`file_formats_bitstream_setting`) + + .. option:: --file or -f + + Specify the file name. For example, ``--file bitstream_setting.xml`` + + .. option:: --verbose + + Show verbose log + +write_openfpga_bitstream_setting +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Write the OpenFPGA XML bitstream settings to a file + + .. option:: --file or -f + + Specify the file name. For example, ``--file auto_bitstream_setting_echo.xml``. + See details about file format at :ref:`file_formats_bitstream_setting`. + + .. option:: --verbose + + Show verbose log + link_openfpga_arch ~~~~~~~~~~~~~~~~~~ From 7f14dfbe875b3fef5e2b409e02c54acfc2501795 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 09:18:08 -0700 Subject: [PATCH 25/40] [Script] Add example script to use bitstream setting --- .../bitstream_setting_example_script.openfpga | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga new file mode 100644 index 000000000..fe73408ec --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga @@ -0,0 +1,77 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Read OpenFPGA bitstream settings +read_openfpga_bitstream_setting -f ${OPENFPGA_BITSTREAM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From 9ff5e7926bd0b74453375b816c9e26b937824f54 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 09:24:39 -0700 Subject: [PATCH 26/40] [Test] Update test case to use the adder benchmark --- .../tasks/fpga_verilog/adder/soft_adder/config/task.conf | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index 98c283a53..8a94c37ea 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -16,21 +16,22 @@ timeout_each_job = 1*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From d3397f693651c0dff808ca7239330aaec5e02f61 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 09:25:36 -0700 Subject: [PATCH 27/40] [Script] Remove activity from bitstream setting example script --- .../bitstream_setting_example_script.openfpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga index fe73408ec..0f4b1d7f6 100644 --- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga @@ -13,7 +13,7 @@ read_openfpga_bitstream_setting -f ${OPENFPGA_BITSTREAM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml From 39e6f62d91557afe7074c569fffcb6fca455f6d1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 09:32:42 -0700 Subject: [PATCH 28/40] [Benchmark] Use eblif in naming the adder_8 micro benchmark --- openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act | 2 ++ .../micro_benchmark/adder_8/{adder_8.blif => adder_8.eblif} | 0 2 files changed, 2 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act rename openfpga_flow/benchmarks/micro_benchmark/adder_8/{adder_8.blif => adder_8.eblif} (100%) diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act new file mode 100644 index 000000000..c070b2570 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act @@ -0,0 +1,2 @@ +# This is just a placehold activity file which is empty +# This is due to that ACE2 does not support eblif file format diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif rename to openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif From 5e2847bc41937f7f76e4280bd23c758b3d94c8b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 09:33:41 -0700 Subject: [PATCH 29/40] [Test] Update test case to use eblif file --- .../tasks/fpga_verilog/adder/soft_adder/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index 8a94c37ea..93f0c2d6a 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -26,7 +26,7 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif [SYNTHESIS_PARAM] bench0_top = and2 From 62803dc04479a9462819af5ddccca52f991d8365 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 14:59:31 -0700 Subject: [PATCH 30/40] [Benchmark] Add eblif example for and2 benchmark --- .../benchmarks/micro_benchmark/and2/and2.eblif | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif new file mode 100644 index 000000000..94a629572 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif @@ -0,0 +1,13 @@ +# This is an artificial microbenchmark +# which is designed to validate the support +# on using bitstream information from the .param +# attribute of hard macro of LUTs +# +.model and2 +.inputs a b +.outputs c + +.subckt adder_lut in[1]=a in[0]=b lut2_out[1]=unconn lut2_out[0]=unconn lut4_out[0]=c +.param LUT 1010101010101010 + +.end From 8e36ed1ab65fa111fca82ce1d35f7a8f371b105f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 15:01:15 -0700 Subject: [PATCH 31/40] [Test] Update task configuration to use and2 eblif --- .../tasks/fpga_verilog/adder/soft_adder/config/task.conf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index 93f0c2d6a..fcf40502f 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 1*60 @@ -26,12 +26,12 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From dc320182b0b4cd4eae9bf4d5a31dac178ad66032 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 15:04:43 -0700 Subject: [PATCH 32/40] [Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models --- openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif index 94a629572..28c79fbc4 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif +++ b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif @@ -7,7 +7,7 @@ .inputs a b .outputs c -.subckt adder_lut in[1]=a in[0]=b lut2_out[1]=unconn lut2_out[0]=unconn lut4_out[0]=c +.subckt adder_lut in[3]=unconn in[2]=unconn in[1]=a in[0]=b lut2_out[1]=unconn lut2_out[0]=unconn lut4_out[0]=c .param LUT 1010101010101010 .end From 021520783b2d10e696b1518f3ba26b4760d23ae3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 15:49:43 -0700 Subject: [PATCH 33/40] [Arch] Add dummy timing info to adder_lut4 and carry_follower model --- ...er_scan_chain_nonLR_caravel_io_skywater130nm.xml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 61d15c8af..3bc866586 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -35,7 +35,7 @@ - + @@ -54,9 +54,9 @@ - - - + + + @@ -500,12 +500,17 @@ + + + + + From 2c06960e4f7bcbfa646c6a57826a50f1b7d9f990 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 15:51:16 -0700 Subject: [PATCH 34/40] [Benchmark] Add subckt definition to micro benchmark and2.eblif --- openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif index 28c79fbc4..404af2538 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif +++ b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif @@ -7,7 +7,13 @@ .inputs a b .outputs c -.subckt adder_lut in[3]=unconn in[2]=unconn in[1]=a in[0]=b lut2_out[1]=unconn lut2_out[0]=unconn lut4_out[0]=c +.subckt adder_lut in[1]=a in[0]=b lut4_out[0]=c .param LUT 1010101010101010 .end + +.model adder_lut4 +.inputs in[3] in[2] in[1] in[0] +.outputs lut2_out[1] lut2_out[0] lut4_out[0] +.blackbox +.end From 05d63567d06e6df94c8c463ba17055a1f2e3cc4a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Feb 2021 09:21:38 -0700 Subject: [PATCH 35/40] [Benchmark] Use latest adder eblif file --- .../micro_benchmark/adder_8/adder_8.eblif | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif index 5e984d0ec..c7619c22e 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif +++ b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif @@ -1,4 +1,4 @@ -# Generated by Yosys 0.9+2406 (git sha1 e6ff764e, clang 12.0.0 -fPIC -Os) +# Generated by Yosys 0.9+2406 (git sha1 1fafc16a, clang 12.0.0 -fPIC -Os) .model adder_8 .inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] cin @@ -7,33 +7,33 @@ .names $true 1 .names $undef -.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7] in[1]=$false in[0]=$false lut2_out[1]=cout_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=cout_frac_lut4_lut4_out_lut2_out[0] lut4_out=cout +.subckt frac_lut4 in[3]=$false in[2]=$false in[1]=cin in[0]=$false lut2_out[1]=cin_frac_lut4_in_lut2_out[1] lut2_out[0]=cin_frac_lut4_in_lut2_out[0] +.param LUT 1100000000000011 +.subckt carry_follower a=cin_frac_lut4_in_lut2_out[1] cin=cin_frac_lut4_in_lut2_out[0] cout=sum_frac_lut4_lut4_out_7_in +.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7] in[1]=$false in[0]=$false lut2_out[1]=cout_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=cout_frac_lut4_lut4_out_lut2_out[0] lut4_out=cout .param LUT 0110100101100001 -.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] in[1]=a[7] in[0]=b[7] lut2_out[1]=sum_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_lut2_out[0] lut4_out=sum[7] +.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] in[1]=a[7] in[0]=b[7] lut2_out[1]=sum_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_lut2_out[0] lut4_out=sum[7] .param LUT 0110100101100001 -.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] in[1]=a[6] in[0]=b[6] lut2_out[1]=sum_frac_lut4_lut4_out_1_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_1_lut2_out[0] lut4_out=sum[6] +.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] in[1]=a[6] in[0]=b[6] lut2_out[1]=sum_frac_lut4_lut4_out_1_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_1_lut2_out[0] lut4_out=sum[6] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_1_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] cin=sum_frac_lut4_lut4_out_1_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] -.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] in[1]=a[5] in[0]=b[5] lut2_out[1]=sum_frac_lut4_lut4_out_2_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_2_lut2_out[0] lut4_out=sum[5] +.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] in[1]=a[5] in[0]=b[5] lut2_out[1]=sum_frac_lut4_lut4_out_2_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_2_lut2_out[0] lut4_out=sum[5] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_2_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] cin=sum_frac_lut4_lut4_out_2_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] -.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] in[1]=a[4] in[0]=b[4] lut2_out[1]=sum_frac_lut4_lut4_out_3_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_3_lut2_out[0] lut4_out=sum[4] +.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] in[1]=a[4] in[0]=b[4] lut2_out[1]=sum_frac_lut4_lut4_out_3_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_3_lut2_out[0] lut4_out=sum[4] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_3_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] cin=sum_frac_lut4_lut4_out_3_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] -.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] in[1]=a[3] in[0]=b[3] lut2_out[1]=sum_frac_lut4_lut4_out_4_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_4_lut2_out[0] lut4_out=sum[3] +.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] in[1]=a[3] in[0]=b[3] lut2_out[1]=sum_frac_lut4_lut4_out_4_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_4_lut2_out[0] lut4_out=sum[3] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_4_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] cin=sum_frac_lut4_lut4_out_4_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] -.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] in[1]=a[2] in[0]=b[2] lut2_out[1]=sum_frac_lut4_lut4_out_5_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_5_lut2_out[0] lut4_out=sum[2] +.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] in[1]=a[2] in[0]=b[2] lut2_out[1]=sum_frac_lut4_lut4_out_5_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_5_lut2_out[0] lut4_out=sum[2] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_5_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] cin=sum_frac_lut4_lut4_out_5_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] -.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] in[1]=a[1] in[0]=b[1] lut2_out[1]=sum_frac_lut4_lut4_out_6_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_6_lut2_out[0] lut4_out=sum[1] +.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] in[1]=a[1] in[0]=b[1] lut2_out[1]=sum_frac_lut4_lut4_out_6_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_6_lut2_out[0] lut4_out=sum[1] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_6_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] cin=sum_frac_lut4_lut4_out_6_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] -.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_7_in in[1]=a[0] in[0]=b[0] lut2_out[1]=sum_frac_lut4_lut4_out_7_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_7_lut2_out[0] lut4_out=sum[0] +.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_7_in in[1]=a[0] in[0]=b[0] lut2_out[1]=sum_frac_lut4_lut4_out_7_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_7_lut2_out[0] lut4_out=sum[0] .param LUT 0110100101100001 -.subckt carry_follower a=sum_frac_lut4_lut4_out_7_lut2_out[1] cin=sum_frac_lut4_lut4_out_7_lut2_out[0] cout=sum_frac_lut4_lut4_out_7_in -.subckt adder_lut4 in[3]=$undef in[2]=$undef in[1]=cin in[0]=$undef lut2_out[1]=sum_frac_lut4_lut4_out_7_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_7_lut2_out[0] -.param LUT 1100000000000011 -.subckt carry_follower a=sum_frac_lut4_lut4_out_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] cin=sum_frac_lut4_lut4_out_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7] .subckt carry_follower a=sum_frac_lut4_lut4_out_7_lut2_out[1] b=sum_frac_lut4_lut4_out_7_in cin=sum_frac_lut4_lut4_out_7_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] +.subckt carry_follower a=sum_frac_lut4_lut4_out_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] cin=sum_frac_lut4_lut4_out_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7] .end From 31441c0b64dd7df8e5c057282e604a916754be67 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Feb 2021 09:26:38 -0700 Subject: [PATCH 36/40] [Test] Deploy adder_8 to soft adder test --- .../tasks/fpga_verilog/adder/soft_adder/config/task.conf | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index fcf40502f..3eebeb32e 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_sof [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif [SYNTHESIS_PARAM] bench0_top = and2 @@ -34,6 +35,11 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 +bench1_top = adder_8 +bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act +bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v +bench1_chan_width = 300 + [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= vpr_fpga_verilog_formal_verification_top_netlist= From 4c825b27b3af81f42a3a21f89be0cbc349c7ef22 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Feb 2021 09:37:48 -0700 Subject: [PATCH 37/40] [Benchmark] Change to use adder lut4 to be consistent with architecture --- .../micro_benchmark/adder_8/adder_8.eblif | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif index c7619c22e..812f1a24d 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif +++ b/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif @@ -7,32 +7,32 @@ .names $true 1 .names $undef -.subckt frac_lut4 in[3]=$false in[2]=$false in[1]=cin in[0]=$false lut2_out[1]=cin_frac_lut4_in_lut2_out[1] lut2_out[0]=cin_frac_lut4_in_lut2_out[0] +.subckt adder_lut4 in[3]=$false in[2]=$false in[1]=cin in[0]=$false lut2_out[1]=cin_frac_lut4_in_lut2_out[1] lut2_out[0]=cin_frac_lut4_in_lut2_out[0] .param LUT 1100000000000011 .subckt carry_follower a=cin_frac_lut4_in_lut2_out[1] cin=cin_frac_lut4_in_lut2_out[0] cout=sum_frac_lut4_lut4_out_7_in -.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7] in[1]=$false in[0]=$false lut2_out[1]=cout_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=cout_frac_lut4_lut4_out_lut2_out[0] lut4_out=cout +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7] in[1]=$false in[0]=$false lut2_out[1]=cout_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=cout_frac_lut4_lut4_out_lut2_out[0] lut4_out=cout .param LUT 0110100101100001 -.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] in[1]=a[7] in[0]=b[7] lut2_out[1]=sum_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_lut2_out[0] lut4_out=sum[7] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] in[1]=a[7] in[0]=b[7] lut2_out[1]=sum_frac_lut4_lut4_out_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_lut2_out[0] lut4_out=sum[7] .param LUT 0110100101100001 -.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] in[1]=a[6] in[0]=b[6] lut2_out[1]=sum_frac_lut4_lut4_out_1_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_1_lut2_out[0] lut4_out=sum[6] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] in[1]=a[6] in[0]=b[6] lut2_out[1]=sum_frac_lut4_lut4_out_1_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_1_lut2_out[0] lut4_out=sum[6] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_1_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] cin=sum_frac_lut4_lut4_out_1_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] -.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] in[1]=a[5] in[0]=b[5] lut2_out[1]=sum_frac_lut4_lut4_out_2_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_2_lut2_out[0] lut4_out=sum[5] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] in[1]=a[5] in[0]=b[5] lut2_out[1]=sum_frac_lut4_lut4_out_2_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_2_lut2_out[0] lut4_out=sum[5] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_2_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] cin=sum_frac_lut4_lut4_out_2_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[5] -.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] in[1]=a[4] in[0]=b[4] lut2_out[1]=sum_frac_lut4_lut4_out_3_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_3_lut2_out[0] lut4_out=sum[4] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] in[1]=a[4] in[0]=b[4] lut2_out[1]=sum_frac_lut4_lut4_out_3_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_3_lut2_out[0] lut4_out=sum[4] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_3_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] cin=sum_frac_lut4_lut4_out_3_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[4] -.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] in[1]=a[3] in[0]=b[3] lut2_out[1]=sum_frac_lut4_lut4_out_4_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_4_lut2_out[0] lut4_out=sum[3] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] in[1]=a[3] in[0]=b[3] lut2_out[1]=sum_frac_lut4_lut4_out_4_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_4_lut2_out[0] lut4_out=sum[3] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_4_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] cin=sum_frac_lut4_lut4_out_4_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[3] -.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] in[1]=a[2] in[0]=b[2] lut2_out[1]=sum_frac_lut4_lut4_out_5_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_5_lut2_out[0] lut4_out=sum[2] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] in[1]=a[2] in[0]=b[2] lut2_out[1]=sum_frac_lut4_lut4_out_5_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_5_lut2_out[0] lut4_out=sum[2] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_5_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] cin=sum_frac_lut4_lut4_out_5_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[2] -.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] in[1]=a[1] in[0]=b[1] lut2_out[1]=sum_frac_lut4_lut4_out_6_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_6_lut2_out[0] lut4_out=sum[1] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] in[1]=a[1] in[0]=b[1] lut2_out[1]=sum_frac_lut4_lut4_out_6_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_6_lut2_out[0] lut4_out=sum[1] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_6_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] cin=sum_frac_lut4_lut4_out_6_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[1] -.subckt frac_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_7_in in[1]=a[0] in[0]=b[0] lut2_out[1]=sum_frac_lut4_lut4_out_7_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_7_lut2_out[0] lut4_out=sum[0] +.subckt adder_lut4 in[3]=$false in[2]=sum_frac_lut4_lut4_out_7_in in[1]=a[0] in[0]=b[0] lut2_out[1]=sum_frac_lut4_lut4_out_7_lut2_out[1] lut2_out[0]=sum_frac_lut4_lut4_out_7_lut2_out[0] lut4_out=sum[0] .param LUT 0110100101100001 .subckt carry_follower a=sum_frac_lut4_lut4_out_7_lut2_out[1] b=sum_frac_lut4_lut4_out_7_in cin=sum_frac_lut4_lut4_out_7_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[0] .subckt carry_follower a=sum_frac_lut4_lut4_out_lut2_out[1] b=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[6] cin=sum_frac_lut4_lut4_out_lut2_out[0] cout=sum_frac_lut4_lut4_out_lut2_out_carry_follower_a_cout[7] From cac1160bf7046d024c6ee89bb40666d7b4b4f973 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Feb 2021 11:20:56 -0700 Subject: [PATCH 38/40] [Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution --- ...n_chain_nonLR_caravel_io_skywater130nm.xml | 35 ++++++++++++++----- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 3bc866586..1ea0cd4af 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -417,6 +417,9 @@ + + + @@ -522,15 +525,28 @@ - - - - - - - + + + + + + + + + + + + + + + + - + + + + + @@ -790,11 +806,14 @@ + + + From a4c266d59a6977f47d2d8937599285d46cae46cd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Feb 2021 19:11:15 -0700 Subject: [PATCH 39/40] [Arch] Add pack patterns for soft adders; Still fail in packing --- ...n_chain_nonLR_caravel_io_skywater130nm.xml | 55 ++++++++++--------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 1ea0cd4af..e1753cf4a 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -42,6 +42,16 @@ + + + + + + + + + + @@ -52,7 +62,7 @@ - + @@ -412,7 +422,7 @@ - + @@ -495,9 +505,8 @@ - + - @@ -515,49 +524,41 @@ - - - - - - - - + - + + - + - - + - - - - - - - - - - - + + + + + + + + + From 8853370c60454409c0c96fd3083def2421871c28 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Feb 2021 20:20:10 -0700 Subject: [PATCH 40/40] [Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file --- .../benchmarks/micro_benchmark/and2/and2.eblif | 4 ++-- .../bitstream_setting_example_script.openfpga | 2 +- .../fpga_verilog/adder/soft_adder/config/task.conf | 13 ++++++++----- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif index 404af2538..45d20d1c8 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif +++ b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif @@ -7,8 +7,8 @@ .inputs a b .outputs c -.subckt adder_lut in[1]=a in[0]=b lut4_out[0]=c -.param LUT 1010101010101010 +.subckt adder_lut4 in[1]=a in[0]=b lut4_out[0]=c +.param LUT 1000100010001000 .end diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga index 0f4b1d7f6..ac0a1eafd 100644 --- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index 3eebeb32e..2be42b84c 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml +openfpga_vpr_circuit_format=eblif external_fabric_key_file= [ARCHITECTURES] @@ -27,7 +28,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_sof [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif +#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif [SYNTHESIS_PARAM] bench0_top = and2 @@ -35,10 +36,12 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 -bench1_top = adder_8 -bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act -bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v -bench1_chan_width = 300 +########################## +# Due to the limitation in pack pattern, 8-bit adder benchmark cannot pass VPR +#bench1_top = adder_8 +#bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act +#bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v +#bench1_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=