diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 5b5b5f561..10f9fd227 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -2,6 +2,7 @@ #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_log.h" +#include "command_exit_codes.h" /* begin namespace openfpga */ namespace openfpga { @@ -11,11 +12,50 @@ namespace openfpga { * This is used by bitstream generator mainly as a fast look-up to * get mapped blocks with a given coordinate *******************************************************************/ -int append_clock_rr_graph(DeviceContext& device_ctx, - const ClockNetwork& clk_ntwk) { - VTR_LOG("Adding clock nodes to routing resource graph..."); +int append_clock_rr_graph(DeviceContext& vpr_device_ctx, + const ClockNetwork& clk_ntwk, + const bool& verbose) { + vtr::ScopedStartFinishTimer timer("Adding clock nodes to routing resource graph"); - VTR_LOG("Done\n"); + /* Skip if there is no clock tree */ + if (clk_ntwk.num_trees()) { + VTR_LOG("Skip due to 0 clock trees.\nDouble check your clock architecture definition if this is unexpected\n"); + return CMD_EXEC_SUCCESS; + } + + /* Walk through the GSB array and add clock nodes to each GSB. + * Note that the GSB array is smaller than the grids by 1 column and 1 row!!! + */ + vtr::Point gsb_range(vpr_device_ctx.grid.width() - 1, + vpr_device_ctx.grid.height() - 1); + + size_t gsb_cnt = 0; + /* For each switch block, determine the size of array */ + for (size_t ix = 0; ix < gsb_range.x(); ++ix) { + for (size_t iy = 0; iy < gsb_range.y(); ++iy) { + /* Here we give the builder the fringe coordinates so that it can handle + * the GSBs at the borderside correctly sort drive_rr_nodes should be + * called if required by users + */ + const RRGSB& rr_gsb = + build_rr_gsb(vpr_device_ctx, + vtr::Point(vpr_device_ctx.grid.width() - 2, + vpr_device_ctx.grid.height() - 2), + vtr::Point(ix, iy)); + + /* Add clock nodes to device_rr_gsb */ + vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); + gsb_cnt++; /* Update counter */ + /* Print info */ + VTR_LOGV(verbose, "[%lu%] Added clock nodes to GSB[%lu][%lu]\r", + 100 * gsb_cnt / (gsb_range.x() * gsb_range.y()), ix, iy); + } + } + /* Report number of added clock nodes and edges */ + VTR_LOGV(verbose, "Appended clock nodes to %d General Switch Blocks (GSBs).\n", + gsb_range.x() * gsb_range.y()); + + return CMD_EXEC_SUCCESS; } } /* end namespace openfpga */ diff --git a/openfpga/src/annotation/append_clock_rr_graph.h b/openfpga/src/annotation/append_clock_rr_graph.h index d3658c9e1..9c20c51a6 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.h +++ b/openfpga/src/annotation/append_clock_rr_graph.h @@ -14,8 +14,9 @@ /* begin namespace openfpga */ namespace openfpga { -int append_clock_rr_graph(DeviceContext& device_ctx, - const ClockNetwork& clk_ntwk); +int append_clock_rr_graph(DeviceContext& vpr_device_ctx, + const ClockNetwork& clk_ntwk, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index ae601ae0b..99651b5a7 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -197,7 +197,7 @@ int append_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, CommandOptionId opt_verbose = cmd.option("verbose"); - return append_clock_rr_graph(g_vpr_ctx.mutable_device(), openfpga_ctx.clock_arch()); + return append_clock_rr_graph(g_vpr_ctx.mutable_device(), openfpga_ctx.clock_arch(), cmd_context.option_enable(cmd, opt_verbose)); }