From edd5be2cae572f45ff036b644d2ac184adc4bf6b Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 2 Jul 2021 12:51:34 -0600 Subject: [PATCH] [CI] Added testcase for benchmark variable --- openfpga_flow/scripts/run_fpga_task.py | 10 +++++++--- .../global_tile_4clock/config/task.conf | 3 ++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 66ac0f838..2fedb5cf6 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -271,9 +271,11 @@ def generate_each_task_actions(taskname): fallback=ys_rewrite_for_task_common) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) + benchVariable = [] for eachKey, eachValue in SynthSection.items(): - eachKey = eachKey.replace(bech_name+"_","").upper() - CurrBenchPara[eachKey] = eachValue + if bech_name in eachKey: + eachKey = eachKey.replace(bech_name+"_", "").upper() + benchVariable = benchVariable+[f"--{eachKey}"] + [eachValue] if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist @@ -335,7 +337,7 @@ def generate_each_task_actions(taskname): "bench": bench, "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, - "commands": command, + "commands": command + benchVariable, "finished": False, "status": False}) @@ -346,6 +348,8 @@ def generate_each_task_actions(taskname): # Make the directory name unique by including the benchmark index in the list. # This is because benchmarks may share the same top module names + + def get_flow_rundir(arch, top_module, flow_params=None): path = [ os.path.basename(arch).replace(".xml", ""), diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf index e7cbcb5ab..679b8e6ac 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf @@ -20,7 +20,6 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml -openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml @@ -31,7 +30,9 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch [SYNTHESIS_PARAM] bench0_top = counter4bit_2clock +bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml bench1_top = and2_latch_2clock +bench1_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=