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[test] add new tests to validate intermediate drivers in clock

This commit is contained in:
tangxifan 2024-09-20 19:27:40 -07:00
parent 2bb87ea278
commit ed33b62a60
9 changed files with 175 additions and 0 deletions
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1
openfpga_flow/regression_test_scripts/basic_reg_test.sh
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@ -262,6 +262,7 @@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver $@
echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific";
run-task basic_tests/verific_test $@ run-task basic_tests/verific_test $@

37
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml Normal file
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@ -0,0 +1,37 @@
<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
<clock_network name="clk_tree_2lvl" global_port="op_clk[0:1]">
<spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
<intermediate_driver x="1" y="1">
<tap from_pin="clb.O[0:7]" to_pin="op_clk[1:1]"/>
</intermediate_driver>
<switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/>
<switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/>
<switch_point tap="clk_rib_lvl1_sw1_upper" x="2" y="1"/>
<switch_point tap="clk_rib_lvl1_sw1_lower" x="2" y="1"/>
</spine>
<spine name="clk_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="clk_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
<all from_pin="op_clk[0:0]" to_pin="clb[0:0].I[0:11]"/>
<all from_pin="op_clk[1:1]" to_pin="clb[0:0].clk[0:0]"/>
</taps>
</clock_network>
<clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]">
<spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
<switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/>
<switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/>
<switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/>
<switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/>
</spine>
<spine name="rst_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rst_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
</taps>
</clock_network>
</clock_networks>

35
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml Normal file
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@ -0,0 +1,35 @@
<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
<clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]">
<spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
<switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/>
<switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/>
<switch_point tap="clk_rib_lvl1_sw1_upper" x="2" y="1"/>
<switch_point tap="clk_rib_lvl1_sw1_lower" x="2" y="1"/>
</spine>
<spine name="clk_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="clk_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
</taps>
</clock_network>
<clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]">
<spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
<intermediate_driver x="1" y="1">
<internal_driver from_pin="clb.O[0:7]" to_pin="op_reset[0:0]"/>
</intermediate_driver>
<switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1">
<switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1">
<switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/>
<switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/>
</spine>
<spine name="rst_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rst_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
</taps>
</clock_network>
</clock_networks>

9
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_clk_cond.xml Normal file
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@ -0,0 +1,9 @@
<pin_constraints>
<!-- For a given .blif file, we want to assign
- the reset signal to the op_reset[0] port of the FPGA fabric
-->
<set_io pin="op_reset[0]" net="OPEN"/>
<set_io pin="op_clk[0]" net="clk_i"/>
<set_io pin="op_clk[1]" net="int_clk"/>
</pin_constraints>

8
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_rst_cond.xml Normal file
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@ -0,0 +1,8 @@
<pin_constraints>
<!-- For a given .blif file, we want to assign
- the reset signal to the op_reset[0] port of the FPGA fabric
-->
<set_io pin="op_reset[0]" net="int_rst"/>
<set_io pin="op_clk[0]" net="clk_i"/>
</pin_constraints>

4
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/repack_pin_constraints.xml Normal file
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@ -0,0 +1,4 @@
<repack_design_constraints>
<!-- Intended to be dummy -->
</repack_design_constraints>

57
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/task.conf Normal file
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@ -0,0 +1,57 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 3*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=32
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml
openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
openfpga_route_clock_options=
openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = clk_cond
bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_cond.xml
bench0_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml
bench0_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml
bench1_top = rst_cond
bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_cond.xml
bench1_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_rst_cond.xml
bench1_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

12
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml Normal file
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@ -0,0 +1,12 @@
<vpr_constraints tool_name="vpr">
<partition_list>
<partition name="q_o_part">
<add_atom name_pattern="q_o"/>
<add_region x_low="1" y_low="2" x_high="1" y_high="2"/>
</partition>
<partition name="int_clk_part">
<add_atom name_pattern="int_clk*"/>
<add_region x_low="1" y_low="1" x_high="1" y_high="1"/>
</partition>
</partition_list>
</vpr_constraints>

12
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml Normal file
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@ -0,0 +1,12 @@
<vpr_constraints tool_name="vpr">
<partition_list>
<partition name="q_o_part">
<add_atom name_pattern="q_o"/>
<add_region x_low="1" y_low="2" x_high="1" y_high="2"/>
</partition>
<partition name="int_rst_part">
<add_atom name_pattern="int_rst*"/>
<add_region x_low="1" y_low="1" x_high="1" y_high="1"/>
</partition>
</partition_list>
</vpr_constraints>