add frame decoder build-up to top-level module

openfpga/src/fabric/build_device_module.cpp

@@ -105,7 +105,9 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
   }
 
   /* Build FPGA fabric top-level module */
-  build_top_module(module_manager, io_location_map,
+  build_top_module(module_manager,
+                   io_location_map,
+                   decoder_lib,
                    openfpga_ctx.arch().circuit_lib, 
                    vpr_device_ctx.grid,
                    vpr_device_ctx.rr_graph,

openfpga/src/fabric/build_top_module.cpp

@@ -311,6 +311,7 @@ vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& mod
  *******************************************************************/
 void build_top_module(ModuleManager& module_manager,
                       IoLocationMap& io_location_map,
+                      DecoderLibrary& decoder_lib,
                       const CircuitLibrary& circuit_lib,
                       const DeviceGrid& grids,
                       const RRGraph& rr_graph,
@@ -390,7 +391,8 @@ void build_top_module(ModuleManager& module_manager,
    * This is a one-shot addition that covers all the memory modules in this pb module!
    */
   if (0 < module_manager.configurable_children(top_module).size()) {
-    add_top_module_nets_memory_config_bus(module_manager, top_module, 
+    add_top_module_nets_memory_config_bus(module_manager, decoder_lib,
+                                          top_module, 
                                           sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
 }

openfpga/src/fabric/build_top_module.h

@@ -11,6 +11,7 @@
 #include "rr_graph_obj.h"
 #include "device_rr_gsb.h"
 #include "circuit_library.h"
+#include "decoder_library.h"
 #include "tile_direct.h"
 #include "arch_direct.h"
 #include "module_manager.h"
@@ -25,6 +26,7 @@ namespace openfpga {
 
 void build_top_module(ModuleManager& module_manager,
                       IoLocationMap& io_location_map,
+                      DecoderLibrary& decoder_lib,
                       const CircuitLibrary& circuit_lib,
                       const DeviceGrid& grids,
                       const RRGraph& rr_graph,

openfpga/src/fabric/build_top_module_memory.cpp

@@ -408,6 +408,7 @@ void organize_top_module_memory_modules(ModuleManager& module_manager,
  **********************************************************************/
 static 
 void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
+                                                DecoderLibrary& decoder_lib,
                                                 const ModuleId& parent_module,
                                                 const e_config_protocol_type& sram_orgz_type) {
   switch (sram_orgz_type) {
@@ -423,6 +424,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
     break;
   case CONFIG_MEM_FRAME_BASED:
     /* TODO: */
+    add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
     break;
   default:
     VTR_LOGF_ERROR(__FILE__, __LINE__,
@@ -464,12 +466,14 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
  * and its child module (logic_module and memory_module) is created! 
  *******************************************************************/
 void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                           DecoderLibrary& decoder_lib,
                                            const ModuleId& parent_module,
                                            const e_config_protocol_type& sram_orgz_type, 
                                            const e_circuit_model_design_tech& mem_tech) {
   switch (mem_tech) {
   case CIRCUIT_MODEL_DESIGN_CMOS:
-    add_top_module_nets_cmos_memory_config_bus(module_manager, parent_module, 
+    add_top_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,
+                                               parent_module, 
                                                sram_orgz_type);
     break;
   case CIRCUIT_MODEL_DESIGN_RRAM:

openfpga/src/fabric/build_top_module_memory.h

@@ -11,6 +11,7 @@
 #include "module_manager.h"
 #include "circuit_types.h"
 #include "circuit_library.h"
+#include "decoder_library.h"
 #include "device_grid.h"
 #include "device_rr_gsb.h"
 
@@ -34,6 +35,7 @@ void organize_top_module_memory_modules(ModuleManager& module_manager,
                                         const bool& compact_routing_hierarchy);
 
 void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                           DecoderLibrary& decoder_lib,
                                            const ModuleId& parent_module,
                                            const e_config_protocol_type& sram_orgz_type, 
                                            const e_circuit_model_design_tech& mem_tech);