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[core] code format

This commit is contained in:
tangxifan 2024-06-21 17:11:32 -07:00
parent 3ddaefc2a2
commit ecd31955b1
4 changed files with 26 additions and 14 deletions
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11
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -181,8 +181,12 @@ std::string ClockNetwork::default_driver_switch_name() const {
return default_driver_switch_name_;
}
RRSwitchId ClockNetwork::default_tap_switch() const { return default_tap_switch_id_; }
RRSwitchId ClockNetwork::default_driver_switch() const { return default_driver_switch_id_; }
RRSwitchId ClockNetwork::default_tap_switch() const {
return default_tap_switch_id_;
}
RRSwitchId ClockNetwork::default_driver_switch() const {
return default_driver_switch_id_;
}
std::string ClockNetwork::tree_name(const ClockTreeId& tree_id) const {
VTR_ASSERT(valid_tree_id(tree_id));
@ -636,7 +640,8 @@ bool ClockNetwork::validate_tree() const {
bool ClockNetwork::validate() const {
is_dirty_ = true;
if (default_segment_id_ && default_tap_switch_id_ && default_driver_switch_id_ && validate_tree()) {
if (default_segment_id_ && default_tap_switch_id_ &&
default_driver_switch_id_ && validate_tree()) {
is_dirty_ = false;
}
return true;

8
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -253,11 +253,11 @@ class ClockNetwork {
std::string default_segment_name_; /* The routing segment representing the
clock wires */
RRSegmentId default_segment_id_;
std::string
default_tap_switch_name_; /* The routing switch interconnecting clock wire */
std::string default_tap_switch_name_; /* The routing switch interconnecting
clock wire */
RRSwitchId default_tap_switch_id_;
std::string
default_driver_switch_name_; /* The routing switch interconnecting clock wire */
std::string default_driver_switch_name_; /* The routing switch interconnecting
clock wire */
RRSwitchId default_driver_switch_id_;
/* Fast lookup */

13
libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp
View File

@ -45,12 +45,16 @@ static int link_clock_network_rr_switches(ClockNetwork& clk_ntwk,
}
}
if (status != CMD_EXEC_SUCCESS) {
VTR_LOG("Unable to find the default tap switch '%s' in VPR architecture description!\n", default_tap_switch_name.c_str());
VTR_LOG(
"Unable to find the default tap switch '%s' in VPR architecture "
"description!\n",
default_tap_switch_name.c_str());
return CMD_EXEC_FATAL_ERROR;
}
/* default driver switch id */
status = CMD_EXEC_FATAL_ERROR;
std::string default_driver_switch_name = clk_ntwk.default_driver_switch_name();
std::string default_driver_switch_name =
clk_ntwk.default_driver_switch_name();
for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches();
++rr_switch_id) {
if (std::string(rr_graph.rr_switch_inf(RRSwitchId(rr_switch_id)).name) ==
@ -61,7 +65,10 @@ static int link_clock_network_rr_switches(ClockNetwork& clk_ntwk,
}
}
if (status != CMD_EXEC_SUCCESS) {
VTR_LOG("Unable to find the default driver switch '%s' in VPR architecture description!\n", default_driver_switch_name.c_str());
VTR_LOG(
"Unable to find the default driver switch '%s' in VPR architecture "
"description!\n",
default_driver_switch_name.c_str());
return CMD_EXEC_FATAL_ERROR;
}

8
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -525,8 +525,8 @@ static void add_rr_graph_block_clock_edges(
chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir)) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(src_node, des_node,
clk_ntwk.default_driver_switch(), false);
rr_graph_builder.create_edge(
src_node, des_node, clk_ntwk.default_driver_switch(), false);
edge_count++;
}
VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n",
@ -541,8 +541,8 @@ static void add_rr_graph_block_clock_edges(
itree, ClockTreePinId(ipin))) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(src_node, des_node,
clk_ntwk.default_tap_switch(), false);
rr_graph_builder.create_edge(
src_node, des_node, clk_ntwk.default_tap_switch(), false);
edge_count++;
}
VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n",