From ec3b4c86c4202549edb6090c3ff9b5b4cf5b0147 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 21 May 2019 12:15:38 -0600 Subject: [PATCH] update file organization and be ready for SB/CB class --- .gitignore | 3 + .../fpga_spice/k6_N10_sram_tsmc40nm_TT.conf | 34 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h | 2 +- .../fpga_x2p/base/fpga_x2p_unique_routing.c | 2 +- .../base/{rr_chan.cpp => rr_blocks.cpp} | 2 +- .../fpga_x2p/base/{rr_chan.h => rr_blocks.h} | 0 vpr7_x2p/vpr/SRC/tags | 4699 ----------------- 7 files changed, 23 insertions(+), 4719 deletions(-) rename vpr7_x2p/vpr/SRC/fpga_x2p/base/{rr_chan.cpp => rr_blocks.cpp} (99%) rename vpr7_x2p/vpr/SRC/fpga_x2p/base/{rr_chan.h => rr_blocks.h} (100%) delete mode 100644 vpr7_x2p/vpr/SRC/tags diff --git a/.gitignore b/.gitignore index 524324315..4205795c4 100644 --- a/.gitignore +++ b/.gitignore @@ -4,6 +4,9 @@ # temp files .DS_Store +# ctags +tags + # log files **/logs *.log diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf index b0dcf89f6..9d3ab267d 100644 --- a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf +++ b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf @@ -1,27 +1,27 @@ # Standard Configuration Example [dir_path] -script_base = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/scripts/ -benchmark_dir = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench/ -yosys_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../yosys/yosys -odin2_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/odin2.exe -cirkit_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/cirkit -abc_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../yosys/yosys-abc -abc_mccl_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc -abc_with_bb_support_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../abc_with_bb_support/abc -mpack1_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/mpack1 -m2net_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/m2net -mpack2_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/not_used_atm/mpack2 -vpr_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../vpr7_x2p/vpr/vpr -rpt_dir = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/results -ace_path = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/../ace2/ace +script_base = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/scripts/ +benchmark_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench/ +yosys_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../yosys/yosys +odin2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/odin2.exe +cirkit_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/cirkit +abc_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../yosys/yosys-abc +abc_mccl_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../abc_with_bb_support/abc +abc_with_bb_support_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../abc_with_bb_support/abc +mpack1_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack1 +m2net_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/m2net +mpack2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack2 +vpr_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../vpr7_x2p/vpr/vpr +rpt_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/results +ace_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../ace2/ace [flow_conf] flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr -vpr_arch = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK +vpr_arch = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +m2net_conf = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = /var/tmp/Presentation_OpenFPGA/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK +power_tech_xml = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK [csv_tags] mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h index 12270b785..2ef8e95f1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h @@ -1,7 +1,7 @@ #ifndef FPGA_X2P_GLOBALS_H #define FPGA_X2P_GLOBALS_H -#include "rr_chan.h" +#include "rr_blocks.h" /* global parameters for FPGA-SPICE tool suites */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index 62de45d08..c4da1741e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -27,7 +27,7 @@ /* Include spice support headers*/ #include "read_xml_spice_util.h" #include "linkedlist.h" -#include "rr_chan.h" +#include "rr_blocks.h" #include "fpga_x2p_types.h" #include "fpga_x2p_globals.h" #include "fpga_x2p_utils.h" diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp similarity index 99% rename from vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index f88428237..98c0dfff7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -1,6 +1,6 @@ #include -#include "rr_chan.h" +#include "rr_blocks.h" /* Member Functions of Class RRChan */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h diff --git a/vpr7_x2p/vpr/SRC/tags b/vpr7_x2p/vpr/SRC/tags deleted file mode 100644 index 3a97f03ea..000000000 --- a/vpr7_x2p/vpr/SRC/tags +++ /dev/null @@ -1,4699 +0,0 @@ -!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ -!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ -!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ -!_TAG_PROGRAM_NAME Exuberant Ctags // -!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ -!_TAG_PROGRAM_VERSION 5.8 // -AAPACK_MAX_FEASIBLE_BLOCK_ARRAY_SIZE ./pack/cluster.c 35;" d file: -AAPACK_MAX_HIGH_FANOUT_EXPLORE ./pack/cluster.c 37;" d file: -AAPACK_MAX_NET_SINKS_IGNORE ./pack/cluster.c 36;" d file: -AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST ./pack/cluster.c 33;" d file: -AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC ./pack/cluster.c 32;" d file: -ABORTED ./place/place.c /^ REJECTED, ACCEPTED, ABORTED$/;" e enum:swap_result file: -ABS_DIFF ./place/place_stats.c 7;" d file: -ACCEPTED ./place/place.c /^ REJECTED, ACCEPTED, ABORTED$/;" e enum:swap_result file: -ACTIVITY_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 5;" d -ALLOW_SWITCH_OFF ./route/rr_graph2.c 16;" d file: -ALL_NETS ./base/draw.c /^ ALL_NETS, HIGHLIGHTED$/;" e enum:e_draw_net_type file: -ANALYSIS_CMD ./fpga_x2p/shell/shell_types.h /^ ANALYSIS_CMD,$/;" e enum:e_cmd_category -ANY ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -ANYBUT ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -ANYOF ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -AUTO_SCHED ./base/vpr_types.h /^ AUTO_SCHED, USER_SCHED$/;" e enum:sched_type -ActFile ./base/ReadOptions.h /^ char *ActFile;$/;" m struct:s_options -ActFile ./base/vpr_types.h /^ char *ActFile;$/;" m struct:s_file_name_opts -AnnealSched ./base/vpr_types.h /^ struct s_annealing_sched AnnealSched; \/* Placement option annealing schedule *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_annealing_sched -ArchFile ./base/ReadOptions.h /^ char *ArchFile;$/;" m struct:s_options -ArchFile ./base/vpr_types.h /^ char *ArchFile;$/;" m struct:s_file_name_opts -BASIC_CMD ./fpga_x2p/shell/shell_types.h /^ BASIC_CMD,$/;" e enum:e_cmd_category -BISQUE ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -BI_DIRECTION ./base/vpr_types.h /^ INC_DIRECTION = 0, DEC_DIRECTION = 1, BI_DIRECTION = 2$/;" e enum:e_direction -BLACK ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types -BLIF_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 1;" d -BLIF_LUT_KEYWORD ./fpga_x2p/base/fpga_x2p_types.h 18;" d -BLIF_TOKENS ./base/read_blif.c 235;" d file: -BLK_FAILED_FEASIBLE ./base/vpr_types.h /^ BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_FAILED_ROUTE, BLK_STATUS_UNDEFINED$/;" e enum:e_block_pack_status -BLK_FAILED_ROUTE ./base/vpr_types.h /^ BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_FAILED_ROUTE, BLK_STATUS_UNDEFINED$/;" e enum:e_block_pack_status -BLK_PASSED ./base/vpr_types.h /^ BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_FAILED_ROUTE, BLK_STATUS_UNDEFINED$/;" e enum:e_block_pack_status -BLK_STATUS_UNDEFINED ./base/vpr_types.h /^ BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_FAILED_ROUTE, BLK_STATUS_UNDEFINED$/;" e enum:e_block_pack_status -BLOCK_COUNT ./place/timing_place_lookup.c 52;" d file: -BLUE ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types -BOL ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -BOUNDING_BOX_PLACE ./base/vpr_types.h /^ BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE$/;" e enum:e_place_algorithm -BRANCH ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -BREADTH_FIRST ./base/vpr_types.h /^ BREADTH_FIRST, TIMING_DRIVEN, NO_TIMING$/;" e enum:e_router_algorithm -BUFFER_INSERTION_H ./mrfpga/buffer_insertion.h 2;" d -BUFSIZE ./base/graphics.c 184;" d file: -BUF_AND_PTRANS_FLAG ./route/check_rr_graph.c 16;" d file: -BUF_FLAG ./route/check_rr_graph.c 14;" d file: -BUTTON_POLY ./base/graphics.c /^ BUTTON_POLY,$/;" e enum:__anon3 file: -BUTTON_SEPARATOR ./base/graphics.c /^ BUTTON_SEPARATOR$/;" e enum:__anon3 file: -BUTTON_TEXT ./base/graphics.c /^ BUTTON_TEXT = 0,$/;" e enum:__anon3 file: -BUTTON_TEXT_LEN ./base/graphics.c 183;" d file: -BitstreamGenOpts ./base/vpr_types.h /^ t_bitstream_gen_opts BitstreamGenOpts; \/* Xifan Bitsteam Generator *\/$/;" m struct:s_fpga_spice_opts -BlifFile ./base/ReadOptions.h /^ char *BlifFile;$/;" m struct:s_options -BlifFile ./base/vpr_types.h /^ char *BlifFile;$/;" m struct:s_file_name_opts -ButtonsWND ./base/graphics.c /^ButtonsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: -C ./base/vpr_types.h /^ float C;$/;" m struct:s_rr_node -CAL_CAPACITANCE_H ./mrfpga/cal_capacitance.h 2;" d -CHANX ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type -CHANX_COST_INDEX_START ./base/vpr_types.h /^ CHANX_COST_INDEX_START$/;" e enum:e_cost_indices -CHANY ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type -CHECK ./place/place.c /^ NORMAL, CHECK$/;" e enum:cost_methods file: -CHECK_NETLIST_H ./base/check_netlist.h 2;" d -CHECK_RR_GRAPH_H ./route/check_rr_graph.h 2;" d -CLOCK_DENS ./power/power.h 37;" d -CLOCK_PROB ./power/power.h 36;" d -CLOSE ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -CLUSTER_FEASIBILITY_CHECK_H ./pack/cluster_feasibility_filter.h 23;" d -CLUSTER_LEGALITY_H ./pack/cluster_legality.h 2;" d -CLUSTER_PLACEMENT_H ./pack/cluster_placement.h 7;" d -CMOS_TECH_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 7;" d -CONVERT_NM_PER_M ./power/power.c 50;" d file: -CONVERT_UM_PER_M ./power/power.c 51;" d file: -CORAL ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -CREATE_ERROR ./base/graphics.c 219;" d file: -CYAN ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -C_d ./power/power.h /^ float C_d;$/;" m struct:s_transistor_size_inf -C_downstream ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: -C_downstream ./route/route_tree_timing.h /^ float C_downstream;$/;" m struct:s_rt_node -C_downstream ./timing/net_delay_types.h /^ float C_downstream;$/;" m struct:s_rc_node -C_g ./power/power.h /^ float C_g;$/;" m struct:s_transistor_size_inf -C_load ./base/vpr_types.h /^ float C_load;$/;" m struct:s_rr_indexed_data -C_s ./power/power.h /^ float C_s;$/;" m struct:s_transistor_size_inf -C_tile_per_m ./base/vpr_types.h /^ float C_tile_per_m;$/;" m struct:s_rr_indexed_data -CheckArch ./base/CheckArch.c /^void CheckArch(INP t_arch Arch, INP boolean TimingEnabled) {$/;" f -CheckGrid ./base/SetupGrid.c /^static void CheckGrid() {$/;" f file: -CheckOptions ./base/CheckOptions.c /^void CheckOptions(INP t_options Options, INP boolean TimingEnabled) {$/;" f -CheckSegments ./base/CheckArch.c /^static void CheckSegments(INP t_arch Arch) {$/;" f file: -CheckSetup ./base/CheckSetup.c /^void CheckSetup(INP enum e_operation Operation,$/;" f -CheckSwitches ./base/CheckArch.c /^static void CheckSwitches(INP t_arch Arch, INP boolean TimingEnabled) {$/;" f file: -CircuitName ./base/ReadOptions.h /^ char *CircuitName;$/;" m struct:s_options -CircuitName ./base/vpr_types.h /^ char *CircuitName;$/;" m struct:s_file_name_opts -Cmetal ./base/vpr_types.h /^ float Cmetal;$/;" m struct:s_seg_details -Cmetal_per_m ./base/vpr_types.h /^ float Cmetal_per_m; \/* Used for power *\/$/;" m struct:s_seg_details -CmosTechFile ./base/ReadOptions.h /^ char *CmosTechFile;$/;" m struct:s_options -CmosTechFile ./base/vpr_types.h /^ char *CmosTechFile;$/;" m struct:s_file_name_opts -Count ./base/ReadOptions.h /^ int Count[OT_BASE_UNKNOWN];$/;" m struct:s_options -CreateEchoFile ./base/ReadOptions.h /^ boolean CreateEchoFile;$/;" m struct:s_options -Cseg_global ./mrfpga/mrfpga_globals.c /^float Rseg_global, Cseg_global;$/;" v -DARKGREEN ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -DARKGREY ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types -DARKKHAKI ./base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types -DARKSLATEBLUE ./base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types -DASHED ./base/easygl_constants.h /^enum line_types {SOLID, DASHED};$/;" e enum:line_types -DEBUG ./base/vpr_types.h 46;" d -DEBUG_TIMING_PLACE_LOOKUP ./place/timing_place_lookup.c 61;" d file: -DEC_DIRECTION ./base/vpr_types.h /^ INC_DIRECTION = 0, DEC_DIRECTION = 1, BI_DIRECTION = 2$/;" e enum:e_direction -DEFAULT_MUX_PATH_ID ./fpga_x2p/base/fpga_x2p_types.h 13;" d -DEFAULT_PATH_ID ./fpga_x2p/base/fpga_x2p_types.h 10;" d -DEFAULT_PREV_NODE ./fpga_x2p/base/fpga_x2p_types.h 7;" d -DEFAULT_SWITCH_ID ./fpga_x2p/base/fpga_x2p_types.h 4;" d -DEGTORAD ./base/graphics.c 228;" d file: -DELAY_NORMALIZED ./base/vpr_types.h /^ INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY$/;" e enum:e_base_cost_type -DELETE_ERROR ./base/graphics.c 218;" d file: -DEMAND_ONLY ./base/vpr_types.h /^ INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY$/;" e enum:e_base_cost_type -DETAILED ./base/vpr_types.h /^ GLOBAL, DETAILED$/;" e enum:e_route_type -DIGIT ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -DISCOUNT_FUNCTION_BASE ./timing/path_delay.h 23;" d -DO_NOT_ANALYSE ./timing/path_delay.h 4;" d -DRAW_ALL_BUT_BUFFERS_RR ./base/draw.c /^ DRAW_ALL_BUT_BUFFERS_RR,$/;" e enum:e_draw_rr_toggle file: -DRAW_ALL_RR ./base/draw.c /^ DRAW_ALL_RR,$/;" e enum:e_draw_rr_toggle file: -DRAW_ERROR ./base/graphics.c 220;" d file: -DRAW_NODES_AND_SBOX_RR ./base/draw.c /^ DRAW_NODES_AND_SBOX_RR,$/;" e enum:e_draw_rr_toggle file: -DRAW_NODES_RR ./base/draw.c /^ DRAW_NODES_RR,$/;" e enum:e_draw_rr_toggle file: -DRAW_NORMAL ./base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/;" e enum:e_draw_mode -DRAW_NO_RR ./base/draw.c /^ DRAW_NO_RR = 0,$/;" e enum:e_draw_rr_toggle file: -DRAW_RR_TOGGLE_MAX ./base/draw.c /^ DRAW_RR_TOGGLE_MAX$/;" e enum:e_draw_rr_toggle file: -DRAW_XOR ./base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/;" e enum:e_draw_mode -DUMPFILE ./place/timing_place_lookup.c 63;" d file: -DeviceRRChan ./fpga_x2p/base/rr_chan.h /^class DeviceRRChan {$/;" c -EASYGL_CONSTANTS_H ./base/easygl_constants.h 2;" d -EMPTY ./base/vpr_types.h 90;" d -EMPTY_TYPE ./base/globals.c /^t_type_ptr EMPTY_TYPE = NULL;$/;" v -EMPTY_TYPE_BACKUP ./place/timing_place_lookup.c /^static t_type_ptr EMPTY_TYPE_BACKUP;$/;" v file: -ENABLE_REVERSE ./route/rr_graph2.c 21;" d file: -END ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -EOL ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -EPSILON ./base/vpr_types.h 83;" d -ERROR_THRESHOLD ./base/check_netlist.c 15;" d file: -ERROR_TOL ./place/place.c 31;" d file: -ERROR_TOL ./route/route_timing.c 884;" d file: -EXACT ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -E_CRITICALITY_FILE ./base/ReadOptions.h /^ E_CRITICALITY_FILE,$/;" e enum:e_output_files -E_CRIT_PATH_FILE ./base/ReadOptions.h /^ E_CRIT_PATH_FILE,$/;" e enum:e_output_files -E_DETAILED_ROUTE_AT_END_ONLY ./pack/cluster.c /^ E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END$/;" e enum:e_detailed_routing_stages file: -E_DETAILED_ROUTE_END ./pack/cluster.c /^ E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END$/;" e enum:e_detailed_routing_stages file: -E_DETAILED_ROUTE_FOR_EACH_ATOM ./pack/cluster.c /^ E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END$/;" e enum:e_detailed_routing_stages file: -E_DIR_EXIST ./fpga_x2p/base/fpga_x2p_utils.c /^ E_DIR_EXIST$/;" e enum:e_dir_err file: -E_DIR_NOT_EXIST ./fpga_x2p/base/fpga_x2p_utils.c /^ E_DIR_NOT_EXIST,$/;" e enum:e_dir_err file: -E_ECHO_ARCH ./base/ReadOptions.h /^ E_ECHO_ARCH,$/;" e enum:e_echo_files -E_ECHO_BLIF_INPUT ./base/ReadOptions.h /^ E_ECHO_BLIF_INPUT,$/;" e enum:e_echo_files -E_ECHO_CLUSTERING_BLOCK_CRITICALITIES ./base/ReadOptions.h /^ E_ECHO_CLUSTERING_BLOCK_CRITICALITIES,$/;" e enum:e_echo_files -E_ECHO_CLUSTERING_TIMING_INFO ./base/ReadOptions.h /^ E_ECHO_CLUSTERING_TIMING_INFO,$/;" e enum:e_echo_files -E_ECHO_COMPLETE_NET_TRACE ./base/ReadOptions.h /^ E_ECHO_COMPLETE_NET_TRACE,$/;" e enum:e_echo_files -E_ECHO_CRITICALITY ./base/ReadOptions.h /^ E_ECHO_CRITICALITY,$/;" e enum:e_echo_files -E_ECHO_CRITICAL_PATH ./base/ReadOptions.h /^ E_ECHO_CRITICAL_PATH,$/;" e enum:e_echo_files -E_ECHO_END_CLB_PLACEMENT ./base/ReadOptions.h /^ E_ECHO_END_CLB_PLACEMENT,$/;" e enum:e_echo_files -E_ECHO_END_TOKEN ./base/ReadOptions.h /^ E_ECHO_END_TOKEN$/;" e enum:e_echo_files -E_ECHO_FINAL_PLACEMENT_CRITICALITY ./base/ReadOptions.h /^ E_ECHO_FINAL_PLACEMENT_CRITICALITY,$/;" e enum:e_echo_files -E_ECHO_FINAL_PLACEMENT_SLACK ./base/ReadOptions.h /^ E_ECHO_FINAL_PLACEMENT_SLACK,$/;" e enum:e_echo_files -E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH ./base/ReadOptions.h /^ E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH,$/;" e enum:e_echo_files -E_ECHO_INITIAL_CLB_PLACEMENT ./base/ReadOptions.h /^ E_ECHO_INITIAL_CLB_PLACEMENT = 0,$/;" e enum:e_echo_files -E_ECHO_INITIAL_PLACEMENT_CRITICALITY ./base/ReadOptions.h /^ E_ECHO_INITIAL_PLACEMENT_CRITICALITY,$/;" e enum:e_echo_files -E_ECHO_INITIAL_PLACEMENT_SLACK ./base/ReadOptions.h /^ E_ECHO_INITIAL_PLACEMENT_SLACK,$/;" e enum:e_echo_files -E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH ./base/ReadOptions.h /^ E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH,$/;" e enum:e_echo_files -E_ECHO_LUT_REMAPPING ./base/ReadOptions.h /^ E_ECHO_LUT_REMAPPING,$/;" e enum:e_echo_files -E_ECHO_MEM ./base/ReadOptions.h /^ E_ECHO_MEM,$/;" e enum:e_echo_files -E_ECHO_NET_DELAY ./base/ReadOptions.h /^ E_ECHO_NET_DELAY,$/;" e enum:e_echo_files -E_ECHO_PB_GRAPH ./base/ReadOptions.h /^ E_ECHO_PB_GRAPH,$/;" e enum:e_echo_files -E_ECHO_PLACEMENT_CRITICAL_PATH ./base/ReadOptions.h /^ E_ECHO_PLACEMENT_CRITICAL_PATH,$/;" e enum:e_echo_files -E_ECHO_PLACEMENT_CRIT_PATH ./base/ReadOptions.h /^ E_ECHO_PLACEMENT_CRIT_PATH,$/;" e enum:e_echo_files -E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS ./base/ReadOptions.h /^ E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS,$/;" e enum:e_echo_files -E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS ./base/ReadOptions.h /^ E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS,$/;" e enum:e_echo_files -E_ECHO_PLACEMENT_SINK_DELAYS ./base/ReadOptions.h /^ E_ECHO_PLACEMENT_SINK_DELAYS,$/;" e enum:e_echo_files -E_ECHO_POST_FLOW_TIMING_GRAPH ./base/ReadOptions.h /^ E_ECHO_POST_FLOW_TIMING_GRAPH,$/;" e enum:e_echo_files -E_ECHO_POST_PACK_NETLIST ./base/ReadOptions.h /^ E_ECHO_POST_PACK_NETLIST,$/;" e enum:e_echo_files -E_ECHO_PRE_PACKING_CRITICALITY ./base/ReadOptions.h /^ E_ECHO_PRE_PACKING_CRITICALITY,$/;" e enum:e_echo_files -E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS ./base/ReadOptions.h /^ E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS,$/;" e enum:e_echo_files -E_ECHO_PRE_PACKING_SLACK ./base/ReadOptions.h /^ E_ECHO_PRE_PACKING_SLACK,$/;" e enum:e_echo_files -E_ECHO_PRE_PACKING_TIMING_GRAPH ./base/ReadOptions.h /^ E_ECHO_PRE_PACKING_TIMING_GRAPH,$/;" e enum:e_echo_files -E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF ./base/ReadOptions.h /^ E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF,$/;" e enum:e_echo_files -E_ECHO_ROUTING_SINK_DELAYS ./base/ReadOptions.h /^ E_ECHO_ROUTING_SINK_DELAYS,$/;" e enum:e_echo_files -E_ECHO_RR_GRAPH ./base/ReadOptions.h /^ E_ECHO_RR_GRAPH,$/;" e enum:e_echo_files -E_ECHO_SEG_DETAILS ./base/ReadOptions.h /^ E_ECHO_SEG_DETAILS,$/;" e enum:e_echo_files -E_ECHO_SLACK ./base/ReadOptions.h /^ E_ECHO_SLACK,$/;" e enum:e_echo_files -E_ECHO_TIMING_CONSTRAINTS ./base/ReadOptions.h /^ E_ECHO_TIMING_CONSTRAINTS,$/;" e enum:e_echo_files -E_ECHO_TIMING_GRAPH ./base/ReadOptions.h /^ E_ECHO_TIMING_GRAPH,$/;" e enum:e_echo_files -E_EXIST_BUT_NOT_DIR ./fpga_x2p/base/fpga_x2p_utils.c /^ E_EXIST_BUT_NOT_DIR,$/;" e enum:e_dir_err file: -E_FILE_END_TOKEN ./base/ReadOptions.h /^ E_FILE_END_TOKEN$/;" e enum:e_output_files -E_SLACK_FILE ./base/ReadOptions.h /^ E_SLACK_FILE,$/;" e enum:e_output_files -EchoEnabled ./base/ReadOptions.c /^static boolean EchoEnabled;$/;" v file: -Enum ./base/vpr_types.h /^ int Enum;$/;" m struct:s_TokenPair -Error ./base/ReadOptions.c /^static void Error(INP const char *Token) {$/;" f file: -FALSE ./base/graphics.c 146;" d file: -FEASIBLE ./pack/cluster.c /^ FEASIBLE, INFEASIBLE$/;" e enum:e_feasibility file: -FILL_TYPE ./base/globals.c /^t_type_ptr FILL_TYPE = NULL;$/;" v -FILL_TYPE_BACKUP ./place/timing_place_lookup.c /^static t_type_ptr FILL_TYPE_BACKUP;$/;" v file: -FINAL_DISCOUNT_FUNCTION_BASE ./timing/path_delay.h 28;" d -FIRST_ITER_WIRELENTH_LIMIT ./base/vpr_types.h 88;" d -FONTMAG ./base/graphics.c 229;" d file: -FPGA_SPICE_Opts ./base/vpr_types.h /^ t_fpga_spice_opts FPGA_SPICE_Opts; \/* Xifan TANG: FPGA-SPICE support *\/$/;" m struct:s_vpr_setup -FPGA_X2P_GLOBALS_H ./fpga_x2p/base/fpga_x2p_globals.h 2;" d -FPGA_X2P_IDENTIFY_ROUTING ./fpga_x2p/base/fpga_x2p_identify_routing.h 3;" d -FPGA_X2P_UTILS_H ./fpga_x2p/base/fpga_x2p_utils.h 2;" d -FREE ./base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type -FROM_X_TO_Y ./base/draw.c /^ FROM_X_TO_Y, FROM_Y_TO_X$/;" e enum:e_edge_dir file: -FROM_Y_TO_X ./base/draw.c /^ FROM_X_TO_Y, FROM_Y_TO_X$/;" e enum:e_edge_dir file: -FileNameOpts ./base/vpr_types.h /^ struct s_file_name_opts FileNameOpts; \/* File names *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_file_name_opts -Fs ./base/vpr_types.h /^ int Fs;$/;" m struct:s_det_routing_arch -Fs_seed ./base/globals.c /^int Fs_seed = -1;$/;" v -GAIN ./pack/cluster.c /^ GAIN, NO_GAIN$/;" e enum:e_gain_update file: -GLOBAL ./base/vpr_types.h /^ GLOBAL, DETAILED$/;" e enum:e_route_type -GLOBALS_H ./base/globals.h 13;" d -GOT_FROM_SCRATCH ./place/place.c 47;" d file: -GRAPHICS_H ./base/graphics.h 3;" d -GRAPH_BIDIR ./route/rr_graph.h /^ GRAPH_BIDIR, \/* Detailed bidirectional graph *\/$/;" e enum:e_graph_type -GRAPH_GLOBAL ./route/rr_graph.h /^ GRAPH_GLOBAL, \/* One node per channel with wire capacity > 1 and full connectivity *\/$/;" e enum:e_graph_type -GRAPH_UNIDIR ./route/rr_graph.h /^ GRAPH_UNIDIR, \/* Detailed unidir graph, untilable *\/$/;" e enum:e_graph_type -GRAPH_UNIDIR_TILEABLE ./route/rr_graph.h /^ GRAPH_UNIDIR_TILEABLE \/* Detail unidir graph with wire groups multiples of 2*L *\/$/;" e enum:e_graph_type -GREEN ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types -Generate_PostSynthesis_Netlist ./base/ReadOptions.c /^static boolean Generate_PostSynthesis_Netlist;$/;" v file: -Generate_Post_Synthesis_Netlist ./base/ReadOptions.h /^ boolean Generate_Post_Synthesis_Netlist;$/;" m struct:s_options -GetPostSynthesisOption ./base/ReadOptions.c /^boolean GetPostSynthesisOption(void){$/;" f -GetTokenTypeFromChar ./util/token.c /^enum e_token_type GetTokenTypeFromChar(INP enum e_token_type cur_token_type,$/;" f -GetTokensFromString ./util/token.c /^t_token *GetTokensFromString(INP const char* inString, OUTP int * num_tokens) {$/;" f -GraphPause ./base/ReadOptions.h /^ int GraphPause;$/;" m struct:s_options -GraphPause ./base/vpr_types.h /^ int GraphPause; \/* user interactiveness graphics option *\/$/;" m struct:s_vpr_setup -GraphicsWND ./base/graphics.c /^GraphicsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: -HASHSIZE ./util/hash.h 1;" d -HELP_OPT_NAME ./fpga_x2p/shell/read_opt_types.h 54;" d -HELP_OPT_TAG ./fpga_x2p/shell/read_opt_types.h 53;" d -HIGHLIGHTED ./base/draw.c /^ ALL_NETS, HIGHLIGHTED$/;" e enum:e_draw_net_type file: -HIGH_FANOUT_NET_LIM ./base/vpr_types.h 86;" d -HILL_CLIMBING ./pack/cluster.c /^ HILL_CLIMBING, NOT_HILL_CLIMBING$/;" e enum:e_gain_type file: -HUGE_NEGATIVE_FLOAT ./base/vpr_types.h 80;" d -HUGE_POSITIVE_FLOAT ./base/vpr_types.h 79;" d -IMPOSSIBLE ./place/timing_place_lookup.h 1;" d -INC_DIRECTION ./base/vpr_types.h /^ INC_DIRECTION = 0, DEC_DIRECTION = 1, BI_DIRECTION = 2$/;" e enum:e_direction -INFEASIBLE ./pack/cluster.c /^ FEASIBLE, INFEASIBLE$/;" e enum:e_feasibility file: -INFINITE ./base/place_and_route.h 1;" d -INPUT ./pack/cluster.c /^ INPUT, OUTPUT$/;" e enum:e_net_relation_to_clustered_block file: -INTRA_CLUSTER_EDGE ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type -INTRINSIC_DELAY ./base/vpr_types.h /^ INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY$/;" e enum:e_base_cost_type -INV_1X_C ./power/power.h /^ float INV_1X_C;$/;" m struct:s_power_commonly_used -INV_1X_C_in ./power/power.h /^ float INV_1X_C_in;$/;" m struct:s_power_commonly_used -INV_2X_C ./power/power.h /^ float INV_2X_C;$/;" m struct:s_power_commonly_used -IO_TYPE ./base/globals.c /^t_type_ptr IO_TYPE = NULL;$/;" v -IO_TYPE_BACKUP ./place/timing_place_lookup.c /^static t_type_ptr IO_TYPE_BACKUP;$/;" v file: -IPIN ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type -IPIN_COST_INDEX ./base/vpr_types.h /^ IPIN_COST_INDEX,$/;" e enum:e_cost_indices -InEventLoop ./base/graphics.c /^static boolean InEventLoop = FALSE;$/;" v file: -IsEchoEnabled ./base/ReadOptions.c /^boolean IsEchoEnabled(INP t_options *Options) {$/;" f -IsPostSynthesisEnabled ./base/ReadOptions.c /^boolean IsPostSynthesisEnabled(INP t_options *Options) {$/;" f -IsTimingEnabled ./base/ReadOptions.c /^boolean IsTimingEnabled(INP t_options *Options) {$/;" f -KHAKI ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -LAST_CMD_CATEGORY ./fpga_x2p/shell/shell_types.h /^ LAST_CMD_CATEGORY$/;" e enum:e_cmd_category -LAST_CMD_NAME ./fpga_x2p/shell/shell_types.h 37;" d -LAST_OPT_NAME ./fpga_x2p/shell/read_opt_types.h 57;" d -LAST_OPT_TAG ./fpga_x2p/shell/read_opt_types.h 56;" d -LEAVE_CLUSTERED ./pack/cluster.c /^ REMOVE_CLUSTERED, LEAVE_CLUSTERED$/;" e enum:e_removal_policy file: -LIGHTBLUE ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -LIGHTGREY ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types -LINELENGTH ./pack/output_blif.c 18;" d file: -LINELENGTH ./pack/output_clustering.c 16;" d file: -LONGLINE ./route/segment_stats.c 9;" d file: -L_wire ./fpga_x2p/verilog/verilog_report_timing.c /^ int L_wire;$/;" m struct:s_wireL_cnt file: -MAGENTA ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -MAJOR ./base/vpr_types.h 73;" d -MARKED_FRAC ./pack/cluster.c 87;" d file: -MAXPIXEL ./base/graphics.c 202;" d file: -MAXPIXEL ./base/graphics.c 225;" d file: -MAXPTS ./base/easygl_constants.h 10;" d -MAX_ATOM_PARSE ./base/read_blif.c 20;" d file: -MAX_BLOCK_COLOURS ./base/draw.c 21;" d file: -MAX_FONT_SIZE ./base/graphics.c 179;" d file: -MAX_INV_TIMING_COST ./place/place.c 64;" d file: -MAX_LEN ./place/place_stats.c 9;" d file: -MAX_LOGS ./power/power.h 33;" d -MAX_MOVES_BEFORE_RECOMPUTE ./place/place.c 36;" d file: -MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY ./place/place.c 41;" d file: -MAX_SHORT ./base/vpr_types.h 75;" d -MAX_STRING_LEN ./util/vpr_utils.c 18;" d file: -MAX_X ./place/place_stats.c 8;" d file: -MEDIUMPURPLE ./base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types -MINOR ./base/vpr_types.h 72;" d -MINPIXEL ./base/graphics.c 203;" d file: -MINPIXEL ./base/graphics.c 226;" d file: -MODEL_INPUT ./base/vpr_types.h 299;" d -MODEL_LATCH ./base/vpr_types.h 298;" d -MODEL_LOGIC ./base/vpr_types.h 297;" d -MODEL_OUTPUT ./base/vpr_types.h 300;" d -MOLECULE_FORCED_PACK ./base/vpr_types.h /^ MOLECULE_SINGLE_ATOM, MOLECULE_FORCED_PACK$/;" e enum:e_pack_pattern_molecule_type -MOLECULE_SINGLE_ATOM ./base/vpr_types.h /^ MOLECULE_SINGLE_ATOM, MOLECULE_FORCED_PACK$/;" e enum:e_pack_pattern_molecule_type -MRFPGA_H ./mrfpga/mrfpga_globals.h 2;" d -MULTI_BUFFERED ./base/vpr_types.h /^ MULTI_BUFFERED, SINGLE$/;" e enum:e_drivers -MWIDTH ./base/graphics.c 177;" d file: -MainWND ./base/graphics.c /^MainWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: -MergeOptions ./base/ReadOptions.c /^static void MergeOptions(INOUTP t_options * dest, INP t_options * src, int id)$/;" f file: -NDEBUG ./base/vpr_types.h 63;" d -NEGATIVE_EPSILON ./base/vpr_types.h 84;" d -NET_COUNT ./place/timing_place_lookup.c 41;" d file: -NET_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 2;" d -NET_TIMING_DRIVEN_PLACE ./base/vpr_types.h /^ BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE$/;" e enum:e_place_algorithm -NET_USED ./place/timing_place_lookup.c 45;" d file: -NET_USED_SINK_BLOCK ./place/timing_place_lookup.c 48;" d file: -NET_USED_SOURCE_BLOCK ./place/timing_place_lookup.c 47;" d file: -NEVER_CLUSTER ./base/vpr_types.h 99;" d -NMOS ./power/power.h /^ NMOS, PMOS$/;" e enum:__anon11 -NMOS_1X_C_d ./power/power.h /^ float NMOS_1X_C_d;$/;" m struct:s_power_commonly_used -NMOS_1X_C_g ./power/power.h /^ float NMOS_1X_C_g;$/;" m struct:s_power_commonly_used -NMOS_1X_C_s ./power/power.h /^ float NMOS_1X_C_s;$/;" m struct:s_power_commonly_used -NMOS_1X_st_leakage ./power/power.h /^ float NMOS_1X_st_leakage;$/;" m struct:s_power_commonly_used -NMOS_2X_st_leakage ./power/power.h /^ float NMOS_2X_st_leakage;$/;" m struct:s_power_commonly_used -NMOS_inf ./power/power.h /^ t_transistor_inf NMOS_inf;$/;" m struct:s_power_tech -NONSPACE ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -NORMAL ./place/place.c /^ NORMAL, CHECK$/;" e enum:cost_methods file: -NORMAL_LUT_MODE_INDEX ./fpga_x2p/base/fpga_x2p_types.h 25;" d -NOT_FOUND ./base/place_and_route.h 2;" d -NOT_HILL_CLIMBING ./pack/cluster.c /^ HILL_CLIMBING, NOT_HILL_CLIMBING$/;" e enum:e_gain_type file: -NOT_UPDATED_YET ./place/place.c 45;" d file: -NOT_VALID ./base/vpr_types.h 100;" d -NO_CLUSTER ./base/vpr_types.h 98;" d -NO_FIXED_CHANNEL_WIDTH ./base/vpr_types.h 739;" d -NO_GAIN ./pack/cluster.c /^ GAIN, NO_GAIN$/;" e enum:e_gain_update file: -NO_GRAPHICS ./base/vpr_types.h 62;" d -NO_PICTURE ./base/vpr_types.h /^ NO_PICTURE, PLACEMENT, ROUTING$/;" e enum:pic_type -NO_PREVIOUS ./base/vpr_types.h 939;" d -NO_ROUTE_THROUGHS ./route/route_tree_timing.c 255;" d file: -NO_TIMING ./base/vpr_types.h /^ BREADTH_FIRST, TIMING_DRIVEN, NO_TIMING$/;" e enum:e_router_algorithm -NUM_BUCKETS ./timing/path_delay.c 148;" d file: -NUM_COLOR ./base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types -NUM_FONT_TYPES ./base/graphics.c 2781;" d file: -NUM_RR_TYPES ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type -NUM_TYPES_USED ./place/timing_place_lookup.c 59;" d file: -NetFile ./base/ReadOptions.h /^ char *NetFile;$/;" m struct:s_options -NetFile ./base/vpr_types.h /^ char *NetFile;$/;" m struct:s_file_name_opts -OFF ./base/graphics.c 1362;" d file: -ON ./base/graphics.c 1363;" d file: -OPEN ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -OPIN ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type -OPIN_COST_INDEX ./base/vpr_types.h /^ OPIN_COST_INDEX,$/;" e enum:e_cost_indices -OPTIONTOKENS_H ./base/OptionTokens.h 2;" d -OPT_CHAR ./fpga_x2p/shell/read_opt_types.h /^ OPT_CHAR,$/;" e enum:opt_val_type -OPT_DEF ./fpga_x2p/shell/read_opt_types.h /^ OPT_DEF,$/;" e enum:opt_default -OPT_DOUBLE ./fpga_x2p/shell/read_opt_types.h /^ OPT_DOUBLE$/;" e enum:opt_val_type -OPT_FLOAT ./fpga_x2p/shell/read_opt_types.h /^ OPT_FLOAT,$/;" e enum:opt_val_type -OPT_INT ./fpga_x2p/shell/read_opt_types.h /^ OPT_INT,$/;" e enum:opt_val_type -OPT_NONDEF ./fpga_x2p/shell/read_opt_types.h /^ OPT_NONDEF$/;" e enum:opt_default -OPT_NONVAL ./fpga_x2p/shell/read_opt_types.h /^ OPT_NONVAL,$/;" e enum:opt_with_val -OPT_OPT ./fpga_x2p/shell/read_opt_types.h /^ OPT_OPT$/;" e enum:opt_manda -OPT_REQ ./fpga_x2p/shell/read_opt_types.h /^ OPT_REQ,$/;" e enum:opt_manda -OPT_WITHVAL ./fpga_x2p/shell/read_opt_types.h /^ OPT_WITHVAL$/;" e enum:opt_with_val -OT_ACC_FAC ./base/OptionTokens.h /^ OT_ACC_FAC,$/;" e enum:e_OptionBaseToken -OT_ACTIVITY_FILE ./base/OptionTokens.h /^ OT_ACTIVITY_FILE,$/;" e enum:e_OptionBaseToken -OT_ALLOW_EARLY_EXIT ./base/OptionTokens.h /^ OT_ALLOW_EARLY_EXIT,$/;" e enum:e_OptionBaseToken -OT_ALLOW_UNRELATED_CLUSTERING ./base/OptionTokens.h /^ OT_ALLOW_UNRELATED_CLUSTERING,$/;" e enum:e_OptionBaseToken -OT_ALPHA_CLUSTERING ./base/OptionTokens.h /^ OT_ALPHA_CLUSTERING,$/;" e enum:e_OptionBaseToken -OT_ALPHA_T ./base/OptionTokens.h /^ OT_ALPHA_T,$/;" e enum:e_OptionBaseToken -OT_ARG_UNKNOWN ./base/OptionTokens.h /^ OT_ARG_UNKNOWN \/* Must be last since used for counting enum items *\/$/;" e enum:e_OptionArgToken -OT_ASTAR_FAC ./base/OptionTokens.h /^ OT_ASTAR_FAC,$/;" e enum:e_OptionBaseToken -OT_AUTO ./base/OptionTokens.h /^ OT_AUTO,$/;" e enum:e_OptionBaseToken -OT_BASE_COST_TYPE ./base/OptionTokens.h /^ OT_BASE_COST_TYPE,$/;" e enum:e_OptionBaseToken -OT_BASE_UNKNOWN ./base/OptionTokens.h /^ OT_BASE_UNKNOWN \/* Must be last since used for counting enum items *\/$/;" e enum:e_OptionBaseToken -OT_BB_FACTOR ./base/OptionTokens.h /^ OT_BB_FACTOR,$/;" e enum:e_OptionBaseToken -OT_BEND_COST ./base/OptionTokens.h /^ OT_BEND_COST,$/;" e enum:e_OptionBaseToken -OT_BETA_CLUSTERING ./base/OptionTokens.h /^ OT_BETA_CLUSTERING,$/;" e enum:e_OptionBaseToken -OT_BLIF_FILE ./base/OptionTokens.h /^ OT_BLIF_FILE,$/;" e enum:e_OptionBaseToken -OT_BLOCK_DIST ./base/OptionTokens.h /^ OT_BLOCK_DIST,$/;" e enum:e_OptionBaseToken -OT_BOUNDING_BOX ./base/OptionTokens.h /^ OT_BOUNDING_BOX,$/;" e enum:e_OptionArgToken -OT_BREADTH_FIRST ./base/OptionTokens.h /^ OT_BREADTH_FIRST,$/;" e enum:e_OptionArgToken -OT_BRUTE_FORCE ./base/OptionTokens.h /^ OT_BRUTE_FORCE,$/;" e enum:e_OptionArgToken -OT_CLUSTER_BLOCK_DELAY ./base/OptionTokens.h /^ OT_CLUSTER_BLOCK_DELAY,$/;" e enum:e_OptionBaseToken -OT_CLUSTER_SEED ./base/OptionTokens.h /^ OT_CLUSTER_SEED,$/;" e enum:e_OptionBaseToken -OT_CMOS_TECH_BEHAVIOR_FILE ./base/OptionTokens.h /^ OT_CMOS_TECH_BEHAVIOR_FILE,$/;" e enum:e_OptionBaseToken -OT_CONNECTION_DRIVEN_CLUSTERING ./base/OptionTokens.h /^ OT_CONNECTION_DRIVEN_CLUSTERING,$/;" e enum:e_OptionBaseToken -OT_CREATE_ECHO_FILE ./base/OptionTokens.h /^ OT_CREATE_ECHO_FILE,$/;" e enum:e_OptionBaseToken -OT_CRITICALITY_EXP ./base/OptionTokens.h /^ OT_CRITICALITY_EXP,$/;" e enum:e_OptionBaseToken -OT_DELAY_NORMALIZED ./base/OptionTokens.h /^ OT_DELAY_NORMALIZED,$/;" e enum:e_OptionArgToken -OT_DEMAND_ONLY ./base/OptionTokens.h /^ OT_DEMAND_ONLY,$/;" e enum:e_OptionArgToken -OT_DETAILED ./base/OptionTokens.h /^ OT_DETAILED,$/;" e enum:e_OptionArgToken -OT_ENABLE_TIMING_COMPUTATIONS ./base/OptionTokens.h /^ OT_ENABLE_TIMING_COMPUTATIONS,$/;" e enum:e_OptionBaseToken -OT_EXIT_T ./base/OptionTokens.h /^ OT_EXIT_T,$/;" e enum:e_OptionBaseToken -OT_FAST ./base/OptionTokens.h /^ OT_FAST,$/;" e enum:e_OptionBaseToken -OT_FIRST_ITER_PRES_FAC ./base/OptionTokens.h /^ OT_FIRST_ITER_PRES_FAC,$/;" e enum:e_OptionBaseToken -OT_FIX_PINS ./base/OptionTokens.h /^ OT_FIX_PINS,$/;" e enum:e_OptionBaseToken -OT_FPGA_BITSTREAM_GENERATOR ./base/OptionTokens.h /^ OT_FPGA_BITSTREAM_GENERATOR,$/;" e enum:e_OptionBaseToken -OT_FPGA_BITSTREAM_OUTPUT_FILE ./base/OptionTokens.h /^ OT_FPGA_BITSTREAM_OUTPUT_FILE,$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE ./base/OptionTokens.h /^ OT_FPGA_SPICE, \/* Xifan TANG: FPGA SPICE Model Support *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_DIR ./base/OptionTokens.h /^ OT_FPGA_SPICE_DIR, \/* Xifan TANG: FPGA SPICE Model Support *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_LEAKAGE_ONLY ./base/OptionTokens.h /^ OT_FPGA_SPICE_LEAKAGE_ONLY, \/* Xifan TANG: Print SPICE Testbench for MUXes *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PARASITIC_NET_ESTIMATION ./base/OptionTokens.h /^ OT_FPGA_SPICE_PARASITIC_NET_ESTIMATION, \/* Xifan TANG: turn on\/off the parasitic net estimation*\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_CB_MUX_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_CB_MUX_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for MUXes *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_CB_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_CB_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for CBs *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_GRID_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_GRID_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for Grids *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_HARDLOGIC_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_HARDLOGIC_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for hard logic s *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_IO_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_IO_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for hard logic s *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_LUT_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_LUT_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for LUTs *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_PB_MUX_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_PB_MUX_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for MUXes *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_SB_MUX_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_SB_MUX_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for MUXes *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_SB_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_SB_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for SBs *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_PRINT_TOP_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_SPICE_PRINT_TOP_TESTBENCH, \/* Xifan TANG: Print Top-level SPICE Testbench *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_SIMULATOR_PATH ./base/OptionTokens.h /^ OT_FPGA_SPICE_SIMULATOR_PATH,$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_SIM_MT_NUM ./base/OptionTokens.h /^ OT_FPGA_SPICE_SIM_MT_NUM, \/* number of multi-thread used in simulation *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_SPICE_TESTBENCH_LOAD_EXTRACTION ./base/OptionTokens.h /^ OT_FPGA_SPICE_TESTBENCH_LOAD_EXTRACTION, \/* Xifan TANG: turn on\/off the testbench load extraction *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN, \/* Xifan TANG: Synthesizable Verilog Dump *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_DIR ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_DIR, \/* Xifan TANG: Synthesizable Verilog Dump *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_INCLUDE_ICARUS_SIMULATOR ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_INCLUDE_ICARUS_SIMULATOR,$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_INCLUDE_SIGNAL_INIT ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_INCLUDE_SIGNAL_INIT, \/* Xifan TANG: Include timing constraints in Verilog *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_INCLUDE_TIMING ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_INCLUDE_TIMING, \/* Xifan TANG: Include timing constraints in Verilog *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH, \/* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_PRINT_FORMAL_VERIFICATION_TOP_NETLIST ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_FORMAL_VERIFICATION_TOP_NETLIST, \/* Xifan Tang: Synthesizable Verilog, turn on option: output netlists in a compact way *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH, \/* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for the orignial input blif *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK,$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_PRINT_REPORT_TIMING_TCL ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_REPORT_TIMING_TCL,$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS,$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR,$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH, \/* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_PRINT_USER_DEFINED_TEMPLATE ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_PRINT_USER_DEFINED_TEMPLATE,$/;" e enum:e_OptionBaseToken -OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH ./base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH,$/;" e enum:e_OptionBaseToken -OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY ./base/OptionTokens.h /^ OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY, \/* use a compact routing hierarchy in SPICE\/Verilog generation *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_X2P_RENAME_ILLEGAL_PORT ./base/OptionTokens.h /^ OT_FPGA_X2P_RENAME_ILLEGAL_PORT, $/;" e enum:e_OptionBaseToken -OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT ./base/OptionTokens.h /^ OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT, \/* The weight of signal density in determining number of clock cycles in simulation *\/$/;" e enum:e_OptionBaseToken -OT_FPGA_X2P_SIM_WINDOW_SIZE ./base/OptionTokens.h /^ OT_FPGA_X2P_SIM_WINDOW_SIZE, \/* Window size in determining number of clock cycles in simulation *\/$/;" e enum:e_OptionBaseToken -OT_FULL_STATS ./base/OptionTokens.h /^ OT_FULL_STATS,$/;" e enum:e_OptionBaseToken -OT_GENERATE_POST_SYNTHESIS_NETLIST ./base/OptionTokens.h /^ OT_GENERATE_POST_SYNTHESIS_NETLIST,$/;" e enum:e_OptionBaseToken -OT_GLOBAL ./base/OptionTokens.h /^ OT_GLOBAL,$/;" e enum:e_OptionArgToken -OT_GLOBAL_CLOCKS ./base/OptionTokens.h /^ OT_GLOBAL_CLOCKS,$/;" e enum:e_OptionBaseToken -OT_GREEDY ./base/OptionTokens.h /^ OT_GREEDY,$/;" e enum:e_OptionArgToken -OT_HILL_CLIMBING_FLAG ./base/OptionTokens.h /^ OT_HILL_CLIMBING_FLAG,$/;" e enum:e_OptionBaseToken -OT_INITIAL_PRES_FAC ./base/OptionTokens.h /^ OT_INITIAL_PRES_FAC,$/;" e enum:e_OptionBaseToken -OT_INIT_T ./base/OptionTokens.h /^ OT_INIT_T,$/;" e enum:e_OptionBaseToken -OT_INNER_LOOP_RECOMPUTE_DIVIDER ./base/OptionTokens.h /^ OT_INNER_LOOP_RECOMPUTE_DIVIDER,$/;" e enum:e_OptionBaseToken -OT_INNER_NUM ./base/OptionTokens.h /^ OT_INNER_NUM,$/;" e enum:e_OptionBaseToken -OT_INTER_CLUSTER_NET_DELAY ./base/OptionTokens.h /^ OT_INTER_CLUSTER_NET_DELAY,$/;" e enum:e_OptionBaseToken -OT_INTRA_CLUSTER_NET_DELAY ./base/OptionTokens.h /^ OT_INTRA_CLUSTER_NET_DELAY,$/;" e enum:e_OptionBaseToken -OT_INTRINSIC_DELAY ./base/OptionTokens.h /^ OT_INTRINSIC_DELAY,$/;" e enum:e_OptionArgToken -OT_LP ./base/OptionTokens.h /^ OT_LP,$/;" e enum:e_OptionArgToken -OT_MAX_CRITICALITY ./base/OptionTokens.h /^ OT_MAX_CRITICALITY,$/;" e enum:e_OptionBaseToken -OT_MAX_INPUTS ./base/OptionTokens.h /^ OT_MAX_INPUTS,$/;" e enum:e_OptionArgToken -OT_MAX_ROUTER_ITERATIONS ./base/OptionTokens.h /^ OT_MAX_ROUTER_ITERATIONS,$/;" e enum:e_OptionBaseToken -OT_NET_FILE ./base/OptionTokens.h /^ OT_NET_FILE,$/;" e enum:e_OptionBaseToken -OT_NET_TIMING_DRIVEN ./base/OptionTokens.h /^ OT_NET_TIMING_DRIVEN,$/;" e enum:e_OptionArgToken -OT_NODISP ./base/OptionTokens.h /^ OT_NODISP,$/;" e enum:e_OptionBaseToken -OT_NO_TIMING ./base/OptionTokens.h /^ OT_NO_TIMING,$/;" e enum:e_OptionArgToken -OT_OFF ./base/OptionTokens.h /^ OT_OFF,$/;" e enum:e_OptionArgToken -OT_ON ./base/OptionTokens.h /^ OT_ON,$/;" e enum:e_OptionArgToken -OT_OUTFILE_PREFIX ./base/OptionTokens.h /^ OT_OUTFILE_PREFIX,$/;" e enum:e_OptionBaseToken -OT_PACK ./base/OptionTokens.h /^ OT_PACK,$/;" e enum:e_OptionBaseToken -OT_PACKER_ALGORITHM ./base/OptionTokens.h /^ OT_PACKER_ALGORITHM,$/;" e enum:e_OptionBaseToken -OT_PACK_CLB_PIN_REMAP ./base/OptionTokens.h /^ OT_PACK_CLB_PIN_REMAP,$/;" e enum:e_OptionBaseToken -OT_PATH_TIMING_DRIVEN ./base/OptionTokens.h /^ OT_PATH_TIMING_DRIVEN,$/;" e enum:e_OptionArgToken -OT_PLACE ./base/OptionTokens.h /^ OT_PLACE,$/;" e enum:e_OptionBaseToken -OT_PLACE_ALGORITHM ./base/OptionTokens.h /^ OT_PLACE_ALGORITHM,$/;" e enum:e_OptionBaseToken -OT_PLACE_CHAN_WIDTH ./base/OptionTokens.h /^ OT_PLACE_CHAN_WIDTH,$/;" e enum:e_OptionBaseToken -OT_PLACE_CLB_PIN_REMAP ./base/OptionTokens.h /^ OT_PLACE_CLB_PIN_REMAP,$/;" e enum:e_OptionBaseToken -OT_PLACE_COST_EXP ./base/OptionTokens.h /^ OT_PLACE_COST_EXP,$/;" e enum:e_OptionBaseToken -OT_PLACE_FILE ./base/OptionTokens.h /^ OT_PLACE_FILE,$/;" e enum:e_OptionBaseToken -OT_POWER ./base/OptionTokens.h /^ OT_POWER,$/;" e enum:e_OptionBaseToken -OT_POWER_OUT_FILE ./base/OptionTokens.h /^ OT_POWER_OUT_FILE,$/;" e enum:e_OptionBaseToken -OT_PRES_FAC_MULT ./base/OptionTokens.h /^ OT_PRES_FAC_MULT,$/;" e enum:e_OptionBaseToken -OT_RANDOM ./base/OptionTokens.h /^ OT_RANDOM,$/;" e enum:e_OptionArgToken -OT_READ_PLACE_ONLY ./base/OptionTokens.h /^ OT_READ_PLACE_ONLY,$/;" e enum:e_OptionBaseToken -OT_RECOMPUTE_CRIT_ITER ./base/OptionTokens.h /^ OT_RECOMPUTE_CRIT_ITER,$/;" e enum:e_OptionBaseToken -OT_RECOMPUTE_TIMING_AFTER ./base/OptionTokens.h /^ OT_RECOMPUTE_TIMING_AFTER,$/;" e enum:e_OptionBaseToken -OT_ROUTE ./base/OptionTokens.h /^ OT_ROUTE,$/;" e enum:e_OptionBaseToken -OT_ROUTER_ALGORITHM ./base/OptionTokens.h /^ OT_ROUTER_ALGORITHM,$/;" e enum:e_OptionBaseToken -OT_ROUTE_CHAN_WIDTH ./base/OptionTokens.h /^ OT_ROUTE_CHAN_WIDTH,$/;" e enum:e_OptionBaseToken -OT_ROUTE_FILE ./base/OptionTokens.h /^ OT_ROUTE_FILE,$/;" e enum:e_OptionBaseToken -OT_ROUTE_TYPE ./base/OptionTokens.h /^ OT_ROUTE_TYPE,$/;" e enum:e_OptionBaseToken -OT_SDC_FILE ./base/OptionTokens.h /^ OT_SDC_FILE,$/;" e enum:e_OptionBaseToken -OT_SEED ./base/OptionTokens.h /^ OT_SEED,$/;" e enum:e_OptionBaseToken -OT_SETTINGS_FILE ./base/OptionTokens.h /^ OT_SETTINGS_FILE,$/;" e enum:e_OptionBaseToken -OT_SHOW_PASS_TRANS ./base/OptionTokens.h /^ OT_SHOW_PASS_TRANS,$/;" e enum:e_OptionBaseToken -OT_SHOW_SRAM ./base/OptionTokens.h /^ OT_SHOW_SRAM,$/;" e enum:e_OptionBaseToken -OT_SKIP_CLUSTERING ./base/OptionTokens.h /^ OT_SKIP_CLUSTERING,$/;" e enum:e_OptionBaseToken -OT_SWEEP_HANGING_NETS_AND_INPUTS ./base/OptionTokens.h /^ OT_SWEEP_HANGING_NETS_AND_INPUTS,$/;" e enum:e_OptionBaseToken -OT_TD_PLACE_EXP_FIRST ./base/OptionTokens.h /^ OT_TD_PLACE_EXP_FIRST,$/;" e enum:e_OptionBaseToken -OT_TD_PLACE_EXP_LAST ./base/OptionTokens.h /^ OT_TD_PLACE_EXP_LAST,$/;" e enum:e_OptionBaseToken -OT_TIMING ./base/OptionTokens.h /^ OT_TIMING,$/;" e enum:e_OptionArgToken -OT_TIMING_ANALYSIS ./base/OptionTokens.h /^ OT_TIMING_ANALYSIS,$/;" e enum:e_OptionBaseToken -OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY ./base/OptionTokens.h /^ OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY,$/;" e enum:e_OptionBaseToken -OT_TIMING_DRIVEN ./base/OptionTokens.h /^ OT_TIMING_DRIVEN,$/;" e enum:e_OptionArgToken -OT_TIMING_DRIVEN_CLUSTERING ./base/OptionTokens.h /^ OT_TIMING_DRIVEN_CLUSTERING,$/;" e enum:e_OptionBaseToken -OT_TIMING_TRADEOFF ./base/OptionTokens.h /^ OT_TIMING_TRADEOFF,$/;" e enum:e_OptionBaseToken -OT_VERIFY_BINARY_SEARCH ./base/OptionTokens.h /^ OT_VERIFY_BINARY_SEARCH,$/;" e enum:e_OptionBaseToken -OUTPUT ./pack/cluster.c /^ INPUT, OUTPUT$/;" e enum:e_net_relation_to_clustered_block file: -Operation ./base/vpr_types.h /^ enum e_operation Operation; \/* run VPR or do analysis only *\/$/;" m struct:s_vpr_setup typeref:enum:s_vpr_setup::e_operation -OptionArgTokenList ./base/OptionTokens.c /^struct s_TokenPair OptionArgTokenList[] = { { "on", OT_ON }, { "off", OT_OFF },$/;" v typeref:struct:s_TokenPair -OptionBaseTokenList ./base/OptionTokens.c /^struct s_TokenPair OptionBaseTokenList[] = {$/;" v typeref:struct:s_TokenPair -PACK_BRUTE_FORCE ./base/vpr_types.h /^ PACK_GREEDY, PACK_BRUTE_FORCE$/;" e enum:e_packer_algorithm -PACK_CMD ./fpga_x2p/shell/shell_types.h /^ PACK_CMD,$/;" e enum:e_cmd_category -PACK_GREEDY ./base/vpr_types.h /^ PACK_GREEDY, PACK_BRUTE_FORCE$/;" e enum:e_packer_algorithm -PACK_PATH_WEIGHT ./timing/path_delay.h 34;" d -PALCE_MACRO_H ./place/place_macro.h 136;" d -PATH_DELAY ./timing/path_delay.h 2;" d -PATH_TIMING_DRIVEN_PLACE ./base/vpr_types.h /^ BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE$/;" e enum:e_place_algorithm -PB_PIN_EQ_AUTO_DETECT_H ./route/pb_pin_eq_auto_detect.h 3;" d -PB_TYPE_GRAPH_ANNOTATIONS_H ./pack/pb_type_graph_annotations.h 8;" d -PB_TYPE_GRAPH_H ./pack/pb_type_graph.h 2;" d -PI ./base/graphics.c 181;" d file: -PLACEMENT ./base/vpr_types.h /^ NO_PICTURE, PLACEMENT, ROUTING$/;" e enum:pic_type -PLACE_ALWAYS ./base/vpr_types.h /^ PLACE_NEVER, PLACE_ONCE, PLACE_ALWAYS$/;" e enum:pfreq -PLACE_CMD ./fpga_x2p/shell/shell_types.h /^ PLACE_CMD,$/;" e enum:e_cmd_category -PLACE_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 3;" d -PLACE_NEVER ./base/vpr_types.h /^ PLACE_NEVER, PLACE_ONCE, PLACE_ALWAYS$/;" e enum:pfreq -PLACE_ONCE ./base/vpr_types.h /^ PLACE_NEVER, PLACE_ONCE, PLACE_ALWAYS$/;" e enum:pfreq -PLACE_PATH_WEIGHT ./timing/path_delay.h 36;" d -PLUM ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -PLUS ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -PLUSQ ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -PMOS ./power/power.h /^ NMOS, PMOS$/;" e enum:__anon11 -PMOS_1X_C_d ./power/power.h /^ float PMOS_1X_C_d;$/;" m struct:s_power_commonly_used -PMOS_1X_C_g ./power/power.h /^ float PMOS_1X_C_g;$/;" m struct:s_power_commonly_used -PMOS_1X_C_s ./power/power.h /^ float PMOS_1X_C_s;$/;" m struct:s_power_commonly_used -PMOS_1X_st_leakage ./power/power.h /^ float PMOS_1X_st_leakage;$/;" m struct:s_power_commonly_used -PMOS_2X_st_leakage ./power/power.h /^ float PMOS_2X_st_leakage;$/;" m struct:s_power_commonly_used -PMOS_inf ./power/power.h /^ t_transistor_inf PMOS_inf;$/;" m struct:s_power_tech -PN_ratio ./power/power.h /^ float PN_ratio; \/* Ratio of PMOS to NMOS in inverter *\/$/;" m struct:s_power_tech -POSTSCRIPT ./base/graphics.c /^ POSTSCRIPT = 1$/;" e enum:__anon2 file: -POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES$/;" e enum:__anon8 file: -POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT,$/;" e enum:__anon8 file: -POWER_BREAKDOWN_ENTRY_TYPE_INTERC ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_INTERC,$/;" e enum:__anon8 file: -POWER_BREAKDOWN_ENTRY_TYPE_MODE ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_MODE,$/;" e enum:__anon8 file: -POWER_BREAKDOWN_ENTRY_TYPE_PB ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_PB,$/;" e enum:__anon8 file: -POWER_BREAKDOWN_ENTRY_TYPE_TITLE ./power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_TITLE = 0,$/;" e enum:__anon8 file: -POWER_CALLIB_COMPONENT_BUFFER ./power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_BUFFER = 0,$/;" e enum:__anon12 -POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR ./power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR,$/;" e enum:__anon12 -POWER_CALLIB_COMPONENT_FF ./power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_FF,$/;" e enum:__anon12 -POWER_CALLIB_COMPONENT_LUT ./power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_LUT,$/;" e enum:__anon12 -POWER_CALLIB_COMPONENT_MAX ./power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_MAX$/;" e enum:__anon12 -POWER_CALLIB_COMPONENT_MUX ./power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_MUX,$/;" e enum:__anon12 -POWER_COMPONENT_CLOCK ./power/power_components.h /^ POWER_COMPONENT_CLOCK, \/* Clock network *\/$/;" e enum:__anon13 -POWER_COMPONENT_CLOCK_BUFFER ./power/power_components.h /^ POWER_COMPONENT_CLOCK_BUFFER, \/* Buffers in clock network *\/$/;" e enum:__anon13 -POWER_COMPONENT_CLOCK_WIRE ./power/power_components.h /^ POWER_COMPONENT_CLOCK_WIRE, \/* Wires in clock network *\/$/;" e enum:__anon13 -POWER_COMPONENT_IGNORE ./power/power_components.h /^ POWER_COMPONENT_IGNORE = 0, \/* *\/$/;" e enum:__anon13 -POWER_COMPONENT_MAX_NUM ./power/power_components.h /^ POWER_COMPONENT_MAX_NUM$/;" e enum:__anon13 -POWER_COMPONENT_PB ./power/power_components.h /^ POWER_COMPONENT_PB, \/* Logic Blocks, and other hard blocks *\/$/;" e enum:__anon13 -POWER_COMPONENT_PB_BUFS_WIRE ./power/power_components.h /^ POWER_COMPONENT_PB_BUFS_WIRE, \/* Local buffers and wire capacitance *\/$/;" e enum:__anon13 -POWER_COMPONENT_PB_INTERC_MUXES ./power/power_components.h /^ POWER_COMPONENT_PB_INTERC_MUXES, \/* Local interconnect structures (muxes) *\/$/;" e enum:__anon13 -POWER_COMPONENT_PB_OTHER ./power/power_components.h /^ POWER_COMPONENT_PB_OTHER, \/* Power from other estimation methods - not transistor-level *\/$/;" e enum:__anon13 -POWER_COMPONENT_PB_PRIMITIVES ./power/power_components.h /^ POWER_COMPONENT_PB_PRIMITIVES, \/* Primitives (LUTs, FF, etc) *\/$/;" e enum:__anon13 -POWER_COMPONENT_ROUTE_CB ./power/power_components.h /^ POWER_COMPONENT_ROUTE_CB, \/* Connection box*\/$/;" e enum:__anon13 -POWER_COMPONENT_ROUTE_GLB_WIRE ./power/power_components.h /^ POWER_COMPONENT_ROUTE_GLB_WIRE, \/* Wires *\/$/;" e enum:__anon13 -POWER_COMPONENT_ROUTE_SB ./power/power_components.h /^ POWER_COMPONENT_ROUTE_SB, \/* Switch-box *\/$/;" e enum:__anon13 -POWER_COMPONENT_ROUTING ./power/power_components.h /^ POWER_COMPONENT_ROUTING, \/* Power for routing fabric (not local routing) *\/$/;" e enum:__anon13 -POWER_COMPONENT_TOTAL ./power/power_components.h /^ POWER_COMPONENT_TOTAL, \/* Total power for entire FPGA *\/$/;" e enum:__anon13 -POWER_DRC_MIN_DIFF_L ./power/power_sizing.h 34;" d -POWER_DRC_MIN_L ./power/power_sizing.h 32;" d -POWER_DRC_MIN_W ./power/power_sizing.h 33;" d -POWER_DRC_POLY_OVERHANG ./power/power_sizing.h 36;" d -POWER_DRC_SPACING ./power/power_sizing.h 35;" d -POWER_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 6;" d -POWER_LOG_ERROR ./power/power.h /^ POWER_LOG_ERROR, POWER_LOG_WARNING, POWER_LOG_NUM_TYPES$/;" e enum:__anon10 -POWER_LOG_NUM_TYPES ./power/power.h /^ POWER_LOG_ERROR, POWER_LOG_WARNING, POWER_LOG_NUM_TYPES$/;" e enum:__anon10 -POWER_LOG_WARNING ./power/power.h /^ POWER_LOG_ERROR, POWER_LOG_WARNING, POWER_LOG_NUM_TYPES$/;" e enum:__anon10 -POWER_LUT_SLOW ./power/power_components.h 37;" d -POWER_LUT_SLOW ./power/power_components.h 39;" d -POWER_MTA_L ./power/power_sizing.h 39;" d -POWER_MTA_W ./power/power_sizing.h 38;" d -POWER_RET_CODE_ERRORS ./power/power.h /^ POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS$/;" e enum:__anon9 -POWER_RET_CODE_SUCCESS ./power/power.h /^ POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS$/;" e enum:__anon9 -POWER_RET_CODE_WARNINGS ./power/power.h /^ POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS$/;" e enum:__anon9 -PREPACK_H ./pack/prepack.h 8;" d -PROC_TIME ./base/place_and_route.h 6;" d -PRODUCTION_CMD ./fpga_x2p/shell/shell_types.h /^ PRODUCTION_CMD,$/;" e enum:e_cmd_category -PTRANS_FLAG ./route/check_rr_graph.c 15;" d file: -PackerOpts ./base/vpr_types.h /^ struct s_packer_opts PackerOpts; \/* Options for packer *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_packer_opts -PinFile ./base/ReadOptions.h /^ char *PinFile;$/;" m struct:s_options -PlaceAlgorithm ./base/ReadOptions.h /^ enum e_place_algorithm PlaceAlgorithm;$/;" m struct:s_options typeref:enum:s_options::e_place_algorithm -PlaceAlphaT ./base/ReadOptions.h /^ float PlaceAlphaT;$/;" m struct:s_options -PlaceChanWidth ./base/ReadOptions.h /^ int PlaceChanWidth;$/;" m struct:s_options -PlaceExitT ./base/ReadOptions.h /^ float PlaceExitT;$/;" m struct:s_options -PlaceFile ./base/ReadOptions.h /^ char *PlaceFile;$/;" m struct:s_options -PlaceFile ./base/vpr_types.h /^ char *PlaceFile;$/;" m struct:s_file_name_opts -PlaceInitT ./base/ReadOptions.h /^ float PlaceInitT;$/;" m struct:s_options -PlaceInnerNum ./base/ReadOptions.h /^ float PlaceInnerNum;$/;" m struct:s_options -PlaceTimingTradeoff ./base/ReadOptions.h /^ float PlaceTimingTradeoff;$/;" m struct:s_options -PlacerOpts ./base/vpr_types.h /^ struct s_placer_opts PlacerOpts; \/* Options for placer *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_placer_opts -PowerCallibInputs ./power/PowerSpicedComponent.c /^PowerCallibInputs::PowerCallibInputs(PowerSpicedComponent * parent_,$/;" f class:PowerCallibInputs -PowerCallibInputs ./power/PowerSpicedComponent.h /^class PowerCallibInputs {$/;" c -PowerCallibSize ./power/PowerSpicedComponent.h /^ PowerCallibSize(float size, float power_) :$/;" f class:PowerCallibSize -PowerCallibSize ./power/PowerSpicedComponent.h /^class PowerCallibSize {$/;" c -PowerFile ./base/ReadOptions.h /^ char *PowerFile;$/;" m struct:s_options -PowerFile ./base/vpr_types.h /^ char *PowerFile;$/;" m struct:s_file_name_opts -PowerOpts ./base/vpr_types.h /^ t_power_opts PowerOpts;$/;" m struct:s_vpr_setup -PowerSpicedComponent ./power/PowerSpicedComponent.c /^PowerSpicedComponent::PowerSpicedComponent($/;" f class:PowerSpicedComponent -PowerSpicedComponent ./power/PowerSpicedComponent.h /^class PowerSpicedComponent {$/;" c -ProceedPressed ./base/graphics.c /^static int ProceedPressed;$/;" v file: -ProcessOption ./base/ReadOptions.c /^ProcessOption(INP char **Args, INOUTP t_options * Options) {$/;" f file: -Provenance ./base/ReadOptions.h /^ int Provenance[OT_BASE_UNKNOWN];$/;" m struct:s_options -QUEST ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -R ./base/vpr_types.h /^ float R;$/;" m struct:s_rr_node -RANDOM ./base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type -READOPTIONS_H ./base/ReadOptions.h 2;" d -READ_BLIF_H ./base/read_blif.h 2;" d -READ_NETLIST_H ./base/read_netlist.h 9;" d -READ_PLACE_H ./base/read_place.h 2;" d -READ_SDC_H ./timing/read_sdc.h 2;" d -READ_SETTINGS_H ./base/read_settings.h 2;" d -RED ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -REJECTED ./place/place.c /^ REJECTED, ACCEPTED, ABORTED$/;" e enum:swap_result file: -REMOVE_CLUSTERED ./pack/cluster.c /^ REMOVE_CLUSTERED, LEAVE_CLUSTERED$/;" e enum:e_removal_policy file: -RET_SWSEG_TRACK_APPLIED ./route/rr_graph_swseg.c /^ RET_SWSEG_TRACK_APPLIED$/;" e enum:ret_track_swseg_pattern file: -RET_SWSEG_TRACK_DIR_UNMATCH ./route/rr_graph_swseg.c /^ RET_SWSEG_TRACK_DIR_UNMATCH,$/;" e enum:ret_track_swseg_pattern file: -RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN ./route/rr_graph_swseg.c /^ RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN,$/;" e enum:ret_track_swseg_pattern file: -ROUND_UP ./route/route_timing.c 682;" d file: -ROUTE_CMD ./fpga_x2p/shell/shell_types.h /^ ROUTE_CMD,$/;" e enum:e_cmd_category -ROUTE_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 4;" d -ROUTE_PATH_WEIGHT ./timing/path_delay.h 37;" d -ROUTING ./base/vpr_types.h /^ NO_PICTURE, PLACEMENT, ROUTING$/;" e enum:pic_type -RRChan ./fpga_x2p/base/rr_chan.h /^class RRChan {$/;" c -RR_CHAN_H ./fpga_x2p/base/rr_chan.h 6;" d -RR_GRAPH2_H ./route/rr_graph2.h 2;" d -RR_GRAPH_H ./route/rr_graph.h 2;" d -RR_GRAPH_NO_WARN ./route/rr_graph.h /^ RR_GRAPH_NO_WARN = 0x00,$/;" e enum:__anon17 -RR_GRAPH_SBOX_H ./route/rr_graph_sbox.h 2;" d -RR_GRAPH_WARN_CHAN_WIDTH_CHANGED ./route/rr_graph.h /^ RR_GRAPH_WARN_CHAN_WIDTH_CHANGED = 0x02$/;" e enum:__anon17 -RR_GRAPH_WARN_FC_CLIPPED ./route/rr_graph.h /^ RR_GRAPH_WARN_FC_CLIPPED = 0x01,$/;" e enum:__anon17 -RUN_FLOW ./base/vpr_types.h /^ RUN_FLOW, TIMING_ANALYSIS_ONLY$/;" e enum:e_operation -R_minW_nmos ./base/vpr_types.h /^ float R_minW_nmos;$/;" m struct:s_det_routing_arch -R_minW_pmos ./base/vpr_types.h /^ float R_minW_pmos;$/;" m struct:s_det_routing_arch -R_upstream ./route/route_common.h /^ float R_upstream;$/;" m struct:s_heap -R_upstream ./route/route_tree_timing.h /^ float R_upstream;$/;" m struct:s_rt_node -ReadBaseCostType ./base/ReadOptions.c /^ReadBaseCostType(INP char **Args, OUTP enum e_base_cost_type *BaseCostType) {$/;" f file: -ReadBaseToken ./base/ReadOptions.c /^ReadBaseToken(INP char **Args, OUTP enum e_OptionBaseToken *Token) {$/;" f file: -ReadClusterSeed ./base/ReadOptions.c /^ReadClusterSeed(INP char **Args, OUTP enum e_cluster_seed *Type) {$/;" f file: -ReadFixPins ./base/ReadOptions.c /^ReadFixPins(INP char **Args, OUTP char **PinFile) {$/;" f file: -ReadFloat ./base/ReadOptions.c /^ReadFloat(INP char ** Args, OUTP float *Val) {$/;" f file: -ReadInt ./base/ReadOptions.c /^ReadInt(INP char **Args, OUTP int *Val) {$/;" f file: -ReadOnOff ./base/ReadOptions.c /^ReadOnOff(INP char **Args, OUTP boolean * Val) {$/;" f file: -ReadOptions ./base/ReadOptions.c /^void ReadOptions(INP int argc, INP char **argv, OUTP t_options * Options) {$/;" f -ReadPackerAlgorithm ./base/ReadOptions.c /^ReadPackerAlgorithm(INP char **Args, OUTP enum e_packer_algorithm *Algo) {$/;" f file: -ReadPlaceAlgorithm ./base/ReadOptions.c /^ReadPlaceAlgorithm(INP char **Args, OUTP enum e_place_algorithm *Algo) {$/;" f file: -ReadRouteType ./base/ReadOptions.c /^ReadRouteType(INP char **Args, OUTP enum e_route_type *Type) {$/;" f file: -ReadRouterAlgorithm ./base/ReadOptions.c /^ReadRouterAlgorithm(INP char **Args, OUTP enum e_router_algorithm *Algo) {$/;" f file: -ReadString ./base/ReadOptions.c /^ReadString(INP char **Args, OUTP char **Val) {$/;" f file: -ReadToken ./base/ReadOptions.c /^ReadToken(INP char **Args, OUTP enum e_OptionArgToken *Token) {$/;" f file: -RecomputeCritIter ./base/ReadOptions.h /^ int RecomputeCritIter;$/;" m struct:s_options -Rmetal ./base/vpr_types.h /^ float Rmetal;$/;" m struct:s_seg_details -RouteChanWidth ./base/ReadOptions.h /^ int RouteChanWidth;$/;" m struct:s_options -RouteFile ./base/ReadOptions.h /^ char *RouteFile;$/;" m struct:s_options -RouteFile ./base/vpr_types.h /^ char *RouteFile;$/;" m struct:s_file_name_opts -RouteType ./base/ReadOptions.h /^ enum e_route_type RouteType;$/;" m struct:s_options typeref:enum:s_options::e_route_type -RouterAlgorithm ./base/ReadOptions.h /^ enum e_router_algorithm RouterAlgorithm;$/;" m struct:s_options typeref:enum:s_options::e_router_algorithm -RouterOpts ./base/vpr_types.h /^ struct s_router_opts RouterOpts; \/* router options *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_router_opts -RoutingArch ./base/vpr_types.h /^ struct s_det_routing_arch RoutingArch; \/* routing architecture *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_det_routing_arch -Rseg_global ./mrfpga/mrfpga_globals.c /^float Rseg_global, Cseg_global;$/;" v -SAME_TRACK ./route/rr_graph2.c 23;" d file: -SBOX_ERROR ./route/rr_graph_sbox.c 99;" d file: -SCALE_DISTANCE_VAL ./pack/cluster.c 48;" d file: -SCALE_NUM_PATHS ./pack/cluster.c 39;" d file: -SCREEN ./base/graphics.c /^ SCREEN = 0,$/;" e enum:__anon2 file: -SDCFile ./base/ReadOptions.h /^ char *SDCFile;$/;" m struct:s_options -SDCFile ./base/vpr_types.h /^ char *SDCFile;$/;" m struct:s_file_name_opts -SDC_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 8;" d -SDC_TOKENS ./timing/read_sdc.c 452;" d file: -SDF_Adder_delay_printing ./base/verilog_writer.c /^void SDF_Adder_delay_printing(FILE *SDF , t_pb *pb)$/;" f -SDF_Mult_delay_printing ./base/verilog_writer.c /^void SDF_Mult_delay_printing(FILE *SDF , t_pb *pb)$/;" f -SDF_interconnect_delay_printing ./base/verilog_writer.c /^void SDF_interconnect_delay_printing(FILE *SDF , conn_list *downhill)$/;" f -SDF_ram_dual_port_delay_printing ./base/verilog_writer.c /^void SDF_ram_dual_port_delay_printing(FILE *SDF , t_pb *pb)$/;" f -SDF_ram_single_port_delay_printing ./base/verilog_writer.c /^void SDF_ram_single_port_delay_printing(FILE *SDF , t_pb *pb)$/;" f -SELECT_ERROR ./base/graphics.c 217;" d file: -SETUPGRID_H ./base/SetupGrid.h 2;" d -SETUPVPR_H ./base/SetupVPR.h 2;" d -SETUP_CMD ./fpga_x2p/shell/shell_types.h /^ SETUP_CMD,$/;" e enum:e_cmd_category -SHELL_ERROR ./fpga_x2p/shell/read_opt_types.h 62;" d -SHELL_FAIL ./fpga_x2p/shell/read_opt_types.h 61;" d -SHELL_SUCCESS ./fpga_x2p/shell/read_opt_types.h 60;" d -SINGLE ./base/vpr_types.h /^ MULTI_BUFFERED, SINGLE$/;" e enum:e_drivers -SINK ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type -SINK_BLOCK ./place/timing_place_lookup.c 50;" d file: -SINK_COST_INDEX ./base/vpr_types.h /^ SINK_COST_INDEX,$/;" e enum:e_cost_indices -SLACK_DEFINITION ./timing/path_delay.h 8;" d -SLRE_CASE_INSENSITIVE ./timing/slre.h /^enum slre_option {SLRE_CASE_INSENSITIVE = 1};$/;" e enum:slre_option -SLRE_FLOAT ./timing/slre.h /^enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT};$/;" e enum:slre_capture -SLRE_H ./timing/slre.h 78;" d -SLRE_INT ./timing/slre.h /^enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT};$/;" e enum:slre_capture -SLRE_STRING ./timing/slre.h /^enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT};$/;" e enum:slre_capture -SMALL_NET ./place/place.c 27;" d file: -SOLID ./base/easygl_constants.h /^enum line_types {SOLID, DASHED};$/;" e enum:line_types -SOURCE ./base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type -SOURCE_BLOCK ./place/timing_place_lookup.c 49;" d file: -SOURCE_COST_INDEX ./base/vpr_types.h /^ SOURCE_COST_INDEX = 0,$/;" e enum:e_cost_indices -SPACE ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -SPICE_MEASURE_DYNAMIC_POWER ./fpga_x2p/spice/spice_utils.h /^ SPICE_MEASURE_LEAKAGE_POWER, SPICE_MEASURE_DYNAMIC_POWER$/;" e enum:e_measure_type -SPICE_MEASURE_LEAKAGE_POWER ./fpga_x2p/spice/spice_utils.h /^ SPICE_MEASURE_LEAKAGE_POWER, SPICE_MEASURE_DYNAMIC_POWER$/;" e enum:e_measure_type -STAR ./timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: -STARQ ./timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: -Seed ./base/ReadOptions.h /^ int Seed;$/;" m struct:s_options -Segments ./base/vpr_types.h /^ t_segment_inf * Segments; \/* wires in routing architecture *\/$/;" m struct:s_vpr_setup -SetPostSynthesisOption ./base/ReadOptions.c /^void SetPostSynthesisOption(boolean post_synthesis_enabled){$/;" f -SettingsFile ./base/ReadOptions.h /^ char *SettingsFile;$/;" m struct:s_options -SetupAnnealSched ./base/SetupVPR.c /^static void SetupAnnealSched(INP t_options Options,$/;" f file: -SetupBitstreamGenOpts ./base/SetupVPR.c /^static void SetupBitstreamGenOpts(t_options Options, $/;" f file: -SetupFpgaSpiceOpts ./base/SetupVPR.c /^static void SetupFpgaSpiceOpts(t_options Options, $/;" f file: -SetupOperation ./base/SetupVPR.c /^static void SetupOperation(INP t_options Options,$/;" f file: -SetupPackerOpts ./base/SetupVPR.c /^void SetupPackerOpts(INP t_options Options, INP boolean TimingEnabled,$/;" f -SetupPlacerOpts ./base/SetupVPR.c /^static void SetupPlacerOpts(INP t_options Options, INP boolean TimingEnabled,$/;" f file: -SetupPowerOpts ./base/SetupVPR.c /^static void SetupPowerOpts(t_options Options, t_power_opts *power_opts,$/;" f file: -SetupRouterOpts ./base/SetupVPR.c /^static void SetupRouterOpts(INP t_options Options, INP boolean TimingEnabled,$/;" f file: -SetupRoutingArch ./base/SetupVPR.c /^static void SetupRoutingArch(INP t_arch Arch,$/;" f file: -SetupSpiceOpts ./base/SetupVPR.c /^static void SetupSpiceOpts(t_options Options, $/;" f file: -SetupSwitches ./base/SetupVPR.c /^static void SetupSwitches(INP t_arch Arch,$/;" f file: -SetupSwitches_mrFPGA ./base/SetupVPR.c /^static void SetupSwitches_mrFPGA(INP t_arch Arch,$/;" f file: -SetupSynVerilogOpts ./base/SetupVPR.c /^static void SetupSynVerilogOpts(t_options Options, $/;" f file: -SetupTiming ./base/SetupVPR.c /^static void SetupTiming(INP t_options Options, INP t_arch Arch,$/;" f file: -SetupVPR ./base/SetupVPR.c /^void SetupVPR(INP t_options *Options, INP boolean TimingEnabled,$/;" f -ShowAnnealSched ./base/ShowSetup.c /^static void ShowAnnealSched(INP struct s_annealing_sched AnnealSched) {$/;" f file: -ShowGraphics ./base/vpr_types.h /^ boolean ShowGraphics; \/* option to show graphics *\/$/;" m struct:s_vpr_setup -ShowOperation ./base/ShowSetup.c /^static void ShowOperation(INP enum e_operation Operation) {$/;" f file: -ShowPackerOpts ./base/ShowSetup.c /^static void ShowPackerOpts(INP struct s_packer_opts PackerOpts) {$/;" f file: -ShowPlaceTiming ./base/ReadOptions.h /^ boolean ShowPlaceTiming;$/;" m struct:s_options -ShowPlacerOpts ./base/ShowSetup.c /^static void ShowPlacerOpts(INP t_options Options,$/;" f file: -ShowRouterOpts ./base/ShowSetup.c /^static void ShowRouterOpts(INP struct s_router_opts RouterOpts) {$/;" f file: -ShowRoutingArch ./base/ShowSetup.c /^static void ShowRoutingArch(INP struct s_det_routing_arch RoutingArch) {$/;" f file: -ShowSetup ./base/ShowSetup.c /^void ShowSetup(INP t_options options, INP t_vpr_setup vpr_setup) {$/;" f -SpiceOpts ./base/vpr_types.h /^ t_spice_opts SpiceOpts; \/* Xifan TANG: SPICE Support*\/$/;" m struct:s_fpga_spice_opts -StatusWND ./base/graphics.c /^StatusWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: -Str ./base/vpr_types.h /^ const char *Str;$/;" m struct:s_TokenPair -SynVerilogOpts ./base/vpr_types.h /^ t_syn_verilog_opts SynVerilogOpts; \/* Xifan TANG: Synthesizable verilog dumping*\/$/;" m struct:s_fpga_spice_opts -TABLENGTH ./pack/output_blif.c 19;" d file: -TAB_LENGTH ./pack/output_clustering.c 17;" d file: -THISTLE ./base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types -TIMING_ANALYSIS_ONLY ./base/vpr_types.h /^ RUN_FLOW, TIMING_ANALYSIS_ONLY$/;" e enum:e_operation -TIMING_DRIVEN ./base/vpr_types.h /^ BREADTH_FIRST, TIMING_DRIVEN, NO_TIMING$/;" e enum:e_router_algorithm -TIMING_GAIN_PATH_WEIGHT ./timing/path_delay.h 35;" d -TIMING_PLACE ./place/timing_place.h 2;" d -TN_CB_IPIN ./base/vpr_types.h /^ TN_CB_IPIN, \/* input pin to complex block *\/$/;" e enum:__anon7 -TN_CB_OPIN ./base/vpr_types.h /^ TN_CB_OPIN, \/* output pin from complex block *\/$/;" e enum:__anon7 -TN_CONSTANT_GEN_SOURCE ./base/vpr_types.h /^ TN_CONSTANT_GEN_SOURCE \/* source of a constant logic 1 or 0 *\/$/;" e enum:__anon7 -TN_FF_CLOCK ./base/vpr_types.h /^ TN_FF_CLOCK, \/* clock pin of flip-flop *\/$/;" e enum:__anon7 -TN_FF_IPIN ./base/vpr_types.h /^ TN_FF_IPIN, \/* input pin to a flip-flop - goes to TN_FF_SINK *\/$/;" e enum:__anon7 -TN_FF_OPIN ./base/vpr_types.h /^ TN_FF_OPIN, \/* output pin from a flip-flop - comes from TN_FF_SOURCE *\/$/;" e enum:__anon7 -TN_FF_SINK ./base/vpr_types.h /^ TN_FF_SINK, \/* sink (D) pin of flip-flop *\/$/;" e enum:__anon7 -TN_FF_SOURCE ./base/vpr_types.h /^ TN_FF_SOURCE, \/* source (Q) pin of flip-flop *\/$/;" e enum:__anon7 -TN_INPAD_OPIN ./base/vpr_types.h /^ TN_INPAD_OPIN, \/* output from an input I\/O pad *\/$/;" e enum:__anon7 -TN_INPAD_SOURCE ./base/vpr_types.h /^ TN_INPAD_SOURCE, \/* input to an input I\/O pad *\/$/;" e enum:__anon7 -TN_INTERMEDIATE_NODE ./base/vpr_types.h /^ TN_INTERMEDIATE_NODE, \/* Used in post-packed timing graph only: $/;" e enum:__anon7 -TN_OUTPAD_IPIN ./base/vpr_types.h /^ TN_OUTPAD_IPIN, \/* input to an output I\/O pad *\/$/;" e enum:__anon7 -TN_OUTPAD_SINK ./base/vpr_types.h /^ TN_OUTPAD_SINK, \/* output from an output I\/O pad *\/$/;" e enum:__anon7 -TN_PRIMITIVE_IPIN ./base/vpr_types.h /^ TN_PRIMITIVE_IPIN, \/* input pin to a primitive (e.g. a LUT) *\/$/;" e enum:__anon7 -TN_PRIMITIVE_OPIN ./base/vpr_types.h /^ TN_PRIMITIVE_OPIN, \/* output pin from a primitive (e.g. a LUT) *\/$/;" e enum:__anon7 -TOKENS ./base/vpr_types.h 66;" d -TOKEN_CLOSE_SQUARE_BRACKET ./util/token.h /^ TOKEN_CLOSE_SQUARE_BRACKET,$/;" e enum:e_token_type -TOKEN_CLOSE_SQUIG_BRACKET ./util/token.h /^ TOKEN_CLOSE_SQUIG_BRACKET,$/;" e enum:e_token_type -TOKEN_COLON ./util/token.h /^ TOKEN_COLON,$/;" e enum:e_token_type -TOKEN_DOT ./util/token.h /^ TOKEN_DOT$/;" e enum:e_token_type -TOKEN_H ./util/token.h 8;" d -TOKEN_INT ./util/token.h /^ TOKEN_INT,$/;" e enum:e_token_type -TOKEN_NULL ./util/token.h /^ TOKEN_NULL,$/;" e enum:e_token_type -TOKEN_OPEN_SQUARE_BRACKET ./util/token.h /^ TOKEN_OPEN_SQUARE_BRACKET,$/;" e enum:e_token_type -TOKEN_OPEN_SQUIG_BRACKET ./util/token.h /^ TOKEN_OPEN_SQUIG_BRACKET,$/;" e enum:e_token_type -TOKEN_STRING ./util/token.h /^ TOKEN_STRING,$/;" e enum:e_token_type -TRUE ./base/graphics.c 145;" d file: -TURQUOISE ./base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types -T_AREA_HEIGHT ./base/graphics.c 178;" d file: -T_arr ./base/vpr_types.h /^ float T_arr; \/* Arrival time of the last input signal to this node. *\/$/;" m struct:s_tnode -T_crit ./power/power.h /^ float T_crit;$/;" m struct:s_solution_inf -T_linear ./base/vpr_types.h /^ float T_linear;$/;" m struct:s_rr_indexed_data -T_quadratic ./base/vpr_types.h /^ float T_quadratic;$/;" m struct:s_rr_indexed_data -T_req ./base/vpr_types.h /^ float T_req; \/* Required arrival time of the last input signal to this node $/;" m struct:s_tnode -Tdel ./base/vpr_types.h /^ float Tdel; \/* delay to go to to_node along this edge *\/$/;" m struct:s_tedge -Tdel ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: -Tdel ./route/route_tree_timing.h /^ float Tdel;$/;" m struct:s_rt_node -Tdel ./timing/net_delay_types.h /^ float Tdel;$/;" m struct:s_rc_node -Timing ./base/vpr_types.h /^ t_timing_inf Timing; \/* timing information *\/$/;" m struct:s_vpr_setup -TimingAnalysis ./base/ReadOptions.h /^ boolean TimingAnalysis;$/;" m struct:s_options -TimingEnabled ./base/vpr_types.h /^ boolean TimingEnabled; \/* Is VPR timing enabled *\/$/;" m struct:s_vpr_setup -UNDEFINED ./base/vpr_types.h 103;" d -UN_SET ./route/rr_graph2.c 24;" d file: -UPDATED_ONCE ./place/place.c 46;" d file: -USER ./base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type -USER_SCHED ./base/vpr_types.h /^ AUTO_SCHED, USER_SCHED$/;" e enum:sched_type -VERILOG_PORT_CONKT ./fpga_x2p/verilog/verilog_global.h /^VERILOG_PORT_CONKT$/;" e enum:e_dump_verilog_port_type -VERILOG_PORT_INOUT ./fpga_x2p/verilog/verilog_global.h /^VERILOG_PORT_INOUT,$/;" e enum:e_dump_verilog_port_type -VERILOG_PORT_INPUT ./fpga_x2p/verilog/verilog_global.h /^VERILOG_PORT_INPUT,$/;" e enum:e_dump_verilog_port_type -VERILOG_PORT_OUTPUT ./fpga_x2p/verilog/verilog_global.h /^VERILOG_PORT_OUTPUT,$/;" e enum:e_dump_verilog_port_type -VERILOG_PORT_REG ./fpga_x2p/verilog/verilog_global.h /^VERILOG_PORT_REG,$/;" e enum:e_dump_verilog_port_type -VERILOG_PORT_WIRE ./fpga_x2p/verilog/verilog_global.h /^VERILOG_PORT_WIRE,$/;" e enum:e_dump_verilog_port_type -VERILOG_TB_AUTOCHECK_TOP ./fpga_x2p/verilog/verilog_global.h /^VERILOG_TB_AUTOCHECK_TOP,$/;" e enum:e_verilog_tb_type -VERILOG_TB_BLIF_TOP ./fpga_x2p/verilog/verilog_global.h /^VERILOG_TB_BLIF_TOP,$/;" e enum:e_verilog_tb_type -VERILOG_TB_FORMAL_VERIFICATION ./fpga_x2p/verilog/verilog_global.h /^VERILOG_TB_FORMAL_VERIFICATION$/;" e enum:e_verilog_tb_type -VERILOG_TB_TOP ./fpga_x2p/verilog/verilog_global.h /^VERILOG_TB_TOP,$/;" e enum:e_verilog_tb_type -VPACK_COMB ./base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types -VPACK_EMPTY ./base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types -VPACK_INPAD ./base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types -VPACK_LATCH ./base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types -VPACK_MAX_INPUTS ./base/vpr_types.h /^ VPACK_TIMING, VPACK_MAX_INPUTS$/;" e enum:e_cluster_seed -VPACK_OUTPAD ./base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types -VPACK_TIMING ./base/vpr_types.h /^ VPACK_TIMING, VPACK_MAX_INPUTS$/;" e enum:e_cluster_seed -VPRSetupArch ./base/SetupVPR.c /^void VPRSetupArch(t_arch* arch, $/;" f -VPR_API_H ./base/vpr_api.h 27;" d -VPR_TYPES_H ./base/vpr_types.h 34;" d -VPR_UTILS_H ./util/vpr_utils.h 2;" d -Vdd ./power/power.h /^ float Vdd;$/;" m struct:s_power_tech -WHITE ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types -WIRED_LUT_LOGICAL_BLOCK_ID ./fpga_x2p/base/fpga_x2p_types.h 16;" d -WIRED_LUT_MODE_INDEX ./fpga_x2p/base/fpga_x2p_types.h 24;" d -WIRE_SEGMENT_LENGTH ./base/vpr_api.c 518;" d file: -WL ./base/place_and_route.h 5;" d -WNEED ./base/place_and_route.h 4;" d -W_seed ./base/globals.c /^int W_seed = -1;$/;" v -X11 ./base/graphics.h 13;" d -XPOST ./base/graphics.c 161;" d file: -XTOWORLD ./base/graphics.c 167;" d file: -YELLOW ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types -YPOST ./base/graphics.c 162;" d file: -YTOWORLD ./base/graphics.c 168;" d file: -__POWER_CMOS_TECH_H__ ./power/power_cmos_tech.h 26;" d -__POWER_COMPONENTS_H__ ./power/power_components.h 24;" d -__POWER_H__ ./power/power.h 23;" d -__POWER_LOW_LEVEL_H__ ./power/power_lowlevel.h 24;" d -__POWER_MISC_H__ ./power/power_callibrate.h 23;" d -__POWER_POWERSPICEDCOMPONENT_NMOS_H__ ./power/PowerSpicedComponent.h 19;" d -__POWER_TRANSISTOR_CNT_H__ ./power/power_sizing.h 24;" d -__POWER_UTIL_H__ ./power/power_util.h 23;" d -_drawcurve ./base/graphics.c /^static void _drawcurve(t_point *points, int npoints, int fill) {$/;" f file: -absorb_buffer_luts ./base/read_blif.c /^static void absorb_buffer_luts(void) {$/;" f file: -acc_cost ./route/route_common.h /^ float acc_cost;$/;" m struct:__anon15 -acc_fac ./base/ReadOptions.h /^ float acc_fac;$/;" m struct:s_options -acc_fac ./base/vpr_types.h /^ float acc_fac;$/;" m struct:s_router_opts -adapt_truth_table_for_frac_lut ./fpga_x2p/base/fpga_x2p_lut_utils.c /^void adapt_truth_table_for_frac_lut(t_pb_graph_pin* lut_out_pb_graph_pin, $/;" f -add_activity_to_net ./base/read_blif.c /^bool add_activity_to_net(char * net_name, float probability, float density) {$/;" f -add_conf_bit_info_to_llist ./fpga_x2p/base/fpga_x2p_utils.c /^add_conf_bit_info_to_llist(t_llist* head, int index, $/;" f -add_data_point ./power/PowerSpicedComponent.c /^void PowerSpicedComponent::add_data_point(int num_inputs, float transistor_size,$/;" f class:PowerSpicedComponent -add_delay_to_array ./mrfpga/buffer_insertion.c /^static void add_delay_to_array( float* sink_delay, t_linked_int* index, float delay_addition )$/;" f file: -add_entry ./power/PowerSpicedComponent.c /^PowerCallibInputs * PowerSpicedComponent::add_entry(int num_inputs) {$/;" f class:PowerSpicedComponent -add_heap_node_to_rr_graph_heap ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void add_heap_node_to_rr_graph_heap(t_rr_graph* local_rr_graph,$/;" f -add_latch ./base/read_blif.c /^static void add_latch(int doall, INP t_model *latch_model) {$/;" f file: -add_lut ./base/read_blif.c /^static boolean add_lut(int doall, t_model *logic_model) {$/;" f file: -add_molecule_to_pb_stats_candidates ./pack/cluster.c /^static void add_molecule_to_pb_stats_candidates(t_pack_molecule *molecule,$/;" f file: -add_mux_conf_bits_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^add_mux_conf_bits_to_llist(int mux_size,$/;" f -add_mux_conf_bits_to_sram_orgz_info ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^void add_mux_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -add_mux_membank_conf_bits_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^add_mux_membank_conf_bits_to_llist(int mux_size,$/;" f -add_mux_scff_conf_bits_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^add_mux_scff_conf_bits_to_llist(int mux_size,$/;" f -add_net_rr_terminal_cluster ./pack/cluster_legality.c /^static void add_net_rr_terminal_cluster(int iblk_net,$/;" f file: -add_net_to_hash ./base/read_netlist.c /^static int add_net_to_hash(INOUTP struct s_hash **nhash, INP char *net_name,$/;" f file: -add_node ./fpga_x2p/base/rr_chan.cpp /^void RRChan::add_node(t_rr_node* node, size_t node_segment) {$/;" f class:RRChan -add_node_to_rr_graph_heap ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void add_node_to_rr_graph_heap(t_rr_graph* local_rr_graph,$/;" f -add_one_chan_module ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan& rr_chan) {$/;" f class:DeviceRRChan -add_one_conf_bit_to_sram_orgz_info ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^void add_one_conf_bit_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info) {$/;" f -add_one_spice_tb_info_to_llist ./fpga_x2p/spice/spice_utils.c /^t_llist* add_one_spice_tb_info_to_llist(t_llist* cur_head, $/;" f -add_one_subckt_file_name_to_llist ./fpga_x2p/base/fpga_x2p_utils.c /^t_llist* add_one_subckt_file_name_to_llist(t_llist* cur_head, $/;" f -add_opin_fast_edge_to_ipin ./route/rr_graph_opincb.c /^int add_opin_fast_edge_to_ipin(t_rr_node* opin, $/;" f file: -add_opin_list_ipin_list_fast_edge ./route/rr_graph_opincb.c /^int add_opin_list_ipin_list_fast_edge(int num_opins, t_rr_node** opin_list, $/;" f file: -add_opin_rr_edges_to_chan_rr_node ./route/pb_pin_eq_auto_detect.c /^int add_opin_rr_edges_to_chan_rr_node(t_rr_node* chan_rr_node,$/;" f -add_override_constraint ./timing/read_sdc.c /^static void add_override_constraint(char ** from_list, int num_from, char ** to_list, int num_to, $/;" f file: -add_path_to_route_tree ./route/route_tree_timing.c /^add_path_to_route_tree(struct s_heap *hptr, t_rt_node ** sink_rt_node_ptr) {$/;" f file: -add_pattern_name_to_hash ./pack/prepack.c /^static int add_pattern_name_to_hash(INOUTP struct s_hash **nhash,$/;" f file: -add_route_tree_to_heap ./route/route_timing.c /^static void add_route_tree_to_heap(t_rt_node * rt_node, int target_node,$/;" f file: -add_rr_graph_C_from_switches ./route/rr_graph_timing_params.c /^void add_rr_graph_C_from_switches(float C_ipin_cblock) {$/;" f -add_rr_graph_fast_edge_opin_to_cb ./route/rr_graph_opincb.c /^int add_rr_graph_fast_edge_opin_to_cb(t_ivec*** LL_rr_node_indices) {$/;" f -add_rr_graph_one_grid_fast_edge_opin_to_cb ./route/rr_graph_opincb.c /^int add_rr_graph_one_grid_fast_edge_opin_to_cb(int grid_x, $/;" f file: -add_rr_graph_switch_segment_pattern ./route/rr_graph_swseg.c /^int add_rr_graph_switch_segment_pattern(enum e_directionality directionality,$/;" f -add_rr_node_edge_to_one_wired_lut ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void add_rr_node_edge_to_one_wired_lut(t_pb_graph_node* cur_pb_graph_node,$/;" f -add_size ./power/PowerSpicedComponent.c /^void PowerCallibInputs::add_size(float transistor_size, float power) {$/;" f class:PowerCallibInputs -add_sram_conf_bits_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^add_sram_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, $/;" f -add_sram_conf_bits_to_sram_orgz_info ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^void add_sram_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -add_sram_membank_conf_bits_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^void add_sram_membank_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, $/;" f -add_sram_scff_conf_bits_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -add_subckt ./base/read_blif.c /^static void add_subckt(int doall, t_model *user_models) {$/;" f file: -add_to_heap ./route/route_common.c /^static void add_to_heap(struct s_heap *hptr) {$/;" f file: -add_to_mod_list ./route/route_common.c /^void add_to_mod_list(float *fptr) {$/;" f -add_to_rc_tree ./timing/net_delay.c /^void add_to_rc_tree(t_rc_node * parent_rc, t_rc_node * child_rc,$/;" f -add_to_rr_graph_mod_list ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void add_to_rr_graph_mod_list(t_rr_graph* local_rr_graph,$/;" f -add_to_sort_heap ./util/heapsort.c /^static void add_to_sort_heap(int *heap, float *sort_values, int index,$/;" f file: -add_virtual_sources_to_rr_graph_multi_sources ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^int add_virtual_sources_to_rr_graph_multi_sources(t_rr_graph* local_rr_graph) {$/;" f -add_vpack_net ./base/read_blif.c /^static int add_vpack_net(char *ptr, int type, int bnum, int bport, int bpin,$/;" f file: -add_wire_to_switch ./base/SetupVPR.c /^static void add_wire_to_switch(struct s_det_routing_arch *det_routing_arch) {$/;" f file: -adjustButton ./base/graphics.c /^static int windowAdjustFlag = 0, adjustButton = -1;$/;" v file: -adjustRect ./base/graphics.c /^static RECT adjustRect, updateRect;$/;" v file: -adjust_one_rr_occ_and_pcost ./route/route_common.c /^static void adjust_one_rr_occ_and_pcost(int inode, int add_or_sub,$/;" f file: -adjustwin ./base/graphics.c /^adjustwin (void (*drawscreen) (void)) $/;" f file: -alloc_SRAM_values_from_truth_table ./power/power_util.c /^char * alloc_SRAM_values_from_truth_table(int LUT_size,$/;" f -alloc_and_add_fully_capacity_rr_edges_to_one_grid ./route/pb_pin_eq_auto_detect.c /^int alloc_and_add_fully_capacity_rr_edges_to_one_grid(int grid_x, int grid_y, int grid_z,$/;" f -alloc_and_add_fully_capacity_rr_edges_to_source_opin ./route/pb_pin_eq_auto_detect.c /^int alloc_and_add_fully_capacity_rr_edges_to_source_opin(t_type_ptr cur_type_descriptor,$/;" f -alloc_and_add_fully_capacity_sb_rr_edges_to_one_grid ./route/pb_pin_eq_auto_detect.c /^int alloc_and_add_fully_capacity_sb_rr_edges_to_one_grid(int grid_x, int grid_y, int grid_z,$/;" f -alloc_and_add_grids_fully_capacity_rr_edges ./route/pb_pin_eq_auto_detect.c /^int alloc_and_add_grids_fully_capacity_rr_edges(t_ivec*** LL_rr_node_indices,$/;" f -alloc_and_add_grids_fully_capacity_sb_rr_edges ./route/pb_pin_eq_auto_detect.c /^int alloc_and_add_grids_fully_capacity_sb_rr_edges(t_ivec*** LL_rr_node_indices,$/;" f -alloc_and_assign_internal_structures ./place/timing_place_lookup.c /^static void alloc_and_assign_internal_structures(struct s_net **original_net,$/;" f file: -alloc_and_build_connection_blocks_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void alloc_and_build_connection_blocks_info(t_det_routing_arch RoutingArch,$/;" f file: -alloc_and_build_switch_blocks_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void alloc_and_build_switch_blocks_info(t_det_routing_arch RoutingArch,$/;" f file: -alloc_and_init_clustering ./pack/cluster.c /^static void alloc_and_init_clustering(boolean global_clocks, float alpha,$/;" f file: -alloc_and_init_globals_clb_to_clb_directs ./base/SetupVPR.c /^void alloc_and_init_globals_clb_to_clb_directs(int num_directs, $/;" f -alloc_and_init_netlist_from_hash ./base/read_netlist.c /^static struct s_net *alloc_and_init_netlist_from_hash(INP int ncount,$/;" f file: -alloc_and_init_pattern_list_from_hash ./pack/prepack.c /^static t_pack_patterns *alloc_and_init_pattern_list_from_hash(INP int ncount,$/;" f file: -alloc_and_load_actual_fc ./route/rr_graph.c /^alloc_and_load_actual_fc(INP int L_num_types, INP t_type_ptr types,$/;" f file: -alloc_and_load_all_pb_graphs ./pack/pb_type_graph.c /^void alloc_and_load_all_pb_graphs(boolean load_power_structures) {$/;" f -alloc_and_load_blk_pin_from_port_pin ./util/vpr_utils.c /^static void alloc_and_load_blk_pin_from_port_pin(void) {$/;" f file: -alloc_and_load_clb_opins_used_locally ./route/route_common.c /^alloc_and_load_clb_opins_used_locally(void) {$/;" f file: -alloc_and_load_clb_to_clb_directs ./util/vpr_utils.c /^t_clb_to_clb_directs * alloc_and_load_clb_to_clb_directs(INP t_direct_inf *directs, $/;" f -alloc_and_load_cluster_info ./pack/cluster.c /^static void alloc_and_load_cluster_info(INP int num_clb, INOUTP t_block *clb) {$/;" f file: -alloc_and_load_cluster_legality_checker ./pack/cluster_legality.c /^void alloc_and_load_cluster_legality_checker(void) {$/;" f -alloc_and_load_cluster_placement_stats ./pack/cluster_placement.c /^t_cluster_placement_stats *alloc_and_load_cluster_placement_stats(void) {$/;" f -alloc_and_load_complete_interc_edges ./pack/pb_type_graph.c /^static void alloc_and_load_complete_interc_edges($/;" f file: -alloc_and_load_direct_interc_edges ./pack/pb_type_graph.c /^static void alloc_and_load_direct_interc_edges($/;" f file: -alloc_and_load_echo_file_info ./base/ReadOptions.c /^void alloc_and_load_echo_file_info() {$/;" f -alloc_and_load_edges_and_switches ./route/rr_graph.c /^void alloc_and_load_edges_and_switches(INP t_rr_node * L_rr_node, INP int inode,$/;" f -alloc_and_load_final_routing_trace ./base/vpr_api.c /^static t_trace *alloc_and_load_final_routing_trace() {$/;" f file: -alloc_and_load_for_fast_cost_update ./place/place.c /^static void alloc_and_load_for_fast_cost_update(float place_cost_exp) {$/;" f file: -alloc_and_load_global_route_seg_details ./route/rr_graph.c /^alloc_and_load_global_route_seg_details(INP int nodes_per_chan,$/;" f file: -alloc_and_load_grid ./base/SetupGrid.c /^void alloc_and_load_grid(INOUTP int *num_instances_type) {$/;" f -alloc_and_load_idirect_from_blk_pin ./util/vpr_utils.c /^void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, $/;" f -alloc_and_load_imacro_from_iblk ./place/place_macro.c /^static void alloc_and_load_imacro_from_iblk(t_pl_macro * macros, int num_macros) {$/;" f file: -alloc_and_load_interconnect_pins ./pack/pb_type_graph.c /^static void alloc_and_load_interconnect_pins(t_interconnect_pins * interc_pins,$/;" f file: -alloc_and_load_is_clock ./pack/pack.c /^boolean *alloc_and_load_is_clock(boolean global_clocks) {$/;" f -alloc_and_load_legalizer_for_cluster ./pack/cluster_legality.c /^void alloc_and_load_legalizer_for_cluster(INP t_block* clb, INP int clb_index,$/;" f -alloc_and_load_mode_interconnect ./pack/pb_type_graph.c /^static void alloc_and_load_mode_interconnect($/;" f file: -alloc_and_load_mux_graph ./power/power_util.c /^static t_mux_node * alloc_and_load_mux_graph(int num_inputs, int levels) {$/;" f file: -alloc_and_load_mux_graph_recursive ./power/power_util.c /^static void alloc_and_load_mux_graph_recursive(t_mux_node * node,$/;" f file: -alloc_and_load_mux_interc_edges ./pack/pb_type_graph.c /^static void alloc_and_load_mux_interc_edges( INP t_interconnect * interconnect,$/;" f file: -alloc_and_load_net_pin_index ./util/vpr_utils.c /^int ** alloc_and_load_net_pin_index() {$/;" f -alloc_and_load_netlist_clocks_and_ios ./timing/read_sdc.c /^static void alloc_and_load_netlist_clocks_and_ios(void) {$/;" f file: -alloc_and_load_output_file_names ./base/ReadOptions.c /^void alloc_and_load_output_file_names(const char *default_name) {$/;" f -alloc_and_load_pack_molecules ./pack/prepack.c /^t_pack_molecule *alloc_and_load_pack_molecules($/;" f -alloc_and_load_pack_patterns ./pack/prepack.c /^t_pack_patterns *alloc_and_load_pack_patterns(OUTP int *num_packing_patterns) {$/;" f -alloc_and_load_pb_graph ./pack/pb_type_graph.c /^static void alloc_and_load_pb_graph(INOUTP t_pb_graph_node *pb_graph_node,$/;" f file: -alloc_and_load_pb_stats ./pack/cluster.c /^static void alloc_and_load_pb_stats(t_pb *pb, int max_models,$/;" f file: -alloc_and_load_perturb_ipins ./route/rr_graph.c /^alloc_and_load_perturb_ipins(INP int nodes_per_chan, INP int L_num_types,$/;" f file: -alloc_and_load_phy_pb_children_for_one_mapped_block ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void alloc_and_load_phy_pb_children_for_one_mapped_block(t_pb* cur_op_pb,$/;" f -alloc_and_load_phy_pb_for_mapped_block ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void alloc_and_load_phy_pb_for_mapped_block(int num_mapped_blocks, t_block* mapped_block,$/;" f -alloc_and_load_phy_pb_rr_graph_net_rr_terminals ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void alloc_and_load_phy_pb_rr_graph_net_rr_terminals(INP t_pb* cur_op_pb,$/;" f -alloc_and_load_phy_pb_rr_graph_nets ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void alloc_and_load_phy_pb_rr_graph_nets(INP t_pb* cur_op_pb,$/;" f -alloc_and_load_pin_locations_from_pb_graph ./pack/pb_type_graph.c /^static void alloc_and_load_pin_locations_from_pb_graph(t_type_descriptor *type) {$/;" f file: -alloc_and_load_pin_to_track_map ./route/rr_graph.c /^alloc_and_load_pin_to_track_map(INP enum e_pin_type pin_type,$/;" f file: -alloc_and_load_placement_macros ./place/place_macro.c /^int alloc_and_load_placement_macros(t_direct_inf* directs, int num_directs, t_pl_macro ** macros){$/;" f -alloc_and_load_placement_structs ./place/place.c /^static void alloc_and_load_placement_structs($/;" f file: -alloc_and_load_port_pin_from_blk_pin ./util/vpr_utils.c /^static void alloc_and_load_port_pin_from_blk_pin(void) {$/;" f file: -alloc_and_load_port_pin_ptrs_from_string ./pack/pb_type_graph.c /^t_pb_graph_pin *** alloc_and_load_port_pin_ptrs_from_string(INP int line_num,$/;" f -alloc_and_load_pre_packing_timing_graph ./timing/path_delay.c /^t_slack * alloc_and_load_pre_packing_timing_graph(float block_delay,$/;" f -alloc_and_load_prev_node_list_rr_graph_rr_nodes ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void alloc_and_load_prev_node_list_rr_graph_rr_nodes(t_rr_graph* local_rr_graph) {$/;" f -alloc_and_load_rc_tree ./timing/net_delay.c /^alloc_and_load_rc_tree(int inet, t_rc_node ** rc_node_free_list_ptr,$/;" f -alloc_and_load_rr_clb_source ./route/rr_graph.c /^static void alloc_and_load_rr_clb_source(t_ivec *** L_rr_node_indices) {$/;" f file: -alloc_and_load_rr_graph ./route/rr_graph.c /^static void alloc_and_load_rr_graph(INP int num_nodes,$/;" f file: -alloc_and_load_rr_graph_for_pb_graph_node ./pack/cluster_legality.c /^void alloc_and_load_rr_graph_for_pb_graph_node($/;" f -alloc_and_load_rr_graph_for_phy_pb ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void alloc_and_load_rr_graph_for_phy_pb(INP t_pb* cur_op_pb,$/;" f -alloc_and_load_rr_graph_for_phy_pb_graph_node ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void alloc_and_load_rr_graph_for_phy_pb_graph_node(INP t_pb_graph_node* top_pb_graph_node, $/;" f -alloc_and_load_rr_graph_route_structs ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void alloc_and_load_rr_graph_route_structs(t_rr_graph* local_rr_graph) {$/;" f -alloc_and_load_rr_graph_rr_node ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void alloc_and_load_rr_graph_rr_node(INOUTP t_rr_graph* local_rr_graph,$/;" f -alloc_and_load_rr_graph_rr_node_indices ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void alloc_and_load_rr_graph_rr_node_indices(t_rr_graph* local_rr_graph,$/;" f -alloc_and_load_rr_graph_switch_inf ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void alloc_and_load_rr_graph_switch_inf(INOUTP t_rr_graph* local_rr_graph,$/;" f -alloc_and_load_rr_indexed_data ./route/rr_graph_indexed_data.c /^void alloc_and_load_rr_indexed_data(INP t_segment_inf * segment_inf,$/;" f -alloc_and_load_rr_node_indices ./route/rr_graph2.c /^alloc_and_load_rr_node_indices(INP int nodes_per_chan, INP int L_nx,$/;" f -alloc_and_load_rr_node_route_structs ./route/route_common.c /^void alloc_and_load_rr_node_route_structs(void) {$/;" f -alloc_and_load_seg_details ./route/rr_graph2.c /^alloc_and_load_seg_details(INOUTP int *nodes_per_chan, INP int max_len,$/;" f -alloc_and_load_sharable_switch_trans ./route/rr_graph_area.c /^alloc_and_load_sharable_switch_trans(int num_switch, float trans_sram_bit,$/;" f file: -alloc_and_load_switch_block_conn ./route/rr_graph_sbox.c /^alloc_and_load_switch_block_conn(INP int nodes_per_chan,$/;" f -alloc_and_load_timing_graph ./timing/path_delay.c /^t_slack * alloc_and_load_timing_graph(t_timing_inf timing_inf) {$/;" f -alloc_and_load_timing_graph_levels ./timing/path_delay2.c /^int alloc_and_load_timing_graph_levels(void) {$/;" f -alloc_and_load_tnode_fanin_and_check_edges ./timing/path_delay2.c /^alloc_and_load_tnode_fanin_and_check_edges(int *num_sinks_ptr) {$/;" f file: -alloc_and_load_tnodes ./timing/path_delay.c /^static void alloc_and_load_tnodes(t_timing_inf timing_inf) {$/;" f file: -alloc_and_load_tnodes_from_prepacked_netlist ./timing/path_delay.c /^static void alloc_and_load_tnodes_from_prepacked_netlist(float block_delay,$/;" f file: -alloc_and_load_track_to_pin_lookup ./route/rr_graph.c /^alloc_and_load_track_to_pin_lookup(INP int ****pin_to_track_map, INP int *Fc,$/;" f file: -alloc_and_load_try_swap_structs ./place/place.c /^static void alloc_and_load_try_swap_structs() {$/;" f file: -alloc_and_load_unsharable_switch_trans ./route/rr_graph_area.c /^alloc_and_load_unsharable_switch_trans(int num_switch, float trans_sram_bit,$/;" f file: -alloc_block ./place/timing_place_lookup.c /^static void alloc_block(void) {$/;" f file: -alloc_cb_info_array ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^t_cb** alloc_cb_info_array(int LL_nx, int LL_ny) {$/;" f -alloc_crit ./place/timing_place.c /^static float ** alloc_crit(t_chunk *chunk_list_ptr) {$/;" f file: -alloc_delta_arrays ./place/timing_place_lookup.c /^static void alloc_delta_arrays(void) {$/;" f file: -alloc_draw_structs ./base/draw.c /^void alloc_draw_structs(void) {$/;" f -alloc_global_routing_conf_bits ./fpga_x2p/verilog/verilog_api.c /^void alloc_global_routing_conf_bits() {$/;" f file: -alloc_hash_table ./util/hash.c /^alloc_hash_table(void) {$/;" f -alloc_heap_data ./route/route_common.c /^alloc_heap_data(void) {$/;" f file: -alloc_internal_cb_nets ./base/read_netlist.c /^static void alloc_internal_cb_nets(INOUTP t_pb *top_level,$/;" f file: -alloc_isink_to_inode ./mrfpga/buffer_insertion.c /^static int alloc_isink_to_inode( int inet, int** isink_to_inode_ptr )$/;" f file: -alloc_legal_placements ./place/place.c /^static void alloc_legal_placements() {$/;" f file: -alloc_linked_f_pointer ./route/route_common.c /^alloc_linked_f_pointer(void) {$/;" f file: -alloc_linked_rc_edge ./timing/net_delay.c /^alloc_linked_rc_edge(t_linked_rc_edge ** rc_edge_free_list_ptr) {$/;" f -alloc_linked_rt_edge ./route/route_tree_timing.c /^alloc_linked_rt_edge(void) {$/;" f file: -alloc_lookups_and_criticalities ./place/timing_place.c /^t_slack * alloc_lookups_and_criticalities(t_chan_width_dist chan_width_dist,$/;" f -alloc_net ./place/timing_place_lookup.c /^static void alloc_net(void) {$/;" f file: -alloc_net_delay ./timing/net_delay.c /^alloc_net_delay(t_chunk *chunk_list_ptr, struct s_net *nets,$/;" f -alloc_net_rr_terminals ./route/rr_graph.c /^static void alloc_net_rr_terminals(void) {$/;" f file: -alloc_net_rr_terminals_cluster ./pack/cluster_legality.c /^static void alloc_net_rr_terminals_cluster(void) {$/;" f file: -alloc_one_conf_bit_info ./fpga_x2p/base/fpga_x2p_utils.c /^alloc_one_conf_bit_info(int index,$/;" f -alloc_one_mem_bank_info ./fpga_x2p/base/fpga_x2p_utils.c /^t_mem_bank_info* alloc_one_mem_bank_info() {$/;" f -alloc_one_scff_info ./fpga_x2p/base/fpga_x2p_utils.c /^t_scff_info* alloc_one_scff_info() {$/;" f -alloc_one_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^t_sram_orgz_info* alloc_one_sram_orgz_info() {$/;" f -alloc_one_standalone_sram_info ./fpga_x2p/base/fpga_x2p_utils.c /^t_standalone_sram_info* alloc_one_standalone_sram_info() {$/;" f -alloc_pb_rr_graph_rr_indexed_data ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void alloc_pb_rr_graph_rr_indexed_data(t_rr_graph* local_rr_graph) {$/;" f -alloc_pin_classes_in_pb_graph_node ./pack/cluster_feasibility_filter.c /^static void alloc_pin_classes_in_pb_graph_node($/;" f file: -alloc_rc_node ./timing/net_delay.c /^alloc_rc_node(t_rc_node ** rc_node_free_list_ptr) {$/;" f -alloc_route_static_structs ./route/route_common.c /^void alloc_route_static_structs(void) {$/;" f -alloc_route_structs ./route/route_common.c /^alloc_route_structs(void) {$/;" f -alloc_route_tree_timing_structs ./route/route_tree_timing.c /^void alloc_route_tree_timing_structs(void) {$/;" f -alloc_routing_structs ./place/timing_place_lookup.c /^static void alloc_routing_structs(struct s_router_opts router_opts,$/;" f file: -alloc_rr_graph_heap_data ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^t_heap * alloc_rr_graph_heap_data(t_rr_graph* local_rr_graph) {$/;" f -alloc_rr_graph_linked_f_pointer ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^t_linked_f_pointer* alloc_rr_graph_linked_f_pointer(t_rr_graph* local_rr_graph) {$/;" f -alloc_rr_graph_net_rr_sources_and_sinks ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void alloc_rr_graph_net_rr_sources_and_sinks(t_rr_graph* local_rr_graph) {$/;" f -alloc_rr_graph_net_rr_terminals ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void alloc_rr_graph_net_rr_terminals(t_rr_graph* local_rr_graph) {$/;" f -alloc_rr_graph_route_static_structs ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void alloc_rr_graph_route_static_structs(t_rr_graph* local_rr_graph,$/;" f -alloc_rr_graph_rr_indexed_data ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void alloc_rr_graph_rr_indexed_data(t_rr_graph* local_rr_graph, int L_num_rr_indexed_data) {$/;" f -alloc_rr_graph_trace_data ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^t_trace* alloc_rr_graph_trace_data(t_rr_graph* local_rr_graph) {$/;" f -alloc_rt_node ./route/route_tree_timing.c /^alloc_rt_node(void) {$/;" f file: -alloc_saved_routing ./route/route_common.c /^alloc_saved_routing(t_ivec ** clb_opins_used_locally,$/;" f -alloc_sb_info_array ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^t_sb** alloc_sb_info_array(int LL_nx, int LL_ny) {$/;" f -alloc_sblock_pattern_lookup ./route/rr_graph2.c /^alloc_sblock_pattern_lookup(INP int L_nx, INP int L_ny, INP int nodes_per_chan) {$/;" f -alloc_slacks ./timing/path_delay.c /^static t_slack * alloc_slacks(void) {$/;" f file: -alloc_spice_model_grid_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void alloc_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) {$/;" f -alloc_spice_model_num_tedges ./fpga_x2p/base/fpga_x2p_timing_utils.c /^void alloc_spice_model_num_tedges(t_spice_model* cur_spice_model) {$/;" f -alloc_spice_model_routing_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void alloc_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) {$/;" f -alloc_timing_driven_route_structs ./route/route_timing.c /^void alloc_timing_driven_route_structs(float **pin_criticality_ptr,$/;" f -alloc_timing_stats ./timing/path_delay.c /^static void alloc_timing_stats(void) {$/;" f file: -alloc_trace_data ./route/route_common.c /^alloc_trace_data(void) {$/;" f file: -allocate_and_load_critical_path ./timing/path_delay.c /^t_linked_int * allocate_and_load_critical_path(void) {$/;" f -allocate_wired_lut_pbs ./fpga_x2p/base/fpga_x2p_lut_utils.c /^void allocate_wired_lut_pbs(t_pb*** wired_lut_pbs, $/;" f -allow_early_exit ./base/ReadOptions.h /^ boolean allow_early_exit;$/;" m struct:s_options -allow_early_exit ./base/vpr_types.h /^ boolean allow_early_exit;$/;" m struct:s_packer_opts -allow_unrelated_clustering ./base/ReadOptions.h /^ boolean allow_unrelated_clustering;$/;" m struct:s_options -allow_unrelated_clustering ./base/vpr_types.h /^ boolean allow_unrelated_clustering;$/;" m struct:s_packer_opts -alpha ./base/ReadOptions.h /^ float alpha;$/;" m struct:s_options -alpha ./base/vpr_types.h /^ float alpha;$/;" m struct:s_packer_opts -alpha_t ./base/vpr_types.h /^ float alpha_t;$/;" m struct:s_annealing_sched -anchored ./timing/slre.c /^ int anchored; \/\/ Must match from string start$/;" m struct:slre file: -angnorm ./base/graphics.c /^angnorm (float ang) $/;" f file: -annotate_grid_block_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void annotate_grid_block_info() {$/;" f -annotate_pb_type_port_to_phy_pb_type ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void annotate_pb_type_port_to_phy_pb_type(t_pb_type* cur_pb_type, $/;" f -annotate_physical_mode_pin_to_pb_type ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void annotate_physical_mode_pin_to_pb_type(t_port* cur_pb_type_port,$/;" f -annotate_physical_mode_pins_in_pb_graph_node ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void annotate_physical_mode_pins_in_pb_graph_node() {$/;" f -annotate_spice_model_timing ./fpga_x2p/base/fpga_x2p_timing_utils.c /^void annotate_spice_model_timing(t_spice_model* cur_spice_model) {$/;" f -anyof ./timing/slre.c /^static void anyof(struct slre *r, const char **re) {$/;" f file: -apply_swseg_pattern_chanx_track ./route/rr_graph_swseg.c /^ apply_swseg_pattern_chanx_track(INP int track_id,$/;" f file: -apply_swseg_pattern_chany_track ./route/rr_graph_swseg.c /^ apply_swseg_pattern_chany_track(INP int track_id,$/;" f file: -arch ./fpga_x2p/shell/shell_types.h /^ t_arch arch;$/;" m struct:s_shell_env -aspect ./base/vpr_types.h /^ float aspect;$/;" m struct:s_packer_opts -assess_swap ./place/place.c /^static enum swap_result assess_swap(float delta_c, float t) {$/;" f file: -assign_blocks_and_route_net ./place/timing_place_lookup.c /^static float assign_blocks_and_route_net(t_type_ptr source_type,$/;" f file: -assign_connection_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void assign_connection_block_mirror(t_cb* src, t_cb* des) {$/;" f -assign_locations ./place/timing_place_lookup.c /^static void assign_locations(t_type_ptr source_type, int source_x_loc,$/;" f file: -assign_lut_truth_table ./fpga_x2p/base/fpga_x2p_lut_utils.c /^char** assign_lut_truth_table(t_logical_block* mapped_logical_block,$/;" f -assign_mirror_connection_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void assign_mirror_connection_blocks() {$/;" f -assign_mirror_switch_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void assign_mirror_switch_blocks() {$/;" f -assign_pb_graph_node_pin_temp_net_num_by_mode_index ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void assign_pb_graph_node_pin_temp_net_num_by_mode_index(t_pb_graph_pin* cur_pb_graph_pin,$/;" f -assign_post_routing_lut_truth_table ./fpga_x2p/base/fpga_x2p_lut_utils.c /^char** assign_post_routing_lut_truth_table(t_logical_block* mapped_logical_block,$/;" f -assign_post_routing_wired_lut_truth_table ./fpga_x2p/base/fpga_x2p_lut_utils.c /^char** assign_post_routing_wired_lut_truth_table(int lut_output_vpack_net_num,$/;" f -assign_switch_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void assign_switch_block_mirror(t_sb* src, t_sb* des) {$/;" f -astar_fac ./base/ReadOptions.h /^ float astar_fac;$/;" m struct:s_options -astar_fac ./base/vpr_types.h /^ float astar_fac;$/;" m struct:s_router_opts -auto_compute_inter_cluster_net_delay ./base/vpr_types.h /^ boolean auto_compute_inter_cluster_net_delay;$/;" m struct:s_packer_opts -auto_detect_and_reserve_locally_used_opins ./route/route_common.c /^void auto_detect_and_reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins,$/;" f -auto_detect_and_reserve_used_opins ./route/pb_pin_eq_auto_detect.c /^void auto_detect_and_reserve_used_opins(float pres_fac) {$/;" f -auto_select_max_sim_num_clock_cycles ./fpga_x2p/spice/spice_grid_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: -auto_select_max_sim_num_clock_cycles ./fpga_x2p/spice/spice_mux_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: -auto_select_max_sim_num_clock_cycles ./fpga_x2p/spice/spice_primitive_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: -auto_select_max_sim_num_clock_cycles ./fpga_x2p/spice/spice_routing_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: -auto_select_num_sim_clock_cycle ./fpga_x2p/base/fpga_x2p_utils.c /^void auto_select_num_sim_clock_cycle(t_spice* spice,$/;" f -autocheck_testbench_postfix ./fpga_x2p/verilog/verilog_global.c /^char* autocheck_testbench_postfix = "_autocheck";$/;" v -autocheck_testbench_reference_output_postfix ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^static char* autocheck_testbench_reference_output_postfix = "_benchmark";$/;" v file: -autocheck_testbench_verification_output_postfix ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^static char* autocheck_testbench_verification_output_postfix = "_verification";$/;" v file: -autocheck_top_testbench_verilog_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* autocheck_top_testbench_verilog_file_postfix = "_autocheck_top_tb.v"; \/* !!! must be consist with the modelsim_autocheck_testbench_module_postfix *\/ $/;" v -autochecked_simulation_flag ./fpga_x2p/verilog/verilog_global.c /^char* autochecked_simulation_flag = "AUTOCHECKED_SIMULATION"; \/\/ the flag to enable autochecked functional verification$/;" v -back_annotate_one_pb_rr_node_map_info_rec ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void back_annotate_one_pb_rr_node_map_info_rec(t_pb* cur_pb,$/;" f file: -back_annotate_pb_rr_node_map_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void back_annotate_pb_rr_node_map_info() {$/;" f file: -back_annotate_rr_node_map_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void back_annotate_rr_node_map_info() {$/;" f file: -backannotate_clb_nets_act_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void backannotate_clb_nets_act_info() {$/;" f file: -backannotate_clb_nets_init_val ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void backannotate_clb_nets_init_val() {$/;" f file: -backannotate_one_pb_rr_nodes_net_info_rec ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void backannotate_one_pb_rr_nodes_net_info_rec(t_phy_pb* cur_pb) {$/;" f file: -backannotate_pb_rr_nodes_net_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void backannotate_pb_rr_nodes_net_info() {$/;" f file: -backannotate_pb_wired_luts ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void backannotate_pb_wired_luts(int num_mapped_blocks, t_block* mapped_block,$/;" f file: -backannotate_rr_graph_routing_results_to_net_name ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void backannotate_rr_graph_routing_results_to_net_name(t_rr_graph* local_rr_graph) {$/;" f -backannotate_rr_nodes_parasitic_net_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void backannotate_rr_nodes_parasitic_net_info() {$/;" f file: -background_cindex ./base/graphics.c /^ int background_cindex;$/;" m struct:__anon5 file: -backup_one_pb_rr_node_pack_prev_node_edge ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void backup_one_pb_rr_node_pack_prev_node_edge(t_rr_node* pb_rr_node) {$/;" f -backward_expand_pack_pattern_from_edge ./pack/prepack.c /^static void backward_expand_pack_pattern_from_edge($/;" f file: -backward_infer_pattern ./pack/prepack.c /^static void backward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin) {$/;" f file: -backward_path_cost ./route/route_common.h /^ float backward_path_cost;$/;" m struct:__anon15 -backward_path_cost ./route/route_common.h /^ float backward_path_cost;$/;" m struct:s_heap -backward_weight ./base/vpr_types.h /^ float forward_weight, backward_weight; \/* Weightings of the importance of paths $/;" m struct:s_tnode -base_cost ./base/vpr_types.h /^ float base_cost;$/;" m struct:s_rr_indexed_data -base_cost_type ./base/ReadOptions.h /^ enum e_base_cost_type base_cost_type;$/;" m struct:s_options typeref:enum:s_options::e_base_cost_type -base_cost_type ./base/vpr_types.h /^ enum e_base_cost_type base_cost_type;$/;" m struct:s_router_opts typeref:enum:s_router_opts::e_base_cost_type -base_gain ./base/vpr_types.h /^ float base_gain; \/* Intrinsic "goodness" score for molecule independant of rest of netlist *\/$/;" m struct:s_pack_molecule -basics_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* basics_spice_file_name = "inv_buf_trans_gate.sp";$/;" v -bb_coords ./place/place.c /^static struct s_bb *bb_coords = NULL, *bb_num_on_edges = NULL;$/;" v typeref:struct:s_bb file: -bb_factor ./base/ReadOptions.h /^ int bb_factor;$/;" m struct:s_options -bb_factor ./base/vpr_types.h /^ int bb_factor;$/;" m struct:s_router_opts -bb_num_on_edges ./place/place.c /^static struct s_bb *bb_coords = NULL, *bb_num_on_edges = NULL;$/;" v typeref:struct: file: -bb_updated_before ./place/place.c /^static char * bb_updated_before = NULL;$/;" v file: -bench_postfix ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* bench_postfix = "_bench";$/;" v file: -bend_cost ./base/ReadOptions.h /^ float bend_cost;$/;" m struct:s_options -bend_cost ./base/vpr_types.h /^ float bend_cost;$/;" m struct:s_router_opts -best_routing ./pack/cluster_legality.c /^static struct s_trace **best_routing;$/;" v typeref:struct:s_trace file: -beta ./base/ReadOptions.h /^ float beta;$/;" m struct:s_options -beta ./base/vpr_types.h /^ float beta;$/;" m struct:s_packer_opts -binary_not ./power/power_callibrate.c /^static char binary_not(char c) {$/;" f file: -binary_search ./base/globals.c /^int binary_search = -1;$/;" v -binary_search_place_and_route ./base/place_and_route.c /^static int binary_search_place_and_route(struct s_placer_opts placer_opts,$/;" f file: -bitfield ./base/vpr_types.h /^typedef size_t bitfield;$/;" t -bitstream_output_file ./base/vpr_types.h /^ char* bitstream_output_file;$/;" m struct:s_bitstream_gen_opts -blif ./base/read_blif.c /^static FILE *blif;$/;" v file: -blif_circuit_name ./base/globals.c /^char *blif_circuit_name = NULL;$/;" v -blif_file_name ./base/vpr_types.h /^ char *blif_file_name;$/;" m struct:s_packer_opts -blif_hash ./base/read_blif.c /^static struct s_hash **blif_hash;$/;" v typeref:struct:s_hash file: -blif_testbench_verilog_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* blif_testbench_verilog_file_postfix = "_blif_tb.v";$/;" v -blk_index ./place/place_macro.h /^ int blk_index;$/;" m struct:s_pl_macro_member -block ./base/globals.c /^struct s_block *block = NULL;$/;" v typeref:struct:s_block -block ./base/globals_declare.h /^struct s_block *block;$/;" v typeref:struct:s_block -block ./base/vpr_types.h /^ int block; \/* logical block primitive which this tnode is part of *\/$/;" m struct:s_tnode -block_color ./base/draw.c /^static enum color_types *net_color, *block_color;$/;" v typeref:enum: file: -block_criticality ./pack/cluster.c /^static float *block_criticality = NULL;$/;" v file: -block_delay ./base/ReadOptions.h /^ float block_delay;$/;" m struct:s_options -block_delay ./base/vpr_types.h /^ float block_delay;$/;" m struct:s_packer_opts -block_dist ./base/ReadOptions.h /^ int block_dist;$/;" m struct:s_options -block_dist ./base/vpr_types.h /^ int block_dist;$/;" m struct:s_placer_opts -block_num ./place/place.c /^ int block_num;$/;" m struct:s_pl_moved_block file: -blocks ./base/vpr_types.h /^ int *blocks;$/;" m struct:s_grid_tile -blocks_affected ./place/place.c /^static t_pl_blocks_to_be_moved blocks_affected;$/;" v file: -breadth_first_add_one_source_to_rr_graph_heap ./fpga_x2p/router/fpga_x2p_router.c /^void breadth_first_add_one_source_to_rr_graph_heap(t_rr_graph* local_rr_graph,$/;" f -breadth_first_add_source_to_heap ./route/route_breadth_first.c /^static void breadth_first_add_source_to_heap(int inet) {$/;" f file: -breadth_first_add_source_to_heap_cluster ./pack/cluster_legality.c /^static void breadth_first_add_source_to_heap_cluster(int inet) {$/;" f file: -breadth_first_add_source_to_rr_graph_heap ./fpga_x2p/router/fpga_x2p_router.c /^void breadth_first_add_source_to_rr_graph_heap(t_rr_graph* local_rr_graph,$/;" f -breadth_first_expand_neighbours ./route/route_breadth_first.c /^static void breadth_first_expand_neighbours(int inode, float pcost, int inet,$/;" f file: -breadth_first_expand_neighbours_cluster ./pack/cluster_legality.c /^static void breadth_first_expand_neighbours_cluster(int inode, float pcost,$/;" f file: -breadth_first_expand_rr_graph_neighbours ./fpga_x2p/router/fpga_x2p_router.c /^void breadth_first_expand_rr_graph_neighbours(t_rr_graph* local_rr_graph,$/;" f -breadth_first_expand_rr_graph_trace_segment ./fpga_x2p/router/fpga_x2p_router.c /^void breadth_first_expand_rr_graph_trace_segment(t_rr_graph* local_rr_graph,$/;" f -breadth_first_expand_trace_segment ./route/route_breadth_first.c /^static void breadth_first_expand_trace_segment(struct s_trace *start_ptr,$/;" f file: -breadth_first_expand_trace_segment_cluster ./pack/cluster_legality.c /^static void breadth_first_expand_trace_segment_cluster($/;" f file: -breadth_first_route_net ./route/route_breadth_first.c /^static boolean breadth_first_route_net(int inet, float bend_cost) {$/;" f file: -breadth_first_route_net_cluster ./pack/cluster_legality.c /^static boolean breadth_first_route_net_cluster(int inet) {$/;" f file: -breadth_first_route_one_multi_source_net_pb_rr_graph ./fpga_x2p/router/fpga_x2p_router.c /^boolean breadth_first_route_one_multi_source_net_pb_rr_graph(t_rr_graph* local_rr_graph, $/;" f -breadth_first_route_one_net_pb_rr_graph ./fpga_x2p/router/fpga_x2p_router.c /^boolean breadth_first_route_one_net_pb_rr_graph(t_rr_graph* local_rr_graph, $/;" f -breadth_first_route_one_single_source_net_pb_rr_graph ./fpga_x2p/router/fpga_x2p_router.c /^boolean breadth_first_route_one_single_source_net_pb_rr_graph(t_rr_graph* local_rr_graph, $/;" f -break_loops ./fpga_x2p/verilog/verilog_sdc.c /^ boolean break_loops;$/;" m struct:s_sdc_opts file: -break_loops_mux ./fpga_x2p/verilog/verilog_sdc.c /^ boolean break_loops_mux;$/;" m struct:s_sdc_opts file: -buffer_net ./place/timing_place_lookup.c /^static void buffer_net( float* cur_net_delay )$/;" f file: -buffer_size_inf ./power/power.h /^ t_power_buffer_size_inf * buffer_size_inf;$/;" m struct:s_power_tech -buffered ./base/vpr_types.h /^ int buffered;$/;" m struct:s_rr_node -build_bidir_rr_opins ./route/rr_graph.c /^static void build_bidir_rr_opins(INP int i, INP int j,$/;" f file: -build_default_menu ./base/graphics.c /^build_default_menu (void) $/;" f file: -build_device_rr_chan ./fpga_x2p/base/fpga_x2p_identify_routing.c /^DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node, $/;" f -build_ending_rr_node_for_one_sb_wire ./fpga_x2p/verilog/verilog_report_timing.c /^void build_ending_rr_node_for_one_sb_wire(t_rr_node* wire_rr_node, $/;" f -build_one_connection_block_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void build_one_connection_block_info(t_cb* cur_cb, int cb_x, int cb_y, t_rr_type cb_type,$/;" f -build_one_rr_chan ./fpga_x2p/base/fpga_x2p_identify_routing.c /^RRChan build_one_rr_chan(t_rr_type chan_type, size_t chan_x, size_t chan_y,$/;" f -build_one_switch_block_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void build_one_switch_block_info(t_sb* cur_sb, int sb_x, int sb_y, $/;" f -build_prev_node_list_rr_nodes ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void build_prev_node_list_rr_nodes(int LL_num_rr_nodes,$/;" f -build_rr_graph ./route/rr_graph.c /^void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,$/;" f -build_rr_sinks_sources ./route/rr_graph.c /^static void build_rr_sinks_sources(INP int i, INP int j,$/;" f file: -build_rr_xchan ./route/rr_graph.c /^static void build_rr_xchan(INP int i, INP int j,$/;" f file: -build_rr_ychan ./route/rr_graph.c /^static void build_rr_ychan(INP int i, INP int j,$/;" f file: -build_textarea ./base/graphics.c /^static void build_textarea (void) $/;" f file: -build_unidir_rr_opins ./route/rr_graph.c /^static void build_unidir_rr_opins(INP int i, INP int j,$/;" f file: -button ./base/graphics.c /^static t_button *button = NULL; \/* [0..num_buttons-1] *\/$/;" v file: -cal_capacitance_from_routing ./mrfpga/cal_capacitance.c /^void cal_capacitance_from_routing ( ) {$/;" f -calc_buffer_stage_effort ./power/power_util.c /^float calc_buffer_stage_effort(int N, float final_stage_size) {$/;" f -calculate_constraint ./timing/read_sdc.c /^static float calculate_constraint(t_sdc_clock source_domain, t_sdc_clock sink_domain) {$/;" f file: -callibrate ./power/PowerSpicedComponent.c /^void PowerCallibInputs::callibrate() {$/;" f class:PowerCallibInputs -callibrate ./power/PowerSpicedComponent.c /^void PowerSpicedComponent::callibrate(void) {$/;" f class:PowerSpicedComponent -cap ./timing/slre.c /^struct cap {$/;" s file: -capacity ./base/vpr_types.h /^ float capacity;$/;" m struct:s_place_region -capacity ./base/vpr_types.h /^ short capacity;$/;" m struct:s_rr_node -capture ./timing/slre.c /^static const char *capture(const struct cap *caps, int num_caps, va_list ap) {$/;" f file: -capture_float ./timing/slre.c /^static const char *capture_float(const struct cap *cap, void *p, size_t len) {$/;" f file: -capture_int ./timing/slre.c /^static const char *capture_int(const struct cap *cap, void *p, size_t len) {$/;" f file: -capture_string ./timing/slre.c /^static const char *capture_string(const struct cap *cap, void *p, size_t len) {$/;" f file: -casecmp ./timing/slre.c /^static int casecmp(const void *p1, const void *p2, size_t len) {$/;" f file: -category ./fpga_x2p/shell/shell_types.h /^ e_cmd_category category;$/;" m struct:s_shell_cmd -cb ./base/vpr_types.h /^ boolean *cb;$/;" m struct:s_seg_details -cbx_info ./base/globals.c /^t_cb** cbx_info = NULL;$/;" v -cbx_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* cbx_spice_file_name_prefix = "cbx_";$/;" v -cbx_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* cbx_verilog_file_name_prefix = "cbx_";$/;" v -cby_info ./base/globals.c /^t_cb** cby_info = NULL;$/;" v -cby_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* cby_spice_file_name_prefix = "cby_";$/;" v -cby_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* cby_verilog_file_name_prefix = "cby_";$/;" v -cc_constraints ./base/vpr_types.h /^ t_override_constraint * cc_constraints; \/* [0..num_cc_constraints - 1] array of such constraints *\/$/;" m struct:s_timing_constraints -cf_constraints ./base/vpr_types.h /^ t_override_constraint * cf_constraints; \/* [0..num_cf_constraints - 1] array of such constraints *\/$/;" m struct:s_timing_constraints -chain_pattern ./base/vpr_types.h /^ t_model_chain_pattern *chain_pattern; \/* If this is a chain molecule, chain that this molecule matches *\/$/;" m struct:s_pack_molecule -chan_rr_node ./base/vpr_types.h /^ t_rr_node*** chan_rr_node;$/;" m struct:s_cb -chan_rr_node ./base/vpr_types.h /^ t_rr_node*** chan_rr_node;$/;" m struct:s_sb -chan_rr_node_direction ./base/vpr_types.h /^ enum PORTS** chan_rr_node_direction;$/;" m struct:s_cb typeref:enum:s_cb::PORTS -chan_rr_node_direction ./base/vpr_types.h /^ enum PORTS** chan_rr_node_direction;$/;" m struct:s_sb typeref:enum:s_sb::PORTS -chan_width ./base/vpr_types.h /^ int* chan_width;$/;" m struct:s_cb -chan_width ./base/vpr_types.h /^ int* chan_width;$/;" m struct:s_sb -chan_width_x ./base/globals.c /^int *chan_width_x = NULL; \/* [0..ny] *\/$/;" v -chan_width_x ./base/globals_declare.h /^int *chan_width_x, *chan_width_y; \/* numerical form *\/$/;" v -chan_width_y ./base/globals.c /^int *chan_width_y = NULL; \/* [0..nx] *\/$/;" v -chan_width_y ./base/globals_declare.h /^int *chan_width_x, *chan_width_y; \/* numerical form *\/$/;" v -change_button_text ./base/graphics.c /^void change_button_text(const char *button_name, const char *new_button_text) {$/;" f -change_button_text ./base/graphics.c /^void change_button_text(const char *button_text, const char *new_button_text) { }$/;" f -channel_width ./power/power.h /^ int channel_width;$/;" m struct:s_solution_inf -chanx_chany_adjacent ./route/check_route.c /^static int chanx_chany_adjacent(int chanx_node, int chany_node) {$/;" f file: -chanx_module_ids_ ./fpga_x2p/base/rr_chan.h /^ std::vector< std::vector > chanx_module_ids_; \/* Module id in modules_ for each X-direction rr_channel *\/ $/;" m class:DeviceRRChan -chanx_modules_ ./fpga_x2p/base/rr_chan.h /^ std::vector chanx_modules_; \/* Detailed internal structure of each unique module *\/$/;" m class:DeviceRRChan -chanx_place_cost_fac ./place/place.c /^static float **chanx_place_cost_fac, **chany_place_cost_fac;$/;" v file: -chanx_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* chanx_spice_file_name_prefix = "chanx_";$/;" v -chanx_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* chanx_verilog_file_name_prefix = "chanx_";$/;" v -chany_module_ids_ ./fpga_x2p/base/rr_chan.h /^ std::vector< std::vector > chany_module_ids_; \/* Module id in modules_ for each Y-direction rr_channel *\/ $/;" m class:DeviceRRChan -chany_modules_ ./fpga_x2p/base/rr_chan.h /^ std::vector chany_modules_; \/* Detailed internal structure of each unique module *\/$/;" m class:DeviceRRChan -chany_place_cost_fac ./place/place.c /^static float **chanx_place_cost_fac, **chany_place_cost_fac;$/;" v file: -chany_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* chany_spice_file_name_prefix = "chany_";$/;" v -chany_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* chany_verilog_file_name_prefix = "chany_";$/;" v -checkTokenType ./util/token.c /^boolean checkTokenType(INP t_token token, OUTP enum e_token_type token_type) {$/;" f -check_adjacent ./route/check_route.c /^static boolean check_adjacent(int from_node, int to_node) {$/;" f file: -check_all_tracks_reach_pins ./route/rr_graph.c /^static void check_all_tracks_reach_pins(t_type_ptr type,$/;" f file: -check_and_add_mux_to_linked_list ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void check_and_add_mux_to_linked_list(t_llist** muxes_head,$/;" f -check_and_add_one_global_port_to_llist ./fpga_x2p/base/fpga_x2p_setup.c /^t_llist* check_and_add_one_global_port_to_llist(t_llist* old_head, $/;" f file: -check_and_count_models ./base/read_blif.c /^static void check_and_count_models(int doall, const char* model_name,$/;" f file: -check_and_rename_logical_block_and_net_names ./fpga_x2p/base/fpga_x2p_setup.c /^int check_and_rename_logical_block_and_net_names(t_llist* LL_reserved_syntax_char_head, $/;" f file: -check_clb_conn ./base/check_netlist.c /^static int check_clb_conn(int iblk, int num_conn) {$/;" f file: -check_clb_internal_nets ./base/check_netlist.c /^static int check_clb_internal_nets(int iblk) {$/;" f file: -check_clocks ./pack/cluster.c /^static void check_clocks(boolean *is_clock) {$/;" f file: -check_cluster_logical_blocks ./pack/cluster.c /^static void check_cluster_logical_blocks(t_pb *pb, boolean *blocks_checked) {$/;" f file: -check_clustering ./pack/cluster.c /^static void check_clustering(int num_clb, t_block *clb, boolean *is_clock) {$/;" f file: -check_conflict_syntax_char_in_string ./fpga_x2p/base/fpga_x2p_setup.c /^int check_conflict_syntax_char_in_string(t_llist* LL_reserved_syntax_char_head,$/;" f file: -check_connections_to_global_clb_pins ./base/check_netlist.c /^static int check_connections_to_global_clb_pins(int inet) {$/;" f file: -check_consistency_logical_block_net_num ./fpga_x2p/base/fpga_x2p_utils.c /^int check_consistency_logical_block_net_num(t_logical_block* lgk_blk, $/;" f -check_des_blk_pin ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int check_des_blk_pin(int n_blks, t_block* blk,$/;" f -check_drive_rr_node_imply_short ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^boolean check_drive_rr_node_imply_short(t_sb cur_sb_info,$/;" f -check_ff_spice_model_ports ./fpga_x2p/base/fpga_x2p_utils.c /^void check_ff_spice_model_ports(t_spice_model* cur_spice_model,$/;" f -check_fontsize ./base/graphics.c /^static int check_fontsize(int pointsize,$/;" f file: -check_for_duplicated_names ./base/check_netlist.c /^static int check_for_duplicated_names(void) {$/;" f file: -check_keywords_conflict ./fpga_x2p/base/fpga_x2p_setup.c /^void check_keywords_conflict(t_arch Arch) {$/;" f -check_locally_used_clb_opins ./route/check_route.c /^static void check_locally_used_clb_opins(t_ivec ** clb_opins_used_locally,$/;" f file: -check_lookahead_pins_used ./pack/cluster.c /^static boolean check_lookahead_pins_used(t_pb *cur_pb) {$/;" f file: -check_macro_can_be_placed ./place/place.c /^static int check_macro_can_be_placed(int imacro, int itype, int x, int y, int z) {$/;" f file: -check_macros_contained ./place/place_macro.c /^int check_macros_contained(t_pl_macro pl_macro_a,$/;" f -check_mem_model_blwl_inverted ./fpga_x2p/base/fpga_x2p_utils.c /^void check_mem_model_blwl_inverted(t_spice_model* cur_mem_model, $/;" f -check_negative_variation ./fpga_x2p/base/fpga_x2p_utils.c /^boolean check_negative_variation(float avg_val, $/;" f -check_net ./base/read_blif.c /^static void check_net(boolean sweep_hanging_nets_and_inputs) {$/;" f file: -check_netlist ./base/check_netlist.c /^void check_netlist() {$/;" f -check_node ./route/check_rr_graph.c /^void check_node(int inode, enum e_route_type route_type) {$/;" f -check_node_and_range ./route/check_route.c /^static void check_node_and_range(int inode, enum e_route_type route_type) {$/;" f file: -check_pass_transistors ./route/check_rr_graph.c /^static void check_pass_transistors(int from_node) {$/;" f file: -check_pb_graph ./pack/pb_type_graph.c /^static int check_pb_graph(void) {$/;" f file: -check_pb_graph_edge ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void check_pb_graph_edge(t_pb_graph_edge pb_graph_edge) {$/;" f -check_pb_graph_pin_edges ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void check_pb_graph_pin_edges(t_pb_graph_pin pb_graph_pin) {$/;" f -check_pin_number_match_phy_pb_graph_pin ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^boolean check_pin_number_match_phy_pb_graph_pin(t_pb_graph_pin* cur_pb_graph_pin, $/;" f -check_place ./place/place.c /^static void check_place(float bb_cost, float timing_cost, $/;" f file: -check_primitives ./base/check_netlist.c /^static int check_primitives(int iblk, int isub) {$/;" f file: -check_route ./route/check_route.c /^void check_route(enum e_route_type route_type, int num_switch,$/;" f -check_rr_graph ./route/check_rr_graph.c /^void check_rr_graph(INP t_graph_type graph_type, INP t_type_ptr types,$/;" f -check_sink ./route/check_route.c /^static void check_sink(int inode, int inet, boolean * pin_done) {$/;" f file: -check_source ./route/check_route.c /^static void check_source(int inode, int inet) {$/;" f file: -check_spice_model_name_conflict_syntax_char ./fpga_x2p/base/fpga_x2p_setup.c /^void check_spice_model_name_conflict_syntax_char(t_arch Arch,$/;" f file: -check_spice_model_structure_match_switch_inf ./fpga_x2p/base/fpga_x2p_utils.c /^boolean check_spice_model_structure_match_switch_inf(t_switch_inf target_switch_inf) {$/;" f -check_spice_models_grid_tb_cnt ./fpga_x2p/base/fpga_x2p_utils.c /^void check_spice_models_grid_tb_cnt(int num_spice_models,$/;" f -check_sram_spice_model_ports ./fpga_x2p/base/fpga_x2p_utils.c /^void check_sram_spice_model_ports(t_spice_model* cur_spice_model,$/;" f -check_src_blk_pin ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int check_src_blk_pin(int n_blks, t_block* blk,$/;" f -check_subblock_internal_nets ./base/check_netlist.c /^static int check_subblock_internal_nets(int iblk, int isub) {$/;" f file: -check_subblocks ./base/check_netlist.c /^static int check_subblocks(int iblk) {$/;" f file: -check_subckt_file_exist_in_llist ./fpga_x2p/base/fpga_x2p_utils.c /^boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head,$/;" f -check_switch ./route/check_route.c /^static void check_switch(struct s_trace *tptr, int num_switch) {$/;" f file: -check_timing_graph ./timing/path_delay2.c /^void check_timing_graph(int num_sinks) {$/;" f -child ./route/route_tree_timing.h /^ struct s_rt_node *child;$/;" m struct:s_linked_rt_edge typeref:struct:s_linked_rt_edge::s_rt_node -child ./timing/net_delay_types.h /^ struct s_rc_node *child;$/;" m struct:s_linked_rc_edge typeref:struct:s_linked_rc_edge::s_rc_node -child_list ./route/route_tree_timing.h /^ t_linked_rt_edge *child_list;$/;" m union:s_rt_node::__anon16 -child_list ./timing/net_delay_types.h /^ t_linked_rc_edge *child_list;$/;" m union:s_rc_node::__anon18 -child_pbs ./base/vpr_types.h /^ struct s_pb **child_pbs; \/* children pbs attached to this pb [0..num_child_pb_types - 1][0..child_type->num_pb - 1] *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb -child_pbs ./fpga_x2p/base/fpga_x2p_types.h /^ t_phy_pb **child_pbs; \/* children pbs attached to this pb [0..num_child_pb_types - 1][0..child_type->num_pb - 1] *\/$/;" m struct:fpga_spice_phy_pb -children ./power/power.h /^ t_mux_node * children; \/* Multiplexers that drive the inputs [0..num_inputs-1] *\/$/;" m struct:s_mux_node -chomp_file_name_postfix ./fpga_x2p/base/fpga_x2p_utils.c /^char* chomp_file_name_postfix(char* file_name) {$/;" f -chomp_spice_node_prefix ./fpga_x2p/base/fpga_x2p_utils.c /^char* chomp_spice_node_prefix(char* spice_node_prefix) {$/;" f -chomp_verilog_prefix ./fpga_x2p/verilog/verilog_utils.c /^char* chomp_verilog_prefix(char* verilog_node_prefix) {$/;" f -circuit_p_io_removed ./base/globals.c /^struct s_linked_vptr *circuit_p_io_removed = NULL;$/;" v typeref:struct:s_linked_vptr -clay_logical_equivalence_handling ./base/vpr_api.c /^static void clay_logical_equivalence_handling(const t_arch *arch) {$/;" f file: -clay_lut_input_rebalancing ./base/vpr_api.c /^static void clay_lut_input_rebalancing(int iblock, t_pb *pb) {$/;" f file: -clay_reload_ble_locations ./base/vpr_api.c /^static void clay_reload_ble_locations(int iblock) {$/;" f file: -clb2clb_direct ./base/globals.c /^t_clb_to_clb_directs* clb2clb_direct = NULL;$/;" v -clb_index ./base/vpr_types.h /^ int clb_index; \/* Complex block index that this logical block got mapped to *\/$/;" m struct:s_logical_block -clb_iteration ./fpga_x2p/verilog/verilog_formality_autodeck.c /^static void clb_iteration(FILE *fp, char* chomped_circuit_name, int h){$/;" f file: -clb_net ./base/globals.c /^struct s_net *clb_net = NULL;$/;" v typeref:struct:s_net -clb_net_density ./power/power_util.c /^float clb_net_density(int net_idx) {$/;" f -clb_net_prob ./power/power_util.c /^float clb_net_prob(int net_idx) {$/;" f -clb_opins_used_locally ./place/timing_place_lookup.c /^static t_ivec **clb_opins_used_locally;$/;" v file: -clb_to_vpack_net_mapping ./base/globals.c /^int *clb_to_vpack_net_mapping = NULL; \/* [0..num_clb_nets - 1] *\/$/;" v -clear ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::clear() {$/;" f class:DeviceRRChan -clear ./fpga_x2p/base/rr_chan.cpp /^void RRChan::clear() {$/;" f class:RRChan -clear_buffer ./mrfpga/buffer_insertion.c /^void clear_buffer( )$/;" f -clear_chan ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::clear_chan(t_rr_type chan_type) {$/;" f class:DeviceRRChan -clearscreen ./base/graphics.c /^clearscreen (void) $/;" f -clearscreen ./base/graphics.c /^void clearscreen (void) { }$/;" f -clock_delay ./base/vpr_types.h /^ float clock_delay; \/* The time taken for a clock signal to get to the flip-flop or I\/O (assumed 0 for I\/Os). *\/$/;" m struct:s_tnode -clock_domain ./base/vpr_types.h /^ int clock_domain; \/* Index of the clock in g_sdc->constrained_clocks which this flip-flop or I\/O is constrained on. *\/$/;" m struct:s_tnode -clock_input_name ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* clock_input_name = NULL;$/;" v file: -clock_name ./base/vpr_types.h /^ char * clock_name; \/* Clock it was constrained on *\/$/;" m struct:s_io -clock_names ./timing/read_sdc.c /^ char ** clock_names;$/;" m struct:s_sdc_exclusive_group file: -clock_net ./base/vpr_types.h /^ int clock_net; \/* Clock net connected to this logical_block. *\/$/;" m struct:s_logical_block -clock_net ./base/vpr_types.h /^ int clock_net; \/* Records clock net driving a flip-flop, valid only for lowest-level, flip-flop PBs *\/$/;" m struct:s_pb -clock_net_tnode ./base/vpr_types.h /^ struct s_tnode *clock_net_tnode; \/* correspnding clock net tnode *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_tnode -close_graphics ./base/graphics.c /^close_graphics (void) $/;" f -close_graphics ./base/graphics.c /^void close_graphics (void) { }$/;" f -close_postscript ./base/graphics.c /^void close_postscript (void) $/;" f -close_postscript ./base/graphics.c /^void close_postscript (void) { }$/;" f -cluster_seed_type ./base/ReadOptions.h /^ enum e_cluster_seed cluster_seed_type;$/;" m struct:s_options typeref:enum:s_options::e_cluster_seed -cluster_seed_type ./base/vpr_types.h /^ enum e_cluster_seed cluster_seed_type;$/;" m struct:s_packer_opts typeref:enum:s_packer_opts::e_cluster_seed -cluster_size ./base/ReadOptions.h /^ int cluster_size;$/;" m struct:s_options -cmd ./fpga_x2p/shell/shell_types.h /^ t_shell_cmd* cmd;$/;" m struct:s_shell_env -cmd_category ./fpga_x2p/shell/shell_cmds.h /^t_cmd_category cmd_category[] = {$/;" v -cmd_category ./fpga_x2p/shell/shell_types.h /^ t_cmd_category* cmd_category;$/;" m struct:s_shell_env -cnt ./fpga_x2p/verilog/verilog_report_timing.c /^ int cnt;$/;" m struct:s_wireL_cnt file: -code ./timing/slre.c /^ unsigned char code[256];$/;" m struct:slre file: -code_size ./timing/slre.c /^ int code_size;$/;" m struct:slre file: -color_types ./base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" g -colors ./base/graphics.c /^static int colors[NUM_COLOR];$/;" v file: -combine_buffer_plan ./mrfpga/buffer_insertion.c /^static t_buffer_plan combine_buffer_plan( t_buffer_plan slow_branch, t_buffer_plan* plan_whole, int num_whole, int num_pins )$/;" f file: -commit_lookahead_pins_used ./pack/cluster.c /^static void commit_lookahead_pins_used(t_pb *cur_pb) {$/;" f file: -commit_primitive ./pack/cluster_placement.c /^void commit_primitive(INOUTP t_cluster_placement_stats *cluster_placement_stats,$/;" f -comp_bb_cost ./place/place.c /^static float comp_bb_cost(enum cost_methods method) {$/;" f file: -comp_delta_td_cost ./place/place.c /^static void comp_delta_td_cost(float *delta_timing, float *delta_delay) {$/;" f file: -comp_td_costs ./place/place.c /^static void comp_td_costs(float *timing_cost, float *connection_delay_sum) {$/;" f file: -comp_td_point_to_point_delay ./place/place.c /^static float comp_td_point_to_point_delay(int inet, int ipin) {$/;" f file: -comp_width ./base/place_and_route.c /^static float comp_width(t_chan * chan, float x, float separation) {$/;" f file: -compact_routing_hierarchy ./base/vpr_types.h /^ boolean compact_routing_hierarchy; \/* use compact routing hierarchy *\/$/;" m struct:s_fpga_spice_opts -compact_verilog_get_grid_phy_block_subckt_name ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descriptor,$/;" f -compact_verilog_update_grid_spice_model_and_sram_orgz_info ./fpga_x2p/verilog/verilog_compact_netlist.c /^void compact_verilog_update_grid_spice_model_and_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,$/;" f file: -compact_verilog_update_one_spice_model_grid_index ./fpga_x2p/verilog/verilog_compact_netlist.c /^void compact_verilog_update_one_spice_model_grid_index(t_type_ptr phy_block_type,$/;" f file: -compact_verilog_update_sram_orgz_info_grid_index ./fpga_x2p/verilog/verilog_compact_netlist.c /^void compact_verilog_update_sram_orgz_info_grid_index(t_sram_orgz_info* cur_sram_orgz_info,$/;" f file: -compare_molecule_gain ./pack/cluster.c /^static int compare_molecule_gain(const void *a, const void *b) {$/;" f file: -compare_pack_pattern ./pack/prepack.c /^static int compare_pack_pattern(const t_pack_patterns *pattern_a, const t_pack_patterns *pattern_b) {$/;" f file: -compile ./timing/slre.c /^static void compile(struct slre *r, const char **re) {$/;" f file: -compile2 ./timing/slre.c /^static const char *compile2(struct slre *r, const char *re) {$/;" f file: -complete_truth_table_line ./fpga_x2p/base/fpga_x2p_lut_utils.c /^char* complete_truth_table_line(int lut_size,$/;" f -component_callibration ./power/power.h /^ PowerSpicedComponent ** component_callibration;$/;" m struct:s_power_commonly_used -component_usage ./power/PowerSpicedComponent.h /^ float (*component_usage)(int num_inputs, float transistor_size);$/;" m class:PowerSpicedComponent -components ./power/power_components.h /^ t_power_usage * components;$/;" m struct:s_power_breakdown -compress_netlist ./base/read_blif.c /^static void compress_netlist(void) {$/;" f file: -compute_and_mark_lookahead_pins_used ./pack/cluster.c /^static void compute_and_mark_lookahead_pins_used(int ilogical_block) {$/;" f file: -compute_and_mark_lookahead_pins_used_for_pin ./pack/cluster.c /^static void compute_and_mark_lookahead_pins_used_for_pin($/;" f file: -compute_delay_lookup_tables ./place/timing_place_lookup.c /^void compute_delay_lookup_tables(struct s_router_opts router_opts,$/;" f -compute_delta_arrays ./place/timing_place_lookup.c /^static void compute_delta_arrays(struct s_router_opts router_opts,$/;" f file: -compute_delta_clb_to_clb ./place/timing_place_lookup.c /^static void compute_delta_clb_to_clb(struct s_router_opts router_opts,$/;" f file: -compute_delta_clb_to_io ./place/timing_place_lookup.c /^static void compute_delta_clb_to_io(struct s_router_opts router_opts,$/;" f file: -compute_delta_io_to_clb ./place/timing_place_lookup.c /^static void compute_delta_io_to_clb(struct s_router_opts router_opts,$/;" f file: -compute_delta_io_to_io ./place/timing_place_lookup.c /^static void compute_delta_io_to_io(struct s_router_opts router_opts,$/;" f file: -compute_primitive_base_cost ./util/vpr_utils.c /^float compute_primitive_base_cost(INP t_pb_graph_node *primitive) {$/;" f -conf_bits_head ./fpga_x2p/verilog/verilog_global.c /^t_llist* conf_bits_head = NULL;$/;" v -conf_bits_lsb ./base/vpr_types.h /^ int conf_bits_lsb; \/* LSB of configuration bits *\/$/;" m struct:s_cb -conf_bits_lsb ./base/vpr_types.h /^ int conf_bits_lsb; \/* LSB of configuration bits *\/$/;" m struct:s_sb -conf_bits_msb ./base/vpr_types.h /^ int conf_bits_msb; \/* MSB of configuration bits *\/$/;" m struct:s_cb -conf_bits_msb ./base/vpr_types.h /^ int conf_bits_msb; \/* MSB of configuration bits *\/$/;" m struct:s_sb -config_one_spice_model_buffer ./fpga_x2p/base/fpga_x2p_utils.c /^void config_one_spice_model_buffer(int num_spice_models, $/;" f -config_peripheral_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* config_peripheral_verilog_file_name = "config_peripherals.v";$/;" v -config_spice_model_input_output_buffers_pass_gate ./fpga_x2p/base/fpga_x2p_utils.c /^void config_spice_model_input_output_buffers_pass_gate(int num_spice_models, $/;" f -config_spice_model_port_inv_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^void config_spice_model_port_inv_spice_model(int num_spice_models, $/;" f -config_spice_models_sram_port_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^void config_spice_models_sram_port_spice_model(int num_spice_model,$/;" f -configure_lut_sram_bits_per_line_rec ./fpga_x2p/base/fpga_x2p_lut_utils.c /^void configure_lut_sram_bits_per_line_rec(int** sram_bits, $/;" f -configure_one_tedge_delay ./fpga_x2p/base/fpga_x2p_timing_utils.c /^void configure_one_tedge_delay(t_spice_model_tedge* cur_tedge,$/;" f -configure_tedges_delay_matrix ./fpga_x2p/base/fpga_x2p_timing_utils.c /^void configure_tedges_delay_matrix(enum spice_model_delay_type delay_type,$/;" f -conn_list ./base/verilog_writer.h /^}conn_list;$/;" t typeref:struct:found_connectivity -connect_one_rr_node_for_phy_pb_graph_node ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void connect_one_rr_node_for_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin,$/;" f -connect_pb_des_pin_to_src_pin ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void connect_pb_des_pin_to_src_pin(t_pb* src_pb,$/;" f -connection_driven ./base/ReadOptions.h /^ boolean connection_driven;$/;" m struct:s_options -connection_driven ./base/vpr_types.h /^ boolean connection_driven;$/;" m struct:s_packer_opts -connectiongain ./base/vpr_types.h /^ std::map connectiongain; \/* [0..num_logical_blocks-1] Weighted sum of connections to attraction function *\/$/;" m struct:s_pb_stats -constant_net_delay ./base/ReadOptions.h /^ float constant_net_delay;$/;" m struct:s_options -constant_net_delay ./base/vpr_types.h /^ float constant_net_delay; \/* timing information when place and route not run *\/$/;" m struct:s_vpr_setup -constrain_cbs ./fpga_x2p/verilog/verilog_sdc.c /^ boolean constrain_cbs;$/;" m struct:s_sdc_opts file: -constrain_pbs ./fpga_x2p/verilog/verilog_sdc.c /^ boolean constrain_pbs;$/;" m struct:s_sdc_opts file: -constrain_routing_channels ./fpga_x2p/verilog/verilog_sdc.c /^ boolean constrain_routing_channels;$/;" m struct:s_sdc_opts file: -constrain_sbs ./fpga_x2p/verilog/verilog_sdc.c /^ boolean constrain_sbs;$/;" m struct:s_sdc_opts file: -constrained_clocks ./base/vpr_types.h /^ t_clock * constrained_clocks; \/* [0..g_sdc->num_constrained_clocks - 1] array of clocks with timing constraints *\/$/;" m struct:s_timing_constraints -constrained_inputs ./base/vpr_types.h /^ t_io * constrained_inputs; \/* [0..num_constrained_inputs - 1] array of inputs with timing constraints *\/$/;" m struct:s_timing_constraints -constrained_outputs ./base/vpr_types.h /^ t_io * constrained_outputs; \/* [0..num_constrained_outputs - 1] array of outputs with timing constraints *\/$/;" m struct:s_timing_constraints -constraint ./base/vpr_types.h /^ float constraint;$/;" m struct:s_override_constraint -convert_cb_type_to_string ./fpga_x2p/base/fpga_x2p_utils.c /^char* convert_cb_type_to_string(t_rr_type chan_type) {$/;" f -convert_chan_rr_node_direction_to_string ./fpga_x2p/base/fpga_x2p_utils.c /^char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction) {$/;" f -convert_chan_type_to_string ./fpga_x2p/base/fpga_x2p_utils.c /^char* convert_chan_type_to_string(t_rr_type chan_type) {$/;" f -convert_const_input_value_to_str ./fpga_x2p/spice/spice_utils.c /^char* convert_const_input_value_to_str(int const_input_val) {$/;" f -convert_modelsim_time_unit_to_float ./fpga_x2p/verilog/verilog_modelsim_autodeck.c /^float convert_modelsim_time_unit_to_float(char* modelsim_time_unit) {$/;" f -convert_option_mandatory_to_str ./fpga_x2p/shell/read_opt.c /^char* convert_option_mandatory_to_str(enum opt_manda cur) {$/;" f -convert_process_corner_to_string ./fpga_x2p/base/fpga_x2p_utils.c /^char* convert_process_corner_to_string(enum e_process_corner process_corner) {$/;" f -convert_side_index_to_string ./fpga_x2p/base/fpga_x2p_utils.c /^char* convert_side_index_to_string(int side) {$/;" f -convert_spice_model_port_type_to_verilog_port_type ./fpga_x2p/verilog/verilog_utils.c /^convert_spice_model_port_type_to_verilog_port_type(enum e_spice_model_port_type spice_model_port_type) {$/;" f -copy_delay ./mrfpga/buffer_insertion.c /^static void copy_delay( float* base, float* source, t_linked_int* index )$/;" f file: -copy_from_float_array ./mrfpga/buffer_insertion.c /^static float* copy_from_float_array( float* source, int num )$/;" f file: -copy_from_list ./mrfpga/mrfpga_util.c /^t_linked_int* copy_from_list( t_linked_int* base, t_linked_int* target )$/;" f -copy_nb_clusters ./base/globals.c /^int copy_nb_clusters = 0;$/;" v -copy_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^void copy_sram_orgz_info(t_sram_orgz_info* des_sram_orgz_info,$/;" f -cost ./base/vpr_types.h /^ float cost;$/;" m struct:s_place_region -cost ./route/route_common.h /^ float cost;$/;" m struct:s_heap -cost_index ./base/vpr_types.h /^ short cost_index;$/;" m struct:s_rr_node -cost_methods ./place/place.c /^enum cost_methods {$/;" g file: -count ./base/read_blif.c /^ int count;$/;" m struct:s_model_stats file: -count ./util/hash.h /^ int count;$/;" m struct:s_hash -count_bidir_routing_transistors ./route/rr_graph_area.c /^void count_bidir_routing_transistors(int num_switch, float R_minW_nmos,$/;" f -count_blk_one_class_num_conflict ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int count_blk_one_class_num_conflict(t_block* target_blk, int class_index,$/;" f -count_cb_info_num_ipin_rr_nodes ./fpga_x2p/base/fpga_x2p_utils.c /^int count_cb_info_num_ipin_rr_nodes(t_cb cur_cb_info) {$/;" f -count_connections ./place/place.c /^static int count_connections() {$/;" f file: -count_netlist_clocks ./base/stats.c /^int count_netlist_clocks(void) {$/;" f -count_netlist_clocks_as_constrained_clocks ./timing/read_sdc.c /^static void count_netlist_clocks_as_constrained_clocks(void) {$/;" f file: -count_netlist_ios_as_constrained_ios ./timing/read_sdc.c /^static void count_netlist_ios_as_constrained_ios(char * clock_name, float io_delay) {$/;" f file: -count_num_conf_bit_one_interc ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int count_num_conf_bit_one_interc(t_interconnect* cur_interc,$/;" f -count_num_conf_bits_one_generic_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_conf_bits_one_generic_spice_model(t_spice_model* cur_spice_model,$/;" f -count_num_conf_bits_one_lut_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model,$/;" f -count_num_conf_bits_one_mux_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model,$/;" f -count_num_conf_bits_one_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_conf_bits_one_spice_model(t_spice_model* cur_spice_model,$/;" f -count_num_conf_bits_pb_type_mode_interc ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int count_num_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode,$/;" f -count_num_mode_bits_one_generic_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_mode_bits_one_generic_spice_model(t_spice_model* cur_spice_model) {$/;" f -count_num_mode_bits_one_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_mode_bits_one_spice_model(t_spice_model* cur_spice_model) {$/;" f -count_num_reserved_conf_bit_one_interc ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc,$/;" f -count_num_reserved_conf_bits_one_lut_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_reserved_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model,$/;" f -count_num_reserved_conf_bits_one_mux_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_reserved_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model,$/;" f -count_num_reserved_conf_bits_one_rram_sram_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_reserved_conf_bits_one_rram_sram_spice_model(t_spice_model* cur_spice_model,$/;" f -count_num_reserved_conf_bits_one_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model,$/;" f -count_num_reserved_conf_bits_pb_type_mode_interc ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int count_num_reserved_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode,$/;" f -count_num_sram_bits_one_generic_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_sram_bits_one_generic_spice_model(t_spice_model* cur_spice_model) {$/;" f -count_num_sram_bits_one_lut_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_sram_bits_one_lut_spice_model(t_spice_model* cur_spice_model) {$/;" f -count_num_sram_bits_one_mux_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model,$/;" f -count_num_sram_bits_one_spice_model ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model,$/;" f -count_pb_graph_node_input_edge_in_phy_mode ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int count_pb_graph_node_input_edge_in_phy_mode(t_pb_graph_pin* cur_pb_graph_pin,$/;" f -count_pb_graph_node_output_edge_in_phy_mode ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int count_pb_graph_node_output_edge_in_phy_mode(t_pb_graph_pin* cur_pb_graph_pin,$/;" f -count_pin_number_one_pb_graph_node ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int count_pin_number_one_pb_graph_node(t_pb_graph_node* cur_pb_graph_node) {$/;" f -count_pin_number_one_port_pb_graph_node ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int count_pin_number_one_port_pb_graph_node(int num_ports, int* num_pins) {$/;" f -count_routing_memristor_buffer ./mrfpga/buffer_insertion.c /^void count_routing_memristor_buffer( int num_per_channel, float buffer_size )$/;" f -count_routing_transistors ./route/rr_graph_area.c /^void count_routing_transistors(enum e_directionality directionality,$/;" f -count_sinks_internal_cb_rr_graph_net_nums ./base/read_netlist.c /^static int count_sinks_internal_cb_rr_graph_net_nums($/;" f file: -count_unidir_routing_transistors ./route/rr_graph_area.c /^void count_unidir_routing_transistors(t_segment_inf * segment_inf,$/;" f -count_verilog_connection_box_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -count_verilog_connection_box_interc_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -count_verilog_connection_box_interc_reserved_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_connection_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -count_verilog_connection_box_one_side_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_connection_box_one_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -count_verilog_connection_box_one_side_reserved_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -count_verilog_connection_box_reserved_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -count_verilog_switch_box_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -count_verilog_switch_box_interc_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -count_verilog_switch_box_interc_reserved_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -count_verilog_switch_box_reserved_conf_bits ./fpga_x2p/verilog/verilog_routing.c /^int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -cpd ./base/vpr_types.h /^ float ** cpd;$/;" m struct:s_timing_stats -cpt_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* cpt_subckt_name = "cpt";$/;" v -create_button ./base/graphics.c /^void create_button (const char *prev_button_text , const char *button_text, $/;" f -create_button ./base/graphics.c /^void create_button (const char *prev_button_text , const char *button_text,$/;" f -create_dir_path ./fpga_x2p/base/fpga_x2p_utils.c /^int create_dir_path(char* dir_path) {$/;" f -create_wireL_report_timing_tcl_file_handler ./fpga_x2p/verilog/verilog_report_timing.c /^FILE* create_wireL_report_timing_tcl_file_handler(t_trpt_opts trpt_opts, $/;" f -criticality_exp ./base/ReadOptions.h /^ float criticality_exp;$/;" m struct:s_options -criticality_exp ./base/vpr_types.h /^ float criticality_exp;$/;" m struct:s_router_opts -critindexarray ./pack/cluster.c /^static int *critindexarray = NULL;$/;" v file: -cross_count ./place/place.c /^static const float cross_count[50] = { \/* [0..49] *\/1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974,$/;" v file: -curr_cluster_index ./pack/cluster_legality.c /^static int curr_cluster_index;$/;" v file: -curr_molecule ./base/vpr_types.h /^ t_pack_molecule *curr_molecule; \/* current molecule being considered for packing *\/$/;" m struct:s_cluster_placement_stats -current_draw_mode ./base/graphics.c /^static e_draw_mode current_draw_mode;$/;" v file: -current_gc ./base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: -currentcolor ./base/graphics.c /^static int currentcolor;$/;" v file: -currentfontsize ./base/graphics.c /^static int currentfontsize;$/;" v file: -currentlinestyle ./base/graphics.c /^static int currentlinestyle;$/;" v file: -currentlinewidth ./base/graphics.c /^static int currentlinewidth;$/;" v file: -cxClient ./base/graphics.c /^static int cxClient, cyClient;$/;" v file: -cyClient ./base/graphics.c /^static int cxClient, cyClient;$/;" v file: -data ./timing/slre.c /^ unsigned char data[256];$/;" m struct:slre file: -data ./util/token.h /^ char *data;$/;" m struct:s_token -data_size ./timing/slre.c /^ int data_size;$/;" m struct:slre file: -dealloc_mux_graph ./power/power.c /^static void dealloc_mux_graph(t_mux_node * node) {$/;" f file: -dealloc_mux_graph_rec ./power/power.c /^static void dealloc_mux_graph_rec(t_mux_node * node) {$/;" f file: -decode_and_add_sram_membank_conf_bit_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^decode_and_add_sram_membank_conf_bit_to_llist(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -decode_cmos_mux_sram_bits ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void decode_cmos_mux_sram_bits(t_spice_model* mux_spice_model,$/;" f -decode_memory_bank_sram ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^void decode_memory_bank_sram(t_spice_model* cur_sram_spice_model, int sram_bit,$/;" f -decode_mode_bits ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int* decode_mode_bits(char* mode_bits, int* num_sram_bits) {$/;" f -decode_multilevel_4t1r_mux ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void decode_multilevel_4t1r_mux(int num_level, int num_input_basis,$/;" f -decode_multilevel_mux_sram_bits ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int* decode_multilevel_mux_sram_bits(int fan_in,$/;" f -decode_one_level_4t1r_mux ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void decode_one_level_4t1r_mux(int path_id, $/;" f -decode_onelevel_mux_sram_bits ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int* decode_onelevel_mux_sram_bits(int fan_in,$/;" f -decode_physical_mode_pin_annotation ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void decode_physical_mode_pin_annotation(int phy_pb_type_port_size,$/;" f -decode_rram_mux ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void decode_rram_mux(t_spice_model* mux_spice_model,$/;" f -decode_tree_mux_sram_bits ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int* decode_tree_mux_sram_bits(int fan_in,$/;" f -def_clk_name ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* def_clk_name = "clk";$/;" v file: -default_lb_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_lb_dir_name = "lb\/";$/;" v -default_message ./base/draw.c /^static char default_message[BUFSIZE]; \/* Default screen message on screen *\/$/;" v file: -default_modelsim_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_modelsim_dir_name = "msim_projects\/";$/;" v -default_msim_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_msim_dir_name = "MSIM\/";$/;" v -default_output_name ./base/globals.c /^char *default_output_name = NULL;$/;" v -default_report_timing_rpt_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_report_timing_rpt_dir_name = "RPT\/";$/;" v -default_rr_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_rr_dir_name = "routing\/";$/;" v -default_sdc_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_sdc_dir_name = "SDC\/";$/;" v -default_sdc_folder ./fpga_x2p/base/fpga_x2p_globals.c /^char* default_sdc_folder = "SDC\/";$/;" v -default_signal_init_value ./fpga_x2p/base/fpga_x2p_globals.c /^int default_signal_init_value = 0;$/;" v -default_snpsfm_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_snpsfm_dir_name = "SNPS_FM\/";$/;" v -default_spice_dir_path ./fpga_x2p/spice/spice_api.c /^static char* default_spice_dir_path = "spice_netlists\/";$/;" v file: -default_src_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_src_dir_name = "SRC\/";$/;" v -default_submodule_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_submodule_dir_name = "sub_module\/";$/;" v -default_tcl_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_tcl_dir_name = "SCRIPTS\/";$/;" v -default_verilog_dir_name ./fpga_x2p/verilog/verilog_global.c /^char* default_verilog_dir_name = "syn_verilogs\/";$/;" v -defines_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* defines_verilog_file_name = "fpga_defines.v";$/;" v -defines_verilog_simulation_file_name ./fpga_x2p/verilog/verilog_global.c /^char* defines_verilog_simulation_file_name = "define_simulation.v";$/;" v -delay ./base/vpr_types.h /^ float delay; \/* Delay through the I\/O in this constraint *\/$/;" m struct:s_io -delayless_switch ./base/vpr_types.h /^ short delayless_switch;$/;" m struct:s_det_routing_arch -delayless_switch_index ./fpga_x2p/base/fpga_x2p_types.h /^ int delayless_switch_index;$/;" m struct:fpga_spice_rr_graph -delta_clb_to_clb ./place/timing_place_lookup.c /^float **delta_clb_to_clb;$/;" v -delta_clb_to_io ./place/timing_place_lookup.c /^float **delta_clb_to_io;$/;" v -delta_io_to_clb ./place/timing_place_lookup.c /^float **delta_io_to_clb;$/;" v -delta_io_to_io ./place/timing_place_lookup.c /^float **delta_io_to_io;$/;" v -density ./base/vpr_types.h /^ float density;$/;" m struct:s_net_power -description ./fpga_x2p/shell/read_opt_types.h /^ char* description;$/;" m struct:s_opt_info -deselect_all ./base/draw.c /^static void deselect_all(void) {$/;" f file: -design_param_header_file_name ./fpga_x2p/spice/spice_globals.c /^char* design_param_header_file_name = "design_params.sp";$/;" v -design_param_postfix_input_buf_size ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_input_buf_size = "_input_buf_size"; $/;" v -design_param_postfix_output_buf_size ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_output_buf_size = "_output_buf_size"; $/;" v -design_param_postfix_pass_gate_logic_nmos_size ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_pass_gate_logic_nmos_size = "_pgl_nmos_size"; $/;" v -design_param_postfix_pass_gate_logic_pmos_size ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_pass_gate_logic_pmos_size = "_pgl_pmos_size"; $/;" v -design_param_postfix_rram_roff ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_rram_roff = "_rram_roff"; $/;" v -design_param_postfix_rram_ron ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_rram_ron = "_rram_ron"; $/;" v -design_param_postfix_rram_wprog_reset_nmos ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_rram_wprog_reset_nmos = "_rram_wprog_reset_nmos"; $/;" v -design_param_postfix_rram_wprog_reset_pmos ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_rram_wprog_reset_pmos = "_rram_wprog_reset_pmos"; $/;" v -design_param_postfix_rram_wprog_set_nmos ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_rram_wprog_set_nmos = "_rram_wprog_set_nmos"; $/;" v -design_param_postfix_rram_wprog_set_pmos ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_rram_wprog_set_pmos = "_rram_wprog_set_pmos"; $/;" v -design_param_postfix_wire_param_cap_val ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_wire_param_cap_val = "_wire_param_cap_val"; $/;" v -design_param_postfix_wire_param_res_val ./fpga_x2p/spice/spice_globals.c /^char* design_param_postfix_wire_param_res_val = "_wire_param_res_val"; $/;" v -destroy_button ./base/graphics.c /^destroy_button (const char *button_text) $/;" f -destroy_button ./base/graphics.c /^void destroy_button (const char *button_text) { }$/;" f -determine_actual_pb_interc_type ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^enum e_interconnect determine_actual_pb_interc_type(t_interconnect* def_interc, $/;" f -determine_blwl_decoder_size ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^void determine_blwl_decoder_size(INP t_sram_orgz_info* cur_sram_orgz_info,$/;" f -determine_decoder_size ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^int determine_decoder_size(int num_addr_out) {$/;" f -determine_io_grid_side ./fpga_x2p/base/fpga_x2p_utils.c /^int determine_io_grid_side(int x,$/;" f -determine_lut_path_id ./fpga_x2p/base/fpga_x2p_lut_utils.c /^int determine_lut_path_id(int lut_size,$/;" f -determine_lut_truth_table_on_set ./fpga_x2p/base/fpga_x2p_lut_utils.c /^int determine_lut_truth_table_on_set(int truth_table_len,$/;" f -determine_num_input_basis_multilevel_mux ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int determine_num_input_basis_multilevel_mux(int mux_size,$/;" f -determine_num_sram_bits_mux_basis_subckt ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int determine_num_sram_bits_mux_basis_subckt(t_spice_model* mux_spice_model,$/;" f -determine_rr_node_default_prev_node ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int determine_rr_node_default_prev_node(t_rr_node* cur_rr_node) {$/;" f -determine_sb_port_coordinator ./fpga_x2p/base/fpga_x2p_utils.c /^void determine_sb_port_coordinator(t_sb cur_sb_info, int side, $/;" f -determine_tree_mux_level ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int determine_tree_mux_level(int mux_size) {$/;" f -determine_verilog_generic_port_split_sign ./fpga_x2p/verilog/verilog_utils.c /^char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type) {$/;" f -device_rr_chan ./fpga_x2p/base/fpga_x2p_globals.c /^DeviceRRChan device_rr_chan;$/;" v -diff_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^t_sram_orgz_info* diff_sram_orgz_info(t_sram_orgz_info* des_sram_orgz_info, $/;" f -direction ./base/vpr_types.h /^ enum e_direction direction; \/* UDSD by AY *\/$/;" m struct:s_rr_node typeref:enum:s_rr_node::e_direction -direction ./base/vpr_types.h /^ enum e_direction direction; \/* UDSD by AY *\/$/;" m struct:s_seg_details typeref:enum:s_seg_details::e_direction -directionality ./base/vpr_types.h /^ enum e_directionality directionality; \/* UDSD by AY *\/$/;" m struct:s_det_routing_arch typeref:enum:s_det_routing_arch::e_directionality -directionality ./base/vpr_types.h /^ enum e_directionality directionality; \/* UDSD by AY *\/$/;" m struct:s_cb typeref:enum:s_cb::e_directionality -directionality ./base/vpr_types.h /^ enum e_directionality directionality; \/* UDSD by AY *\/$/;" m struct:s_sb typeref:enum:s_sb::e_directionality -discover_all_forced_connections ./pack/cluster_feasibility_filter.c /^static void discover_all_forced_connections(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f file: -discover_pattern_names_in_pb_graph_node ./pack/prepack.c /^static void discover_pattern_names_in_pb_graph_node($/;" f file: -disp_type ./base/graphics.c /^ int disp_type;$/;" m struct:__anon5 file: -display ./base/graphics.c /^static Display *display;$/;" v file: -display_height ./base/graphics.c /^static int display_width, display_height; \/* screen size *\/$/;" v file: -display_width ./base/graphics.c /^static int display_width, display_height; \/* screen size *\/$/;" v file: -displaybuffer ./base/graphics.c /^void displaybuffer(void) { }$/;" f -displaybuffer ./base/graphics.c /^void displaybuffer(void) {$/;" f -distr ./route/rr_graph.c /^ int *distr;$/;" m struct:s_mux_size_distribution file: -doPacking ./base/vpr_types.h /^ boolean doPacking;$/;" m struct:s_packer_opts -doPlacement ./base/vpr_types.h /^ boolean doPlacement;$/;" m struct:s_placer_opts -doRouting ./base/vpr_types.h /^ boolean doRouting;$/;" m struct:s_router_opts -do_clustering ./pack/cluster.c /^void do_clustering(const t_arch *arch, t_pack_molecule *molecule_head,$/;" f -do_constant_net_delay_timing_analysis ./timing/path_delay.c /^void do_constant_net_delay_timing_analysis(t_timing_inf timing_inf,$/;" f -do_fpga_spice ./base/vpr_types.h /^ boolean do_fpga_spice;$/;" m struct:s_fpga_spice_opts -do_lut_rebalancing ./timing/path_delay.c /^static void do_lut_rebalancing() {$/;" f file: -do_path_counting ./timing/path_delay.c /^static void do_path_counting(float criticality_denom) {$/;" f file: -do_power ./base/vpr_types.h /^ boolean do_power; \/* Perform power estimation? *\/$/;" m struct:s_power_opts -do_quicksort_float_index ./fpga_x2p/base/quicksort.c /^void do_quicksort_float_index(int len, $/;" f -do_spice ./base/vpr_types.h /^ boolean do_spice;$/;" m struct:s_spice_opts -do_timing_analysis ./timing/path_delay.c /^void do_timing_analysis(t_slack * slacks, boolean is_prepacked, boolean do_lut_input_balancing, boolean is_final_analysis) {$/;" f -do_timing_analysis_for_constraint ./timing/path_delay.c /^static float do_timing_analysis_for_constraint(int source_clock_domain, int sink_clock_domain, $/;" f file: -domain_constraint ./base/vpr_types.h /^ float ** domain_constraint; \/* [0..num_constrained_clocks - 1 (source)][0..num_constrained_clocks - 1 (destination)] *\/$/;" m struct:s_timing_constraints -done_callibration ./power/PowerSpicedComponent.h /^ bool done_callibration;$/;" m class:PowerCallibInputs -done_callibration ./power/PowerSpicedComponent.h /^ bool done_callibration;$/;" m class:PowerSpicedComponent -draw_chanx_to_chanx_edge ./base/draw.c /^static void draw_chanx_to_chanx_edge(int from_node, int from_track, int to_node,$/;" f file: -draw_chanx_to_chany_edge ./base/draw.c /^static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track,$/;" f file: -draw_chany_to_chany_edge ./base/draw.c /^static void draw_chany_to_chany_edge(int from_node, int from_track, int to_node,$/;" f file: -draw_congestion ./base/draw.c /^static void draw_congestion(void) {$/;" f file: -draw_message ./base/graphics.c /^draw_message (void) $/;" f -draw_message ./base/graphics.c /^void draw_message (void) { }$/;" f -draw_pin_to_chan_edge ./base/draw.c /^static void draw_pin_to_chan_edge(int pin_node, int chan_node) {$/;" f file: -draw_pin_to_pin ./base/draw.c /^static void draw_pin_to_pin(int opin_node, int ipin_node) {$/;" f file: -draw_route_type ./base/draw.c /^static enum e_route_type draw_route_type;$/;" v typeref:enum:e_route_type file: -draw_rr ./base/draw.c /^void draw_rr(void) {$/;" f -draw_rr_chanx ./base/draw.c /^static void draw_rr_chanx(int inode, int itrack) {$/;" f file: -draw_rr_chany ./base/draw.c /^static void draw_rr_chany(int inode, int itrack) {$/;" f file: -draw_rr_edges ./base/draw.c /^static void draw_rr_edges(int inode) {$/;" f file: -draw_rr_pin ./base/draw.c /^static void draw_rr_pin(int inode, enum color_types color) {$/;" f file: -draw_rr_switch ./base/draw.c /^static void draw_rr_switch(float from_x, float from_y, float to_x, float to_y,$/;" f file: -draw_rr_toggle ./base/draw.c /^static enum e_draw_rr_toggle draw_rr_toggle = DRAW_NO_RR; \/* UDSD by AY *\/$/;" v typeref:enum:e_draw_rr_toggle file: -draw_triangle_along_line ./base/draw.c /^static void draw_triangle_along_line(float xend, float yend, float x1, float x2,$/;" f file: -draw_x ./base/draw.c /^static void draw_x(float x, float y, float size) {$/;" f file: -drawarc ./base/graphics.c /^drawarc (float xc, float yc, float rad, float startang, $/;" f -drawarc ./base/graphics.c /^void drawarc (float xcen, float ycen, float rad, float startang,$/;" f -drawbut ./base/graphics.c /^static void drawbut (int bnum) $/;" f file: -drawcurve ./base/graphics.c /^void drawcurve(t_point *points, int npoints) { }$/;" f -drawcurve ./base/graphics.c /^void drawcurve(t_point *points,$/;" f -drawellipticarc ./base/graphics.c /^drawellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent) $/;" f -drawellipticarc ./base/graphics.c /^void drawellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent) { }$/;" f -drawline ./base/graphics.c /^drawline (float x1, float y1, float x2, float y2) $/;" f -drawline ./base/graphics.c /^void drawline (float x1, float y1, float x2, float y2) { }$/;" f -drawmenu ./base/graphics.c /^static void drawmenu(void) $/;" f file: -drawnets ./base/draw.c /^static void drawnets(void) {$/;" f file: -drawplace ./base/draw.c /^static void drawplace(void) {$/;" f file: -drawrect ./base/graphics.c /^drawrect (float x1, float y1, float x2, float y2) $/;" f -drawrect ./base/graphics.c /^void drawrect (float x1, float y1, float x2, float y2) { }$/;" f -drawroute ./base/draw.c /^static void drawroute(enum e_draw_net_type draw_net_type) {$/;" f file: -drawscreen ./base/draw.c /^static void drawscreen() {$/;" f file: -drawscreen_ptr ./base/graphics.c /^static void (*drawscreen_ptr)(void);$/;" v file: -drawtext ./base/graphics.c /^drawtext (float xc, float yc, const char *text, float boundx) $/;" f -drawtext ./base/graphics.c /^void drawtext (float xc, float yc, const char *text, float boundx) { }$/;" f -drawtobuffer ./base/graphics.c /^void drawtobuffer(void) { }$/;" f -drawtobuffer ./base/graphics.c /^void drawtobuffer(void) {$/;" f -drawtoscreen ./base/graphics.c /^void drawtoscreen(void) { }$/;" f -drawtoscreen ./base/graphics.c /^void drawtoscreen(void) {$/;" f -drive_rr_nodes ./base/vpr_types.h /^ t_rr_node** drive_rr_nodes;$/;" m struct:s_rr_node -drive_switches ./base/vpr_types.h /^ int* drive_switches;$/;" m struct:s_rr_node -driver_pb ./base/verilog_writer.h /^ t_pb *driver_pb;$/;" m struct:found_connectivity -driver_pin ./base/verilog_writer.h /^ t_pb_graph_pin *driver_pin;$/;" m struct:found_connectivity -driver_switch ./base/vpr_types.h /^ short driver_switch; \/* Xifan TANG: Switch Segment Pattern Support*\/$/;" m struct:s_rr_node -driver_switch_type ./power/power.h /^ short driver_switch_type; \/* Switch type that drives this resource *\/$/;" m struct:s_rr_node_power -driver_to_load_delay ./base/verilog_writer.h /^ float driver_to_load_delay;$/;" m struct:found_connectivity -drivers ./base/vpr_types.h /^ enum e_drivers drivers; \/* UDSD by AY *\/$/;" m struct:s_rr_node typeref:enum:s_rr_node::e_drivers -drivers ./base/vpr_types.h /^ enum e_drivers drivers; \/* UDSD by AY *\/$/;" m struct:s_seg_details typeref:enum:s_seg_details::e_drivers -dum_parse ./base/read_blif.c /^void dum_parse(char *buf) {$/;" f -dummy_type_descriptors ./place/timing_place_lookup.c /^static t_type_descriptor dummy_type_descriptors[NUM_TYPES_USED];$/;" v file: -dump_compact_verilog_defined_channels ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_channels(FILE* fp) {$/;" f -dump_compact_verilog_defined_connection_boxes ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_compact_verilog_defined_grids ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_compact_verilog_defined_one_channel ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_one_channel(FILE* fp,$/;" f file: -dump_compact_verilog_defined_one_connection_box ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_compact_verilog_defined_one_grid ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,$/;" f file: -dump_compact_verilog_defined_one_switch_box ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_compact_verilog_defined_switch_boxes ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_compact_verilog_grid_pins ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_compact_verilog_grid_pins(FILE* fp,$/;" f -dump_compact_verilog_io_grid_block_subckt_pins ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,$/;" f -dump_compact_verilog_io_grid_pins ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_compact_verilog_io_grid_pins(FILE* fp,$/;" f -dump_compact_verilog_logic_blocks ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_compact_verilog_one_physical_block ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_compact_verilog_top_netlist ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_conf_bits_to_bitstream_file ./fpga_x2p/bitstream/fpga_bitstream.c /^void dump_conf_bits_to_bitstream_file(FILE* fp, $/;" f file: -dump_fpga_spice_bitstream ./fpga_x2p/bitstream/fpga_bitstream.c /^void dump_fpga_spice_bitstream(char* bitstream_file_name, $/;" f -dump_include_user_defined_verilog_netlists ./fpga_x2p/verilog/verilog_utils.c /^void dump_include_user_defined_verilog_netlists(FILE* fp,$/;" f -dump_one_verilog_template_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_one_verilog_template_module(FILE* fp,$/;" f -dump_one_verilog_template_module_one_port ./fpga_x2p/verilog/verilog_submodules.c /^void dump_one_verilog_template_module_one_port(FILE* fp, int* cnt,$/;" f -dump_rr_graph ./route/rr_graph.c /^void dump_rr_graph(INP const char *file_name) {$/;" f -dump_sdc_one_clb_muxes ./fpga_x2p/verilog/verilog_sdc.c /^void dump_sdc_one_clb_muxes(FILE* fp,$/;" f -dump_sdc_pb_graph_node_muxes ./fpga_x2p/verilog/verilog_sdc.c /^void dump_sdc_pb_graph_node_muxes (FILE* fp,$/;" f -dump_sdc_pb_graph_pin_interc ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_sdc_pb_graph_pin_muxes ./fpga_x2p/verilog/verilog_sdc.c /^void dump_sdc_pb_graph_pin_muxes (FILE* fp,$/;" f -dump_sdc_pb_graph_port_interc ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^void dump_sdc_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_sdc_physical_blocks ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^void dump_sdc_physical_blocks(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_sdc_rec_one_pb_muxes ./fpga_x2p/verilog/verilog_sdc.c /^void dump_sdc_rec_one_pb_muxes(FILE* fp,$/;" f -dump_seg_details ./route/rr_graph2.c /^void dump_seg_details(t_seg_details * seg_details, int nodes_per_chan,$/;" f -dump_simulation_preproc ./fpga_x2p/verilog/verilog_utils.c /^void dump_simulation_preproc(FILE* fp, $/;" f -dump_syn_verilog ./base/vpr_types.h /^ boolean dump_syn_verilog;$/;" m struct:s_syn_verilog_opts -dump_verilog_autocheck_top_testbench ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_clb2clb_directs ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_clb2clb_directs(FILE* fp, $/;" f -dump_verilog_cmos_mux_config_bus ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, $/;" f -dump_verilog_cmos_mux_config_bus_ports ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, $/;" f -dump_verilog_cmos_mux_mem_submodule ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_mem_submodule(FILE* fp,$/;" f -dump_verilog_cmos_mux_multilevel_structure ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, $/;" f -dump_verilog_cmos_mux_one_basis_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_one_basis_module(FILE* fp, $/;" f -dump_verilog_cmos_mux_one_basis_module_structural ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, $/;" f file: -dump_verilog_cmos_mux_onelevel_structure ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, $/;" f -dump_verilog_cmos_mux_submodule ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_submodule(FILE* fp,$/;" f -dump_verilog_cmos_mux_tree_structure ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_tree_structure(FILE* fp, $/;" f -dump_verilog_config_peripherals ./fpga_x2p/verilog/verilog_decoder.c /^void dump_verilog_config_peripherals(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_configuration_circuits ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_configuration_circuits(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_verilog_configuration_circuits_memory_bank ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_configuration_circuits_memory_bank(FILE* fp, $/;" f file: -dump_verilog_configuration_circuits_scan_chains ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_configuration_circuits_standalone_srams ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_configuration_circuits_standalone_srams(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_connection_box_interc ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_connection_box_mux ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_connection_box_short_interc ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_connection_box_short_interc(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_dangling_des_pb_graph_pin_interc ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_dangling_des_pb_graph_pin_interc(FILE* fp,$/;" f -dump_verilog_decoder ./fpga_x2p/verilog/verilog_decoder.c /^void dump_verilog_decoder(FILE* fp,$/;" f file: -dump_verilog_decoder_memory_bank_ports ./fpga_x2p/verilog/verilog_decoder.c /^void dump_verilog_decoder_memory_bank_ports(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_verilog_defined_channels ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_defined_channels(FILE* fp,$/;" f -dump_verilog_defined_connection_boxes ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_defined_one_channel ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_defined_one_channel(FILE* fp,$/;" f file: -dump_verilog_defined_one_connection_box ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_defined_one_grid ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_defined_one_switch_box ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_defined_switch_boxes ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_verilog_defines_preproc ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_defines_preproc(char* subckt_dir,$/;" f -dump_verilog_file_header ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_file_header(FILE* fp,$/;" f -dump_verilog_formal_verfication_top_netlist_call_top_module ./fpga_x2p/verilog/verilog_verification_top_netlist.c /^void dump_verilog_formal_verfication_top_netlist_call_top_module(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_formal_verification_mux_sram_ports_wiring ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp, $/;" f -dump_verilog_formal_verification_sram_ports ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_formal_verification_sram_ports(FILE* fp, $/;" f -dump_verilog_formal_verification_sram_ports_wiring ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_formal_verification_sram_ports_wiring(FILE* fp, $/;" f -dump_verilog_formal_verification_top_netlist ./fpga_x2p/verilog/verilog_verification_top_netlist.c /^void dump_verilog_formal_verification_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_formal_verification_top_netlist_config_bitstream ./fpga_x2p/verilog/verilog_verification_top_netlist.c /^void dump_verilog_formal_verification_top_netlist_config_bitstream(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_formal_verification_top_netlist_connect_global_ports ./fpga_x2p/verilog/verilog_verification_top_netlist.c /^void dump_verilog_formal_verification_top_netlist_connect_global_ports(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_formal_verification_top_netlist_connect_ios ./fpga_x2p/verilog/verilog_verification_top_netlist.c /^void dump_verilog_formal_verification_top_netlist_connect_ios(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_formal_verification_top_netlist_initialization ./fpga_x2p/verilog/verilog_verification_top_netlist.c /^void dump_verilog_formal_verification_top_netlist_initialization(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_formal_verification_top_netlist_internal_wires ./fpga_x2p/verilog/verilog_verification_top_netlist.c /^void dump_verilog_formal_verification_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_formal_verification_top_netlist_ports ./fpga_x2p/verilog/verilog_verification_top_netlist.c /^void dump_verilog_formal_verification_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_gate_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_gate_module(FILE* fp,$/;" f -dump_verilog_generic_port ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_generic_port(FILE* fp, $/;" f -dump_verilog_generic_port_no_repeat ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_generic_port_no_repeat(FILE* fp, $/;" f -dump_verilog_global_ports ./fpga_x2p/verilog/verilog_utils.c /^int dump_verilog_global_ports(FILE* fp, t_llist* head,$/;" f -dump_verilog_grid_block_subckt_pins ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_grid_block_subckt_pins(FILE* fp,$/;" f -dump_verilog_grid_common_port ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,$/;" f -dump_verilog_grid_pins ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_grid_pins(FILE* fp,$/;" f -dump_verilog_grid_side_pin_with_given_index ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, $/;" f -dump_verilog_grid_side_pins ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_grid_side_pins(FILE* fp,$/;" f -dump_verilog_hard_wired_gnd ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_hard_wired_gnd(FILE* fp, $/;" f -dump_verilog_hard_wired_vdd ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_hard_wired_vdd(FILE* fp, $/;" f -dump_verilog_input_blif_testbench ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_input_blif_testbench(char* circuit_name,$/;" f -dump_verilog_input_blif_testbench_call_top_module ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_input_blif_testbench_call_top_module(FILE* fp, $/;" f file: -dump_verilog_input_blif_testbench_ports ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_input_blif_testbench_ports(FILE* fp,$/;" f file: -dump_verilog_input_blif_testbench_stimuli ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_input_blif_testbench_stimuli(FILE* fp,$/;" f file: -dump_verilog_invbuf_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_invbuf_module(FILE* fp,$/;" f -dump_verilog_io_grid_block_subckt_pins ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_io_grid_block_subckt_pins(FILE* fp,$/;" f -dump_verilog_io_grid_pins ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_io_grid_pins(FILE* fp,$/;" f -dump_verilog_logic_blocks ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_mem_config_bus ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model, $/;" f -dump_verilog_mem_module_one_port_map ./fpga_x2p/verilog/verilog_utils.c /^int dump_verilog_mem_module_one_port_map(FILE* fp,$/;" f -dump_verilog_mem_module_port_map ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_mem_module_port_map(FILE* fp, $/;" f -dump_verilog_mem_sram_submodule ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_mem_sram_submodule(FILE* fp,$/;" f -dump_verilog_membank_config_module ./fpga_x2p/verilog/verilog_decoder.c /^void dump_verilog_membank_config_module(FILE* fp,$/;" f file: -dump_verilog_modelsim_autodeck ./fpga_x2p/verilog/verilog_modelsim_autodeck.c /^void dump_verilog_modelsim_autodeck(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_verilog_modelsim_proc_auto_script ./fpga_x2p/verilog/verilog_modelsim_autodeck.c /^void dump_verilog_modelsim_proc_auto_script(char* modelsim_proc_filename,$/;" f file: -dump_verilog_modelsim_proc_script ./fpga_x2p/verilog/verilog_modelsim_autodeck.c /^void dump_verilog_modelsim_proc_script(char* modelsim_proc_filename,$/;" f file: -dump_verilog_modelsim_top_auto_script ./fpga_x2p/verilog/verilog_modelsim_autodeck.c /^void dump_verilog_modelsim_top_auto_script(char* modelsim_top_auto_script_filename,$/;" f file: -dump_verilog_modelsim_top_script ./fpga_x2p/verilog/verilog_modelsim_autodeck.c /^void dump_verilog_modelsim_top_script(char* modelsim_top_script_filename,$/;" f file: -dump_verilog_mux_basis_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_mux_basis_module(FILE* fp, $/;" f -dump_verilog_mux_config_bus ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, $/;" f -dump_verilog_mux_config_bus_ports ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, $/;" f -dump_verilog_mux_mem_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_mux_mem_module(FILE* fp, $/;" f -dump_verilog_mux_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_mux_module(FILE* fp, $/;" f -dump_verilog_mux_one_basis_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_mux_one_basis_module(FILE* fp, $/;" f -dump_verilog_mux_sram_one_local_outport ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_mux_sram_one_local_outport(FILE* fp, $/;" f -dump_verilog_mux_sram_one_outport ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_mux_sram_one_outport(FILE* fp, $/;" f -dump_verilog_mux_sram_submodule ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_one_clb2clb_direct ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_one_clb2clb_direct(FILE* fp, $/;" f file: -dump_verilog_one_sb_chan_pin ./fpga_x2p/verilog/verilog_tcl_utils.c /^void dump_verilog_one_sb_chan_pin(FILE* fp, $/;" f -dump_verilog_one_sb_routing_pin ./fpga_x2p/verilog/verilog_tcl_utils.c /^void dump_verilog_one_sb_routing_pin(FILE* fp,$/;" f -dump_verilog_one_sb_wire_segemental_report_timing ./fpga_x2p/verilog/verilog_report_timing.c /^void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp,$/;" f -dump_verilog_passgate_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_passgate_module(FILE* fp,$/;" f -dump_verilog_pb_generic_primitive ./fpga_x2p/verilog/verilog_primitives.c /^void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_pb_graph_interc ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_pb_graph_pin_interc ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_pb_graph_port_interc ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_pb_graph_primitive_node ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_pb_graph_primitive_node(FILE* fp,$/;" f -dump_verilog_pb_primitive_lut ./fpga_x2p/verilog/verilog_primitives.c /^void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_pb_primitive_verilog_model ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_pb_type_bus_ports ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_pb_type_bus_ports(FILE* fp,$/;" f -dump_verilog_pb_type_ports ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_pb_type_ports(FILE* fp,$/;" f -dump_verilog_phy_pb_graph_node_rec ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_physical_block ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_physical_grid_blocks ./fpga_x2p/verilog/verilog_pbtypes.c /^void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_preproc ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_preproc(FILE* fp, $/;" f -dump_verilog_random_testbench_call_top_module ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^void dump_verilog_random_testbench_call_top_module(FILE* fp,$/;" f file: -dump_verilog_random_top_testbench ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^void dump_verilog_random_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_reserved_sram_one_port ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_reserved_sram_one_port(FILE* fp, $/;" f -dump_verilog_reserved_sram_ports ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_reserved_sram_ports(FILE* fp, $/;" f -dump_verilog_routing_chan_subckt ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_routing_connection_box_subckt ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_routing_resources ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_routing_switch_box_subckt ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_rram_mux_multilevel_structure ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_rram_mux_multilevel_structure(FILE* fp, $/;" f -dump_verilog_rram_mux_one_basis_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_rram_mux_one_basis_module(FILE* fp, $/;" f -dump_verilog_rram_mux_one_basis_module_structural ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp, $/;" f file: -dump_verilog_rram_mux_onelevel_structure ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_rram_mux_onelevel_structure(FILE* fp, $/;" f -dump_verilog_rram_mux_submodule ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_rram_mux_submodule(FILE* fp,$/;" f -dump_verilog_rram_mux_tree_structure ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_rram_mux_tree_structure(FILE* fp, $/;" f -dump_verilog_sb_through_routing_pins ./fpga_x2p/verilog/verilog_report_timing.c /^void dump_verilog_sb_through_routing_pins(FILE* fp,$/;" f -dump_verilog_scan_chain_config_module ./fpga_x2p/verilog/verilog_decoder.c /^void dump_verilog_scan_chain_config_module(FILE* fp,$/;" f file: -dump_verilog_scff_config_bus ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_scff_config_bus(FILE* fp,$/;" f -dump_verilog_sdc_file_header ./fpga_x2p/verilog/verilog_tcl_utils.c /^void dump_verilog_sdc_file_header(FILE* fp,$/;" f -dump_verilog_simulation_preproc ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_simulation_preproc(char* subckt_dir,$/;" f -dump_verilog_sram_config_bus_internal_wires ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_verilog_sram_local_ports ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_sram_local_ports(FILE* fp, $/;" f -dump_verilog_sram_one_local_outport ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_sram_one_local_outport(FILE* fp, $/;" f -dump_verilog_sram_one_outport ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_sram_one_outport(FILE* fp, $/;" f -dump_verilog_sram_one_port ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_sram_one_port(FILE* fp, $/;" f -dump_verilog_sram_outports ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_sram_outports(FILE* fp, $/;" f -dump_verilog_sram_ports ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_sram_ports(FILE* fp, $/;" f -dump_verilog_sram_submodule ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_standalone_sram_config_module ./fpga_x2p/verilog/verilog_decoder.c /^void dump_verilog_standalone_sram_config_module(FILE* fp,$/;" f file: -dump_verilog_subckt_header_file ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_subckt_header_file(t_llist* subckt_llist_head,$/;" f -dump_verilog_submodule_essentials ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_essentials(char* verilog_dir, char* submodule_dir,$/;" f -dump_verilog_submodule_luts ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_luts(char* verilog_dir,$/;" f -dump_verilog_submodule_memories ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_submodule_muxes ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_submodule_one_lut ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_one_lut(FILE* fp, $/;" f -dump_verilog_submodule_one_mem ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_one_mem(FILE* fp, $/;" f -dump_verilog_submodule_signal_init ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_signal_init(FILE* fp,$/;" f -dump_verilog_submodule_templates ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_verilog_submodule_timing ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_timing(FILE* fp,$/;" f -dump_verilog_submodule_wires ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodule_wires(char* verilog_dir,$/;" f -dump_verilog_submodules ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_switch_box_chan_port ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_switch_box_chan_port(FILE* fp,$/;" f -dump_verilog_switch_box_interc ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_switch_box_mux ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_switch_box_short_interc ./fpga_x2p/verilog/verilog_routing.c /^void dump_verilog_switch_box_short_interc(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_timeout_and_vcd ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^void dump_verilog_timeout_and_vcd(FILE * fp,$/;" f file: -dump_verilog_timeout_and_vcd ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^void dump_verilog_timeout_and_vcd(FILE * fp,$/;" f file: -dump_verilog_top_auto_testbench_call_benchmark ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^void dump_verilog_top_auto_testbench_call_benchmark(FILE* fp, $/;" f file: -dump_verilog_top_auto_testbench_check ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^void dump_verilog_top_auto_testbench_check(FILE* fp){$/;" f file: -dump_verilog_top_auto_testbench_ports ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^void dump_verilog_top_auto_testbench_ports(FILE* fp,$/;" f file: -dump_verilog_top_module_ports ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_verilog_top_netlist_internal_wires ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_verilog_top_netlist_memory_bank_internal_wires ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_top_netlist_memory_bank_internal_wires(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_netlist_ports ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_top_netlist_scan_chain_internal_wires ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_netlist_scan_chain_ports ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_verilog_top_netlist_scan_chain_ports(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_random_stimuli ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^void dump_verilog_top_random_stimuli(FILE* fp,$/;" f file: -dump_verilog_top_random_testbench_call_benchmark ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^void dump_verilog_top_random_testbench_call_benchmark(FILE* fp, $/;" f file: -dump_verilog_top_random_testbench_check ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^void dump_verilog_top_random_testbench_check(FILE* fp){$/;" f file: -dump_verilog_top_random_testbench_ports ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^void dump_verilog_top_random_testbench_ports(FILE* fp,$/;" f file: -dump_verilog_top_testbench ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_top_testbench_call_top_module ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -dump_verilog_top_testbench_conf_bits_serial ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_conf_bits_serial(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_find_num_config_clock_cycles ./fpga_x2p/verilog/verilog_top_testbench.c /^int dump_verilog_top_testbench_find_num_config_clock_cycles(t_sram_orgz_info* cur_sram_orgz_info,$/;" f file: -dump_verilog_top_testbench_global_ports ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_global_ports(FILE* fp, t_llist* head,$/;" f -dump_verilog_top_testbench_global_ports_stimuli ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_global_ports_stimuli(FILE* fp, t_llist* head) {$/;" f -dump_verilog_top_testbench_memory_bank_conf_bits_serial ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_memory_bank_conf_bits_serial(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_one_conf_bit_serial ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_one_conf_bit_serial(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_ports ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_ports(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_rram_memory_bank_conf_bits_serial ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_rram_memory_bank_conf_bits_serial(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_scan_chain_conf_bits_serial ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_scan_chain_conf_bits_serial(FILE* fp, $/;" f file: -dump_verilog_top_testbench_sram_memory_bank_conf_bits_serial ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_sram_memory_bank_conf_bits_serial(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_stimuli ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_stimuli(t_sram_orgz_info* cur_sram_orgz_info, $/;" f -dump_verilog_top_testbench_stimuli_serial_version ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_stimuli_serial_version(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_stimuli_serial_version_tasks ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_stimuli_serial_version_tasks(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_stimuli_serial_version_tasks_scan_chain ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_stimuli_serial_version_tasks_scan_chain(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: -dump_verilog_top_testbench_wire_one_global_port_stimuli ./fpga_x2p/verilog/verilog_top_testbench.c /^void dump_verilog_top_testbench_wire_one_global_port_stimuli(FILE* fp, t_spice_model_port* cur_global_port, $/;" f file: -dump_verilog_toplevel_one_grid_side_pin_with_given_index ./fpga_x2p/verilog/verilog_utils.c /^void dump_verilog_toplevel_one_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, $/;" f -dump_verilog_wire_module ./fpga_x2p/verilog/verilog_submodules.c /^void dump_verilog_wire_module(FILE* fp,$/;" f -dumped_num_conf_bits ./fpga_x2p/bitstream/fpga_bitstream.c /^static int dumped_num_conf_bits = 0;$/;" v file: -e_OptionArgToken ./base/OptionTokens.h /^enum e_OptionArgToken {$/;" g -e_OptionBaseToken ./base/OptionTokens.h /^enum e_OptionBaseToken {$/;" g -e_base_cost_type ./base/vpr_types.h /^enum e_base_cost_type {$/;" g -e_block_pack_status ./base/vpr_types.h /^enum e_block_pack_status {$/;" g -e_cluster_seed ./base/vpr_types.h /^enum e_cluster_seed {$/;" g -e_cmd_category ./fpga_x2p/shell/shell_types.h /^enum e_cmd_category {$/;" g -e_cost_indices ./base/vpr_types.h /^enum e_cost_indices {$/;" g -e_detailed_routing_stages ./pack/cluster.c /^enum e_detailed_routing_stages {$/;" g file: -e_dir_err ./fpga_x2p/base/fpga_x2p_utils.c /^enum e_dir_err {$/;" g file: -e_direction ./base/vpr_types.h /^enum e_direction {$/;" g -e_draw_mode ./base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/;" g -e_draw_net_type ./base/draw.c /^enum e_draw_net_type {$/;" g file: -e_draw_rr_toggle ./base/draw.c /^enum e_draw_rr_toggle {$/;" g file: -e_drivers ./base/vpr_types.h /^enum e_drivers {$/;" g -e_dump_verilog_port_type ./fpga_x2p/verilog/verilog_global.h /^enum e_dump_verilog_port_type {$/;" g -e_echo_files ./base/ReadOptions.h /^enum e_echo_files {$/;" g -e_edge_dir ./base/draw.c /^enum e_edge_dir {$/;" g file: -e_feasibility ./pack/cluster.c /^enum e_feasibility {$/;" g file: -e_gain_type ./pack/cluster.c /^enum e_gain_type {$/;" g file: -e_gain_update ./pack/cluster.c /^enum e_gain_update {$/;" g file: -e_graph_type ./route/rr_graph.h /^enum e_graph_type {$/;" g -e_measure_type ./fpga_x2p/spice/spice_utils.h /^enum e_measure_type {$/;" g -e_net_relation_to_clustered_block ./pack/cluster.c /^enum e_net_relation_to_clustered_block {$/;" g file: -e_operation ./base/vpr_types.h /^enum e_operation {$/;" g -e_output_files ./base/ReadOptions.h /^enum e_output_files {$/;" g -e_pack_pattern_molecule_type ./base/vpr_types.h /^enum e_pack_pattern_molecule_type {$/;" g -e_packer_algorithm ./base/vpr_types.h /^enum e_packer_algorithm {$/;" g -e_pad_loc_type ./base/vpr_types.h /^enum e_pad_loc_type {$/;" g -e_place_algorithm ./base/vpr_types.h /^enum e_place_algorithm {$/;" g -e_power_breakdown_entry_type ./power/power.c /^} e_power_breakdown_entry_type;$/;" t typeref:enum:__anon8 file: -e_power_callib_component ./power/power_callibrate.h /^} e_power_callib_component;$/;" t typeref:enum:__anon12 -e_power_component_type ./power/power_components.h /^} e_power_component_type;$/;" t typeref:enum:__anon13 -e_power_log_type ./power/power.h /^} e_power_log_type;$/;" t typeref:enum:__anon10 -e_power_ret_code ./power/power.h /^} e_power_ret_code;$/;" t typeref:enum:__anon9 -e_removal_policy ./pack/cluster.c /^enum e_removal_policy {$/;" g file: -e_route_type ./base/vpr_types.h /^enum e_route_type {$/;" g -e_router_algorithm ./base/vpr_types.h /^enum e_router_algorithm {$/;" g -e_rr_type ./base/vpr_types.h /^typedef enum e_rr_type {$/;" g -e_tnode_type ./base/vpr_types.h /^} e_tnode_type;$/;" t typeref:enum:__anon7 -e_token_type ./util/token.h /^enum e_token_type {$/;" g -e_tx_type ./power/power.h /^} e_tx_type;$/;" t typeref:enum:__anon11 -e_verilog_tb_type ./fpga_x2p/verilog/verilog_global.h /^enum e_verilog_tb_type {$/;" g -echoFileEnabled ./base/ReadOptions.c /^static boolean *echoFileEnabled = NULL;$/;" v file: -echoFileNames ./base/ReadOptions.c /^static char **echoFileNames = NULL;$/;" v file: -echo_input ./base/read_blif.c /^void echo_input(char *blif_file, char *echo_file, t_model *library_models) {$/;" f -echo_pb_graph ./pack/pb_type_graph.c /^void echo_pb_graph(char * filename) {$/;" f -echo_pb_pins ./pack/pb_type_graph.c /^static void echo_pb_pins(INP t_pb_graph_pin **pb_graph_pins, INP int num_ports,$/;" f file: -echo_pb_rec ./pack/pb_type_graph.c /^static void echo_pb_rec(const INP t_pb_graph_node *pb_graph_node, INP int level,$/;" f file: -edge ./route/rr_graph_util.h /^ int edge;$/;" m struct:s_linked_edge -edges ./base/vpr_types.h /^ int *edges;$/;" m struct:s_rr_node -edges_head ./pack/pb_type_graph.c /^static struct s_linked_vptr *edges_head;$/;" v typeref:struct:s_linked_vptr file: -emit ./timing/slre.c /^static void emit(struct slre *r, int code) {$/;" f file: -empty_heap ./route/route_common.c /^void empty_heap(void) {$/;" f -empty_rr_graph_heap ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void empty_rr_graph_heap(t_rr_graph* local_rr_graph) {$/;" f -enable_or_disable_button ./base/graphics.c /^void enable_or_disable_button (int ibutton, bool enabled) {$/;" f -enable_or_disable_button ./base/graphics.c /^void enable_or_disable_button(int ibutton, bool enabled) { }$/;" f -enable_timing_computations ./base/vpr_types.h /^ boolean enable_timing_computations;$/;" m struct:s_placer_opts -enabled ./base/graphics.c /^ bool enabled;$/;" m struct:__anon4 file: -encode_decoder_addr ./fpga_x2p/bitstream/fpga_bitstream.c /^void encode_decoder_addr(int input,$/;" f -endlines ./base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: -entries ./power/PowerSpicedComponent.h /^ std::vector entries;$/;" m class:PowerSpicedComponent -entries ./power/PowerSpicedComponent.h /^ std::vector entries;$/;" m class:PowerCallibInputs -error_counter ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^static char* error_counter = "nb_error";$/;" v file: -error_counter ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* error_counter = "nb_error";$/;" v file: -error_no_match ./timing/slre.c /^static const char *error_no_match = "No match";$/;" v file: -error_string ./timing/slre.c /^ const char *error_string; \/\/ Error string$/;" m struct:slre file: -essentials_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* essentials_verilog_file_name = "inv_buf_passgate.v";$/;" v -esti_distance_num_seg_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^float esti_distance_num_seg_delay(int distance,$/;" f -esti_one_segment_net_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^float esti_one_segment_net_delay(int distance, t_segment_inf segment_inf) {$/;" f -esti_pin2pin_one_net_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^float esti_pin2pin_one_net_delay(t_block src_blk,$/;" f -esti_pin_chan_coordinate ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void esti_pin_chan_coordinate(int* pin_x, int* pin_y,$/;" f -estimate_post_place_one_net_sink_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^float estimate_post_place_one_net_sink_delay(int net_index, $/;" f -event_loop ./base/graphics.c /^event_loop (void (*act_on_mousebutton)(float x, float y), $/;" f -event_loop ./base/graphics.c /^void event_loop (void (*act_on_mousebutton) (float x, float y),$/;" f -exact ./timing/slre.c /^static void exact(struct slre *r, const char **re) {$/;" f file: -exact_one_char ./timing/slre.c /^static void exact_one_char(struct slre *r, int ch) {$/;" f file: -execute ./fpga_x2p/shell/shell_types.h /^ void (*execute)(t_shell_env*, t_opt_info*);$/;" m struct:s_shell_cmd -exists_free_primitive_for_logical_block ./pack/cluster_placement.c /^boolean exists_free_primitive_for_logical_block($/;" f -exit_crit ./place/place.c /^static int exit_crit(float t, float cost,$/;" f file: -exit_opts ./fpga_x2p/shell/cmd_exit.h /^t_opt_info exit_opts[] = {$/;" v -exit_t ./base/vpr_types.h /^ float exit_t;$/;" m struct:s_annealing_sched -expand_forced_pack_molecule_placement ./pack/cluster_placement.c /^static boolean expand_forced_pack_molecule_placement($/;" f file: -expand_pack_molecule_pin_edge ./pack/cluster_placement.c /^static t_pb_graph_pin *expand_pack_molecule_pin_edge(INP int pattern_id,$/;" f file: -expand_pb_graph_node_and_load_output_to_input_connections ./pack/cluster_feasibility_filter.c /^static void expand_pb_graph_node_and_load_output_to_input_connections($/;" f file: -expand_pb_graph_node_and_load_pin_class_by_depth ./pack/cluster_feasibility_filter.c /^static void expand_pb_graph_node_and_load_pin_class_by_depth($/;" f file: -expand_routing_trace ./base/vpr_api.c /^static t_trace *expand_routing_trace(t_trace *trace, int ivpack_net) {$/;" f file: -expected_lowest_cost_primitive ./base/vpr_types.h /^ t_pb_graph_node *expected_lowest_cost_primitive; \/* predicted ideal primitive to use for this logical block *\/$/;" m struct:s_logical_block -ext_clock_rr_node_index ./pack/cluster_legality.c /^ ext_clock_rr_node_index, max_ext_index;$/;" v file: -ext_input_rr_node_index ./pack/cluster_legality.c /^static int ext_input_rr_node_index, ext_output_rr_node_index,$/;" v file: -ext_output_rr_node_index ./pack/cluster_legality.c /^static int ext_input_rr_node_index, ext_output_rr_node_index,$/;" v file: -f_blk_pin_from_port_pin ./util/vpr_utils.c /^static int *** f_blk_pin_from_port_pin = NULL;$/;" v file: -f_direct_type_from_blk_pin ./place/place_macro.c /^static int ** f_direct_type_from_blk_pin = NULL;$/;" v file: -f_idirect_from_blk_pin ./place/place_macro.c /^static int ** f_idirect_from_blk_pin = NULL;$/;" v file: -f_imacro_from_iblk ./place/place_macro.c /^static int * f_imacro_from_iblk = NULL;$/;" v file: -f_net_to_driver_tnode ./timing/path_delay.c /^static int * f_net_to_driver_tnode; $/;" v file: -f_port_from_blk_pin ./util/vpr_utils.c /^static int ** f_port_from_blk_pin = NULL;$/;" v file: -f_port_pin_from_blk_pin ./util/vpr_utils.c /^static int ** f_port_pin_from_blk_pin = NULL;$/;" v file: -f_timing_stats ./timing/path_delay.c /^static t_timing_stats * f_timing_stats = NULL; \/* Critical path delay and worst-case slack per constraint. *\/$/;" v file: -factor ./power/PowerSpicedComponent.h /^ float factor;$/;" m class:PowerCallibSize -falling_edge ./timing/read_sdc.c /^ float falling_edge;$/;" m struct:s_sdc_clock file: -fan_in ./base/vpr_types.h /^ short fan_in;$/;" m struct:s_rr_node -fanout ./base/vpr_types.h /^ int fanout;$/;" m struct:s_clock -fc ./base/place_and_route.h /^ int fc; \/* at this fc *\/$/;" m struct:s_fmap_cell -fc_constraints ./base/vpr_types.h /^ t_override_constraint * fc_constraints; \/* [0..num_fc_constraints - 1] *\/$/;" m struct:s_timing_constraints -fc_in ./base/vpr_types.h /^ int fc_in;$/;" m struct:s_cb -fc_out ./base/vpr_types.h /^ int fc_out;$/;" m struct:s_sb -fclose_wire_L_file_handler_in_llist ./fpga_x2p/verilog/verilog_report_timing.c /^void fclose_wire_L_file_handler_in_llist(t_llist* rr_path_cnt) {$/;" f -fcn ./base/graphics.c /^ void (*fcn) (void (*drawscreen) (void));$/;" m struct:__anon4 file: -feasible_blocks ./base/vpr_types.h /^ struct s_pack_molecule **feasible_blocks;$/;" m struct:s_pb_stats typeref:struct:s_pb_stats::s_pack_molecule -feasible_routing ./route/route_common.c /^boolean feasible_routing(void) {$/;" f -feasible_routing_rr_graph ./fpga_x2p/router/fpga_x2p_router.c /^boolean feasible_routing_rr_graph(t_rr_graph* local_rr_graph, $/;" f -ff_constraints ./base/vpr_types.h /^ t_override_constraint * ff_constraints; \/* [0..num_ff_constraints - 1] array of such constraints *\/$/;" m struct:s_timing_constraints -file_handler ./fpga_x2p/verilog/verilog_report_timing.c /^ FILE* file_handler;$/;" m struct:s_wireL_cnt file: -file_line_number ./base/vpr_types.h /^ int file_line_number; \/* line in the SDC file I\/O was constrained on - used for error reporting *\/$/;" m struct:s_io -file_line_number ./base/vpr_types.h /^ int file_line_number; \/* line in the SDC file clock was constrained on - used for error reporting *\/$/;" m struct:s_override_constraint -fillarc ./base/graphics.c /^fillarc (float xc, float yc, float rad, float startang, float angextent) {$/;" f -fillarc ./base/graphics.c /^void fillarc (float xcen, float ycen, float rad, float startang,$/;" f -fillcurve ./base/graphics.c /^void fillcurve(t_point *points, int npoints) { }$/;" f -fillcurve ./base/graphics.c /^void fillcurve(t_point *points,$/;" f -fillellipticarc ./base/graphics.c /^fillellipticarc (float xc, float yc, float radx, float rady, float startang, $/;" f -fillellipticarc ./base/graphics.c /^void fillellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent) { }$/;" f -fillpoly ./base/graphics.c /^fillpoly (t_point *points, int npoints) $/;" f -fillpoly ./base/graphics.c /^void fillpoly (t_point *points, int npoints) { }$/;" f -fillrect ./base/graphics.c /^fillrect (float x1, float y1, float x2, float y2) $/;" f -fillrect ./base/graphics.c /^void fillrect (float x1, float y1, float x2, float y2) { }$/;" f -find_affected_blocks ./place/place.c /^static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to) {$/;" f file: -find_affected_nets ./place/place.c /^static int find_affected_nets(int *nets_to_update) {$/;" f file: -find_all_the_macro ./place/place_macro.c /^static void find_all_the_macro (int * num_of_macro, int * pl_macro_member_blk_num_of_this_blk, $/;" f file: -find_bl_wl_ports_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^void find_bl_wl_ports_spice_model(t_spice_model* cur_spice_model,$/;" f -find_blb_wlb_ports_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^void find_blb_wlb_ports_spice_model(t_spice_model* cur_spice_model,$/;" f -find_blk_net_pin_side ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int find_blk_net_pin_side(t_block target_blk,$/;" f -find_blk_net_pin_sides ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void find_blk_net_pin_sides(t_block target_blk,$/;" f -find_blk_net_type_pins ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void find_blk_net_type_pins(int n_blks, t_block* blk,$/;" f -find_cc_constraint ./timing/read_sdc.c /^static int find_cc_constraint(char * source_clock_name, char * sink_clock_name) {$/;" f file: -find_cf_constraint ./timing/path_delay.c /^static int find_cf_constraint(char * source_clock_name, char * sink_ff_name) {$/;" f file: -find_clock ./timing/path_delay.c /^static int find_clock(char * net_name) {$/;" f file: -find_clock_name ./base/verilog_writer.c /^char *find_clock_name(void)$/;" f -find_connected_primitives_downhill ./base/verilog_writer.c /^conn_list *find_connected_primitives_downhill(int block_num , t_pb *pb , conn_list*list)$/;" f -find_constrained_clock ./timing/read_sdc.c /^static int find_constrained_clock(char * ptr) {$/;" f file: -find_drive_rr_nodes_switch_box ./fpga_x2p/base/fpga_x2p_utils.c /^void find_drive_rr_nodes_switch_box(int switch_box_x,$/;" f -find_expansion_edge_of_pattern ./pack/prepack.c /^static t_pb_graph_edge * find_expansion_edge_of_pattern(INP int pattern_index,$/;" f file: -find_fanin_rr_node ./pack/output_blif.c /^static int find_fanin_rr_node(t_pb *cur_pb, enum PORTS type, int rr_node_index) {$/;" f file: -find_ff_clock_tnode ./timing/path_delay.c /^static t_tnode * find_ff_clock_tnode(int inode, boolean is_prepacked) {$/;" f file: -find_grid_mapped_logical_block ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int find_grid_mapped_logical_block(int x, int y,$/;" f -find_index ./base/verilog_writer.c /^int find_index(char *row,int inputs)\/*returns the index of the 64bit truth table that this temporary truth table row corresponds to*\/$/;" f -find_input ./timing/path_delay.c /^static int find_input(char * net_name) {$/;" f file: -find_interc_des_pb_graph_pin ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void find_interc_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin,$/;" f -find_interc_fan_in_des_pb_graph_pin ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin,$/;" f -find_iopad_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_model* find_iopad_spice_model(int num_spice_model,$/;" f -find_label_of_track ./route/rr_graph2.c /^static int find_label_of_track(int *wire_mux_on_track, int num_wire_muxes,$/;" f file: -find_matched_block_id_for_one_grid ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int find_matched_block_id_for_one_grid(int x, int y) {$/;" f -find_mosfet_tech_lib ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib,$/;" f -find_name_matched_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_model* find_name_matched_spice_model(char* spice_model_name,$/;" f -find_new_root_atom_for_chain ./pack/prepack.c /^static int find_new_root_atom_for_chain(INP int block_index, INP t_pack_patterns *list_of_pack_pattern) {$/;" f file: -find_number_of_inputs ./base/verilog_writer.c /^int find_number_of_inputs(t_pb *pb)$/;" f -find_output ./timing/path_delay.c /^static int find_output(char * net_name) {$/;" f file: -find_parent_pb_type_child_index ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int find_parent_pb_type_child_index(t_pb_type* parent_pb_type,$/;" f -find_path_id_between_pb_rr_nodes ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph,$/;" f -find_path_id_prev_rr_node ./fpga_x2p/base/fpga_x2p_utils.c /^int find_path_id_prev_rr_node(int num_drive_rr_nodes,$/;" f -find_pb_graph_pin_in_edges_interc_spice_model ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_spice_model* find_pb_graph_pin_in_edges_interc_spice_model(t_pb_graph_pin pb_graph_pin) {$/;" f -find_pb_graph_pin_in_edges_interc_type ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) {$/;" f -find_pb_graph_pin_in_edges_interc_verilog_model ./fpga_x2p/verilog/verilog_pbtypes.c /^t_spice_model* find_pb_graph_pin_in_edges_interc_verilog_model(t_pb_graph_pin pb_graph_pin) {$/;" f -find_pb_mapped_logical_block_rec ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int find_pb_mapped_logical_block_rec(t_pb* cur_pb,$/;" f -find_pb_type_idle_mode_index ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int find_pb_type_idle_mode_index(t_pb_type cur_pb_type) {$/;" f -find_pb_type_physical_mode_index ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int find_pb_type_physical_mode_index(t_pb_type cur_pb_type) {$/;" f -find_pb_type_port_match_spice_model_port ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type,$/;" f -find_pb_type_ports_match_spice_model_port_type ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type,$/;" f -find_prev_rr_nodes_with_src ./fpga_x2p/base/fpga_x2p_utils.c /^void find_prev_rr_nodes_with_src(t_rr_node* src_rr_node,$/;" f -find_rr_nodes_ipin_driver_switch ./route/rr_graph_opincb.c /^void find_rr_nodes_ipin_driver_switch() {$/;" f file: -find_spice_model_config_done_ports ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_model_port** find_spice_model_config_done_ports(t_spice_model* spice_model,$/;" f -find_spice_model_port_by_name ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_model_port* find_spice_model_port_by_name(t_spice_model* cur_spice_model,$/;" f -find_spice_model_ports ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_model_port** find_spice_model_ports(t_spice_model* spice_model,$/;" f -find_spice_mux_arch_special_basis_size ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int find_spice_mux_arch_special_basis_size(t_spice_mux_arch spice_mux_arch) {$/;" f -find_spice_testbench_pb_pin_mux_load_inv_size ./fpga_x2p/spice/spice_utils.c /^float find_spice_testbench_pb_pin_mux_load_inv_size(t_spice_model* fan_out_spice_model) {$/;" f -find_spice_testbench_rr_mux_load_inv_size ./fpga_x2p/spice/spice_utils.c /^float find_spice_testbench_rr_mux_load_inv_size(t_rr_node* load_rr_node,$/;" f -find_src_pb_pin_to_rr_nodes ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void find_src_pb_pin_to_rr_nodes(t_pb* src_pb,$/;" f -find_tnode_net_name ./timing/path_delay.c /^static char * find_tnode_net_name(int inode, boolean is_prepacked) {$/;" f file: -find_to ./place/place.c /^static boolean find_to(int x_from, int y_from, t_type_ptr type, float rlim, int *x_to, int *y_to) {$/;" f file: -find_type_col ./base/SetupGrid.c /^static t_type_ptr find_type_col(INP int x) {$/;" f file: -findfontsize ./base/graphics.c /^int findfontsize(float ymax) { }$/;" f -findfontsize ./base/graphics.c /^int findfontsize(float ymax) {$/;" f -first_iter_pres_fac ./base/ReadOptions.h /^ float first_iter_pres_fac;$/;" m struct:s_options -first_iter_pres_fac ./base/vpr_types.h /^ float first_iter_pres_fac;$/;" m struct:s_router_opts -fix_name ./base/verilog_writer.c /^char *fix_name(char *name)$/;" f -fixed_channel_width ./base/vpr_types.h /^ int fixed_channel_width;$/;" m struct:s_router_opts -fixup_branch ./timing/slre.c /^static void fixup_branch(struct slre *r, int fixup) {$/;" f file: -flag_postfix ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* flag_postfix = "_flag";$/;" v file: -flush_intermediate_queues ./pack/cluster_placement.c /^static void flush_intermediate_queues($/;" f file: -flushinput ./base/graphics.c /^flushinput (void) $/;" f -flushinput ./base/graphics.c /^void flushinput (void) { }$/;" f -font_info ./base/graphics.c /^static LOGFONT *font_info[MAX_FONT_SIZE+1]; \/* Data for each size *\/$/;" v file: -font_info ./base/graphics.c /^static XFontStruct *font_info[MAX_FONT_SIZE+1]; \/* Data for each size *\/$/;" v file: -font_is_loaded ./base/graphics.c /^static bool font_is_loaded[MAX_FONT_SIZE + 1];$/;" v file: -force_post_place_route_cb_input_pins ./pack/cluster_legality.c /^void force_post_place_route_cb_input_pins(int iblock) {$/;" f -force_setcolor ./base/graphics.c /^static void force_setcolor (int cindex) $/;" f file: -force_setfontsize ./base/graphics.c /^static void force_setfontsize (int pointsize) $/;" f file: -force_setlinestyle ./base/graphics.c /^static void force_setlinestyle (int linestyle) $/;" f file: -force_setlinewidth ./base/graphics.c /^static void force_setlinewidth (int linewidth) $/;" f file: -formal_random_top_tb_postfix ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* formal_random_top_tb_postfix = "_top_formal_verification_random_tb";$/;" v file: -formal_simulation_flag ./fpga_x2p/verilog/verilog_global.c /^char* formal_simulation_flag = "FORMAL_SIMULATION"; \/\/ the flag to enable formal functional verification$/;" v -formal_verification_top_module_port_postfix ./fpga_x2p/verilog/verilog_global.c /^char* formal_verification_top_module_port_postfix = "_fm";$/;" v -formal_verification_top_module_postfix ./fpga_x2p/verilog/verilog_global.c /^char* formal_verification_top_module_postfix = "_top_formal_verification";$/;" v -formal_verification_top_module_uut_name ./fpga_x2p/verilog/verilog_global.c /^char* formal_verification_top_module_uut_name = "U0_formal_verification";$/;" v -formal_verification_top_postfix ./fpga_x2p/verilog/verilog_global.c /^char* formal_verification_top_postfix = "_top_formal_verification";$/;" v -formal_verification_verilog_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* formal_verification_verilog_file_postfix = "_top_formal_verification.v"; $/;" v -formality_include_user_defined_verilog_netlists ./fpga_x2p/verilog/verilog_formality_autodeck.c /^void formality_include_user_defined_verilog_netlists(FILE* fp,$/;" f file: -formality_script_name_postfix ./fpga_x2p/verilog/verilog_global.c /^char* formality_script_name_postfix = "_formality_script.tcl";$/;" v -format_dir_path ./fpga_x2p/base/fpga_x2p_utils.c /^char* format_dir_path(char* dir_path) {$/;" f -format_spice_node_prefix ./fpga_x2p/base/fpga_x2p_utils.c /^char* format_spice_node_prefix(char* spice_node_prefix) {$/;" f -format_verilog_node_prefix ./fpga_x2p/verilog/verilog_utils.c /^char* format_verilog_node_prefix(char* verilog_node_prefix) {$/;" f -forward_expand_pack_pattern_from_edge ./pack/prepack.c /^static void forward_expand_pack_pattern_from_edge($/;" f file: -forward_infer_pattern ./pack/prepack.c /^static void forward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin) {$/;" f file: -forward_weight ./base/vpr_types.h /^ float forward_weight, backward_weight; \/* Weightings of the importance of paths $/;" m struct:s_tnode -found_connectivity ./base/verilog_writer.h /^typedef struct found_connectivity{$/;" s -found_pins ./base/verilog_writer.h /^typedef struct found_pins{$/;" s -fpga_bitstream_file ./base/ReadOptions.h /^ char* fpga_bitstream_file;$/;" m struct:s_options -fpga_bitstream_opts ./fpga_x2p/shell/cmd_fpga_bitstream.h /^t_opt_info fpga_bitstream_opts[] = {$/;" v -fpga_spice_atof_2D ./fpga_x2p/base/fpga_x2p_timing_utils.c /^float** fpga_spice_atof_2D(int num_in_port, int num_out_port, char* str) {$/;" f -fpga_spice_bitstream_logic_block_log_file_postfix ./fpga_x2p/base/fpga_x2p_globals.c /^char* fpga_spice_bitstream_logic_block_log_file_postfix = "_lb_bitstream.log";$/;" v -fpga_spice_bitstream_output_file_postfix ./fpga_x2p/base/fpga_x2p_globals.c /^char* fpga_spice_bitstream_output_file_postfix = ".bitstream";$/;" v -fpga_spice_bitstream_routing_log_file_postfix ./fpga_x2p/base/fpga_x2p_globals.c /^char* fpga_spice_bitstream_routing_log_file_postfix = "_routing_bitstream.log";$/;" v -fpga_spice_create_one_subckt_filename ./fpga_x2p/base/fpga_x2p_utils.c /^char* fpga_spice_create_one_subckt_filename(char* file_name_prefix,$/;" f -fpga_spice_generate_bitstream_connection_box_interc ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_connection_box_interc(FILE* fp,$/;" f file: -fpga_spice_generate_bitstream_connection_box_mux ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_connection_box_mux(FILE* fp,$/;" f file: -fpga_spice_generate_bitstream_connection_box_short_interc ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_connection_box_short_interc(t_cb* cur_cb_info,$/;" f file: -fpga_spice_generate_bitstream_logic_block ./fpga_x2p/bitstream/fpga_bitstream_pbtypes.c /^void fpga_spice_generate_bitstream_logic_block(char* lb_bitstream_log_file_path,$/;" f -fpga_spice_generate_bitstream_one_physical_block ./fpga_x2p/bitstream/fpga_bitstream_pbtypes.c /^void fpga_spice_generate_bitstream_one_physical_block(FILE* fp,$/;" f -fpga_spice_generate_bitstream_pb_generic_primitive ./fpga_x2p/bitstream/fpga_bitstream_primitives.c /^void fpga_spice_generate_bitstream_pb_generic_primitive(FILE* fp,$/;" f -fpga_spice_generate_bitstream_pb_graph_interc ./fpga_x2p/bitstream/fpga_bitstream_pbtypes.c /^void fpga_spice_generate_bitstream_pb_graph_interc(FILE* fp,$/;" f -fpga_spice_generate_bitstream_pb_graph_pin_interc ./fpga_x2p/bitstream/fpga_bitstream_pbtypes.c /^void fpga_spice_generate_bitstream_pb_graph_pin_interc(FILE* fp,$/;" f -fpga_spice_generate_bitstream_pb_graph_port_interc ./fpga_x2p/bitstream/fpga_bitstream_pbtypes.c /^void fpga_spice_generate_bitstream_pb_graph_port_interc(FILE* fp,$/;" f -fpga_spice_generate_bitstream_pb_primitive ./fpga_x2p/bitstream/fpga_bitstream_pbtypes.c /^void fpga_spice_generate_bitstream_pb_primitive(FILE* fp,$/;" f -fpga_spice_generate_bitstream_pb_primitive_lut ./fpga_x2p/bitstream/fpga_bitstream_primitives.c /^void fpga_spice_generate_bitstream_pb_primitive_lut(FILE* fp,$/;" f -fpga_spice_generate_bitstream_phy_pb_graph_node_rec ./fpga_x2p/bitstream/fpga_bitstream_pbtypes.c /^void fpga_spice_generate_bitstream_phy_pb_graph_node_rec(FILE* fp,$/;" f -fpga_spice_generate_bitstream_physical_grid_block ./fpga_x2p/bitstream/fpga_bitstream_pbtypes.c /^void fpga_spice_generate_bitstream_physical_grid_block(FILE* fp,$/;" f -fpga_spice_generate_bitstream_routing_chan_subckt ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_routing_chan_subckt(int x, int y,$/;" f file: -fpga_spice_generate_bitstream_routing_connection_box_subckt ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_routing_connection_box_subckt(FILE* fp,$/;" f file: -fpga_spice_generate_bitstream_routing_resources ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log_file_path,$/;" f -fpga_spice_generate_bitstream_routing_switch_box_subckt ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_routing_switch_box_subckt(FILE* fp, $/;" f file: -fpga_spice_generate_bitstream_switch_box_interc ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp,$/;" f file: -fpga_spice_generate_bitstream_switch_box_mux ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp,$/;" f file: -fpga_spice_generate_bitstream_switch_box_short_interc ./fpga_x2p/bitstream/fpga_bitstream_routing.c /^void fpga_spice_generate_bitstream_switch_box_short_interc(t_sb* cur_sb_info,$/;" f file: -fpga_spice_inpad_model ./fpga_x2p/base/fpga_x2p_globals.c /^t_spice_model* fpga_spice_inpad_model = NULL;$/;" v -fpga_spice_iopad_model ./fpga_x2p/base/fpga_x2p_globals.c /^t_spice_model* fpga_spice_iopad_model = NULL;$/;" v -fpga_spice_leakage_only ./base/vpr_types.h /^ boolean fpga_spice_leakage_only;$/;" m struct:s_spice_opts -fpga_spice_opts ./fpga_x2p/shell/cmd_fpga_spice.h /^t_opt_info fpga_spice_opts[] = {$/;" v -fpga_spice_outpad_model ./fpga_x2p/base/fpga_x2p_globals.c /^t_spice_model* fpga_spice_outpad_model = NULL;$/;" v -fpga_spice_parasitic_net_estimation ./base/ReadOptions.h /^ boolean fpga_spice_parasitic_net_estimation;$/;" m struct:s_options -fpga_spice_parasitic_net_estimation ./base/vpr_types.h /^ boolean fpga_spice_parasitic_net_estimation;$/;" m struct:s_spice_opts -fpga_spice_phy_pb ./fpga_x2p/base/fpga_x2p_types.h /^struct fpga_spice_phy_pb {$/;" s -fpga_spice_print_cb_mux_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_cb_mux_testbench; $/;" m struct:s_spice_opts -fpga_spice_print_cb_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_cb_testbench; $/;" m struct:s_spice_opts -fpga_spice_print_grid_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_grid_testbench; $/;" m struct:s_spice_opts -fpga_spice_print_hardlogic_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_hardlogic_testbench; $/;" m struct:s_spice_opts -fpga_spice_print_io_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_io_testbench; $/;" m struct:s_spice_opts -fpga_spice_print_lut_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_lut_testbench; $/;" m struct:s_spice_opts -fpga_spice_print_pb_mux_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_pb_mux_testbench; $/;" m struct:s_spice_opts -fpga_spice_print_sb_mux_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_sb_mux_testbench; $/;" m struct:s_spice_opts -fpga_spice_print_sb_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_sb_testbench; $/;" m struct:s_spice_opts -fpga_spice_print_top_testbench ./base/vpr_types.h /^ boolean fpga_spice_print_top_testbench; $/;" m struct:s_spice_opts -fpga_spice_rr_graph ./fpga_x2p/base/fpga_x2p_types.h /^struct fpga_spice_rr_graph {$/;" s -fpga_spice_signal_density_weight ./base/ReadOptions.h /^ float fpga_spice_signal_density_weight;$/;" m struct:s_options -fpga_spice_sim_mt_num ./base/ReadOptions.h /^ int fpga_spice_sim_mt_num;$/;" m struct:s_options -fpga_spice_sim_multi_thread_num ./base/vpr_types.h /^ int fpga_spice_sim_multi_thread_num;$/;" m struct:s_spice_opts -fpga_spice_sim_window_size ./base/ReadOptions.h /^ float fpga_spice_sim_window_size;$/;" m struct:s_options -fpga_spice_simulator_path ./base/ReadOptions.h /^ char* fpga_spice_simulator_path;$/;" m struct:s_options -fpga_spice_sram_model ./fpga_x2p/base/fpga_x2p_globals.c /^t_spice_model* fpga_spice_sram_model = NULL;$/;" v -fpga_spice_sram_orgz_type ./fpga_x2p/base/fpga_x2p_globals.c /^enum e_sram_orgz fpga_spice_sram_orgz_type = SPICE_SRAM_STANDALONE;$/;" v typeref:enum:e_sram_orgz -fpga_spice_strtok ./fpga_x2p/base/fpga_x2p_utils.c /^char** fpga_spice_strtok(char* str, $/;" f -fpga_spice_testbench_load_extraction ./base/ReadOptions.h /^ boolean fpga_spice_testbench_load_extraction;$/;" m struct:s_options -fpga_spice_testbench_load_extraction ./base/vpr_types.h /^ boolean fpga_spice_testbench_load_extraction;$/;" m struct:s_spice_opts -fpga_syn_verilog_dir ./base/ReadOptions.h /^ char* fpga_syn_verilog_dir;$/;" m struct:s_options -fpga_verilog_modelsim_ini_path ./base/ReadOptions.h /^ char* fpga_verilog_modelsim_ini_path;$/;" m struct:s_options -fpga_verilog_opts ./fpga_x2p/shell/cmd_fpga_verilog.h /^t_opt_info fpga_verilog_opts[] = {$/;" v -fpga_verilog_reference_benchmark_file ./base/ReadOptions.h /^ char* fpga_verilog_reference_benchmark_file;$/;" m struct:s_options -fpga_verilog_report_timing_path ./base/ReadOptions.h /^ char* fpga_verilog_report_timing_path;$/;" m struct:s_options -fpga_x2p_free ./fpga_x2p/base/fpga_x2p_setup.c /^void fpga_x2p_free(t_arch* Arch) {$/;" f -fpga_x2p_setup ./fpga_x2p/base/fpga_x2p_setup.c /^void fpga_x2p_setup(t_vpr_setup vpr_setup,$/;" f -fpga_x2p_setup_opts ./fpga_x2p/shell/cmd_fpga_x2p_setup.h /^t_opt_info fpga_x2p_setup_opts[] = {$/;" v -fprint_call_defined_channels ./fpga_x2p/spice/spice_utils.c /^void fprint_call_defined_channels(FILE* fp,$/;" f -fprint_call_defined_connection_boxes ./fpga_x2p/spice/spice_utils.c /^void fprint_call_defined_connection_boxes(FILE* fp) {$/;" f -fprint_call_defined_grids ./fpga_x2p/spice/spice_utils.c /^void fprint_call_defined_grids(FILE* fp) {$/;" f -fprint_call_defined_one_channel ./fpga_x2p/spice/spice_utils.c /^void fprint_call_defined_one_channel(FILE* fp,$/;" f -fprint_call_defined_one_connection_box ./fpga_x2p/spice/spice_utils.c /^void fprint_call_defined_one_connection_box(FILE* fp,$/;" f -fprint_call_defined_one_switch_box ./fpga_x2p/spice/spice_utils.c /^void fprint_call_defined_one_switch_box(FILE* fp,$/;" f -fprint_call_defined_switch_boxes ./fpga_x2p/spice/spice_utils.c /^void fprint_call_defined_switch_boxes(FILE* fp) {$/;" f -fprint_commented_sram_bits ./fpga_x2p/base/fpga_x2p_utils.c /^void fprint_commented_sram_bits(FILE* fp,$/;" f -fprint_connection_box_interc ./fpga_x2p/spice/spice_routing.c /^void fprint_connection_box_interc(FILE* fp,$/;" f -fprint_connection_box_mux ./fpga_x2p/spice/spice_routing.c /^void fprint_connection_box_mux(FILE* fp,$/;" f -fprint_connection_box_short_interc ./fpga_x2p/spice/spice_routing.c /^void fprint_connection_box_short_interc(FILE* fp,$/;" f -fprint_global_pad_ports_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_global_pad_ports_spice_model(FILE* fp, $/;" f -fprint_global_vdds_logical_block_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_global_vdds_logical_block_spice_model(FILE* fp,$/;" f -fprint_global_vdds_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_global_vdds_spice_model(FILE* fp, $/;" f -fprint_grid_block_subckt_pins ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_grid_block_subckt_pins(FILE* fp,$/;" f -fprint_grid_blocks ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_grid_blocks(char* subckt_dir,$/;" f -fprint_grid_float_port_stimulation ./fpga_x2p/spice/spice_utils.c /^void fprint_grid_float_port_stimulation(FILE* fp) {$/;" f -fprint_grid_global_vdds_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_grid_global_vdds_spice_model(FILE* fp, int x, int y, $/;" f -fprint_grid_physical_blocks ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_grid_physical_blocks(char* subckt_dir,$/;" f -fprint_grid_pins ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_grid_pins(FILE* fp,$/;" f -fprint_grid_side_pin_with_given_index ./fpga_x2p/spice/spice_routing.c /^void fprint_grid_side_pin_with_given_index(FILE* fp,$/;" f -fprint_grid_side_pins ./fpga_x2p/spice/spice_routing.c /^void fprint_grid_side_pins(FILE* fp,$/;" f -fprint_grid_splited_vdds_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_grid_splited_vdds_spice_model(FILE* fp, int grid_x, int grid_y,$/;" f -fprint_grid_testbench_one_grid_stimulation ./fpga_x2p/spice/spice_grid_testbench.c /^void fprint_grid_testbench_one_grid_stimulation(FILE* fp, $/;" f -fprint_include_user_defined_netlists ./fpga_x2p/spice/spice_utils.c /^void fprint_include_user_defined_netlists(FILE* fp,$/;" f -fprint_io_grid_block_subckt_pins ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_io_grid_block_subckt_pins(FILE* fp,$/;" f -fprint_io_grid_pins ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_io_grid_pins(FILE* fp,$/;" f -fprint_measure_grid_vdds_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_measure_grid_vdds_spice_model(FILE* fp, int grid_x, int grid_y,$/;" f -fprint_measure_vdds_cbs ./fpga_x2p/spice/spice_top_netlist.c /^void fprint_measure_vdds_cbs(FILE* fp,$/;" f file: -fprint_measure_vdds_logical_block_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_measure_vdds_logical_block_spice_model(FILE* fp,$/;" f -fprint_measure_vdds_sbs ./fpga_x2p/spice/spice_top_netlist.c /^void fprint_measure_vdds_sbs(FILE* fp,$/;" f file: -fprint_measure_vdds_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_measure_vdds_spice_model(FILE* fp,$/;" f -fprint_one_design_param_w_wo_variation ./fpga_x2p/spice/spice_utils.c /^void fprint_one_design_param_w_wo_variation(FILE* fp,$/;" f -fprint_pb_primitive_generic ./fpga_x2p/spice/spice_primitive.c /^void fprint_pb_primitive_generic(FILE* fp,$/;" f -fprint_pb_primitive_lut ./fpga_x2p/spice/spice_lut.c /^void fprint_pb_primitive_lut(FILE* fp,$/;" f -fprint_pb_primitive_spice_model ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_pb_primitive_spice_model(FILE* fp,$/;" f -fprint_pb_type_ports ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_pb_type_ports(FILE* fp,$/;" f -fprint_routing_chan_subckt ./fpga_x2p/spice/spice_routing.c /^void fprint_routing_chan_subckt(char* subckt_dir,$/;" f -fprint_routing_connection_box_subckt ./fpga_x2p/spice/spice_routing.c /^void fprint_routing_connection_box_subckt(char* subckt_dir,$/;" f -fprint_routing_switch_box_subckt ./fpga_x2p/spice/spice_routing.c /^void fprint_routing_switch_box_subckt(char* subckt_dir, $/;" f -fprint_run_hspice_shell_script ./fpga_x2p/spice/spice_run_scripts.c /^void fprint_run_hspice_shell_script(t_spice spice,$/;" f -fprint_spice_block ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_spice_block(FILE* fp,$/;" f -fprint_spice_cb_testbench_global_ports ./fpga_x2p/spice/spice_routing_testbench.c /^void fprint_spice_cb_testbench_global_ports(FILE* fp,$/;" f file: -fprint_spice_circuit_param ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_circuit_param(FILE* fp,$/;" f -fprint_spice_clb2clb_directs ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_clb2clb_directs(FILE* fp, $/;" f -fprint_spice_cmos_mux_multilevel_structure ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_cmos_mux_multilevel_structure(FILE* fp, $/;" f -fprint_spice_cmos_mux_onelevel_structure ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_cmos_mux_onelevel_structure(FILE* fp, char* mux_basis_subckt_name,$/;" f -fprint_spice_cmos_mux_tree_structure ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_cmos_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name,$/;" f -fprint_spice_dangling_des_pb_graph_pin_interc ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_spice_dangling_des_pb_graph_pin_interc(FILE* fp,$/;" f -fprint_spice_design_param_header ./fpga_x2p/spice/spice_heads.c /^void fprint_spice_design_param_header(char* design_param_file_name,$/;" f file: -fprint_spice_generic_testbench_global_ports ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_generic_testbench_global_ports(FILE* fp, $/;" f -fprint_spice_global_ports ./fpga_x2p/spice/spice_utils.c /^int fprint_spice_global_ports(FILE* fp, t_llist* head) {$/;" f -fprint_spice_global_vdd_connection_boxes ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_global_vdd_connection_boxes(FILE* fp) {$/;" f -fprint_spice_global_vdd_switch_boxes ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_global_vdd_switch_boxes(FILE* fp) {$/;" f -fprint_spice_grid_testbench_call_defined_core_grids ./fpga_x2p/spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_call_defined_core_grids(FILE* fp) {$/;" f -fprint_spice_grid_testbench_call_one_defined_grid ./fpga_x2p/spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_call_one_defined_grid(FILE* fp, int ix, int iy) {$/;" f -fprint_spice_grid_testbench_global_ports ./fpga_x2p/spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_global_ports(FILE* fp, int x, int y,$/;" f file: -fprint_spice_grid_testbench_measurements ./fpga_x2p/spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_measurements(FILE* fp, int grid_x, int grid_y, $/;" f file: -fprint_spice_grid_testbench_stimulations ./fpga_x2p/spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_stimulations(FILE* fp, $/;" f file: -fprint_spice_head ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_head(FILE* fp,$/;" f -fprint_spice_idle_block ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_spice_idle_block(FILE* fp,$/;" f -fprint_spice_idle_pb_graph_node_rec ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_spice_idle_pb_graph_node_rec(FILE* fp,$/;" f -fprint_spice_include_key_subckts ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_include_key_subckts(FILE* fp,$/;" f -fprint_spice_include_param_headers ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_include_param_headers(FILE* fp,$/;" f -fprint_spice_lut_subckt ./fpga_x2p/spice/spice_lut.c /^void fprint_spice_lut_subckt(FILE* fp,$/;" f -fprint_spice_meas_header ./fpga_x2p/spice/spice_heads.c /^void fprint_spice_meas_header(char* meas_file_name,$/;" f file: -fprint_spice_mux_model_basis_cmos_subckt ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_mux_model_basis_cmos_subckt(FILE* fp, char* subckt_name,$/;" f file: -fprint_spice_mux_model_basis_rram_subckt ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_mux_model_basis_rram_subckt(FILE* fp, char* subckt_name,$/;" f file: -fprint_spice_mux_model_basis_subckt ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_mux_model_basis_subckt(FILE* fp, $/;" f file: -fprint_spice_mux_model_cmos_subckt ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_mux_model_cmos_subckt(FILE* fp,$/;" f -fprint_spice_mux_model_rram_subckt ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_mux_model_rram_subckt(FILE* fp,$/;" f -fprint_spice_mux_model_subckt ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_mux_model_subckt(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_call_one_grid_cb_muxes ./fpga_x2p/spice/spice_mux_testbench.c /^int fprint_spice_mux_testbench_call_one_grid_cb_muxes(FILE* fp, $/;" f file: -fprint_spice_mux_testbench_call_one_grid_pb_muxes ./fpga_x2p/spice/spice_mux_testbench.c /^int fprint_spice_mux_testbench_call_one_grid_pb_muxes(FILE* fp, int ix, int iy,$/;" f file: -fprint_spice_mux_testbench_call_one_grid_sb_muxes ./fpga_x2p/spice/spice_mux_testbench.c /^int fprint_spice_mux_testbench_call_one_grid_sb_muxes(FILE* fp, $/;" f file: -fprint_spice_mux_testbench_cb_interc ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_cb_interc(FILE* fp, $/;" f -fprint_spice_mux_testbench_cb_mux_meas ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_cb_mux_meas(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_cb_one_mux ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_cb_one_mux(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_global_ports ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_global_ports(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_measurements ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_measurements(FILE* fp, $/;" f file: -fprint_spice_mux_testbench_one_mux ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_one_mux(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_pb_graph_node_pin_interc ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_graph_node_pin_interc(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_pb_graph_node_pin_mux ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_graph_node_pin_mux(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_pb_interc ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_interc(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_pb_mux_meas ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_mux_meas(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_pb_muxes_rec ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_muxes_rec(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_pb_pin_interc ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_pin_interc(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_pb_pin_mux ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_pin_mux(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_sb_mux_meas ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_sb_mux_meas(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_sb_one_mux ./fpga_x2p/spice/spice_mux_testbench.c /^int fprint_spice_mux_testbench_sb_one_mux(FILE* fp,$/;" f file: -fprint_spice_mux_testbench_stimulations ./fpga_x2p/spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_stimulations(FILE* fp, $/;" f file: -fprint_spice_netlist_generic_measurements ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_netlist_generic_measurements(FILE* fp, $/;" f -fprint_spice_netlist_measurement_one_design_param ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_netlist_measurement_one_design_param(FILE* fp,$/;" f -fprint_spice_netlist_transient_setting ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_netlist_transient_setting(FILE* fp, $/;" f -fprint_spice_one_cb_testbench ./fpga_x2p/spice/spice_routing_testbench.c /^int fprint_spice_one_cb_testbench(char* formatted_spice_dir,$/;" f -fprint_spice_one_clb2clb_direct ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_one_clb2clb_direct(FILE* fp, $/;" f -fprint_spice_one_grid_testbench ./fpga_x2p/spice/spice_grid_testbench.c /^int fprint_spice_one_grid_testbench(char* formatted_spice_dir,$/;" f -fprint_spice_one_mux_testbench ./fpga_x2p/spice/spice_mux_testbench.c /^int fprint_spice_one_mux_testbench(char* formatted_spice_dir,$/;" f -fprint_spice_one_primitive_testbench ./fpga_x2p/spice/spice_primitive_testbench.c /^int fprint_spice_one_primitive_testbench(char* formatted_spice_dir,$/;" f -fprint_spice_one_sb_testbench ./fpga_x2p/spice/spice_routing_testbench.c /^int fprint_spice_one_sb_testbench(char* formatted_spice_dir,$/;" f -fprint_spice_one_specific_sram_subckt ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_one_specific_sram_subckt(FILE* fp,$/;" f -fprint_spice_one_sram_subckt ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_one_sram_subckt(FILE* fp,$/;" f -fprint_spice_options ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_options(FILE* fp,$/;" f -fprint_spice_pb_graph_interc ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_spice_pb_graph_interc(FILE* fp, $/;" f -fprint_spice_pb_graph_node_rec ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_spice_pb_graph_node_rec(FILE* fp, $/;" f -fprint_spice_pb_graph_primitive_node ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_spice_pb_graph_primitive_node(FILE* fp,$/;" f -fprint_spice_phy_pb_graph_node_rec ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_spice_phy_pb_graph_node_rec(FILE* fp, $/;" f -fprint_spice_physical_block ./fpga_x2p/spice/spice_pbtypes.c /^void fprint_spice_physical_block(FILE* fp,$/;" f -fprint_spice_primitive_testbench_call_one_grid_defined_primitives ./fpga_x2p/spice/spice_primitive_testbench.c /^void fprint_spice_primitive_testbench_call_one_grid_defined_primitives(FILE* fp,$/;" f -fprint_spice_primitive_testbench_call_one_primitive ./fpga_x2p/spice/spice_primitive_testbench.c /^void fprint_spice_primitive_testbench_call_one_primitive(FILE* fp, $/;" f -fprint_spice_primitive_testbench_global_ports ./fpga_x2p/spice/spice_primitive_testbench.c /^void fprint_spice_primitive_testbench_global_ports(FILE* fp, int grid_x, int grid_y, $/;" f file: -fprint_spice_primitive_testbench_measurements ./fpga_x2p/spice/spice_primitive_testbench.c /^void fprint_spice_primitive_testbench_measurements(FILE* fp, int grid_x, int grid_y, $/;" f -fprint_spice_primitive_testbench_one_pb_primitive ./fpga_x2p/spice/spice_primitive_testbench.c /^void fprint_spice_primitive_testbench_one_pb_primitive(FILE* fp, $/;" f -fprint_spice_primitive_testbench_one_primitive_input_stimuli ./fpga_x2p/spice/spice_primitive_testbench.c /^void fprint_spice_primitive_testbench_one_primitive_input_stimuli(FILE* fp, $/;" f -fprint_spice_primitive_testbench_one_primitive_output_loads ./fpga_x2p/spice/spice_primitive_testbench.c /^void fprint_spice_primitive_testbench_one_primitive_output_loads(FILE* fp, $/;" f -fprint_spice_primitive_testbench_rec_pb_primitives ./fpga_x2p/spice/spice_primitive_testbench.c /^void fprint_spice_primitive_testbench_rec_pb_primitives(FILE* fp, $/;" f -fprint_spice_primitive_testbench_stimulations ./fpga_x2p/spice/spice_primitive_testbench.c /^void fprint_spice_primitive_testbench_stimulations(FILE* fp, int grid_x, int grid_y, $/;" f file: -fprint_spice_routing_testbench_call_one_cb_tb ./fpga_x2p/spice/spice_routing_testbench.c /^int fprint_spice_routing_testbench_call_one_cb_tb(FILE* fp,$/;" f file: -fprint_spice_routing_testbench_call_one_sb_tb ./fpga_x2p/spice/spice_routing_testbench.c /^int fprint_spice_routing_testbench_call_one_sb_tb(FILE* fp, $/;" f file: -fprint_spice_routing_testbench_global_ports ./fpga_x2p/spice/spice_routing_testbench.c /^void fprint_spice_routing_testbench_global_ports(FILE* fp,$/;" f file: -fprint_spice_rram_mux_multilevel_structure ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_rram_mux_multilevel_structure(FILE* fp, char* mux_basis_subckt_name,$/;" f -fprint_spice_rram_mux_onelevel_structure ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_rram_mux_onelevel_structure(FILE* fp, $/;" f -fprint_spice_rram_mux_tree_structure ./fpga_x2p/spice/spice_mux.c /^void fprint_spice_rram_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name,$/;" f -fprint_spice_sb_testbench_global_ports ./fpga_x2p/spice/spice_routing_testbench.c /^void fprint_spice_sb_testbench_global_ports(FILE* fp,$/;" f file: -fprint_spice_sram_one_outport ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_sram_one_outport(FILE* fp,$/;" f -fprint_spice_stimulate_header ./fpga_x2p/spice/spice_heads.c /^void fprint_spice_stimulate_header(char* stimulate_file_name,$/;" f file: -fprint_spice_testbench_generic_global_ports_stimuli ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_testbench_generic_global_ports_stimuli(FILE* fp,$/;" f -fprint_spice_testbench_global_ports_stimuli ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_testbench_global_ports_stimuli(FILE* fp, $/;" f -fprint_spice_testbench_global_sram_inport_stimuli ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_testbench_global_sram_inport_stimuli(FILE* fp,$/;" f -fprint_spice_testbench_global_vdd_port_stimuli ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_testbench_global_vdd_port_stimuli(FILE* fp,$/;" f -fprint_spice_testbench_one_cb_mux_loads ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_testbench_one_cb_mux_loads(FILE* fp, int* testbench_load_cnt,$/;" f -fprint_spice_testbench_one_grid_pin_loads ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_testbench_one_grid_pin_loads(FILE* fp, int x, int y, $/;" f -fprint_spice_testbench_one_grid_pin_stimulation ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_testbench_one_grid_pin_stimulation(FILE* fp, int x, int y, $/;" f -fprint_spice_testbench_pb_graph_pin_inv_loads_rec ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_testbench_pb_graph_pin_inv_loads_rec(FILE* fp, int* testbench_load_cnt, $/;" f -fprint_spice_testbench_rr_node_load_version ./fpga_x2p/spice/spice_utils.c /^char* fprint_spice_testbench_rr_node_load_version(FILE* fp, int* testbench_load_cnt,$/;" f -fprint_spice_testbench_wire_one_global_port_stimuli ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_testbench_wire_one_global_port_stimuli(FILE* fp, $/;" f -fprint_spice_toplevel_one_grid_side_pin_with_given_index ./fpga_x2p/spice/spice_utils.c /^void fprint_spice_toplevel_one_grid_side_pin_with_given_index(FILE* fp, $/;" f -fprint_spice_wire_model ./fpga_x2p/spice/spice_subckt.c /^void fprint_spice_wire_model(FILE* fp,$/;" f -fprint_splited_vdds_logical_block_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_splited_vdds_logical_block_spice_model(FILE* fp,$/;" f -fprint_splited_vdds_spice_model ./fpga_x2p/spice/spice_utils.c /^void fprint_splited_vdds_spice_model(FILE* fp,$/;" f -fprint_stimulate_dangling_grid_pins ./fpga_x2p/spice/spice_utils.c /^void fprint_stimulate_dangling_grid_pins(FILE* fp) {$/;" f -fprint_stimulate_dangling_io_grid_pins ./fpga_x2p/spice/spice_utils.c /^void fprint_stimulate_dangling_io_grid_pins(FILE* fp,$/;" f -fprint_stimulate_dangling_normal_grid_pins ./fpga_x2p/spice/spice_utils.c /^void fprint_stimulate_dangling_normal_grid_pins(FILE* fp,$/;" f -fprint_stimulate_dangling_one_grid_pin ./fpga_x2p/spice/spice_utils.c /^void fprint_stimulate_dangling_one_grid_pin(FILE* fp,$/;" f -fprint_switch_box_chan_port ./fpga_x2p/spice/spice_routing.c /^void fprint_switch_box_chan_port(FILE* fp,$/;" f -fprint_switch_box_interc ./fpga_x2p/spice/spice_routing.c /^void fprint_switch_box_interc(FILE* fp, $/;" f -fprint_switch_box_mux ./fpga_x2p/spice/spice_routing.c /^void fprint_switch_box_mux(FILE* fp, $/;" f -fprint_switch_box_short_interc ./fpga_x2p/spice/spice_routing.c /^void fprint_switch_box_short_interc(FILE* fp, $/;" f -fprint_tech_lib ./fpga_x2p/spice/spice_utils.c /^void fprint_tech_lib(FILE* fp,$/;" f -fprint_top_netlist_global_ports ./fpga_x2p/spice/spice_top_netlist.c /^void fprint_top_netlist_global_ports(FILE* fp,$/;" f file: -fprint_top_netlist_measurements ./fpga_x2p/spice/spice_top_netlist.c /^void fprint_top_netlist_measurements(FILE* fp, $/;" f file: -fprint_top_netlist_stimulations ./fpga_x2p/spice/spice_top_netlist.c /^void fprint_top_netlist_stimulations(FILE* fp,$/;" f file: -fprint_voltage_pulse_params ./fpga_x2p/spice/spice_utils.c /^void fprint_voltage_pulse_params(FILE* fp,$/;" f -fprintf_spice_mux_testbench_pb_graph_port_interc ./fpga_x2p/spice/spice_mux_testbench.c /^void fprintf_spice_mux_testbench_pb_graph_port_interc(FILE* fp,$/;" f file: -fprintf_spice_pb_graph_pin_interc ./fpga_x2p/spice/spice_pbtypes.c /^void fprintf_spice_pb_graph_pin_interc(FILE* fp,$/;" f -fprintf_spice_pb_graph_port_interc ./fpga_x2p/spice/spice_pbtypes.c /^void fprintf_spice_pb_graph_port_interc(FILE* fp,$/;" f -fprintf_spice_routing_testbench_generic_stimuli ./fpga_x2p/spice/spice_routing_testbench.c /^void fprintf_spice_routing_testbench_generic_stimuli(FILE* fp,$/;" f file: -fptr ./base/vpr_types.h /^ float *fptr;$/;" m struct:s_linked_f_pointer -freeGrid ./base/SetupGrid.c /^void freeGrid() {$/;" f -freeTokens ./util/token.c /^void freeTokens(INP t_token *tokens, INP int num_tokens) {$/;" f -free_2D_matrix ./fpga_x2p/base/fpga_x2p_timing_utils.c /^void free_2D_matrix(void** delay_matrix,$/;" f -free_all_pb_graph_nodes ./pack/pb_type_graph.c /^void free_all_pb_graph_nodes(void) {$/;" f -free_and_reset_internal_structures ./place/timing_place_lookup.c /^static void free_and_reset_internal_structures(struct s_net *original_net,$/;" f file: -free_arch ./base/vpr_api.c /^void free_arch(t_arch* Arch) {$/;" f -free_backannotate_vpr_post_route_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void free_backannotate_vpr_post_route_info() {$/;" f -free_best_buffer_list ./mrfpga/buffer_insertion.c /^static void free_best_buffer_list( )$/;" f file: -free_blk_pin_from_port_pin ./util/vpr_utils.c /^void free_blk_pin_from_port_pin(void) {$/;" f -free_buffer_list ./mrfpga/buffer_insertion.c /^static void free_buffer_list( t_buffer_plan_list list )$/;" f file: -free_cb ./util/vpr_utils.c /^void free_cb(t_pb *pb) {$/;" f -free_cb_info_array ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void free_cb_info_array(t_cb*** LL_cb_info, int LL_nx, int LL_ny) {$/;" f -free_chunk_memory_trace ./route/route_common.c /^void free_chunk_memory_trace(void) {$/;" f -free_circuit ./base/vpr_api.c /^void free_circuit() {$/;" f -free_clb_nets_spice_net_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void free_clb_nets_spice_net_info() {$/;" f -free_clock_constraint ./timing/read_sdc.c /^static void free_clock_constraint(t_clock *& clock_array, int num_clocks) {$/;" f file: -free_cluster_legality_checker ./pack/cluster_legality.c /^void free_cluster_legality_checker(void) {$/;" f -free_cluster_placement_stats ./pack/cluster_placement.c /^void free_cluster_placement_stats($/;" f -free_complex_block_types ./base/vpr_api.c /^static void free_complex_block_types(void) {$/;" f file: -free_conf_bit ./fpga_x2p/base/fpga_x2p_utils.c /^void free_conf_bit(t_conf_bit* conf_bit) {$/;" f -free_conf_bit_info ./fpga_x2p/base/fpga_x2p_utils.c /^void free_conf_bit_info(t_conf_bit_info* conf_bit_info) {$/;" f -free_crit ./place/timing_place.c /^static void free_crit(t_chunk *chunk_list_ptr){$/;" f file: -free_delta_arrays ./place/timing_place_lookup.c /^static void free_delta_arrays(void) {$/;" f file: -free_draw_structs ./base/draw.c /^void free_draw_structs(void) {$/;" f -free_echo_file_info ./base/ReadOptions.c /^void free_echo_file_info() {$/;" f -free_edge_list_head ./route/rr_graph2.c /^t_linked_edge *free_edge_list_head = NULL;$/;" v -free_fast_cost_update ./place/place.c /^static void free_fast_cost_update(void) {$/;" f file: -free_global_routing_conf_bits ./fpga_x2p/verilog/verilog_api.c /^void free_global_routing_conf_bits() {$/;" f file: -free_hash_table ./util/hash.c /^void free_hash_table(struct s_hash **hash_table) {$/;" f -free_heap_data ./route/route_common.c /^void free_heap_data(struct s_heap *hptr) {$/;" f -free_imacro_from_iblk ./place/place_macro.c /^static void free_imacro_from_iblk(void) {$/;" f file: -free_io_constraint ./timing/read_sdc.c /^static void free_io_constraint(t_io *& io_array, int num_ios) {$/;" f file: -free_legal_placements ./place/place.c /^static void free_legal_placements() {$/;" f file: -free_legalizer_for_cluster ./pack/cluster_legality.c /^void free_legalizer_for_cluster(INP t_block* clb, boolean free_local_rr_graph) {$/;" f -free_linked_list ./base/verilog_writer.c /^pb_list *free_linked_list(pb_list *list)$/;" f -free_linked_list_conn ./base/verilog_writer.c /^conn_list *free_linked_list_conn(conn_list *list)$/;" f -free_linked_rc_edge ./timing/net_delay.c /^void free_linked_rc_edge(t_linked_rc_edge * rc_edge,$/;" f -free_linked_rt_edge ./route/route_tree_timing.c /^static void free_linked_rt_edge(t_linked_rt_edge * rt_edge) {$/;" f file: -free_list_of_pack_patterns ./pack/prepack.c /^void free_list_of_pack_patterns(INP t_pack_patterns *list_of_pack_patterns, INP int num_packing_patterns) {$/;" f -free_logical_blocks ./base/read_netlist.c /^void free_logical_blocks(void) {$/;" f -free_logical_nets ./base/read_netlist.c /^void free_logical_nets(void) {$/;" f -free_lookups_and_criticalities ./place/timing_place.c /^void free_lookups_and_criticalities(float ***net_delay, t_slack * slacks) {$/;" f -free_muxes_llist ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void free_muxes_llist(t_llist* muxes_head) {$/;" f -free_net_delay ./timing/net_delay.c /^void free_net_delay(float **net_delay,$/;" f -free_one_cb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void free_one_cb_info(t_cb* cur_cb) {$/;" f -free_one_mem_bank_info ./fpga_x2p/base/fpga_x2p_utils.c /^void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info) {$/;" f -free_one_sb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void free_one_sb_info(t_sb* cur_sb) {$/;" f -free_one_scff_info ./fpga_x2p/base/fpga_x2p_utils.c /^void free_one_scff_info(t_scff_info* scff_info) {$/;" f -free_one_spice_model_grid_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void free_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) {$/;" f -free_one_spice_model_routing_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void free_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) {$/;" f -free_one_standalone_sram_info ./fpga_x2p/base/fpga_x2p_utils.c /^void free_one_standalone_sram_info(t_standalone_sram_info* standalone_sram_info) {$/;" f -free_options ./base/vpr_api.c /^void free_options(t_options *options) {$/;" f -free_output_file_names ./base/ReadOptions.c /^void free_output_file_names() {$/;" f -free_override_constraint ./timing/read_sdc.c /^void free_override_constraint(t_override_constraint *& constraint_array, int num_constraints) {$/;" f -free_pack_pattern ./pack/prepack.c /^static void free_pack_pattern(INOUTP t_pack_pattern_block *pattern_block, INOUTP t_pack_pattern_block **pattern_block_list) {$/;" f file: -free_parse ./base/read_blif.c /^static void free_parse(void) {$/;" f file: -free_pb ./util/vpr_utils.c /^void free_pb(t_pb *pb) {$/;" f -free_pb_data ./base/place_and_route.c /^void free_pb_data(t_pb *pb) {$/;" f -free_pb_graph ./pack/pb_type_graph.c /^static void free_pb_graph(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f file: -free_pb_stats ./util/vpr_utils.c /^void free_pb_stats(t_pb *pb) {$/;" f -free_pb_stats_recursive ./pack/cluster.c /^static void free_pb_stats_recursive(t_pb *pb) {$/;" f file: -free_pb_type ./base/vpr_api.c /^static void free_pb_type(t_pb_type *pb_type) {$/;" f file: -free_place_lookup_structs ./place/timing_place_lookup.c /^void free_place_lookup_structs(void) {$/;" f -free_placement_macros_structs ./place/place_macro.c /^void free_placement_macros_structs(void) {$/;" f -free_placement_structs ./place/place.c /^static void free_placement_structs($/;" f file: -free_port_pin_from_blk_pin ./util/vpr_utils.c /^void free_port_pin_from_blk_pin(void) {$/;" f -free_rc_edge_free_list ./timing/net_delay.c /^void free_rc_edge_free_list(t_linked_rc_edge * rc_edge_free_list) {$/;" f -free_rc_node ./timing/net_delay.c /^void free_rc_node(t_rc_node * rc_node,$/;" f -free_rc_node_free_list ./timing/net_delay.c /^void free_rc_node_free_list(t_rc_node * rc_node_free_list) {$/;" f -free_rc_tree ./timing/net_delay.c /^void free_rc_tree(t_rc_node * rc_root,$/;" f -free_route_structs ./route/route_common.c /^void free_route_structs() {$/;" f -free_route_tree ./route/route_tree_timing.c /^void free_route_tree(t_rt_node * rt_node) {$/;" f -free_route_tree_timing_structs ./route/route_tree_timing.c /^void free_route_tree_timing_structs(void) {$/;" f -free_routing_structs ./place/timing_place_lookup.c /^static void free_routing_structs(struct s_router_opts router_opts,$/;" f file: -free_rr_graph ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void free_rr_graph(t_rr_graph* local_rr_graph) {$/;" f -free_rr_graph ./route/rr_graph.c /^void free_rr_graph(void) {$/;" f -free_rr_graph_heap_data ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void free_rr_graph_heap_data(t_rr_graph* local_rr_graph,$/;" f -free_rr_graph_route_structs ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void free_rr_graph_route_structs(t_rr_graph* local_rr_graph) { \/* [0..num_rr_nodes-1] *\/$/;" f -free_rr_graph_rr_nodes ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void free_rr_graph_rr_nodes(t_rr_graph* local_rr_graph) {$/;" f -free_rr_graph_switch_inf ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void free_rr_graph_switch_inf(INOUTP t_rr_graph* local_rr_graph) {$/;" f -free_rr_graph_trace_data ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void free_rr_graph_trace_data(t_rr_graph* local_rr_graph,$/;" f -free_rr_graph_traceback ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void free_rr_graph_traceback(t_rr_graph* local_rr_graph, $/;" f -free_rr_node_indices ./route/rr_graph2.c /^void free_rr_node_indices(INP t_ivec *** L_rr_node_indices) {$/;" f -free_rr_node_route_structs ./route/route_common.c /^void free_rr_node_route_structs(void) {$/;" f -free_rt_node ./route/route_tree_timing.c /^static void free_rt_node(t_rt_node * rt_node) {$/;" f file: -free_saved_routing ./route/route_common.c /^void free_saved_routing(struct s_trace **best_routing,$/;" f -free_sb_info_array ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void free_sb_info_array(t_sb*** LL_sb_info, int LL_nx, int LL_ny) {$/;" f -free_sblock_pattern_lookup ./route/rr_graph2.c /^void free_sblock_pattern_lookup(INOUTP short *****sblock_pattern) {$/;" f -free_sdc_related_structs ./timing/read_sdc.c /^void free_sdc_related_structs(void) {$/;" f -free_seg_details ./route/rr_graph2.c /^void free_seg_details(t_seg_details * seg_details, int nodes_per_chan) {$/;" f -free_spice_model_grid_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void free_spice_model_grid_index_low_high(int num_spice_models, $/;" f -free_spice_model_routing_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void free_spice_model_routing_index_low_high(int num_spice_models, $/;" f -free_spice_tb_llist ./fpga_x2p/spice/spice_api.c /^void free_spice_tb_llist() {$/;" f file: -free_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^void free_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -free_switch_block_conn ./route/rr_graph_sbox.c /^void free_switch_block_conn(struct s_ivec ***switch_block_conn,$/;" f -free_timing_driven_route_structs ./route/route_timing.c /^void free_timing_driven_route_structs(float *pin_criticality, int *sink_order,$/;" f -free_timing_graph ./timing/path_delay.c /^void free_timing_graph(t_slack * slacks) {$/;" f -free_timing_stats ./timing/path_delay.c /^void free_timing_stats(void) {$/;" f -free_trace_data ./route/route_common.c /^static void free_trace_data(struct s_trace *tptr) {$/;" f file: -free_trace_structs ./route/route_common.c /^void free_trace_structs(void) {$/;" f -free_traceback ./route/route_common.c /^void free_traceback(int inet) {$/;" f -free_try_swap_arrays ./place/place.c /^static void free_try_swap_arrays(void) {$/;" f file: -free_type_pin_to_track_map ./route/rr_graph.c /^static void free_type_pin_to_track_map(int***** ipin_to_track_map,$/;" f file: -free_type_track_to_ipin_map ./route/rr_graph.c /^static void free_type_track_to_ipin_map(struct s_ivec**** track_to_pin_map,$/;" f file: -free_wire_L_llist ./fpga_x2p/verilog/verilog_report_timing.c /^void free_wire_L_llist(t_llist* rr_path_cnt) {$/;" f -from_clb_pin_end_index ./base/vpr_types.h /^ int from_clb_pin_end_index;$/;" m struct:s_clb_to_clb_directs -from_clb_pin_start_index ./base/vpr_types.h /^ int from_clb_pin_start_index;$/;" m struct:s_clb_to_clb_directs -from_clb_type ./base/vpr_types.h /^ t_type_descriptor *from_clb_type;$/;" m struct:s_clb_to_clb_directs -front ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list;$/;" m struct:s_buffer_plan_list file: -fs ./base/place_and_route.h /^ int fs; \/* at this fs *\/$/;" m struct:s_fmap_cell -fs ./base/vpr_types.h /^ int fs;$/;" m struct:s_sb -full_stats ./base/vpr_types.h /^ boolean full_stats;$/;" m struct:s_router_opts -g_MTA_area ./power/power_sizing.c /^static double g_MTA_area;$/;" v file: -g_buffer_strength_last_searched ./power/power_cmos_tech.c /^static t_power_buffer_strength_inf * g_buffer_strength_last_searched;$/;" v file: -g_clock_arch ./base/globals.c /^t_clock_arch * g_clock_arch;$/;" v -g_mux_volt_last_searched ./power/power_cmos_tech.c /^static t_power_mux_volt_inf * g_mux_volt_last_searched;$/;" v file: -g_power_arch ./power/power.c /^t_power_arch * g_power_arch;$/;" v -g_power_by_component ./power/power_components.c /^t_power_components g_power_by_component;$/;" v -g_power_commonly_used ./power/power.c /^t_power_commonly_used * g_power_commonly_used;$/;" v -g_power_output ./power/power.c /^t_power_output * g_power_output;$/;" v -g_power_searching_nmos_leakage_info ./power/power_cmos_tech.c /^t_power_nmos_leakage_inf * g_power_searching_nmos_leakage_info;$/;" v -g_power_tech ./power/power.c /^t_power_tech * g_power_tech;$/;" v -g_sdc ./timing/read_sdc.c /^t_timing_constraints * g_sdc = NULL;$/;" v -g_solution_inf ./power/power.c /^t_solution_inf g_solution_inf;$/;" v -g_transistor_last_searched ./power/power_cmos_tech.c /^static t_transistor_inf * g_transistor_last_searched;$/;" v file: -gain ./base/vpr_types.h /^ std::map gain; \/* Attraction (inverse of cost) function *\/$/;" m struct:s_pb_stats -gc ./base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: -gc_menus ./base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: -gcxor ./base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: -gen_bitstream ./base/vpr_types.h /^ boolean gen_bitstream;$/;" m struct:s_bitstream_gen_opts -gen_spice_name_tag_pb_rec ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void gen_spice_name_tag_pb_rec(t_pb* cur_pb,$/;" f -gen_spice_name_tag_phy_pb_rec ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void gen_spice_name_tag_phy_pb_rec(t_phy_pb* cur_phy_pb,$/;" f -gen_spice_name_tags_all_pbs ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void gen_spice_name_tags_all_pbs() {$/;" f -gen_spice_name_tags_all_phy_pbs ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void gen_spice_name_tags_all_phy_pbs() {$/;" f -gen_str_spice_model_structure ./fpga_x2p/base/fpga_x2p_utils.c /^char* gen_str_spice_model_structure(enum e_spice_model_structure spice_model_structure) {$/;" f -gen_verilog_grid_one_pin_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_grid_one_pin_name(int x, int y,$/;" f -gen_verilog_one_block_instance_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_block_instance_name(int grid_x, int grid_y, int grid_z) {$/;" f -gen_verilog_one_cb_instance_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_cb_instance_name(t_cb* cur_cb_info) {$/;" f -gen_verilog_one_cb_module_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_cb_module_name(t_cb* cur_cb_info) {$/;" f -gen_verilog_one_grid_instance_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_grid_instance_name(int grid_x, int grid_y) {$/;" f -gen_verilog_one_grid_module_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_grid_module_name(int grid_x, int grid_y) {$/;" f -gen_verilog_one_mux_module_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_mux_module_name(t_spice_model* spice_model, $/;" f -gen_verilog_one_pb_graph_node_full_name_in_hierarchy ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_graph_node_full_name_in_hierarchy(t_pb_graph_node* cur_pb_graph_node) {$/;" f -gen_verilog_one_pb_graph_node_instance_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_graph_node_instance_name(t_pb_graph_node* cur_pb_graph_node) {$/;" f -gen_verilog_one_pb_graph_pin_full_name_in_hierarchy ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy(t_pb_graph_pin* cur_pb_graph_pin) {$/;" f -gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_grand_parent_node ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_grand_parent_node(t_pb_graph_pin* cur_pb_graph_pin) {$/;" f -gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_parent_node ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_parent_node(t_pb_graph_pin* cur_pb_graph_pin) {$/;" f -gen_verilog_one_pb_type_pin_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_pb_type_pin_name(char* prefix, $/;" f -gen_verilog_one_phy_block_instance_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_phy_block_instance_name(t_type_ptr cur_type_ptr, $/;" f -gen_verilog_one_routing_channel_instance_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_routing_channel_instance_name(t_rr_type chan_type,$/;" f -gen_verilog_one_routing_channel_module_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_routing_channel_module_name(t_rr_type chan_type,$/;" f -gen_verilog_one_routing_report_timing_Lwire_dir_path ./fpga_x2p/verilog/verilog_report_timing.c /^char* gen_verilog_one_routing_report_timing_Lwire_dir_path(char* report_timing_path, $/;" f -gen_verilog_one_routing_report_timing_rpt_name ./fpga_x2p/verilog/verilog_report_timing.c /^char* gen_verilog_one_routing_report_timing_rpt_name(char* report_timing_path,$/;" f -gen_verilog_one_sb_instance_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_sb_instance_name(t_sb* cur_sb_info) {$/;" f -gen_verilog_one_sb_module_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_one_sb_module_name(t_sb* cur_sb_info) {$/;" f -gen_verilog_routing_channel_one_midout_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_routing_channel_one_midout_name(t_cb* cur_cb_info,$/;" f -gen_verilog_routing_channel_one_pin_name ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_routing_channel_one_pin_name(t_rr_node* chan_rr_node,$/;" f -gen_verilog_top_module_io_port_prefix ./fpga_x2p/verilog/verilog_utils.c /^char* gen_verilog_top_module_io_port_prefix(char* global_prefix, $/;" f -generate_compact_verilog_grid_module_name ./fpga_x2p/verilog/verilog_compact_netlist.c /^char* generate_compact_verilog_grid_module_name(t_type_ptr phy_block_type,$/;" f file: -generate_compact_verilog_grid_module_name_prefix ./fpga_x2p/verilog/verilog_compact_netlist.c /^char* generate_compact_verilog_grid_module_name_prefix(t_type_ptr phy_block_type,$/;" f file: -generate_frac_lut_sram_bits ./fpga_x2p/base/fpga_x2p_lut_utils.c /^int* generate_frac_lut_sram_bits(t_phy_pb* lut_phy_pb,$/;" f -generate_lut_sram_bits ./fpga_x2p/base/fpga_x2p_lut_utils.c /^int* generate_lut_sram_bits(int truth_table_len,$/;" f -generate_nets_sinks_prefer_sides ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^int generate_nets_sinks_prefer_sides(int n_nets, t_net* nets,$/;" f -generate_spice_basics ./fpga_x2p/spice/spice_subckt.c /^int generate_spice_basics(char* subckt_dir, t_spice spice) {$/;" f file: -generate_spice_logic_blocks ./fpga_x2p/spice/spice_pbtypes.c /^void generate_spice_logic_blocks(char* subckt_dir,$/;" f -generate_spice_luts ./fpga_x2p/spice/spice_lut.c /^void generate_spice_luts(char* subckt_dir, $/;" f -generate_spice_muxes ./fpga_x2p/spice/spice_mux.c /^void generate_spice_muxes(char* subckt_dir,$/;" f -generate_spice_nmos_pmos ./fpga_x2p/spice/spice_subckt.c /^int generate_spice_nmos_pmos(char* subckt_dir,$/;" f -generate_spice_routing_resources ./fpga_x2p/spice/spice_routing.c /^void generate_spice_routing_resources(char* subckt_dir,$/;" f -generate_spice_rram_veriloga ./fpga_x2p/spice/spice_subckt.c /^void generate_spice_rram_veriloga(char* subckt_dir, $/;" f -generate_spice_src_des_pb_graph_pin_prefix ./fpga_x2p/spice/spice_pbtypes.c /^void generate_spice_src_des_pb_graph_pin_prefix(t_pb_graph_pin* src_pb_graph_pin,$/;" f -generate_spice_subckt_powergated_tapbuf ./fpga_x2p/spice/spice_subckt.c /^void generate_spice_subckt_powergated_tapbuf(FILE* fp, $/;" f -generate_spice_subckt_tapbuf ./fpga_x2p/spice/spice_subckt.c /^void generate_spice_subckt_tapbuf(FILE* fp, $/;" f -generate_spice_subckts ./fpga_x2p/spice/spice_subckt.c /^void generate_spice_subckts(char* subckt_dir,$/;" f -generate_spice_wires ./fpga_x2p/spice/spice_subckt.c /^void generate_spice_wires(char* subckt_dir,$/;" f -generate_string_spice_model_type ./fpga_x2p/base/fpga_x2p_utils.c /^char* generate_string_spice_model_type(enum e_spice_model_type spice_model_type) {$/;" f -generate_verilog_mem_subckt_name ./fpga_x2p/verilog/verilog_utils.c /^char* generate_verilog_mem_subckt_name(t_spice_model* spice_model, $/;" f -generate_verilog_mux_subckt_name ./fpga_x2p/verilog/verilog_utils.c /^char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, $/;" f -generate_verilog_src_des_pb_graph_pin_prefix ./fpga_x2p/verilog/verilog_pbtypes.c /^void generate_verilog_src_des_pb_graph_pin_prefix(t_pb_graph_pin* src_pb_graph_pin,$/;" f -generate_verilog_subckt_name ./fpga_x2p/verilog/verilog_utils.c /^char* generate_verilog_subckt_name(t_spice_model* spice_model, $/;" f -generic_compute_matrix ./place/timing_place_lookup.c /^static void generic_compute_matrix(float ***matrix_ptr, t_type_ptr source_type,$/;" f file: -getEchoEnabled ./base/ReadOptions.c /^boolean getEchoEnabled(void) {$/;" f -getEchoFileName ./base/ReadOptions.c /^char *getEchoFileName(enum e_echo_files echo_option) {$/;" f -getOutputFileName ./base/ReadOptions.c /^char *getOutputFileName(enum e_output_files ename) {$/;" f -get_array_size_of_molecule ./pack/cluster_placement.c /^int get_array_size_of_molecule(t_pack_molecule *molecule) {$/;" f -get_average_opin_delay ./route/rr_graph_indexed_data.c /^static float get_average_opin_delay(t_ivec *** L_rr_node_indices,$/;" f file: -get_bb_from_scratch ./place/place.c /^static void get_bb_from_scratch(int inet, struct s_bb *coords,$/;" f file: -get_bidir_opin_connections ./route/rr_graph2.c /^int get_bidir_opin_connections(INP int i, INP int j, INP int ipin,$/;" f -get_bidir_track_to_chan_seg ./route/rr_graph2.c /^static int get_bidir_track_to_chan_seg(INP struct s_ivec conn_tracks,$/;" f file: -get_blif_tok ./base/read_blif.c /^static void get_blif_tok(char *buffer, int doall, boolean *done,$/;" f file: -get_blk_pin_from_port_pin ./util/vpr_utils.c /^void get_blk_pin_from_port_pin(int blk_type_index, int port,int port_pin, $/;" f -get_block_center ./base/draw.c /^static void get_block_center(int bnum, float *x, float *y) {$/;" f file: -get_cblock_trans ./route/rr_graph_area.c /^static float get_cblock_trans(int *num_inputs_to_cblock, int* switches_to_cblock,$/;" f file: -get_chan_rr_node_coorindate_in_sb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void get_chan_rr_node_coorindate_in_sb_info(t_sb cur_sb_info,$/;" f -get_chan_rr_node_end_coordinate ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void get_chan_rr_node_end_coordinate(t_rr_node* chan_rr_node,$/;" f -get_chan_rr_node_ending_cb ./fpga_x2p/verilog/verilog_tcl_utils.c /^t_cb* get_chan_rr_node_ending_cb(t_rr_node* src_rr_node, $/;" f -get_chan_rr_node_ending_sb ./fpga_x2p/verilog/verilog_tcl_utils.c /^t_sb* get_chan_rr_node_ending_sb(t_rr_node* src_rr_node, $/;" f -get_chan_rr_node_start_coordinate ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void get_chan_rr_node_start_coordinate(t_rr_node* chan_rr_node,$/;" f -get_chan_rr_nodes ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^t_rr_node** get_chan_rr_nodes(int* num_chan_rr_nodes,$/;" f -get_chan_width ./fpga_x2p/base/rr_chan.cpp /^size_t RRChan::get_chan_width() const { $/;" f class:RRChan -get_channel_occupancy_stats ./base/stats.c /^static void get_channel_occupancy_stats(void) {$/;" f file: -get_child_pb_for_phy_pb_graph_node ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb) {$/;" f -get_class_range_for_block ./util/vpr_utils.c /^void get_class_range_for_block(INP int iblk, OUTP int *class_low,$/;" f -get_critical_path_delay ./timing/path_delay.c /^float get_critical_path_delay(void) {$/;" f -get_crossing_penalty ./fpga_x2p/clb_pin_remap/post_place_timing.c /^float get_crossing_penalty(int num_sinks) {$/;" f -get_default_spice_model ./fpga_x2p/base/fpga_x2p_utils.c /^t_spice_model* get_default_spice_model(enum e_spice_model_type default_spice_model_type,$/;" f -get_delay_normalization_fac ./route/rr_graph_indexed_data.c /^static float get_delay_normalization_fac(int nodes_per_chan,$/;" f file: -get_empty_buffer_plan_list ./mrfpga/buffer_insertion.c /^static t_buffer_plan_list get_empty_buffer_plan_list( )$/;" f file: -get_entry ./power/PowerSpicedComponent.c /^PowerCallibInputs * PowerSpicedComponent::get_entry(int num_inputs) {$/;" f class:PowerSpicedComponent -get_entry_bound ./power/PowerSpicedComponent.c /^PowerCallibInputs * PowerSpicedComponent::get_entry_bound(bool lower,$/;" f class:PowerSpicedComponent -get_entry_bound ./power/PowerSpicedComponent.c /^PowerCallibSize * PowerCallibInputs::get_entry_bound(bool lower,$/;" f class:PowerCallibInputs -get_escape_char ./timing/slre.c /^static int get_escape_char(const char **re) {$/;" f file: -get_expected_lowest_cost_primitive_for_logical_block ./pack/prepack.c /^static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block(INP int ilogical_block) {$/;" f file: -get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node ./pack/prepack.c /^static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(INP int ilogical_block, INP t_pb_graph_node *curr_pb_graph_node, OUTP float *cost) {$/;" f file: -get_expected_segs_to_target ./route/route_timing.c /^static int get_expected_segs_to_target(int inode, int target_node,$/;" f file: -get_ff_output_init_val ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int get_ff_output_init_val(t_logical_block* ff_logical_block) {$/;" f -get_first_pin ./place/timing_place_lookup.c /^static int get_first_pin(enum e_pin_type pintype, t_type_ptr type) {$/;" f file: -get_fpga_x2p_global_all_clock_ports ./fpga_x2p/base/fpga_x2p_utils.c /^void get_fpga_x2p_global_all_clock_ports(t_llist* head,$/;" f -get_fpga_x2p_global_op_clock_ports ./fpga_x2p/base/fpga_x2p_utils.c /^void get_fpga_x2p_global_op_clock_ports(t_llist* head,$/;" f -get_free_molecule_with_most_ext_inputs_for_cluster ./pack/cluster.c /^static t_pack_molecule *get_free_molecule_with_most_ext_inputs_for_cluster($/;" f file: -get_grid_block_subckt_name ./fpga_x2p/spice/spice_pbtypes.c /^char* get_grid_block_subckt_name(int x,$/;" f -get_grid_phy_block_subckt_name ./fpga_x2p/spice/spice_pbtypes.c /^char* get_grid_phy_block_subckt_name(int x, int y, int z,$/;" f -get_grid_pin_height ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int get_grid_pin_height(int grid_x, int grid_y, int pin_index) {$/;" f -get_grid_pin_side ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int get_grid_pin_side(int grid_x, int grid_y, int pin_index) {$/;" f -get_grid_side_pin_rr_nodes ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^t_rr_node** get_grid_side_pin_rr_nodes(int* num_pin_rr_nodes,$/;" f -get_grid_side_pins ./route/rr_graph_opincb.c /^void get_grid_side_pins(int grid_x, int grid_y, $/;" f file: -get_grid_testbench_one_grid_num_sim_clock_cycles ./fpga_x2p/spice/spice_grid_testbench.c /^int get_grid_testbench_one_grid_num_sim_clock_cycles(FILE* fp, $/;" f -get_hardlogic_child_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_pb* get_hardlogic_child_pb(t_pb* cur_hardlogic_pb,$/;" f -get_hash_entry ./util/hash.c /^get_hash_entry(struct s_hash **hash_table, char *name) {$/;" f -get_hash_stats ./util/hash.c /^void get_hash_stats(struct s_hash **hash_table, char *hash_table_name){$/;" f -get_heap_head ./route/route_common.c /^get_heap_head(void) {$/;" f -get_highest_gain_molecule ./pack/cluster.c /^static t_pack_molecule *get_highest_gain_molecule($/;" f file: -get_imacro_from_iblk ./place/place_macro.c /^void get_imacro_from_iblk(int * imacro, int iblk, t_pl_macro * macros, int num_macros) {$/;" f -get_init_buffer_plan ./mrfpga/buffer_insertion.c /^static t_buffer_plan get_init_buffer_plan( int inode, int num_pins, int* isink_to_inode )$/;" f file: -get_init_buffer_plan_list ./mrfpga/buffer_insertion.c /^static t_buffer_plan_list get_init_buffer_plan_list( int inode, int num_pins, int* isink_to_inode )$/;" f file: -get_int_list_length ./mrfpga/buffer_insertion.c /^static int get_int_list_length( t_linked_int* list )$/;" f file: -get_ipin_switch_index ./route/rr_graph_opincb.c /^int get_ipin_switch_index(t_rr_node* ipin) {$/;" f file: -get_keypress_input ./base/graphics.c /^static bool get_keypress_input, get_mouse_move_input;$/;" v file: -get_length_and_bends_stats ./base/stats.c /^void get_length_and_bends_stats(void) {$/;" f -get_logical_block_output_init_val ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int get_logical_block_output_init_val(t_logical_block* cur_logical_block) {$/;" f -get_logical_block_output_vpack_net_num ./fpga_x2p/base/fpga_x2p_utils.c /^void get_logical_block_output_vpack_net_num(t_logical_block* cur_logical_block,$/;" f -get_longest_segment_length ./place/timing_place_lookup.c /^static int get_longest_segment_length($/;" f file: -get_lut_child_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_pb* get_lut_child_pb(t_pb* cur_lut_pb,$/;" f -get_lut_child_phy_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_phy_pb* get_lut_child_phy_pb(t_phy_pb* cur_lut_pb,$/;" f -get_lut_logical_block_index_with_output_vpack_net_num ./fpga_x2p/base/fpga_x2p_utils.c /^int get_lut_logical_block_index_with_output_vpack_net_num(int target_vpack_net_num) {$/;" f -get_lut_logical_block_input_pin_vpack_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void get_lut_logical_block_input_pin_vpack_net_num(t_logical_block* lut_logical_block,$/;" f -get_lut_output_init_val ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int get_lut_output_init_val(t_logical_block* lut_logical_block) {$/;" f -get_mapped_lut_pb_input_pin_vpack_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb,$/;" f -get_mapped_lut_phy_pb_input_pin_vpack_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void get_mapped_lut_phy_pb_input_pin_vpack_net_num(t_phy_pb* lut_phy_pb,$/;" f -get_mapped_lut_phy_pb_output_pin ./fpga_x2p/base/fpga_x2p_lut_utils.c /^t_pb_graph_pin* get_mapped_lut_phy_pb_output_pin(t_phy_pb* lut_phy_pb, $/;" f -get_max_depth_of_pb_graph_node ./pack/cluster_feasibility_filter.c /^static int get_max_depth_of_pb_graph_node(INP t_pb_graph_node *pb_graph_node) {$/;" f file: -get_max_depth_of_pb_type ./util/vpr_utils.c /^int get_max_depth_of_pb_type(t_pb_type *pb_type) {$/;" f -get_max_nets_in_pb_type ./util/vpr_utils.c /^int get_max_nets_in_pb_type(const t_pb_type *pb_type) {$/;" f -get_max_pins_per_net ./route/route_timing.c /^static int get_max_pins_per_net(void) {$/;" f file: -get_max_primitives_in_pb_type ./util/vpr_utils.c /^int get_max_primitives_in_pb_type(t_pb_type *pb_type) {$/;" f -get_mem_bank_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void get_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info,$/;" f -get_module ./fpga_x2p/base/rr_chan.cpp /^RRChan DeviceRRChan::get_module(t_rr_type chan_type, size_t module_id) const {$/;" f class:DeviceRRChan -get_module_id ./fpga_x2p/base/rr_chan.cpp /^size_t DeviceRRChan::get_module_id(t_rr_type chan_type, size_t x, size_t y) const {$/;" f class:DeviceRRChan -get_module_with_coordinator ./fpga_x2p/base/rr_chan.cpp /^RRChan DeviceRRChan::get_module_with_coordinator(t_rr_type chan_type, size_t x, size_t y) const {$/;" f class:DeviceRRChan -get_molecule_by_num_ext_inputs ./pack/cluster.c /^static t_pack_molecule *get_molecule_by_num_ext_inputs($/;" f file: -get_molecule_for_cluster ./pack/cluster.c /^static t_pack_molecule *get_molecule_for_cluster($/;" f file: -get_molecule_gain ./pack/cluster.c /^static float get_molecule_gain(t_pack_molecule *molecule, std::map &blk_gain) {$/;" f file: -get_most_critical_seed_molecule ./pack/cluster.c /^static t_pack_molecule* get_most_critical_seed_molecule(int * indexofcrit) {$/;" f file: -get_mouse_move_input ./base/graphics.c /^static bool get_keypress_input, get_mouse_move_input;$/;" v file: -get_mrfpga_switch_type ./mrfpga/mrfpga_api.c /^void get_mrfpga_switch_type(boolean is_from_sbox,$/;" f -get_mux_default_path_id ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int get_mux_default_path_id(t_spice_model* mux_spice_model,$/;" f -get_mux_full_input_size ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int get_mux_full_input_size(t_spice_model* mux_spice_model,$/;" f -get_net_corresponding_to_pb_graph_pin ./pack/cluster.c /^static int get_net_corresponding_to_pb_graph_pin(t_pb *cur_pb,$/;" f file: -get_net_cost ./place/place.c /^static float get_net_cost(int inet, struct s_bb *bbptr) {$/;" f file: -get_net_wirelength_estimate ./place/place.c /^static double get_net_wirelength_estimate(int inet, struct s_bb *bbptr) {$/;" f file: -get_next_hash ./util/hash.c /^get_next_hash(struct s_hash **hash_table, struct s_hash_iterator *hash_iterator) {$/;" f -get_next_primitive_list ./pack/cluster_placement.c /^boolean get_next_primitive_list($/;" f -get_node ./fpga_x2p/base/rr_chan.cpp /^t_rr_node* RRChan::get_node(size_t track_num) const {$/;" f class:RRChan -get_node_segment ./fpga_x2p/base/rr_chan.cpp /^int RRChan::get_node_segment(size_t track_num) const {$/;" f class:RRChan -get_node_segment ./fpga_x2p/base/rr_chan.cpp /^int RRChan::get_node_segment(t_rr_node* node) const {$/;" f class:RRChan -get_node_track_id ./fpga_x2p/base/rr_chan.cpp /^int RRChan::get_node_track_id(t_rr_node* node) const {$/;" f class:RRChan -get_non_updateable_bb ./place/place.c /^static void get_non_updateable_bb(int inet, struct s_bb *bb_coord_new) {$/;" f file: -get_num_bends_and_length ./base/stats.c /^void get_num_bends_and_length(int inet, int *bends_ptr, int *len_ptr,$/;" f -get_num_conn ./base/check_netlist.c /^static int get_num_conn(int bnum) {$/;" f file: -get_num_modules ./fpga_x2p/base/rr_chan.cpp /^size_t DeviceRRChan::get_num_modules(t_rr_type chan_type) const {$/;" f class:DeviceRRChan -get_opin_direct_connecions ./route/rr_graph.c /^static int get_opin_direct_connecions(int x, int y, int opin, INOUTP t_linked_edge ** edge_list_ptr, INP t_ivec *** L_rr_node_indices, $/;" f file: -get_opposite_side ./fpga_x2p/base/fpga_x2p_utils.c /^int get_opposite_side(int side){$/;" f -get_opt_float_val ./fpga_x2p/shell/read_opt.c /^float get_opt_float_val(t_opt_info* opts, char* opt_name, float default_val) {$/;" f -get_opt_int_val ./fpga_x2p/shell/read_opt.c /^int get_opt_int_val(t_opt_info* opts, char* opt_name, int default_val) {$/;" f -get_opt_val ./fpga_x2p/shell/read_opt.c /^char* get_opt_val(t_opt_info* opts, char* opt_name) {$/;" f -get_pb_graph_full_name_in_hierarchy ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^char* get_pb_graph_full_name_in_hierarchy(t_pb_graph_node* cur_pb_graph_node) {$/;" f -get_pb_graph_node_pin_from_block_pin ./util/vpr_utils.c /^t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(int iblock, int ipin) {$/;" f -get_pb_graph_node_pin_from_clb_net ./util/vpr_utils.c /^t_pb_graph_pin* get_pb_graph_node_pin_from_clb_net(int inet, int ipin) {$/;" f -get_pb_graph_node_pin_from_model_port_pin ./util/vpr_utils.c /^t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(t_model_ports *model_port, int model_pin, t_pb_graph_node *pb_graph_node) {$/;" f -get_pb_graph_node_pin_from_vpack_net ./util/vpr_utils.c /^t_pb_graph_pin* get_pb_graph_node_pin_from_vpack_net(int inet, int ipin) {$/;" f -get_pb_graph_node_wired_lut_logical_block_index ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_graph_node,$/;" f -get_pb_graph_pin_from_name ./pack/pb_type_graph.c /^static t_pb_graph_pin * get_pb_graph_pin_from_name(INP const char * port_name,$/;" f file: -get_pb_graph_pin_lut_frac_level ./fpga_x2p/base/fpga_x2p_lut_utils.c /^int get_pb_graph_pin_lut_frac_level(t_pb_graph_pin* out_pb_graph_pin) {$/;" f -get_pb_graph_pin_lut_output_mask ./fpga_x2p/base/fpga_x2p_lut_utils.c /^int get_pb_graph_pin_lut_output_mask(t_pb_graph_pin* out_pb_graph_pin) {$/;" f -get_phy_child_pb_for_phy_pb_graph_node ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_phy_pb* get_phy_child_pb_for_phy_pb_graph_node(t_phy_pb* cur_phy_pb, $/;" f -get_port_pin_from_blk_pin ./util/vpr_utils.c /^void get_port_pin_from_blk_pin(int blk_type_index, int blk_pin, int * port,$/;" f -get_routing_seg_sdc_tmax ./fpga_x2p/verilog/verilog_sdc.c /^float get_routing_seg_sdc_tmax (t_segment_inf* cur_seg) {$/;" f -get_rr_cong_cost ./route/route_common.c /^float get_rr_cong_cost(int inode) {$/;" f -get_rr_graph_heap_head ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^t_heap * get_rr_graph_heap_head(t_rr_graph* local_rr_graph) {$/;" f -get_rr_graph_net_index_with_vpack_net ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^int get_rr_graph_net_index_with_vpack_net(t_rr_graph* local_rr_graph,$/;" f -get_rr_graph_net_vpack_net_index ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^int get_rr_graph_net_vpack_net_index(t_rr_graph* local_rr_graph,$/;" f -get_rr_graph_rr_cong_cost ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^float get_rr_graph_rr_cong_cost(t_rr_graph* local_rr_graph,$/;" f -get_rr_graph_rr_node_pack_intrinsic_cost ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^float get_rr_graph_rr_node_pack_intrinsic_cost(t_rr_graph* local_rr_graph,$/;" f -get_rr_graph_seg_start ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^int get_rr_graph_seg_start(INP t_seg_details * seg_details, INP int itrack,$/;" f -get_rr_node_index ./route/rr_graph2.c /^int get_rr_node_index(int x, int y, t_rr_type rr_type, int ptc,$/;" f -get_rr_node_index_in_cb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int get_rr_node_index_in_cb_info(t_rr_node* cur_rr_node,$/;" f -get_rr_node_index_in_sb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int get_rr_node_index_in_sb_info(t_rr_node* cur_rr_node,$/;" f -get_rr_node_net_density ./fpga_x2p/base/fpga_x2p_utils.c /^float get_rr_node_net_density(t_rr_node node) {$/;" f -get_rr_node_net_init_value ./fpga_x2p/base/fpga_x2p_utils.c /^int get_rr_node_net_init_value(t_rr_node node) {$/;" f -get_rr_node_net_probability ./fpga_x2p/base/fpga_x2p_utils.c /^float get_rr_node_net_probability(t_rr_node node) {$/;" f -get_rr_node_side_and_index_in_cb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void get_rr_node_side_and_index_in_cb_info(t_rr_node* cur_rr_node,$/;" f -get_rr_node_side_and_index_in_sb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void get_rr_node_side_and_index_in_sb_info(t_rr_node* cur_rr_node,$/;" f -get_rr_node_wire_length ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^int get_rr_node_wire_length(t_rr_node* src_rr_node) {$/;" f -get_rr_pin_draw_coords ./base/draw.c /^static void get_rr_pin_draw_coords(int inode, int iside, int ioff, float *xcen,$/;" f file: -get_sdc_tok ./timing/read_sdc.c /^static boolean get_sdc_tok(char * buf) {$/;" f file: -get_seed_logical_molecule_with_most_ext_inputs ./pack/cluster.c /^static t_pack_molecule* get_seed_logical_molecule_with_most_ext_inputs($/;" f file: -get_seg_end ./route/rr_graph2.c /^int get_seg_end(INP t_seg_details * seg_details, INP int itrack, INP int istart,$/;" f -get_seg_start ./route/rr_graph2.c /^int get_seg_start(INP t_seg_details * seg_details, INP int itrack,$/;" f -get_seg_track_counts ./route/rr_graph2.c /^get_seg_track_counts(INP int num_sets, INP int num_seg_types,$/;" f file: -get_segment_usage_stats ./route/segment_stats.c /^void get_segment_usage_stats(int num_segment, t_segment_inf * segment_inf) {$/;" f -get_serial_num ./route/route_common.c /^void get_serial_num(void) {$/;" f -get_simple_switch_block_track ./route/rr_graph_sbox.c /^int get_simple_switch_block_track(INP enum e_side from_side,$/;" f -get_simulation_time ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^int get_simulation_time(int num_prog_clock_cycles,$/;" f file: -get_simulation_time ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^int get_simulation_time(int num_prog_clock_cycles,$/;" f file: -get_spice_model_delay_info_ports ./fpga_x2p/base/fpga_x2p_timing_utils.c /^t_spice_model_port** get_spice_model_delay_info_ports(t_spice_model* cur_spice_model, $/;" f -get_spice_model_num_tedges_per_pin ./fpga_x2p/base/fpga_x2p_timing_utils.c /^int get_spice_model_num_tedges_per_pin(t_spice_model* cur_spice_model,$/;" f -get_sram_orgz_info_mem_model ./fpga_x2p/base/fpga_x2p_utils.c /^void get_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -get_sram_orgz_info_num_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void get_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -get_sram_orgz_info_num_mem_bit ./fpga_x2p/base/fpga_x2p_utils.c /^int get_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info) {$/;" f -get_sram_orgz_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void get_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -get_start_end_points_one_macro ./place/place_macro.c /^void get_start_end_points_one_macro(t_pl_macro pl_macro,$/;" f -get_std_dev ./place/place.c /^static double get_std_dev(int n, double sum_x_squared, double av_x) {$/;" f file: -get_switch_info ./pack/pack.c /^float get_switch_info(short switch_index, float &Tdel_switch, float &R_switch, float &Cout_switch) {$/;" f -get_switch_sdc_tmax ./fpga_x2p/verilog/verilog_sdc.c /^float get_switch_sdc_tmax (t_switch_inf* cur_switch_inf) {$/;" f -get_switch_type ./route/rr_graph2.c /^static void get_switch_type(boolean is_from_sbox, boolean is_to_sbox,$/;" f file: -get_timing_driven_expected_cost ./route/route_timing.c /^static float get_timing_driven_expected_cost(int inode, int target_node,$/;" f file: -get_tnode_block_and_output_net ./timing/path_delay.c /^void get_tnode_block_and_output_net(int inode, int *iblk_ptr, int *inet_ptr) {$/;" f -get_tnode_index ./timing/path_delay.c /^static inline int get_tnode_index(t_tnode * node) {$/;" f file: -get_top_of_heap_index ./util/heapsort.c /^static int get_top_of_heap_index(int *heap, float *sort_values, int heap_tail,$/;" f file: -get_track_num ./base/draw.c /^static int get_track_num(int inode, int **chanx_track, int **chany_track) {$/;" f file: -get_track_to_ipins ./route/rr_graph2.c /^int get_track_to_ipins(int seg, int chan, int track,$/;" f -get_track_to_tracks ./route/rr_graph2.c /^int get_track_to_tracks(INP int from_chan, INP int from_seg, INP int from_track,$/;" f -get_type ./fpga_x2p/base/rr_chan.cpp /^t_rr_type RRChan::get_type() const {$/;" f class:RRChan -get_unidir_opin_connections ./route/rr_graph2.c /^int get_unidir_opin_connections(INP int chan, INP int seg, INP int Fc,$/;" f -get_unidir_track_to_chan_seg ./route/rr_graph2.c /^static int get_unidir_track_to_chan_seg(INP boolean is_end_sb,$/;" f file: -get_unused_spice_model_port_tedge ./fpga_x2p/base/fpga_x2p_timing_utils.c /^t_spice_model_tedge* get_unused_spice_model_port_tedge(t_spice_model_port* cur_port,$/;" f -get_verilog_modelsim_simulation_time_period ./fpga_x2p/verilog/verilog_modelsim_autodeck.c /^float get_verilog_modelsim_simulation_time_period(float time_unit,$/;" f file: -get_wire_L_counter_in_llist ./fpga_x2p/verilog/verilog_report_timing.c /^t_llist* get_wire_L_counter_in_llist(t_llist* rr_path_cnt, $/;" f -get_wired_lut_net_name ./fpga_x2p/base/fpga_x2p_lut_utils.c /^int get_wired_lut_net_name(t_pb_graph_node* lut_pb_graph_node,$/;" f -get_wired_lut_truth_table ./fpga_x2p/base/fpga_x2p_lut_utils.c /^char** get_wired_lut_truth_table() {$/;" f -getcolor ./base/graphics.c /^int getcolor (void) { return 0; }$/;" f -getcolor ./base/graphics.c /^int getcolor() {$/;" f -gfpga_postfix ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* gfpga_postfix = "_gfpga";$/;" v file: -gio_inout_prefix ./fpga_x2p/base/fpga_x2p_globals.c /^char* gio_inout_prefix = "gfpga_pad_";$/;" v -gl_state ./base/graphics.c /^static t_gl_state gl_state = {false, SCREEN, 0};$/;" v file: -global_clocks ./base/ReadOptions.h /^ boolean global_clocks;$/;" m struct:s_options -global_clocks ./base/vpr_types.h /^ boolean global_clocks;$/;" m struct:s_packer_opts -global_ports_head ./fpga_x2p/base/fpga_x2p_globals.c /^t_llist* global_ports_head = NULL;$/;" v -global_route_switch ./base/vpr_types.h /^ short global_route_switch;$/;" m struct:s_det_routing_arch -gr_automode ./base/draw.c /^static int gr_automode; \/* Need user input after: 0: each t, *$/;" v file: -grid ./base/globals.c /^struct s_grid_tile **grid = NULL; \/* [0..(nx+1)][0..(ny+1)] Physical block list *\/$/;" v typeref:struct:s_grid_tile -grid ./base/globals_declare.h /^struct s_grid_tile **grid;$/;" v typeref:struct:s_grid_tile -grid_backup ./place/timing_place_lookup.c /^static struct s_grid_tile **grid_backup;$/;" v typeref:struct:s_grid_tile file: -grid_logic_tile_area ./base/globals.c /^float grid_logic_tile_area = 0;$/;" v -grid_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* grid_spice_file_name_prefix = "grid_";$/;" v -grid_spice_subckt_file_path_head ./fpga_x2p/spice/spice_globals.c /^t_llist* grid_spice_subckt_file_path_head = NULL;$/;" v -grid_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* grid_verilog_file_name_prefix = "grid_";$/;" v -grid_verilog_subckt_file_path_head ./fpga_x2p/verilog/verilog_global.c /^t_llist* grid_verilog_subckt_file_path_head = NULL;$/;" v -group_size ./base/vpr_types.h /^ int group_size;$/;" m struct:s_seg_details -group_start ./base/vpr_types.h /^ int group_start;$/;" m struct:s_seg_details -hAllObjtestDC ./base/graphics.c /^hObjtestDC, hAllObjtestDC; \/* object test *\/$/;" v file: -hBackgroundDC ./base/graphics.c /^static HDC hGraphicsDC, hForegroundDC, hBackgroundDC,$/;" v file: -hButtonsWnd ./base/graphics.c /^static HWND hMainWnd, hGraphicsWnd, hButtonsWnd, hStatusWnd;$/;" v file: -hCurrentDC ./base/graphics.c /^hCurrentDC, \/* WC : double-buffer *\/$/;" v file: -hForegroundDC ./base/graphics.c /^static HDC hGraphicsDC, hForegroundDC, hBackgroundDC,$/;" v file: -hGraphicsBrush ./base/graphics.c /^static HBRUSH hGraphicsBrush, hGrayBrush;$/;" v file: -hGraphicsDC ./base/graphics.c /^static HDC hGraphicsDC, hForegroundDC, hBackgroundDC,$/;" v file: -hGraphicsFont ./base/graphics.c /^static HFONT hGraphicsFont;$/;" v file: -hGraphicsPen ./base/graphics.c /^static HPEN hGraphicsPen;$/;" v file: -hGraphicsWnd ./base/graphics.c /^static HWND hMainWnd, hGraphicsWnd, hButtonsWnd, hStatusWnd;$/;" v file: -hGrayBrush ./base/graphics.c /^static HBRUSH hGraphicsBrush, hGrayBrush;$/;" v file: -hMainWnd ./base/graphics.c /^static HWND hMainWnd, hGraphicsWnd, hButtonsWnd, hStatusWnd;$/;" v file: -hObjtestDC ./base/graphics.c /^hObjtestDC, hAllObjtestDC; \/* object test *\/$/;" v file: -hStatusWnd ./base/graphics.c /^static HWND hMainWnd, hGraphicsWnd, hButtonsWnd, hStatusWnd;$/;" v file: -h_ptr ./util/hash.h /^ struct s_hash *h_ptr;$/;" m struct:s_hash_iterator typeref:struct:s_hash_iterator::s_hash -hack_switch_to_rram ./base/SetupVPR.c /^static void hack_switch_to_rram(struct s_det_routing_arch *det_routing_arch) {$/;" f file: -has_printhandler_pre_vpr ./base/vpr_api.c /^static boolean has_printhandler_pre_vpr = FALSE;$/;" v file: -has_valid_T_arr ./timing/path_delay.c /^static inline boolean has_valid_T_arr(int inode) {$/;" f file: -has_valid_T_req ./timing/path_delay.c /^static inline boolean has_valid_T_req(int inode) {$/;" f file: -has_valid_normalized_T_arr ./timing/path_delay.c /^boolean has_valid_normalized_T_arr(int inode) {$/;" f -hash_value ./util/hash.c /^int hash_value(char *name) {$/;" f -heap ./fpga_x2p/base/fpga_x2p_types.h /^ t_heap **heap; \/* Indexed from [1..heap_size] *\/$/;" m struct:fpga_spice_rr_graph -heap ./route/route_common.c /^static struct s_heap **heap; \/* Indexed from [1..heap_size] *\/$/;" v typeref:struct:s_heap file: -heap_ch ./fpga_x2p/base/fpga_x2p_types.h /^ t_chunk heap_ch;$/;" m struct:fpga_spice_rr_graph -heap_ch ./route/route_common.c /^static t_chunk heap_ch = {NULL, 0, NULL};$/;" v file: -heap_free_head ./fpga_x2p/base/fpga_x2p_types.h /^ t_heap *heap_free_head;$/;" m struct:fpga_spice_rr_graph -heap_free_head ./route/route_common.c /^static struct s_heap *heap_free_head = NULL;$/;" v typeref:struct:s_heap file: -heap_size ./fpga_x2p/base/fpga_x2p_types.h /^ int heap_size; \/* Number of slots in the heap array *\/$/;" m struct:fpga_spice_rr_graph -heap_size ./route/route_common.c /^static int heap_size; \/* Number of slots in the heap array *\/$/;" v file: -heap_tail ./fpga_x2p/base/fpga_x2p_types.h /^ int heap_tail; \/* Index of first unused slot in the heap array *\/$/;" m struct:fpga_spice_rr_graph -heap_tail ./route/route_common.c /^static int heap_tail; \/* Index of first unused slot in the heap array *\/$/;" v file: -heapsort ./util/heapsort.c /^void heapsort(int *sort_index, float *sort_values, int nelem, int start_index) {$/;" f -height ./base/graphics.c /^ int height; $/;" m struct:__anon4 file: -help_opts ./fpga_x2p/shell/cmd_help.h /^t_opt_info help_opts[] = {$/;" v -highlight_blocks ./base/draw.c /^static void highlight_blocks(float x, float y) {$/;" f file: -highlight_crit_path ./base/draw.c /^static void highlight_crit_path(void (*drawscreen_ptr)(void)) {$/;" f file: -highlight_nets ./base/draw.c /^static void highlight_nets(char *message) {$/;" f file: -highlight_rr_nodes ./base/draw.c /^static void highlight_rr_nodes(float x, float y) {$/;" f file: -hill_climbing_flag ./base/ReadOptions.h /^ boolean hill_climbing_flag;$/;" m struct:s_options -hill_climbing_flag ./base/vpr_types.h /^ boolean hill_climbing_flag;$/;" m struct:s_packer_opts -hillgain ./base/vpr_types.h /^ std::map hillgain;$/;" m struct:s_pb_stats -hwnd ./base/graphics.c /^ HWND hwnd;$/;" m struct:__anon4 file: -i ./util/hash.h /^ int i;$/;" m struct:s_hash_iterator -i_ds ./power/power.h /^ float i_ds;$/;" m struct:s_power_nmos_leakage_pair -iblock ./base/vpr_types.h /^ int iblock;$/;" m struct:s_trace -icarus_simulator_flag ./fpga_x2p/verilog/verilog_global.c /^char* icarus_simulator_flag = "ICARUS_SIMULATOR"; \/\/ the flag to enable specific Verilog code in testbenches$/;" v -id_path ./base/vpr_types.h /^ int id_path;$/;" m struct:s_rr_node -identify_mirror_connection_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void identify_mirror_connection_blocks() {$/;" f -identify_mirror_switch_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void identify_mirror_switch_blocks() {$/;" f -identify_rr_node_driver_switch ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void identify_rr_node_driver_switch(t_det_routing_arch RoutingArch,$/;" f file: -ilines ./base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: -in_dens ./power/power.h /^ float * in_dens; \/* Switching density of inputs *\/$/;" m struct:s_rr_node_power -in_flight ./base/vpr_types.h /^ t_cluster_placement_primitive *in_flight; \/* ptrs to primitives currently being considered *\/$/;" m struct:s_cluster_placement_stats -in_prob ./power/power.h /^ float * in_prob; \/* Static probability of inputs *\/$/;" m struct:s_rr_node_power -include_dir ./base/vpr_types.h /^ char* include_dir;$/;" m struct:s_spice_opts -include_icarus_simulator ./base/vpr_types.h /^ boolean include_icarus_simulator;$/;" m struct:s_syn_verilog_opts -include_netlists_include_user_defined_verilog_netlists ./fpga_x2p/verilog/verilog_include_netlists.c /^void include_netlists_include_user_defined_verilog_netlists(FILE* fp,$/;" f file: -include_signal_init ./base/vpr_types.h /^ boolean include_signal_init;$/;" m struct:s_syn_verilog_opts -include_timing ./base/vpr_types.h /^ boolean include_timing;$/;" m struct:s_syn_verilog_opts -index ./base/vpr_types.h /^ int index; \/* Index in array that this block can be found *\/$/;" m struct:s_logical_block -index ./base/vpr_types.h /^ int index;$/;" m struct:s_seg_details -index ./base/vpr_types.h /^ int index;$/;" m struct:s_trace -index ./route/route_common.h /^ int index;$/;" m struct:s_heap -index ./util/hash.h /^ int index;$/;" m struct:s_hash -init_and_check_one_sram_inf_orgz ./fpga_x2p/base/fpga_x2p_setup.c /^void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz,$/;" f file: -init_and_check_sram_inf ./fpga_x2p/base/fpga_x2p_setup.c /^void init_and_check_sram_inf(t_arch* arch,$/;" f file: -init_chan ./base/place_and_route.c /^void init_chan(int cfactor, t_chan_width_dist chan_width_dist) {$/;" f -init_chan_module_ids ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::init_chan_module_ids(t_rr_type chan_type, size_t device_width, size_t device_height) {$/;" f class:DeviceRRChan -init_chan_seg_detail_params ./route/rr_graph_swseg.c /^static int init_chan_seg_detail_params(INP char* chan_type,$/;" f file: -init_check_arch_pb_type_idle_and_phy_mode ./fpga_x2p/base/fpga_x2p_setup.c /^void init_check_arch_pb_type_idle_and_phy_mode(t_arch* Arch) {$/;" f file: -init_check_arch_spice_models ./fpga_x2p/base/fpga_x2p_setup.c /^void init_check_arch_spice_models(t_arch* arch,$/;" f -init_draw_coords ./base/draw.c /^void init_draw_coords(float width_val) {$/;" f -init_graphics ./base/graphics.c /^init_graphics (const char *window_name, int cindex) $/;" f -init_graphics ./base/graphics.c /^void init_graphics (const char *window_name, int cindex) { }$/;" f -init_grids_num_conf_bits ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info) {$/;" f -init_grids_num_iopads ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void init_grids_num_iopads() {$/;" f -init_grids_num_mode_bits ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void init_grids_num_mode_bits() {$/;" f -init_include_user_defined_netlists ./fpga_x2p/spice/spice_utils.c /^void init_include_user_defined_netlists(t_spice spice) {$/;" f -init_include_user_defined_verilog_netlists ./fpga_x2p/verilog/verilog_utils.c /^void init_include_user_defined_verilog_netlists(t_spice spice) {$/;" f -init_list_include_netlists ./fpga_x2p/spice/spice_api.c /^void init_list_include_netlists(t_spice* spice) { $/;" f file: -init_list_include_verilog_netlists ./fpga_x2p/verilog/verilog_utils.c /^void init_list_include_verilog_netlists(t_spice* spice) { $/;" f -init_llist_global_ports ./fpga_x2p/base/fpga_x2p_setup.c /^t_llist* init_llist_global_ports(t_spice* spice) {$/;" f file: -init_llist_verilog_and_spice_syntax_char ./fpga_x2p/base/fpga_x2p_setup.c /^t_llist* init_llist_verilog_and_spice_syntax_char() {$/;" f file: -init_logical_block_spice_model_temp_used ./fpga_x2p/spice/spice_utils.c /^void init_logical_block_spice_model_temp_used(t_spice_model* spice_model) {$/;" f -init_logical_block_spice_model_type_temp_used ./fpga_x2p/spice/spice_utils.c /^void init_logical_block_spice_model_type_temp_used(int num_spice_models, t_spice_model* spice_model,$/;" f -init_mem_bank_info ./fpga_x2p/base/fpga_x2p_utils.c /^void init_mem_bank_info(t_mem_bank_info* cur_mem_bank_info,$/;" f -init_module_ids ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::init_module_ids(size_t device_width, size_t device_height) {$/;" f class:DeviceRRChan -init_mux_arch_default ./power/power_util.c /^static void init_mux_arch_default(t_mux_arch * mux_arch, int levels,$/;" f file: -init_one_cb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void init_one_cb_info(t_cb* cur_cb) { $/;" f -init_one_grid_num_conf_bits ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void init_one_grid_num_conf_bits(int ix, int iy, $/;" f -init_one_grid_num_iopads ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void init_one_grid_num_iopads(int ix, int iy) {$/;" f -init_one_grid_num_mode_bits ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void init_one_grid_num_mode_bits(int ix, int iy) {$/;" f -init_one_rr_node_for_phy_pb_graph_node ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void init_one_rr_node_for_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin,$/;" f -init_one_rr_node_pack_cost_for_phy_graph_node ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void init_one_rr_node_pack_cost_for_phy_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin,$/;" f -init_one_sb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void init_one_sb_info(t_sb* cur_sb) { $/;" f -init_parse ./base/read_blif.c /^static void init_parse(int doall) {$/;" f file: -init_postscript ./base/graphics.c /^int init_postscript (const char *fname) $/;" f -init_postscript ./base/graphics.c /^int init_postscript (const char *fname) { $/;" f -init_reserved_syntax_char ./fpga_x2p/base/fpga_x2p_utils.c /^void init_reserved_syntax_char(t_reserved_syntax_char* cur_reserved_syntax_char,$/;" f -init_route_structs ./route/route_common.c /^void init_route_structs(int bb_factor) {$/;" f -init_route_tree_to_source ./route/route_tree_timing.c /^init_route_tree_to_source(int inet) {$/;" f -init_rr_graph ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void init_rr_graph(INOUTP t_rr_graph* local_rr_graph) {$/;" f -init_rr_nodes_is_parasitic_net ./fpga_x2p/base/fpga_x2p_utils.c /^void init_rr_nodes_is_parasitic_net(int LL_num_rr_nodes,$/;" f -init_rr_nodes_vpack_net_num_changed ./fpga_x2p/base/fpga_x2p_utils.c /^void init_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes,$/;" f -init_scff_info ./fpga_x2p/base/fpga_x2p_utils.c /^void init_scff_info(t_scff_info* cur_scff_info,$/;" f -init_shell_env ./fpga_x2p/shell/mini_shell.c /^void init_shell_env(t_shell_env* env) {$/;" f -init_spice_grid_testbench_globals ./fpga_x2p/spice/spice_grid_testbench.c /^void init_spice_grid_testbench_globals(t_spice spice) {$/;" f file: -init_spice_models_grid_tb_cnt ./fpga_x2p/base/fpga_x2p_utils.c /^void init_spice_models_grid_tb_cnt(int num_spice_models,$/;" f -init_spice_models_tb_cnt ./fpga_x2p/base/fpga_x2p_utils.c /^void init_spice_models_tb_cnt(int num_spice_models,$/;" f -init_spice_mux_arch ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void init_spice_mux_arch(t_spice_model* spice_model,$/;" f -init_spice_mux_testbench_globals ./fpga_x2p/spice/spice_mux_testbench.c /^static void init_spice_mux_testbench_globals(t_spice spice) {$/;" f file: -init_spice_net_info ./fpga_x2p/base/fpga_x2p_utils.c /^void init_spice_net_info(t_spice_net_info* spice_net_info) {$/;" f -init_spice_primitive_testbench_globals ./fpga_x2p/spice/spice_primitive_testbench.c /^void init_spice_primitive_testbench_globals(t_spice spice) {$/;" f file: -init_spice_routing_testbench_globals ./fpga_x2p/spice/spice_routing_testbench.c /^static void init_spice_routing_testbench_globals(t_spice spice) {$/;" f file: -init_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^void init_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -init_sram_orgz_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^void init_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -init_standalone_sram_info ./fpga_x2p/base/fpga_x2p_utils.c /^void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info,$/;" f -init_t ./base/vpr_types.h /^ float init_t;$/;" m struct:s_annealing_sched -init_val ./base/vpr_types.h /^ int init_val;$/;" m struct:s_logical_block -init_world ./base/graphics.c /^init_world (float x1, float y1, float x2, float y2) $/;" f -init_world ./base/graphics.c /^void init_world (float xl, float yt, float xr, float yb) { }$/;" f -initial_placement ./place/place.c /^static void initial_placement(enum e_pad_loc_type pad_loc_type,$/;" f file: -initial_placement_blocks ./place/place.c /^static void initial_placement_blocks(int * free_locations, enum e_pad_loc_type pad_loc_type) {$/;" f file: -initial_placement_pl_macros ./place/place.c /^static void initial_placement_pl_macros(int macros_max_num_tries, int * free_locations) {$/;" f file: -initial_pres_fac ./base/ReadOptions.h /^ float initial_pres_fac;$/;" m struct:s_options -initial_pres_fac ./base/vpr_types.h /^ float initial_pres_fac;$/;" m struct:s_router_opts -initial_simulation_flag ./fpga_x2p/verilog/verilog_global.c /^char* initial_simulation_flag = "INITIAL_SIMULATION"; \/\/ the flag to enable initial functional verification$/;" v -initialized ./base/graphics.c /^ bool initialized;$/;" m struct:__anon5 file: -inner_loop_recompute_divider ./base/ReadOptions.h /^ int inner_loop_recompute_divider;$/;" m struct:s_options -inner_loop_recompute_divider ./base/vpr_types.h /^ int inner_loop_recompute_divider;$/;" m struct:s_placer_opts -inner_num ./base/vpr_types.h /^ float inner_num;$/;" m struct:s_annealing_sched -inode ./route/route_tree_timing.h /^ int inode;$/;" m struct:s_rt_node -inode ./timing/net_delay_types.h /^ int inode;$/;" m struct:s_rc_node -inode_head ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: -input_net_tnodes ./base/vpr_types.h /^ struct s_tnode ***input_net_tnodes; \/* [0..num_input_ports-1][0..num_pins -1] correspnding input net tnode *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_tnode -input_nets ./base/vpr_types.h /^ int **input_nets; \/* [0..num_input_ports-1][0..num_port_pins-1] List of input nets connected to this logical_block. *\/$/;" m struct:s_logical_block -input_pins_used ./base/vpr_types.h /^ int **input_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of input pins of this class that are used *\/$/;" m struct:s_pb_stats -inputs_per_cluster ./base/ReadOptions.h /^ int inputs_per_cluster;$/;" m struct:s_options -insert_buffer ./mrfpga/buffer_insertion.c /^static t_buffer_plan_list insert_buffer( t_buffer_plan_list list, int inode, float C, float R, float Tdel, int num_pins )$/;" f file: -insert_buffer_plan_to_list ./mrfpga/buffer_insertion.c /^static t_buffer_plan_list insert_buffer_plan_to_list( t_buffer_plan plan, t_buffer_plan_list list ) {$/;" f file: -insert_in_edge_list ./route/rr_graph_util.c /^insert_in_edge_list(INP t_linked_edge * head, INP int edge, INP short iswitch) {$/;" f -insert_in_hash_table ./util/hash.c /^insert_in_hash_table(struct s_hash **hash_table, char *name,$/;" f -insert_in_int_list2 ./mrfpga/mrfpga_util.c /^t_linked_int* insert_in_int_list2 (t_linked_int *head, int data )$/;" f -insert_switch_to_buffer_list ./mrfpga/buffer_insertion.c /^static void insert_switch_to_buffer_list( t_buffer_plan_list list, struct s_switch_inf switch_inf_local)$/;" f file: -insert_switch_to_buffer_plan ./mrfpga/buffer_insertion.c /^static t_buffer_plan insert_switch_to_buffer_plan( t_buffer_plan plan, struct s_switch_inf switch_inf_local)$/;" f file: -insert_to_linked_list ./base/verilog_writer.c /^pb_list *insert_to_linked_list(t_pb *pb_new , pb_list *list)$/;" f -insert_to_linked_list_conn ./base/verilog_writer.c /^conn_list *insert_to_linked_list_conn(t_pb *driver_new , t_pb *load_new , t_pb_graph_pin *driver_pin_ , t_pb_graph_pin *load_pin_ , float path_delay , conn_list *list)$/;" f -insert_wire_to_buffer_list ./mrfpga/buffer_insertion.c /^static void insert_wire_to_buffer_list( t_buffer_plan_list list, float C,float R )$/;" f file: -insert_wire_to_buffer_plan ./mrfpga/buffer_insertion.c /^static t_buffer_plan insert_wire_to_buffer_plan( t_buffer_plan plan, float C, float R )$/;" f file: -instantiate_SDF_header ./base/verilog_writer.c /^void instantiate_SDF_header(FILE *SDF)$/;" f -instantiate_input_interconnect ./base/verilog_writer.c /^void instantiate_input_interconnect(FILE *verilog , FILE *SDF , char *clock_name)$/;" f -instantiate_interconnect ./base/verilog_writer.c /^void instantiate_interconnect(FILE *verilog , int block_num , t_pb *pb , FILE *SDF)$/;" f -instantiate_primitive_modules ./base/verilog_writer.c /^void instantiate_primitive_modules(FILE *fp, char *clock_name , FILE *SDF)$/;" f -instantiate_top_level_module ./base/verilog_writer.c /^void instantiate_top_level_module(FILE *verilog)$/;" f -instantiate_wires ./base/verilog_writer.c /^void instantiate_wires(FILE *verilog)$/;" f -int_2_binary_str ./power/power_util.c /^static void int_2_binary_str(char * binary_str, int value, int str_length) {$/;" f file: -inter_cluster_net_delay ./base/ReadOptions.h /^ float inter_cluster_net_delay;$/;" m struct:s_options -inter_cluster_net_delay ./base/vpr_types.h /^ float inter_cluster_net_delay;$/;" m struct:s_packer_opts -interconnect_printing ./base/verilog_writer.c /^void interconnect_printing(FILE *fp , conn_list *downhill)$/;" f -interconnect_type_name ./power/power_util.c /^char * interconnect_type_name(enum e_interconnect type) {$/;" f -intra_cluster_net_delay ./base/ReadOptions.h /^ float intra_cluster_net_delay;$/;" m struct:s_options -intra_cluster_net_delay ./base/vpr_types.h /^ float intra_cluster_net_delay;$/;" m struct:s_packer_opts -inv_capacity ./base/vpr_types.h /^ float inv_capacity;$/;" m struct:s_place_region -inv_length ./base/vpr_types.h /^ float inv_length;$/;" m struct:s_rr_indexed_data -invalid ./base/vpr_types.h /^ t_cluster_placement_primitive *invalid; \/* ptrs to primitives that are invalid *\/$/;" m struct:s_cluster_placement_stats -invalidate_heap_entries ./route/route_common.c /^void invalidate_heap_entries(int sink_node, int ipin_node) {$/;" f -invalidate_rr_graph_heap_entries ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void invalidate_rr_graph_heap_entries(t_rr_graph* local_rr_graph, $/;" f -invalidate_screen ./base/graphics.c /^static void invalidate_screen(void)$/;" f file: -io_line ./base/read_blif.c /^static void io_line(int in_or_out, int doall, t_model *io_model) {$/;" f file: -io_nmos_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* io_nmos_subckt_name = "vpr_io_nmos";$/;" v -io_pmos_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* io_pmos_subckt_name = "vpr_io_pmos";$/;" v -iopad_spice_model ./fpga_x2p/spice/spice_globals.c /^t_spice_model* iopad_spice_model = NULL;$/;" v -iopad_verilog_model ./fpga_x2p/verilog/verilog_global.c /^t_spice_model* iopad_verilog_model = NULL;$/;" v -ipin_mux_trans_size ./base/globals.c /^float ipin_mux_trans_size = 0;$/;" v -ipin_rr_node ./base/vpr_types.h /^ t_rr_node*** ipin_rr_node;$/;" m struct:s_cb -ipin_rr_node ./base/vpr_types.h /^ t_rr_node*** ipin_rr_node;$/;" m struct:s_sb -ipin_rr_node_grid_side ./base/vpr_types.h /^ int** ipin_rr_node_grid_side; \/* We need to record the side of a IPIN, because a IPIN may locate on more than one sides *\/$/;" m struct:s_cb -ipin_rr_node_grid_side ./base/vpr_types.h /^ int** ipin_rr_node_grid_side; \/* We need to record the side of a IPIN, because a IPIN may locate on more than one sides *\/$/;" m struct:s_sb -ipin_rr_nodes_vpack_net_num_changed ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^boolean ipin_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes,$/;" f file: -isEchoFileEnabled ./base/ReadOptions.c /^boolean isEchoFileEnabled(enum e_echo_files echo_option) {$/;" f -isFixed ./base/vpr_types.h /^ boolean isFixed;$/;" m struct:s_block -is_any_but ./timing/slre.c /^static int is_any_but(const unsigned char *p, int len, const char *s,$/;" f file: -is_any_of ./timing/slre.c /^static int is_any_of(const unsigned char *p, int len, const char *s, int *ofs) {$/;" f file: -is_cb_exist ./fpga_x2p/base/fpga_x2p_utils.c /^boolean is_cb_exist(t_rr_type cb_type,$/;" f -is_cbox ./route/rr_graph2.c /^boolean is_cbox(INP int chan, INP int seg, INP int track,$/;" f -is_clock ./base/vpr_types.h /^ boolean is_clock;$/;" m struct:s_logical_block -is_const_gen ./base/vpr_types.h /^ boolean is_const_gen;$/;" m struct:s_net -is_des_rr_node_in_src_rr_node_edges ./route/pb_pin_eq_auto_detect.c /^boolean is_des_rr_node_in_src_rr_node_edges(t_rr_node* src_rr_node,$/;" f -is_done_callibration ./power/PowerSpicedComponent.c /^bool PowerSpicedComponent::is_done_callibration(void) {$/;" f class:PowerSpicedComponent -is_empty_heap ./route/route_common.c /^boolean is_empty_heap(void) {$/;" f -is_forced_connection ./pack/cluster_feasibility_filter.c /^static boolean is_forced_connection(INP t_pb_graph_pin *pb_graph_pin) {$/;" f file: -is_global ./base/globals_declare.h /^boolean *is_global;$/;" v -is_global ./base/vpr_types.h /^ boolean is_global;$/;" m struct:s_net -is_grid_coordinate_in_range ./fpga_x2p/base/fpga_x2p_utils.c /^boolean is_grid_coordinate_in_range(int x_min, $/;" f -is_in_heap ./base/vpr_types.h /^ boolean is_in_heap;$/;" m struct:s_rr_node -is_isolation ./mrfpga/mrfpga_globals.c /^boolean is_isolation = FALSE;$/;" v -is_junction ./mrfpga/mrfpga_globals.c /^boolean is_junction = FALSE;$/;" v -is_logical_blk_in_pb ./pack/cluster.c /^static boolean is_logical_blk_in_pb(int iblk, t_pb *pb) {$/;" f file: -is_mirror ./fpga_x2p/base/rr_chan.cpp /^bool RRChan::is_mirror(RRChan& cand) const {$/;" f class:RRChan -is_mrFPGA ./mrfpga/mrfpga_globals.c /^boolean is_mrFPGA = FALSE;$/;" v -is_net_in_cluster ./pack/cluster_legality.c /^static boolean is_net_in_cluster(INP int inet) {$/;" f file: -is_net_pi ./fpga_x2p/base/fpga_x2p_utils.c /^boolean is_net_pi(t_net* cur_net) {$/;" f -is_netlist_clock ./base/vpr_types.h /^ boolean is_netlist_clock; \/* Is this a netlist or virtual (external) clock? *\/$/;" m struct:s_clock -is_number ./timing/read_sdc.c /^static boolean is_number(char * ptr) {$/;" f file: -is_opin ./util/vpr_utils.c /^boolean is_opin(int ipin, t_type_ptr type) {$/;" f -is_opin_in_direct_list ./route/pb_pin_eq_auto_detect.c /^boolean is_opin_in_direct_list(t_type_ptr cur_type_descriptor,$/;" f -is_opt_set ./fpga_x2p/shell/read_opt.c /^boolean is_opt_set(t_opt_info* opts, char* opt_name, boolean default_val) {$/;" f -is_parasitic_net ./base/vpr_types.h /^ boolean is_parasitic_net;$/;" m struct:s_rr_node -is_pb_used_for_wiring ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^boolean is_pb_used_for_wiring(t_pb_graph_node* cur_pb_graph_node,$/;" f -is_pb_wired_lut ./fpga_x2p/base/fpga_x2p_lut_utils.c /^boolean is_pb_wired_lut(t_pb_graph_node* cur_pb_graph_node,$/;" f -is_pin_open ./pack/cluster_legality.c /^boolean is_pin_open(int i) {$/;" f -is_primitive_pb_type ./fpga_x2p/base/fpga_x2p_utils.c /^boolean is_primitive_pb_type(t_pb_type* cur_pb_type) {$/;" f -is_rr_node_exist_opposite_side_in_sb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^int is_rr_node_exist_opposite_side_in_sb_info(t_sb cur_sb_info,$/;" f -is_rr_node_to_be_disable_for_analysis ./fpga_x2p/verilog/verilog_sdc.c /^boolean is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) {$/;" f -is_sbox ./route/rr_graph2.c /^boolean is_sbox(INP int chan, INP int wire_seg, INP int sb_seg, INP int track,$/;" f -is_show_pass_trans ./mrfpga/mrfpga_globals.c /^boolean is_show_sram = FALSE, is_show_pass_trans = FALSE;$/;" v -is_show_sram ./mrfpga/mrfpga_globals.c /^boolean is_show_sram = FALSE, is_show_pass_trans = FALSE;$/;" v -is_stack ./mrfpga/mrfpga_globals.c /^boolean is_stack = FALSE;$/;" v -is_swap2pins_match_prefer_side ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int is_swap2pins_match_prefer_side(int pin0_cur_side, int* pin0_prefer_side,$/;" f -is_two_cb_rr_nodes_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean is_two_cb_rr_nodes_mirror(t_cb* src_cb, t_cb* des_cb, $/;" f -is_two_connection_blocks_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean is_two_connection_blocks_mirror(t_cb* src, t_cb* des) {$/;" f -is_two_sb_rr_nodes_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean is_two_sb_rr_nodes_mirror(t_sb* src_sb, t_sb* des_sb, int side, $/;" f -is_two_switch_blocks_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean is_two_switch_blocks_mirror(t_sb* src, t_sb* des) {$/;" f -is_type_pin_in_class ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int is_type_pin_in_class(t_type_ptr type,$/;" f -is_verilog_and_spice_syntax_conflict_char ./fpga_x2p/base/fpga_x2p_setup.c /^boolean is_verilog_and_spice_syntax_conflict_char(t_llist* LL_reserved_syntax_char_head, $/;" f file: -is_wire_buffer ./mrfpga/mrfpga_globals.c /^boolean is_wire_buffer = FALSE;$/;" v -is_wired_lut ./fpga_x2p/base/fpga_x2p_types.h /^ boolean* is_wired_lut; \/* Specify if this is a wired LUT (used as buffer) *\/$/;" m struct:fpga_spice_phy_pb -ispressed ./base/graphics.c /^ bool ispressed;$/;" m struct:__anon4 file: -iswitch ./base/vpr_types.h /^ short iswitch;$/;" m struct:s_trace -iswitch ./route/route_tree_timing.h /^ short iswitch;$/;" m struct:s_linked_rt_edge -iswitch ./route/rr_graph_util.h /^ short iswitch;$/;" m struct:s_linked_edge -iswitch ./timing/net_delay_types.h /^ short iswitch;$/;" m struct:s_linked_rc_edge -join_left_plan_list_into_whole ./mrfpga/buffer_insertion.c /^static t_buffer_plan_list join_left_plan_list_into_whole( t_buffer_plan_list left, t_buffer_plan_list* whole, int num_whole, t_buffer_plan_list current, int num_pins )$/;" f file: -keypress_ptr ./base/graphics.c /^static void (*keypress_ptr)(char entered_char);$/;" v file: -label ./fpga_x2p/shell/shell_types.h /^ char* label; $/;" m struct:s_cmd_category -label_incoming_wires ./route/rr_graph2.c /^label_incoming_wires(INP int chan_num, INP int seg_num, INP int sb_seg,$/;" f file: -label_wire_muxes ./route/rr_graph2.c /^label_wire_muxes(INP int chan_num, INP int seg_num,$/;" f file: -label_wire_muxes_for_balance ./route/rr_graph2.c /^label_wire_muxes_for_balance(INP int chan_num, INP int seg_num,$/;" f file: -leakage_gate ./power/power.h /^ float leakage_gate;$/;" m struct:s_transistor_size_inf -leakage_pairs ./power/power.h /^ t_power_nmos_leakage_pair * leakage_pairs;$/;" m struct:s_power_nmos_leakage_inf -leakage_subthreshold ./power/power.h /^ float leakage_subthreshold;$/;" m struct:s_transistor_size_inf -least_slack ./base/vpr_types.h /^ float ** least_slack;$/;" m struct:s_timing_stats -legal_pos ./place/place.c /^static t_legal_pos **legal_pos = NULL; \/* [0..num_types-1][0..type_tsize - 1] *\/$/;" v file: -len ./timing/slre.c /^ int len; \/\/ Substring length$/;" m struct:cap file: -length ./base/vpr_types.h /^ int length;$/;" m struct:s_seg_details -level ./power/power.h /^ int level; \/* Level in the full multilevel mux - 0 = primary inputs to mux *\/$/;" m struct:s_mux_node -level_restorer ./power/power.h /^ boolean level_restorer; \/* Whether the output of this mux is level restored *\/$/;" m struct:s_mux_node -levels ./power/power.h /^ int levels;$/;" m struct:s_mux_arch -library_models ./base/vpr_types.h /^ t_model * library_models; \/* blif models in VPR *\/$/;" m struct:s_vpr_setup -line_fuz ./base/draw.c /^static float line_fuz = 0.3;$/;" v file: -line_types ./base/easygl_constants.h /^enum line_types {SOLID, DASHED};$/;" g -link_one_pb_graph_node_pin_to_phy_pb_graph_pin ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void link_one_pb_graph_node_pin_to_phy_pb_graph_pin(t_pb_graph_pin* cur_pb_graph_pin, $/;" f -link_pb_graph_node_pins_to_phy_pb_graph_pins ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void link_pb_graph_node_pins_to_phy_pb_graph_pins(t_pb_graph_node* cur_pb_graph_node, $/;" f -linked_f_pointer_ch ./fpga_x2p/base/fpga_x2p_types.h /^ t_chunk linked_f_pointer_ch;$/;" m struct:fpga_spice_rr_graph -linked_f_pointer_ch ./route/route_common.c /^static t_chunk linked_f_pointer_ch = {NULL, 0, NULL};$/;" v file: -linked_f_pointer_free_head ./fpga_x2p/base/fpga_x2p_types.h /^ t_linked_f_pointer *linked_f_pointer_free_head;$/;" m struct:fpga_spice_rr_graph -linked_f_pointer_free_head ./route/route_common.c /^static struct s_linked_f_pointer *linked_f_pointer_free_head = NULL;$/;" v typeref:struct:s_linked_f_pointer file: -load_best_buffer_list ./mrfpga/buffer_insertion.c /^void load_best_buffer_list( )$/;" f -load_chan_rr_indices ./route/rr_graph2.c /^static void load_chan_rr_indices(INP int nodes_per_chan, INP int chan_len,$/;" f file: -load_channel_occupancies ./base/stats.c /^static void load_channel_occupancies(int **chanx_occ, int **chany_occ) {$/;" f file: -load_clock_domain_and_clock_and_io_delay ./timing/path_delay.c /^static void load_clock_domain_and_clock_and_io_delay(boolean is_prepacked) {$/;" f file: -load_cluster_placement_stats_for_pb_graph_node ./pack/cluster_placement.c /^static void load_cluster_placement_stats_for_pb_graph_node($/;" f file: -load_constant_net_delay ./timing/net_delay.c /^void load_constant_net_delay(float **net_delay, float delay_value,$/;" f -load_critical_path_annotations ./pack/pb_type_graph_annotations.c /^static void load_critical_path_annotations(INP int line_num, $/;" f file: -load_criticalities ./place/timing_place.c /^void load_criticalities(t_slack * slacks, float crit_exponent) {$/;" f -load_default_models ./base/read_blif.c /^static void load_default_models(INP t_model *library_models,$/;" f file: -load_expected_remapped_net_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^void load_expected_remapped_net_delay(float** net_delay, $/;" f -load_external_nets_and_cb ./base/read_netlist.c /^static void load_external_nets_and_cb(INP int L_num_blocks,$/;" f file: -load_font ./base/graphics.c /^load_font(int pointsize) $/;" f file: -load_internal_cb_nets ./base/read_netlist.c /^static void load_internal_cb_nets(INOUTP t_pb *top_level,$/;" f file: -load_internal_cb_rr_graph_net_nums ./base/read_netlist.c /^static void load_internal_cb_rr_graph_net_nums(INP t_rr_node * cur_rr_node,$/;" f file: -load_legal_placements ./place/place.c /^static void load_legal_placements() {$/;" f file: -load_list_of_connectable_input_pin_ptrs ./pack/cluster_feasibility_filter.c /^static void load_list_of_connectable_input_pin_ptrs($/;" f file: -load_net_delay_from_routing ./timing/net_delay.c /^void load_net_delay_from_routing(float **net_delay, struct s_net *nets,$/;" f -load_net_rr_terminals ./route/rr_graph.c /^void load_net_rr_terminals(t_ivec *** L_rr_node_indices) {$/;" f -load_new_path_R_upstream ./route/route_tree_timing.c /^static void load_new_path_R_upstream(t_rt_node * start_of_new_path_rt_node) {$/;" f file: -load_one_constant_net_delay ./timing/net_delay.c /^void load_one_constant_net_delay(float **net_delay, int inet,$/;" f -load_one_net_delay ./timing/net_delay.c /^void load_one_net_delay(float **net_delay, int inet, struct s_net* nets,$/;" f -load_one_pb_graph_pin_temp_net_num_from_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void load_one_pb_graph_pin_temp_net_num_from_pb(t_phy_pb* cur_pb,$/;" f -load_pack_pattern_annotations ./pack/pb_type_graph_annotations.c /^static void load_pack_pattern_annotations(INP int line_num, INOUTP t_pb_graph_node *pb_graph_node,$/;" f file: -load_pb ./base/verilog_writer.h /^ t_pb *load_pb;$/;" m struct:found_connectivity -load_pb_graph_node_temp_net_num_from_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void load_pb_graph_node_temp_net_num_from_pb(t_phy_pb* cur_pb) {$/;" f -load_pb_graph_pin_to_pin_annotations ./pack/pb_type_graph_annotations.c /^void load_pb_graph_pin_to_pin_annotations(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f -load_perturbed_switch_pattern ./route/rr_graph.c /^static void load_perturbed_switch_pattern(INP t_type_ptr type,$/;" f file: -load_pin ./base/verilog_writer.h /^ t_pb_graph_pin *load_pin;$/;" m struct:found_connectivity -load_pin_class_by_depth ./pack/cluster_feasibility_filter.c /^static void load_pin_class_by_depth(INOUTP t_pb_graph_node *pb_graph_node,$/;" f file: -load_pin_classes_in_pb_graph_head ./pack/cluster_feasibility_filter.c /^void load_pin_classes_in_pb_graph_head(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f -load_post_place_net_delay ./fpga_x2p/clb_pin_remap/post_place_timing.c /^void load_post_place_net_delay(float** net_delay,$/;" f -load_rc_tree_C ./timing/net_delay.c /^float load_rc_tree_C(t_rc_node * rc_node) {$/;" f -load_rc_tree_Ctotal ./mrfpga/cal_capacitance.c /^static float load_rc_tree_Ctotal (t_rc_node *rc_node) {$/;" f file: -load_rc_tree_T ./timing/net_delay.c /^void load_rc_tree_T(t_rc_node * rc_node, float T_arrival) {$/;" f -load_route_bb ./route/route_common.c /^static void load_route_bb(int bb_factor) {$/;" f file: -load_rr_graph_chan_rr_indices ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void load_rr_graph_chan_rr_indices(t_rr_graph* local_rr_graph,$/;" f -load_rr_indexed_data_T_values ./route/rr_graph_indexed_data.c /^static void load_rr_indexed_data_T_values(int index_start,$/;" f file: -load_rr_indexed_data_base_costs ./route/rr_graph_indexed_data.c /^static void load_rr_indexed_data_base_costs(int nodes_per_chan,$/;" f file: -load_rt_subtree_Tdel ./route/route_tree_timing.c /^static void load_rt_subtree_Tdel(t_rt_node * subtree_rt_root, float Tarrival) {$/;" f file: -load_sblock_pattern_lookup ./route/rr_graph2.c /^void load_sblock_pattern_lookup(INP int i, INP int j, INP int nodes_per_chan,$/;" f -load_simplified_device ./place/timing_place_lookup.c /^static void load_simplified_device(void) {$/;" f file: -load_timing_graph_net_delays ./timing/path_delay.c /^void load_timing_graph_net_delays(float **net_delay) {$/;" f -load_tnode ./timing/path_delay.c /^static void load_tnode(INP t_pb_graph_pin *pb_graph_pin, INP int iblock,$/;" f file: -load_truth_table ./base/verilog_writer.c /^char *load_truth_table(int inputs , t_pb *pb)$/;" f -load_uniform_switch_pattern ./route/rr_graph.c /^static void load_uniform_switch_pattern(INP t_type_ptr type,$/;" f file: -load_wired_lut_pbs ./fpga_x2p/base/fpga_x2p_lut_utils.c /^void load_wired_lut_pbs(t_pb* lut_pb,$/;" f -local_cross_count ./fpga_x2p/clb_pin_remap/post_place_timing.c /^static const float local_cross_count[50] = { \/* [0..49] *\/1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974,$/;" v file: -local_nets ./base/vpr_types.h /^ struct s_net *local_nets; \/* Records post-packing connections, valid only for top-level *\/$/;" m struct:s_pb typeref:struct:s_pb::s_net -log_msg ./power/power_util.c /^static void log_msg(t_log * log_ptr, char * msg) {$/;" f file: -logic_block_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* logic_block_spice_file_name = "grid_header.sp";$/;" v -logic_block_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* logic_block_verilog_file_name = "logic_blocks.v";$/;" v -logical_block ./base/globals.c /^struct s_logical_block *logical_block = NULL;$/;" v typeref:struct:s_logical_block -logical_block ./base/vpr_types.h /^ int logical_block; \/* If this is a terminating pb, gives the logical (netlist) block that it contains *\/$/;" m struct:s_pb -logical_block ./fpga_x2p/base/fpga_x2p_types.h /^ int* logical_block; \/* If this is a terminating pb, gives the logical (netlist) block that it contains *\/$/;" m struct:fpga_spice_phy_pb -logical_block_input_count ./base/read_blif.c /^static int *logical_block_input_count, *logical_block_output_count;$/;" v file: -logical_block_output_count ./base/read_blif.c /^static int *logical_block_input_count, *logical_block_output_count;$/;" v file: -logical_block_ptrs ./base/vpr_types.h /^ t_logical_block **logical_block_ptrs; \/* [0..num_blocks-1] ptrs to logical blocks that implements this molecule, index on pack_pattern_block->index of pack pattern *\/$/;" m struct:s_pack_molecule -logical_block_types ./base/vpr_types.h /^enum logical_block_types {$/;" g -logs ./power/power.h /^ t_log * logs;$/;" m struct:s_power_output -long_trans_inf ./power/power.h /^ t_transistor_size_inf * long_trans_inf; \/* Long transistor (W=1,L=2) *\/$/;" m struct:s_transistor_inf -longest_path_only ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean longest_path_only;$/;" m struct:s_trpt_opts file: -longline ./base/vpr_types.h /^ boolean longline;$/;" m struct:s_seg_details -lookahead_input_pins_used ./base/vpr_types.h /^ int **lookahead_input_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of input pins of this class that are speculatively used *\/$/;" m struct:s_pb_stats -lookahead_output_pins_used ./base/vpr_types.h /^ int **lookahead_output_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of output pins of this class that are speculatively used *\/$/;" m struct:s_pb_stats -lookup_dump ./place/timing_place_lookup.c /^static FILE *lookup_dump; \/* If debugging mode is on, print out to$/;" v file: -loop_greedy ./timing/slre.c /^static void loop_greedy(const struct slre *r, int pc, const char *s, int len,$/;" f file: -loop_non_greedy ./timing/slre.c /^static void loop_non_greedy(const struct slre *r, int pc, const char *s,$/;" f file: -lowercase ./timing/slre.c /^static int lowercase(const char *s) {$/;" f file: -lut_output_pb_graph_pin ./fpga_x2p/base/fpga_x2p_types.h /^ t_pb_graph_pin** lut_output_pb_graph_pin;$/;" m struct:fpga_spice_phy_pb -lut_pin_remap ./base/vpr_types.h /^ int *lut_pin_remap; \/* [0..num_lut_inputs-1] applies only to LUT primitives, stores how LUT inputs were swapped during CAD flow, $/;" m struct:s_pb -lut_pin_remap ./fpga_x2p/base/fpga_x2p_types.h /^ int *lut_pin_remap; \/* [0..num_lut_inputs-1] applies only to LUT primitives, stores how LUT inputs were swapped during CAD flow, $/;" m struct:fpga_spice_phy_pb -lut_size ./base/ReadOptions.h /^ int lut_size;$/;" m struct:s_options -lut_size ./fpga_x2p/base/fpga_x2p_types.h /^ int* lut_size;$/;" m struct:fpga_spice_phy_pb -luts_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* luts_spice_file_name = "luts.sp";$/;" v -luts_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* luts_verilog_file_name = "luts.v";$/;" v -main ./main.c /^int main(int argc, char **argv) {$/;" f -main ./shell_main.c /^int main(int argc, char ** argv) {$/;" f -main main.c /^int main(int argc, char **argv) {$/;" f -main shell_main.c /^int main(int argc, char ** argv) {$/;" f -main_best_buffer_list ./mrfpga/mrfpga_globals.c /^t_linked_int* main_best_buffer_list;$/;" v -mandatory ./fpga_x2p/shell/read_opt_types.h /^ enum opt_manda mandatory;$/;" m struct:s_opt_info typeref:enum:s_opt_info::opt_manda -map_button ./base/graphics.c /^static void map_button (int bnum) $/;" f file: -map_loop_breaker_onto_edges ./pack/pb_type_graph.c /^static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,$/;" f file: -map_pb_type_port_to_spice_model_ports ./fpga_x2p/base/fpga_x2p_setup.c /^int map_pb_type_port_to_spice_model_ports(t_pb_type* cur_pb_type,$/;" f file: -mapped_spice_model ./base/vpr_types.h /^ t_spice_model* mapped_spice_model;$/;" m struct:s_logical_block -mapped_spice_model_index ./base/vpr_types.h /^ int mapped_spice_model_index; \/* index of spice_model in completed FPGA netlist *\/$/;" m struct:s_logical_block -mark_and_update_partial_gain ./pack/cluster.c /^static void mark_and_update_partial_gain(int inet, enum e_gain_update gain_flag,$/;" f file: -mark_blk_pins_nets_sink_index ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void mark_blk_pins_nets_sink_index(int n_nets, t_net* nets,$/;" f -mark_constant_generators ./base/read_netlist.c /^static void mark_constant_generators(INP int L_num_blocks,$/;" f file: -mark_constant_generators_rec ./base/read_netlist.c /^static void mark_constant_generators_rec(INP t_pb *pb, INP t_rr_node *rr_graph,$/;" f file: -mark_direct_of_pins ./util/vpr_utils.c /^static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, $/;" f file: -mark_direct_of_ports ./util/vpr_utils.c /^static void mark_direct_of_ports (int idirect, int direct_type, char * pb_type_name, $/;" f file: -mark_ends ./route/route_common.c /^void mark_ends(int inet) {$/;" f -mark_ends_cluster ./pack/cluster_legality.c /^static void mark_ends_cluster(int inet) {$/;" f file: -mark_grid_type_pb_graph_node_pins_temp_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void mark_grid_type_pb_graph_node_pins_temp_net_num(int x, int y) {$/;" f -mark_node_expansion_by_bin ./route/route_timing.c /^static int mark_node_expansion_by_bin(int inet, int target_node,$/;" f file: -mark_one_pb_parasitic_nets ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void mark_one_pb_parasitic_nets(t_phy_pb* cur_pb) {$/;" f -mark_pb_graph_node_clock_pins_temp_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void mark_pb_graph_node_clock_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node,$/;" f -mark_pb_graph_node_input_pins_temp_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void mark_pb_graph_node_input_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node,$/;" f -mark_pb_graph_node_output_pins_temp_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void mark_pb_graph_node_output_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node,$/;" f -mark_rr_graph_ends ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void mark_rr_graph_ends(t_rr_graph* local_rr_graph, $/;" f -mark_rr_graph_sinks ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void mark_rr_graph_sinks(t_rr_graph* local_rr_graph, $/;" f -mark_vpack_net_used_in_pb ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void mark_vpack_net_used_in_pb(t_pb* cur_op_pb,$/;" f -mark_vpack_net_used_in_pb_pin ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void mark_vpack_net_used_in_pb_pin(t_pb* cur_op_pb, t_pb_graph_pin* cur_pb_graph_pin,$/;" f -marked_blocks ./base/vpr_types.h /^ int *marked_nets, *marked_blocks;$/;" m struct:s_pb_stats -marked_nets ./base/vpr_types.h /^ int *marked_nets, *marked_blocks;$/;" m struct:s_pb_stats -match ./timing/slre.c /^static const char *match(const struct slre *r, int pc, const char *s, int len,$/;" f file: -match2 ./timing/slre.c /^static const char *match2(const struct slre *r, const char *buf, int len,$/;" f file: -match_pb_types_spice_model_rec ./fpga_x2p/base/fpga_x2p_setup.c /^void match_pb_types_spice_model_rec(t_pb_type* cur_pb_type,$/;" f file: -match_pb_types_verilog_model_rec ./fpga_x2p/verilog/verilog_pbtypes.c /^void match_pb_types_verilog_model_rec(t_pb_type* cur_pb_type,$/;" f -match_registers ./fpga_x2p/verilog/verilog_formality_autodeck.c /^static void match_registers(FILE *fp, char* chomped_circuit_name) {$/;" f file: -max ./base/graphics.c 171;" d file: -max ./mrfpga/mrfpga_util.h 6;" d -max_IPIN_fanin ./power/power.h /^ int max_IPIN_fanin;$/;" m struct:s_power_commonly_used -max_buffer_size ./power/power.h /^ int max_buffer_size;$/;" m struct:s_power_tech -max_criticality ./base/ReadOptions.h /^ float max_criticality;$/;" m struct:s_options -max_criticality ./base/vpr_types.h /^ float max_criticality;$/;" m struct:s_router_opts -max_ext_index ./pack/cluster_legality.c /^ ext_clock_rr_node_index, max_ext_index;$/;" v file: -max_index ./route/rr_graph.c /^ int max_index;$/;" m struct:s_mux_size_distribution file: -max_len_pl_macros ./place/place_macro.c /^int max_len_pl_macros(int num_pl_macros, $/;" f -max_mux_sl_size ./power/power.h /^ int max_mux_sl_size;$/;" m struct:s_power_nmos_mux_inf -max_pins_per_side ./mrfpga/mrfpga_globals.c /^int max_pins_per_side;$/;" v -max_router_iterations ./base/ReadOptions.h /^ int max_router_iterations;$/;" m struct:s_options -max_router_iterations ./base/vpr_types.h /^ int max_router_iterations;$/;" m struct:s_router_opts -max_routing_mux_size ./power/power.h /^ int max_routing_mux_size;$/;" m struct:s_power_commonly_used -max_seg_fanout ./power/power.h /^ int max_seg_fanout;$/;" m struct:s_power_commonly_used -max_seg_to_IPIN_fanout ./power/power.h /^ int max_seg_to_IPIN_fanout;$/;" m struct:s_power_commonly_used -max_seg_to_seg_fanout ./power/power.h /^ int max_seg_to_seg_fanout;$/;" m struct:s_power_commonly_used -max_sim_num_clock_cycles ./fpga_x2p/spice/spice_grid_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: -max_sim_num_clock_cycles ./fpga_x2p/spice/spice_mux_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: -max_sim_num_clock_cycles ./fpga_x2p/spice/spice_primitive_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: -max_sim_num_clock_cycles ./fpga_x2p/spice/spice_routing_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: -max_width_per_trans ./fpga_x2p/spice/spice_globals.c /^float max_width_per_trans = 5.;$/;" v -meas_header_file_name ./fpga_x2p/spice/spice_globals.c /^char* meas_header_file_name = "meas_params.sp";$/;" v -members ./place/place_macro.h /^ t_pl_macro_member* members;$/;" m struct:s_pl_macro -memories_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* memories_verilog_file_name = "memories.v";$/;" v -memory_pool ./pack/cluster.c /^static struct s_molecule_link *memory_pool; \/*Declared here so I can free easily.*\/$/;" v typeref:struct:s_molecule_link file: -memristor_inf ./mrfpga/mrfpga_globals.c /^t_memristor_inf memristor_inf;$/;" v -menu ./base/graphics.c /^static Window toplevel, menu, textarea; \/* various windows *\/$/;" v file: -menu_font_size ./base/graphics.c /^static const int menu_font_size = 12; \/* Font for menus and dialog boxes. *\/$/;" v file: -menutext ./base/graphics.c /^static void menutext(Window win, int xc, int yc, const char *text) $/;" f file: -messages ./power/power.h /^ char ** messages;$/;" m struct:s_log -meta_characters ./timing/slre.c /^static const char *meta_characters = "|.*+?()[\\\\";$/;" v file: -min ./base/graphics.c 174;" d file: -min ./mrfpga/mrfpga_util.h 10;" d -mirror ./base/vpr_types.h /^ t_cb* mirror; \/* an exact mirror of this connection block, with same connection & switches *\/$/;" m struct:s_cb -mirror ./base/vpr_types.h /^ t_sb* mirror; \/* an exact mirror of this switch block, with same connection & switches *\/$/;" m struct:s_sb -mode ./base/vpr_types.h /^ int mode; \/* mode that this pb is set to *\/$/;" m struct:s_pb -mode ./fpga_x2p/base/fpga_x2p_types.h /^ int mode; \/* mode that this pb is set to *\/$/;" m struct:fpga_spice_phy_pb -mode_bits ./fpga_x2p/base/fpga_x2p_types.h /^ char* mode_bits; \/* Mode bits for the logical block *\/$/;" m struct:fpga_spice_phy_pb -model ./base/read_blif.c /^ t_model * model;$/;" m struct:s_model_stats file: -model ./base/read_blif.c /^static char *model = NULL;$/;" v file: -model ./base/vpr_types.h /^ t_model* model; \/* Technology-mapped type (eg. LUT, Flip-flop, memory slice, inpad, etc) *\/$/;" m struct:s_logical_block -model_lines ./base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: -model_pin ./base/vpr_types.h /^ int model_port, model_pin; \/* technology mapped model pin *\/$/;" m struct:s_prepacked_tnode_data -model_port ./base/vpr_types.h /^ int model_port, model_pin; \/* technology mapped model pin *\/$/;" m struct:s_prepacked_tnode_data -model_port_ptr ./base/vpr_types.h /^ t_model_ports *model_port_ptr;$/;" m struct:s_prepacked_tnode_data -modelsim_autocheck_testbench_module_postfix ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_autocheck_testbench_module_postfix = "_autocheck_top_tb";$/;" v -modelsim_include_user_defined_verilog_netlists ./fpga_x2p/verilog/verilog_modelsim_autodeck.c /^void modelsim_include_user_defined_verilog_netlists(FILE* fp,$/;" f file: -modelsim_ini_path ./base/vpr_types.h /^ char* modelsim_ini_path;$/;" m struct:s_syn_verilog_opts -modelsim_proc_script_name_postfix ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_proc_script_name_postfix = "_proc.tcl";$/;" v -modelsim_project_name_postfix ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_project_name_postfix = "_fpga_msim";$/;" v -modelsim_simulation_time_unit ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_simulation_time_unit = "ms";$/;" v -modelsim_testbench_module_postfix ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_testbench_module_postfix = "_top_tb";$/;" v -modelsim_top_script_name_postfix ./fpga_x2p/verilog/verilog_global.c /^char* modelsim_top_script_name_postfix = "_runsim.tcl";$/;" v -moleculeptr ./pack/cluster.c /^ t_pack_molecule *moleculeptr;$/;" m struct:s_molecule_link file: -mouseclick_ptr ./base/graphics.c /^static void (*mouseclick_ptr)(float x, float y);$/;" v file: -mousemove_ptr ./base/graphics.c /^static void (*mousemove_ptr)(float x, float y);$/;" v file: -moved_blocks ./place/place.c /^ t_pl_moved_block * moved_blocks;$/;" m struct:s_pl_blocks_to_be_moved file: -multilevel_mux_last_level_input_num ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit,$/;" f -mux_arch ./power/power.h /^ t_mux_arch * mux_arch;$/;" m struct:s_power_mux_info -mux_arch_fix_levels ./power/power_util.c /^void mux_arch_fix_levels(t_mux_arch * mux_arch) {$/;" f -mux_arch_max_size ./power/power.h /^ int mux_arch_max_size;$/;" m struct:s_power_mux_info -mux_basis_posfix ./fpga_x2p/spice/spice_globals.c /^char* mux_basis_posfix = "_basis";$/;" v -mux_count ./route/rr_graph.c /^ int mux_count;$/;" m struct:s_mux_size_distribution file: -mux_find_selector_values ./power/power_util.c /^boolean mux_find_selector_values(int * selector_values, t_mux_node * mux_node,$/;" f -mux_graph_head ./power/power.h /^ t_mux_node * mux_graph_head;$/;" m struct:s_mux_arch -mux_info ./power/power.h /^ std::map mux_info;$/;" m struct:s_power_commonly_used -mux_size ./power/power.h /^ int mux_size;$/;" m struct:s_power_buffer_sc_levr_inf -mux_special_basis_posfix ./fpga_x2p/spice/spice_globals.c /^char* mux_special_basis_posfix = "_special_basis";$/;" v -mux_voltage_inf ./power/power.h /^ t_power_mux_volt_inf * mux_voltage_inf;$/;" m struct:s_power_nmos_mux_inf -mux_voltage_pairs ./power/power.h /^ t_power_mux_volt_pair * mux_voltage_pairs;$/;" m struct:s_power_mux_volt_inf -muxes_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* muxes_spice_file_name = "muxes.sp";$/;" v -muxes_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* muxes_verilog_file_name = "muxes.v";$/;" v -my_atof_2D ./util/token.c /^void my_atof_2D(INOUTP float **matrix, INP int max_i, INP int max_j,$/;" f -my_decimal2binary ./fpga_x2p/base/fpga_x2p_utils.c /^int* my_decimal2binary(int decimal,$/;" f -my_gettime ./fpga_x2p/base/fpga_x2p_utils.c /^char* my_gettime() {$/;" f -my_itoa ./fpga_x2p/base/fpga_x2p_utils.c /^char* my_itoa(int input) {$/;" f -my_itobin ./fpga_x2p/base/fpga_x2p_utils.c /^char* my_itobin(int in_int, int bin_len) {$/;" f -my_malloc ./base/graphics.c /^static void *my_malloc(int ibytes) {$/;" f file: -my_realloc ./base/graphics.c /^static void *my_realloc(void *memblk, int ibytes) {$/;" f file: -my_remove_file ./fpga_x2p/base/fpga_x2p_utils.c /^void my_remove_file(char* file_path) {$/;" f -my_strcat ./fpga_x2p/base/fpga_x2p_utils.c /^char* my_strcat(char* str1,$/;" f -my_strcmp ./fpga_x2p/shell/shell_utils.c /^int my_strcmp(char* str1, char* str2) {$/;" f -my_strlen_int ./fpga_x2p/base/fpga_x2p_utils.c /^int my_strlen_int(int input_int) {$/;" f -name ./base/vpr_types.h /^ char * name; \/* I\/O port name with an SDC constraint *\/$/;" m struct:s_io -name ./base/vpr_types.h /^ char * name;$/;" m struct:s_clock -name ./base/vpr_types.h /^ char *name; \/* Name of this physical block *\/$/;" m struct:s_pb -name ./base/vpr_types.h /^ char *name; \/* Taken from the first vpack_net which it drives. *\/$/;" m struct:s_logical_block -name ./base/vpr_types.h /^ char *name;$/;" m struct:s_block -name ./base/vpr_types.h /^ char *name;$/;" m struct:s_net -name ./base/vpr_types.h /^ char* name;$/;" m struct:s_clb_to_clb_directs -name ./fpga_x2p/base/fpga_x2p_types.h /^ char *name; \/* Name of this physical block *\/$/;" m struct:fpga_spice_phy_pb -name ./fpga_x2p/shell/read_opt_types.h /^ char* name; \/*The name of option*\/$/;" m struct:s_opt_info -name ./fpga_x2p/shell/read_opt_types.h /^ char* name;$/;" m struct:s_cmd_info -name ./fpga_x2p/shell/shell_types.h /^ char* name;$/;" m struct:s_shell_cmd -name ./fpga_x2p/shell/shell_types.h /^ e_cmd_category name;$/;" m struct:s_cmd_category -name ./power/power.h /^ char * name;$/;" m struct:s_log -name ./timing/read_sdc.c /^ char * name;$/;" m struct:s_sdc_clock file: -name ./util/hash.h /^ char *name;$/;" m struct:s_hash -name_mux ./base/vpr_types.h /^ char* name_mux;$/;" m struct:s_rr_node -name_type ./base/draw.c /^static const char *name_type[] = { "SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY",$/;" v file: -net ./base/globals_declare.h /^struct s_net *net;$/;" v typeref:struct:s_net -net ./fpga_x2p/base/fpga_x2p_types.h /^ t_net** net; \/* nets to route, this is pointer to the existing nets *\/$/;" m struct:fpga_spice_rr_graph -net_cnt ./route/pb_pin_eq_auto_detect.c /^ int net_cnt;$/;" m struct:s_num_mapped_opins_stats file: -net_color ./base/draw.c /^static enum color_types *net_color, *block_color;$/;" v typeref:enum:color_types file: -net_cost ./place/place.c /^static float *net_cost = NULL, *temp_net_cost = NULL; \/* [0..num_nets-1] *\/$/;" v file: -net_delay ./place/timing_place_lookup.c /^static float **net_delay;$/;" v file: -net_delay_ch ./place/timing_place.c /^static t_chunk net_delay_ch = {NULL, 0, NULL};$/;" v file: -net_num ./base/vpr_types.h /^ int net_num;$/;" m struct:s_rr_node -net_num_in_pack ./base/vpr_types.h /^ int net_num_in_pack;$/;" m struct:s_rr_node -net_num_sinks ./fpga_x2p/base/fpga_x2p_types.h /^ int* net_num_sinks;$/;" m struct:fpga_spice_rr_graph -net_num_sources ./fpga_x2p/base/fpga_x2p_types.h /^ int* net_num_sources;$/;" m struct:fpga_spice_rr_graph -net_output_feeds_driving_block_input ./pack/cluster.c /^static int *net_output_feeds_driving_block_input;$/;" v file: -net_pin_index ./place/place.c /^static int **net_pin_index = NULL;$/;" v file: -net_power ./base/vpr_types.h /^ t_net_power * net_power;$/;" m struct:s_net -net_rr_sinks ./fpga_x2p/base/fpga_x2p_types.h /^ int **net_rr_sinks; \/* [0..num_nets-1][0..num_pins-1] *\/$/;" m struct:fpga_spice_rr_graph -net_rr_sources ./fpga_x2p/base/fpga_x2p_types.h /^ int **net_rr_sources; \/* [0..num_nets-1][0..num_pins-1] *\/$/;" m struct:fpga_spice_rr_graph -net_rr_terminals ./base/globals.c /^int **net_rr_terminals = NULL; \/* [0..num_nets-1][0..num_pins-1] *\/$/;" v -net_rr_terminals ./base/globals_declare.h /^int **net_rr_terminals; \/* [0..num_nets-1][0..num_pins-1] *\/$/;" v -net_rr_terminals ./fpga_x2p/base/fpga_x2p_types.h /^ int **net_rr_terminals; \/* [0..num_nets-1][0..num_pins-1] *\/$/;" m struct:fpga_spice_rr_graph -net_to_vpack_net_mapping ./fpga_x2p/base/fpga_x2p_types.h /^ int* net_to_vpack_net_mapping;$/;" m struct:fpga_spice_rr_graph -netlist_clocks ./timing/read_sdc.c /^char ** netlist_clocks; \/* [0..num_netlist_clocks - 1] array of names of clocks in netlist *\/$/;" v -netlist_ios ./timing/read_sdc.c /^char ** netlist_ios; \/* [0..num_netlist_clocks - 1] array of names of ios in netlist *\/$/;" v -nets ./base/vpr_types.h /^ int *nets;$/;" m struct:s_block -nets_in_cluster ./pack/cluster_legality.c /^static int *nets_in_cluster; \/* [0..num_nets_in_cluster-1] *\/$/;" v file: -nets_sink_index ./base/vpr_types.h /^ int* nets_sink_index;$/;" m struct:s_block -next ./base/place_and_route.h /^ struct s_fmap_cell *next;$/;" m struct:s_fmap_cell typeref:struct:s_fmap_cell::s_fmap_cell -next ./base/verilog_writer.h /^ struct found_connectivity *next;$/;" m struct:found_connectivity typeref:struct:found_connectivity::found_connectivity -next ./base/verilog_writer.h /^ struct found_pins *next;$/;" m struct:found_pins typeref:struct:found_pins::found_pins -next ./base/vpr_types.h /^ struct s_linked_f_pointer *next;$/;" m struct:s_linked_f_pointer typeref:struct:s_linked_f_pointer::s_linked_f_pointer -next ./base/vpr_types.h /^ struct s_pack_molecule *next;$/;" m struct:s_pack_molecule typeref:struct:s_pack_molecule::s_pack_molecule -next ./base/vpr_types.h /^ struct s_trace *next;$/;" m struct:s_trace typeref:struct:s_trace::s_trace -next ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" m struct:s_buffer_plan_node typeref:struct:s_buffer_plan_node::s_buffer_plan_node file: -next ./pack/cluster.c /^ struct s_molecule_link *next;$/;" m struct:s_molecule_link typeref:struct:s_molecule_link::s_molecule_link file: -next ./route/route_common.h /^ struct s_heap *next;$/;" m union:s_heap::__anon14 typeref:struct:s_heap::__anon14::s_heap -next ./route/route_tree_timing.h /^ struct s_rt_node *next;$/;" m union:s_rt_node::__anon16 typeref:struct:s_rt_node::__anon16::s_rt_node -next ./route/route_tree_timing.h /^ struct s_linked_rt_edge *next;$/;" m struct:s_linked_rt_edge typeref:struct:s_linked_rt_edge::s_linked_rt_edge -next ./route/rr_graph.c /^ struct s_mux *next;$/;" m struct:s_mux typeref:struct:s_mux::s_mux file: -next ./route/rr_graph.c /^ struct s_mux_size_distribution *next;$/;" m struct:s_mux_size_distribution typeref:struct:s_mux_size_distribution::s_mux_size_distribution file: -next ./route/rr_graph_util.h /^ struct s_linked_edge *next;$/;" m struct:s_linked_edge typeref:struct:s_linked_edge::s_linked_edge -next ./timing/net_delay_types.h /^ struct s_rc_node *next;$/;" m union:s_rc_node::__anon18 typeref:struct:s_rc_node::__anon18::s_rc_node -next ./timing/net_delay_types.h /^ struct s_linked_rc_edge *next;$/;" m struct:s_linked_rc_edge typeref:struct:s_linked_rc_edge::s_linked_rc_edge -next ./timing/net_delay_types.h /^ struct s_linked_rc_ptr *next;$/;" m struct:s_linked_rc_ptr typeref:struct:s_linked_rc_ptr::s_linked_rc_ptr -next ./util/hash.h /^ struct s_hash *next;$/;" m struct:s_hash typeref:struct:s_hash::s_hash -nmos_leakage_info ./power/power.h /^ t_power_nmos_leakage_inf * nmos_leakage_info;$/;" m struct:s_power_tech -nmos_mux_info ./power/power.h /^ t_power_nmos_mux_inf * nmos_mux_info;$/;" m struct:s_power_tech -nmos_pmos_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* nmos_pmos_spice_file_name = "nmos_pmos.sp";$/;" v -nmos_size ./power/power.h /^ float nmos_size;$/;" m struct:s_power_nmos_leakage_inf -nmos_size ./power/power.h /^ float nmos_size;$/;" m struct:s_power_nmos_mux_inf -nmos_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* nmos_subckt_name = "vpr_nmos";$/;" v -node_block ./base/vpr_types.h /^ int *node_block;$/;" m struct:s_net -node_block_pin ./base/vpr_types.h /^ int *node_block_pin;$/;" m struct:s_net -node_block_port ./base/vpr_types.h /^ int *node_block_port;$/;" m struct:s_net -node_segments_ ./fpga_x2p/base/rr_chan.h /^ std::vector node_segments_; \/* segment of each track *\/$/;" m class:RRChan -node_to_heap ./route/route_common.c /^void node_to_heap(int inode, float cost, int prev_node, int prev_edge,$/;" f -nodes_ ./fpga_x2p/base/rr_chan.h /^ std::vector nodes_; \/* rr nodes of each track in the channel *\/$/;" m class:RRChan -normalized_T_arr ./base/vpr_types.h /^ float normalized_T_arr; \/* arrival time (normalized with respect to max time) *\/$/;" m struct:s_prepacked_tnode_data -normalized_slack ./base/vpr_types.h /^ float normalized_slack; \/* slack (normalized with respect to max slack) *\/$/;" m struct:s_prepacked_tnode_data -normalized_total_critical_paths ./base/vpr_types.h /^ float normalized_total_critical_paths; \/* critical path count (normalized with respect to max count) *\/$/;" m struct:s_prepacked_tnode_data -num_blif_models ./base/read_blif.c /^static int num_blif_models;$/;" v file: -num_blocks ./base/globals.c /^int num_blocks = 0;$/;" v -num_blocks ./base/globals_declare.h /^int num_nets, num_blocks;$/;" v -num_blocks ./base/vpr_types.h /^ int num_blocks; \/* number of logical blocks of molecule *\/$/;" m struct:s_pack_molecule -num_blocks ./place/place_macro.h /^ int num_blocks;$/;" m struct:s_pl_macro -num_buttons ./base/graphics.c /^static int num_buttons = 0; \/* Number of menu buttons *\/$/;" v file: -num_caps ./timing/slre.c /^ int num_caps; \/\/ Number of bracket pairs$/;" m struct:slre file: -num_cb_buffers ./power/power.h /^ int num_cb_buffers;$/;" m struct:s_power_commonly_used -num_cc_constraints ./base/vpr_types.h /^ int num_cc_constraints; \/* number of special-case clock-to-clock constraints overriding default, calculated, timing constraints *\/$/;" m struct:s_timing_constraints -num_cf_constraints ./base/vpr_types.h /^ int num_cf_constraints; \/* number of special-case clock-to-flipflop constraints *\/$/;" m struct:s_timing_constraints -num_child_blocks_in_pb ./base/vpr_types.h /^ int num_child_blocks_in_pb;$/;" m struct:s_pb_stats -num_clb2clb_directs ./base/globals.c /^int num_clb2clb_directs = 0;$/;" v -num_clock_names ./timing/read_sdc.c /^ int num_clock_names;$/;" m struct:s_sdc_exclusive_group file: -num_conf_bits ./base/vpr_types.h /^ int num_conf_bits;$/;" m struct:s_pb -num_conf_bits ./fpga_x2p/base/fpga_x2p_types.h /^ int num_conf_bits;$/;" m struct:fpga_spice_phy_pb -num_conf_bits_cbx ./fpga_x2p/base/fpga_x2p_globals.c /^int** num_conf_bits_cbx = NULL;$/;" v -num_conf_bits_cby ./fpga_x2p/base/fpga_x2p_globals.c /^int** num_conf_bits_cby = NULL;$/;" v -num_conf_bits_sb ./fpga_x2p/base/fpga_x2p_globals.c /^int** num_conf_bits_sb = NULL;$/;" v -num_constrained_clocks ./base/vpr_types.h /^ int num_constrained_clocks; \/* number of clocks with timing constraints *\/$/;" m struct:s_timing_constraints -num_constrained_inputs ./base/vpr_types.h /^ int num_constrained_inputs; \/* number of inputs with timing constraints *\/$/;" m struct:s_timing_constraints -num_constrained_outputs ./base/vpr_types.h /^ int num_constrained_outputs; \/* number of outputs with timing constraints *\/$/;" m struct:s_timing_constraints -num_critical_input_paths ./base/vpr_types.h /^ long num_critical_input_paths, num_critical_output_paths; \/* count of critical paths fanning into\/out of this tnode *\/$/;" m struct:s_prepacked_tnode_data -num_critical_output_paths ./base/vpr_types.h /^ long num_critical_input_paths, num_critical_output_paths; \/* count of critical paths fanning into\/out of this tnode *\/$/;" m struct:s_prepacked_tnode_data -num_drive_rr_nodes ./base/vpr_types.h /^ int num_drive_rr_nodes;$/;" m struct:s_rr_node -num_driver ./base/read_blif.c /^static int *num_driver, *temp_num_pins;$/;" v file: -num_edges ./base/vpr_types.h /^ int num_edges;$/;" m struct:s_tnode -num_edges ./base/vpr_types.h /^ short num_edges;$/;" m struct:s_rr_node -num_edges_head ./pack/pb_type_graph.c /^static struct s_linked_vptr *num_edges_head;$/;" v typeref:struct:s_linked_vptr file: -num_ext_inputs ./base/vpr_types.h /^ int num_ext_inputs; \/* number of input pins used by molecule that are not self-contained by pattern molecule matches *\/$/;" m struct:s_pack_molecule -num_ext_inputs_logical_block ./util/vpr_utils.c /^int num_ext_inputs_logical_block(int iblk) {$/;" f -num_fc_constraints ./base/vpr_types.h /^ int num_fc_constraints; \/* number of special-case flipflop-to-clock constraints *\/$/;" m struct:s_timing_constraints -num_feasible_blocks ./base/vpr_types.h /^ int num_feasible_blocks; \/* [0..num_marked_models-1] *\/$/;" m struct:s_pb_stats -num_ff_constraints ./base/vpr_types.h /^ int num_ff_constraints; \/* number of special-case flipflop-to-flipflop constraints *\/$/;" m struct:s_timing_constraints -num_heap_allocated ./fpga_x2p/base/fpga_x2p_types.h /^ int num_heap_allocated;$/;" m struct:fpga_spice_rr_graph -num_heap_allocated ./route/route_common.c /^static int num_heap_allocated = 0;$/;" v file: -num_inpads ./base/vpr_types.h /^ int num_inpads;$/;" m struct:s_pb -num_inpads ./fpga_x2p/base/fpga_x2p_types.h /^ int num_inpads;$/;" m struct:fpga_spice_phy_pb -num_inputs ./power/PowerSpicedComponent.h /^ int num_inputs;$/;" m class:PowerCallibInputs -num_inputs ./power/power.h /^ int num_inputs; \/* Number of inputs *\/$/;" m struct:s_mux_node -num_inputs ./power/power.h /^ int num_inputs;$/;" m struct:s_mux_arch -num_inputs ./power/power.h /^ short num_inputs; \/* Number of inputs *\/$/;" m struct:s_rr_node_power -num_iopads ./base/vpr_types.h /^ int num_iopads;$/;" m struct:s_pb -num_iopads ./fpga_x2p/base/fpga_x2p_types.h /^ int num_iopads;$/;" m struct:fpga_spice_phy_pb -num_ipin_rr_nodes ./base/vpr_types.h /^ int* num_ipin_rr_nodes; \/* Switch block has some inputs that are CLB IPIN*\/$/;" m struct:s_cb -num_ipin_rr_nodes ./base/vpr_types.h /^ int* num_ipin_rr_nodes; \/* Switch block has some inputs that are CLB IPIN*\/$/;" m struct:s_sb -num_latches ./base/read_blif.c /^static int num_luts = 0, num_latches = 0, num_subckts = 0;$/;" v file: -num_leakage_pairs ./power/power.h /^ int num_leakage_pairs;$/;" m struct:s_power_nmos_leakage_inf -num_legal_pos ./place/place.c /^static int *num_legal_pos = NULL; \/* [0..num_legal_pos-1] *\/$/;" v file: -num_levr_entries ./power/power.h /^ int num_levr_entries;$/;" m struct:s_power_buffer_strength_inf -num_linked_f_pointer_allocated ./fpga_x2p/base/fpga_x2p_types.h /^ int num_linked_f_pointer_allocated;$/;" m struct:fpga_spice_rr_graph -num_linked_f_pointer_allocated ./route/route_common.c /^static int num_linked_f_pointer_allocated = 0;$/;" v file: -num_local_nets ./base/vpr_types.h /^ int num_local_nets; \/* Records post-packing connections, valid only for top-level *\/$/;" m struct:s_pb -num_logical_blocks ./base/globals.c /^int num_logical_nets = 0, num_logical_blocks = 0;$/;" v -num_logical_blocks ./fpga_x2p/base/fpga_x2p_types.h /^ int num_logical_blocks;$/;" m struct:fpga_spice_phy_pb -num_logical_nets ./base/globals.c /^int num_logical_nets = 0, num_logical_blocks = 0;$/;" v -num_logs ./power/power.h /^ int num_logs;$/;" m struct:s_power_output -num_luts ./base/read_blif.c /^static int num_luts = 0, num_latches = 0, num_subckts = 0;$/;" v file: -num_mapped_opins ./base/vpr_types.h /^ int num_mapped_opins;$/;" m struct:s_net -num_mapped_opins ./route/pb_pin_eq_auto_detect.c /^ int num_mapped_opins;$/;" m struct:s_num_mapped_opins_stats file: -num_marked_blocks ./base/vpr_types.h /^ int num_marked_nets, num_marked_blocks;$/;" m struct:s_pb_stats -num_marked_nets ./base/vpr_types.h /^ int num_marked_nets, num_marked_blocks;$/;" m struct:s_pb_stats -num_messages ./power/power.h /^ int num_messages;$/;" m struct:s_log -num_mode_bits ./base/vpr_types.h /^ int num_mode_bits;$/;" m struct:s_pb -num_mode_bits ./fpga_x2p/base/fpga_x2p_types.h /^ int num_mode_bits;$/;" m struct:fpga_spice_phy_pb -num_moved_blocks ./place/place.c /^ int num_moved_blocks;$/;" m struct:s_pl_blocks_to_be_moved file: -num_multicycles ./base/vpr_types.h /^ int num_multicycles;$/;" m struct:s_override_constraint -num_netlist_clocks ./timing/read_sdc.c /^int num_netlist_clocks = 0; \/* number of clocks in netlist *\/$/;" v -num_netlist_ios ./timing/read_sdc.c /^int num_netlist_ios = 0; \/* number of clocks in netlist *\/$/;" v -num_nets ./base/globals.c /^int num_nets = 0;$/;" v -num_nets ./base/globals_declare.h /^int num_nets, num_blocks;$/;" v -num_nets ./fpga_x2p/base/fpga_x2p_types.h /^ int num_nets; \/* number of nets to route *\/$/;" m struct:fpga_spice_rr_graph -num_nets_in_cluster ./pack/cluster_legality.c /^static int num_nets_in_cluster;$/;" v file: -num_nmos_leakage_info ./power/power.h /^ int num_nmos_leakage_info;$/;" m struct:s_power_tech -num_nmos_mux_info ./power/power.h /^ int num_nmos_mux_info;$/;" m struct:s_power_tech -num_normal_switch ./mrfpga/mrfpga_globals.c /^short num_normal_switch;$/;" v -num_opin_drivers ./base/vpr_types.h /^ int num_opin_drivers; \/* UDSD by WMF (could use "short") *\/$/;" m struct:s_rr_node -num_opin_rr_nodes ./base/vpr_types.h /^ int* num_opin_rr_nodes; \/* Connection block has some outputs that are CLB OPIN *\/$/;" m struct:s_cb -num_opin_rr_nodes ./base/vpr_types.h /^ int* num_opin_rr_nodes; \/* Connection block has some outputs that are CLB OPIN *\/$/;" m struct:s_sb -num_outpads ./base/vpr_types.h /^ int num_outpads;$/;" m struct:s_pb -num_outpads ./fpga_x2p/base/fpga_x2p_types.h /^ int num_outpads;$/;" m struct:fpga_spice_phy_pb -num_p_inputs ./base/globals.c /^int num_p_inputs = 0, num_p_outputs = 0;$/;" v -num_p_outputs ./base/globals.c /^int num_p_inputs = 0, num_p_outputs = 0;$/;" v -num_pb_types ./base/vpr_types.h /^ int num_pb_types; \/* num primitive pb_types inside complex block *\/$/;" m struct:s_cluster_placement_stats -num_pins_of_net_in_pb ./base/vpr_types.h /^ std::map num_pins_of_net_in_pb;$/;" m struct:s_pb_stats -num_pl_macros ./place/place.c /^static int num_pl_macros;$/;" v file: -num_reserved_conf_bits ./base/vpr_types.h /^ int num_reserved_conf_bits;$/;" m struct:s_pb -num_reserved_conf_bits ./base/vpr_types.h /^ int num_reserved_conf_bits; \/* number of reserved configuration bits *\/$/;" m struct:s_cb -num_reserved_conf_bits ./base/vpr_types.h /^ int num_reserved_conf_bits; \/* number of reserved configuration bits *\/$/;" m struct:s_sb -num_reserved_conf_bits ./fpga_x2p/base/fpga_x2p_types.h /^ int num_reserved_conf_bits;$/;" m struct:fpga_spice_phy_pb -num_rp ./place/place_stats.c /^ int num_rp[MAX_LEN];$/;" m struct:relapos_rec_s file: -num_rr_indexed_data ./base/globals.c /^int num_rr_indexed_data = 0;$/;" v -num_rr_indexed_data ./base/globals_declare.h /^int num_rr_indexed_data;$/;" v -num_rr_indexed_data ./fpga_x2p/base/fpga_x2p_types.h /^ int num_rr_indexed_data;$/;" m struct:fpga_spice_rr_graph -num_rr_nodes ./base/globals.c /^int num_rr_nodes = 0;$/;" v -num_rr_nodes ./base/globals_declare.h /^int num_rr_nodes;$/;" v -num_rr_nodes ./fpga_x2p/base/fpga_x2p_types.h /^ int num_rr_nodes;$/;" m struct:fpga_spice_rr_graph -num_sb_buffers ./power/power.h /^ int num_sb_buffers;$/;" m struct:s_power_commonly_used -num_segment ./base/vpr_types.h /^ int num_segment;$/;" m struct:s_det_routing_arch -num_segments ./fpga_x2p/spice/spice_mux_testbench.c /^static int num_segments;$/;" v file: -num_segments ./fpga_x2p/spice/spice_routing_testbench.c /^static int num_segments;$/;" v file: -num_siblings ./base/vpr_types.h /^ int num_siblings;$/;" m struct:s_trace -num_sides ./base/vpr_types.h /^ int num_sides; \/* Should be fixed to 4 *\/$/;" m struct:s_cb -num_sides ./base/vpr_types.h /^ int num_sides; \/* Should be fixed to 4 *\/$/;" m struct:s_sb -num_sink ./base/vpr_types.h /^ int num_sink;$/;" m struct:s_override_constraint -num_sinks ./base/vpr_types.h /^ int num_sinks;$/;" m struct:s_net -num_size_entries ./power/power.h /^ int num_size_entries;$/;" m struct:s_transistor_inf -num_source ./base/vpr_types.h /^ int num_source;$/;" m struct:s_override_constraint -num_strengths ./power/power.h /^ int num_strengths;$/;" m struct:s_power_buffer_size_inf -num_subckts ./base/read_blif.c /^static int num_luts = 0, num_latches = 0, num_subckts = 0;$/;" v file: -num_swap_aborted ./place/place.c /^static int num_swap_aborted = 0;$/;" v file: -num_swap_accepted ./place/place.c /^static int num_swap_accepted = 0;$/;" v file: -num_swap_rejected ./place/place.c /^static int num_swap_rejected = 0;$/;" v file: -num_switch ./base/vpr_types.h /^ short num_switch;$/;" m struct:s_det_routing_arch -num_switch_inf ./fpga_x2p/base/fpga_x2p_types.h /^ int num_switch_inf;$/;" m struct:fpga_spice_rr_graph -num_swseg_pattern ./base/vpr_types.h /^ int num_swseg_pattern; \/*Xifan TANG: Switch Segment Pattern Support*\/$/;" m struct:s_det_routing_arch -num_timing_nets ./timing/path_delay.c /^static int num_timing_nets = 0;$/;" v file: -num_tnode_levels ./timing/path_delay2.c /^int num_tnode_levels; \/* Number of levels in the timing graph. *\/$/;" v -num_tnodes ./timing/path_delay.c /^int num_tnodes = 0; \/* Number of nodes (pins) in the timing graph *\/$/;" v -num_trace_allocated ./fpga_x2p/base/fpga_x2p_types.h /^ int num_trace_allocated; \/* To watch for memory leaks. *\/$/;" m struct:fpga_spice_rr_graph -num_trace_allocated ./route/route_common.c /^static int num_trace_allocated = 0; \/* To watch for memory leaks. *\/$/;" v file: -num_ts_called ./place/place.c /^static int num_ts_called = 0;$/;" v file: -num_types ./base/globals.c /^int num_types = 0;$/;" v -num_types_backup ./place/timing_place_lookup.c /^static int num_types_backup;$/;" v file: -num_used_cb_mux_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_cb_mux_tb = 0;$/;" v -num_used_cb_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_cb_tb = 0;$/;" v -num_used_grid_mux_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_grid_mux_tb = 0;$/;" v -num_used_grid_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_grid_tb = 0;$/;" v -num_used_hardlogic_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_hardlogic_tb = 0;$/;" v -num_used_io_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_io_tb = 0;$/;" v -num_used_lut_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_lut_tb = 0;$/;" v -num_used_sb_mux_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_sb_mux_tb = 0;$/;" v -num_used_sb_tb ./fpga_x2p/spice/spice_globals.c /^int num_used_sb_tb = 0;$/;" v -num_voltage_pairs ./power/power.h /^ int num_voltage_pairs;$/;" m struct:s_power_mux_volt_inf -num_wire_drivers ./base/vpr_types.h /^ int num_wire_drivers; \/* UDSD by WMF *\/$/;" m struct:s_rr_node -nx ./base/globals.c /^int nx = 0;$/;" v -nx ./base/globals_declare.h /^int nx, ny;$/;" v -ny ./base/globals.c /^int ny = 0;$/;" v -ny ./base/globals_declare.h /^int nx, ny;$/;" v -object_end ./base/graphics.c /^void object_end() { }$/;" f -object_end ./base/graphics.c /^void object_end() {$/;" f -object_start ./base/graphics.c /^void object_start(int all) { }$/;" f -object_start ./base/graphics.c /^void object_start(int all) {$/;" f -occ ./base/vpr_types.h /^ short occ;$/;" m struct:s_rr_node -occupancy ./base/vpr_types.h /^ float occupancy;$/;" m struct:s_place_region -offset ./base/vpr_types.h /^ int offset;$/;" m struct:s_grid_tile -offset_chan ./base/vpr_types.h /^ int* offset_chan; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_cb -offset_chan ./base/vpr_types.h /^ int* offset_chan; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_sb -offset_ipin ./base/vpr_types.h /^ int* offset_ipin; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_cb -offset_ipin ./base/vpr_types.h /^ int* offset_ipin; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_sb -offset_opin ./base/vpr_types.h /^ int* offset_opin; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_cb -offset_opin ./base/vpr_types.h /^ int* offset_opin; \/* [0, ..., num_sides-1]*\/$/;" m struct:s_sb -old_num_rr_nodes ./base/draw.c /^static int old_num_rr_nodes = 0;$/;" v file: -olines ./base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: -operator < ./power/PowerSpicedComponent.h /^ const bool operator<(const PowerCallibSize & rhs) {$/;" f class:PowerCallibSize -opin_rr_node ./base/vpr_types.h /^ t_rr_node*** opin_rr_node;$/;" m struct:s_cb -opin_rr_node ./base/vpr_types.h /^ t_rr_node*** opin_rr_node;$/;" m struct:s_sb -opin_rr_node_grid_side ./base/vpr_types.h /^ int** opin_rr_node_grid_side; \/* We need to record the side of a OPIN, because a OPIN may locate on more than one sides *\/$/;" m struct:s_cb -opin_rr_node_grid_side ./base/vpr_types.h /^ int** opin_rr_node_grid_side; \/* We need to record the side of a OPIN, because a OPIN may locate on more than one sides *\/$/;" m struct:s_sb -opin_switch ./base/vpr_types.h /^ short opin_switch;$/;" m struct:s_seg_details -opin_to_wire_switch ./base/vpr_types.h /^ short opin_to_wire_switch; \/* mrFPGA: Xifan TANG*\/$/;" m struct:s_det_routing_arch -opt_def ./fpga_x2p/shell/read_opt_types.h /^ enum opt_default opt_def;$/;" m struct:s_opt_info typeref:enum:s_opt_info::opt_default -opt_default ./fpga_x2p/shell/read_opt_types.h /^enum opt_default {$/;" g -opt_manda ./fpga_x2p/shell/read_opt_types.h /^enum opt_manda {$/;" g -opt_val_type ./fpga_x2p/shell/read_opt_types.h /^enum opt_val_type {$/;" g -opt_with_val ./fpga_x2p/shell/read_opt_types.h /^enum opt_with_val {$/;" g -options ./timing/slre.c /^ enum slre_option options;$/;" m struct:slre typeref:enum:slre::slre_option file: -opts ./fpga_x2p/shell/read_opt_types.h /^ t_opt_info opts[];$/;" m struct:s_cmd_info -opts ./fpga_x2p/shell/shell_types.h /^ t_opt_info* opts;$/;" m struct:s_shell_cmd -ortho_cost_index ./base/vpr_types.h /^ int ortho_cost_index;$/;" m struct:s_rr_indexed_data -out ./power/power.h /^ FILE * out;$/;" m struct:s_power_output -out_edges ./base/vpr_types.h /^ t_tedge *out_edges; \/* [0..num_edges - 1] array of edges fanning out from this tnode.$/;" m struct:s_tnode -out_file_prefix ./base/ReadOptions.h /^ char *out_file_prefix;$/;" m struct:s_options -out_file_prefix ./base/vpr_types.h /^ char *out_file_prefix;$/;" m struct:s_file_name_opts -outputFileNames ./base/ReadOptions.c /^static char **outputFileNames = NULL;$/;" v file: -output_blif ./pack/output_blif.c /^void output_blif (t_block *clb, int num_clusters, boolean global_clocks,$/;" f -output_clustering ./pack/output_clustering.c /^void output_clustering(t_block *clb, int num_clusters, boolean global_clocks,$/;" f -output_file ./base/vpr_types.h /^ char *output_file;$/;" m struct:s_packer_opts -output_log ./power/power_util.c /^void output_log(t_log * log_ptr, FILE * fp) {$/;" f -output_logs ./power/power_util.c /^void output_logs(FILE * fp, t_log * logs, int num_logs) {$/;" f -output_net_tnodes ./base/vpr_types.h /^ struct s_tnode ***output_net_tnodes; \/* [0..num_output_ports-1][0..num_pins -1] correspnding output net tnode *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_tnode -output_nets ./base/vpr_types.h /^ int **output_nets; \/* [0..num_output_ports-1][0..num_port_pins-1] List of output nets connected to this logical_block. *\/$/;" m struct:s_logical_block -output_pins_used ./base/vpr_types.h /^ int **output_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of output pins of this class that are used *\/$/;" m struct:s_pb_stats -override_one_rr_node_for_top_primitive_phy_pb_graph_node ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void override_one_rr_node_for_top_primitive_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin,$/;" f -pack_clb_pin_remap ./base/vpr_types.h /^ boolean pack_clb_pin_remap;$/;" m struct:s_packer_opts -pack_intrinsic_cost ./base/vpr_types.h /^ float pack_intrinsic_cost;$/;" m struct:s_rr_node -pack_pattern ./base/vpr_types.h /^ t_pack_patterns *pack_pattern; \/* If this is a forced_pack molecule, pattern this molecule matches *\/$/;" m struct:s_pack_molecule -pack_route_time ./base/globals.c /^float pack_route_time = 0.;$/;" v -packed_molecules ./base/vpr_types.h /^ struct s_linked_vptr *packed_molecules; \/* List of t_pack_molecules that this logical block is a part of *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_linked_vptr -packer_algorithm ./base/ReadOptions.h /^ enum e_packer_algorithm packer_algorithm;$/;" m struct:s_options typeref:enum:s_options::e_packer_algorithm -packer_algorithm ./base/vpr_types.h /^ enum e_packer_algorithm packer_algorithm;$/;" m struct:s_packer_opts typeref:enum:s_packer_opts::e_packer_algorithm -pad_loc_file ./base/vpr_types.h /^ char *pad_loc_file;$/;" m struct:s_placer_opts -pad_loc_type ./base/vpr_types.h /^ enum e_pad_loc_type pad_loc_type;$/;" m struct:s_placer_opts typeref:enum:s_placer_opts::e_pad_loc_type -parasitic_net_estimation ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void parasitic_net_estimation() {$/;" f file: -parent ./power/PowerSpicedComponent.h /^ PowerSpicedComponent * parent;$/;" m class:PowerCallibInputs -parent_node ./route/route_tree_timing.h /^ struct s_rt_node *parent_node;$/;" m struct:s_rt_node typeref:struct:s_rt_node::s_rt_node -parent_pb ./base/vpr_types.h /^ struct s_pb *parent_pb; \/* pointer to parent node *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb -parent_pb ./fpga_x2p/base/fpga_x2p_types.h /^ t_phy_pb *parent_pb; \/* pointer to parent node *\/$/;" m struct:fpga_spice_phy_pb -parent_switch ./route/route_tree_timing.h /^ short parent_switch;$/;" m struct:s_rt_node -parse_direct_pin_name ./util/vpr_utils.c /^void parse_direct_pin_name(char * src_string, int line, int * start_pin_index, $/;" f -partition ./fpga_x2p/base/quicksort.c /^int partition(int len, float* sort_value, int pivot_index) {$/;" f file: -partition_index ./fpga_x2p/base/quicksort.c /^int partition_index(int len, int* sort_index, $/;" f file: -path_cost ./route/route_common.h /^ float path_cost;$/;" m struct:__anon15 -path_criticality ./base/vpr_types.h /^ float ** path_criticality;$/;" m struct:s_slack -pathfinder_update_cost ./route/route_common.c /^void pathfinder_update_cost(float pres_fac, float acc_fac) {$/;" f -pathfinder_update_one_cost ./route/route_common.c /^void pathfinder_update_one_cost(struct s_trace *route_segment_start,$/;" f -pathfinder_update_rr_graph_cost ./fpga_x2p/router/fpga_x2p_router.c /^void pathfinder_update_rr_graph_cost(t_rr_graph* local_rr_graph,$/;" f -pathfinder_update_rr_graph_one_cost ./fpga_x2p/router/fpga_x2p_router.c /^void pathfinder_update_rr_graph_one_cost(t_rr_graph* local_rr_graph, $/;" f -pb ./base/verilog_writer.h /^ t_pb *pb;$/;" m struct:found_pins -pb ./base/vpr_types.h /^ t_pb *pb;$/;" m struct:s_block -pb ./base/vpr_types.h /^ t_pb* pb; \/* pb primitive that this block is packed into *\/$/;" m struct:s_logical_block -pb ./base/vpr_types.h /^ t_pb* pb;$/;" m struct:s_rr_node -pb_graph_node ./base/vpr_types.h /^ t_pb_graph_node *pb_graph_node; \/* pointer to pb_graph_node this pb corresponds to *\/$/;" m struct:s_pb -pb_graph_node ./fpga_x2p/base/fpga_x2p_types.h /^ t_pb_graph_node *pb_graph_node; \/* pointer to pb_graph_node this pb corresponds to *\/$/;" m struct:fpga_spice_phy_pb -pb_graph_pin ./base/vpr_types.h /^ t_pb_graph_pin *pb_graph_pin; \/* pb_graph_pin that this block is connected to *\/$/;" m struct:s_tnode -pb_graph_pin ./base/vpr_types.h /^ t_pb_graph_pin *pb_graph_pin;$/;" m struct:s_rr_node -pb_list ./base/verilog_writer.h /^}pb_list;$/;" t typeref:struct:found_pins -pb_max_internal_delay ./base/globals.c /^float pb_max_internal_delay = UNDEFINED; \/* biggest internal delay of physical block *\/$/;" v -pb_pin_density ./fpga_x2p/base/fpga_x2p_utils.c /^float pb_pin_density(t_rr_node* pb_rr_graph, $/;" f -pb_pin_init_value ./fpga_x2p/base/fpga_x2p_utils.c /^int pb_pin_init_value(t_rr_node* pb_rr_graph, $/;" f -pb_pin_net_num ./fpga_x2p/base/fpga_x2p_utils.c /^int pb_pin_net_num(t_rr_node* pb_rr_graph, $/;" f -pb_pin_probability ./fpga_x2p/base/fpga_x2p_utils.c /^float pb_pin_probability(t_rr_node* pb_rr_graph, $/;" f -pb_stats ./base/vpr_types.h /^ struct s_pb_stats *pb_stats; \/* statistics for current pb *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb_stats -pbtype_max_internal_delay ./base/globals.c /^const t_pb_type *pbtype_max_internal_delay = NULL; \/* physical block type with highest internal delay *\/$/;" v -period ./timing/read_sdc.c /^ float period;$/;" m struct:s_sdc_clock file: -pfreq ./base/vpr_types.h /^enum pfreq {$/;" g -phy_pb ./base/vpr_types.h /^ void* phy_pb;$/;" m struct:s_block -phy_pb ./base/vpr_types.h /^ void* phy_pb;$/;" m struct:s_pb -pic_on_screen ./base/draw.c /^static enum pic_type pic_on_screen = NO_PICTURE; \/* What do I draw? *\/$/;" v typeref:enum:pic_type file: -pic_type ./base/vpr_types.h /^enum pic_type {$/;" g -pin_and_chan_adjacent ./route/check_route.c /^static int pin_and_chan_adjacent(int pin_node, int chan_node) {$/;" f file: -pin_count_in_cluster ./pack/pb_type_graph.c /^static int pin_count_in_cluster;$/;" v file: -pin_criticality ./place/timing_place_lookup.c /^static float *pin_criticality;$/;" v file: -pin_dens ./power/power_util.c /^float pin_dens(t_pb * pb, t_pb_graph_pin * pin) {$/;" f -pin_prefer_side ./base/vpr_types.h /^ int** pin_prefer_side; \/* [0..num_pins-1][0..3] *\/$/;" m struct:s_block -pin_prob ./power/power_util.c /^float pin_prob(t_pb * pb, t_pb_graph_pin * pin) {$/;" f -pin_side_count ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int pin_side_count(int pin_side[]) {$/;" f -pin_size ./base/draw.c /^static float tile_width, pin_size;$/;" v file: -pl_macros ./place/place.c /^static t_pl_macro * pl_macros = NULL;$/;" v file: -place_algorithm ./base/vpr_types.h /^ enum e_place_algorithm place_algorithm;$/;" m struct:s_placer_opts typeref:enum:s_placer_opts::e_place_algorithm -place_and_route ./base/place_and_route.c /^void place_and_route(enum e_operation operation,$/;" f -place_chan_width ./base/vpr_types.h /^ int place_chan_width;$/;" m struct:s_placer_opts -place_clb_pin_remap ./base/vpr_types.h /^ boolean place_clb_pin_remap;$/;" m struct:s_placer_opts -place_cost_exp ./base/ReadOptions.h /^ float place_cost_exp;$/;" m struct:s_options -place_cost_exp ./base/vpr_types.h /^ float place_cost_exp;$/;" m struct:s_placer_opts -place_exp_first ./base/ReadOptions.h /^ float place_exp_first;$/;" m struct:s_options -place_exp_last ./base/ReadOptions.h /^ float place_exp_last;$/;" m struct:s_options -place_freq ./base/vpr_types.h /^ enum pfreq place_freq;$/;" m struct:s_placer_opts typeref:enum:s_placer_opts::pfreq -pmos_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* pmos_subckt_name = "vpr_pmos";$/;" v -point_to_point_delay_cost ./place/place.c /^static float **point_to_point_delay_cost = NULL;$/;" v file: -point_to_point_timing_cost ./place/place.c /^static float **point_to_point_timing_cost = NULL;$/;" v file: -poly ./base/graphics.c /^ int poly[3][2]; $/;" m struct:__anon4 file: -post_place_sync ./base/place_and_route.c /^void post_place_sync(INP int L_num_blocks,$/;" f -postscript ./base/graphics.c /^postscript (void (*drawscreen) (void)) $/;" f file: -power ./power/PowerSpicedComponent.h /^ float power;$/;" m class:PowerCallibSize -power_MTAs ./power/power_sizing.c /^static double power_MTAs(float W_size) {$/;" f file: -power_MTAs_L ./power/power_sizing.c /^static double power_MTAs_L(float L_size) {$/;" f file: -power_add_usage ./power/power_util.c /^void power_add_usage(t_power_usage * dest, const t_power_usage * src) {$/;" f -power_alloc_and_init_pb_pin ./power/power.c /^void power_alloc_and_init_pb_pin(t_pb_graph_pin * pin) {$/;" f -power_buffer_size_from_logical_effort ./power/power_util.c /^float power_buffer_size_from_logical_effort(float C_load) {$/;" f -power_calc_buffer_num_stages ./power/power_util.c /^int power_calc_buffer_num_stages(float final_stage_size,$/;" f -power_calc_buffer_size_from_Cout ./power/power_lowlevel.c /^float power_calc_buffer_size_from_Cout(float C_out) {$/;" f -power_calc_leakage_gate ./power/power_lowlevel.c /^static float power_calc_leakage_gate(e_tx_type transistor_type, float size) {$/;" f file: -power_calc_leakage_st ./power/power_lowlevel.c /^static float power_calc_leakage_st(e_tx_type transistor_type, float size) {$/;" f file: -power_calc_leakage_st_pass_transistor ./power/power_lowlevel.c /^static float power_calc_leakage_st_pass_transistor(float size, float v_ds) {$/;" f file: -power_calc_mux_v_out ./power/power_lowlevel.c /^float power_calc_mux_v_out(int num_inputs, float transistor_size, float v_in,$/;" f -power_calc_node_switching ./power/power_lowlevel.c /^float power_calc_node_switching(float capacitance, float density,$/;" f -power_calc_node_switching_v ./power/power_lowlevel.c /^static float power_calc_node_switching_v(float capacitance, float density,$/;" f file: -power_calc_transistor_capacitance ./power/power_lowlevel.c /^static void power_calc_transistor_capacitance(float *C_d, float *C_s,$/;" f file: -power_callib_period ./power/power_callibrate.h /^const float power_callib_period = 5e-9;$/;" v -power_callibrate ./power/power_callibrate.c /^void power_callibrate(void) {$/;" f -power_compare_buffer_sc_levr ./power/power_cmos_tech.c /^static int power_compare_buffer_sc_levr(const void * key_void,$/;" f file: -power_compare_buffer_strength ./power/power_cmos_tech.c /^static int power_compare_buffer_strength(const void * key_void,$/;" f file: -power_compare_leakage_pair ./power/power_cmos_tech.c /^static int power_compare_leakage_pair(const void * key_void,$/;" f file: -power_compare_transistor_size ./power/power_cmos_tech.c /^static int power_compare_transistor_size(const void * key_void,$/;" f file: -power_compare_voltage_pair ./power/power_cmos_tech.c /^static int power_compare_voltage_pair(const void * key_void,$/;" f file: -power_component_add_usage ./power/power_components.c /^void power_component_add_usage(t_power_usage * power_usage,$/;" f -power_component_get_usage ./power/power_components.c /^void power_component_get_usage(t_power_usage * power_usage,$/;" f -power_component_get_usage_sum ./power/power_components.c /^float power_component_get_usage_sum(e_power_component_type component_idx) {$/;" f -power_components_init ./power/power_components.c /^void power_components_init(void) {$/;" f -power_components_uninit ./power/power_components.c /^void power_components_uninit(void) {$/;" f -power_count_transistor_SRAM_bit ./power/power_sizing.c /^static double power_count_transistor_SRAM_bit(void) {$/;" f file: -power_count_transistors_FF ./power/power_sizing.c /^static double power_count_transistors_FF(float size) {$/;" f file: -power_count_transistors_LUT ./power/power_sizing.c /^static double power_count_transistors_LUT(int LUT_inputs,$/;" f file: -power_count_transistors_buffer ./power/power_sizing.c /^double power_count_transistors_buffer(float buffer_size) {$/;" f -power_count_transistors_connectionbox ./power/power_sizing.c /^static double power_count_transistors_connectionbox(void) {$/;" f file: -power_count_transistors_interc ./power/power_sizing.c /^static double power_count_transistors_interc(t_interconnect * interc) {$/;" f file: -power_count_transistors_inv ./power/power_sizing.c /^static double power_count_transistors_inv(float size) {$/;" f file: -power_count_transistors_levr ./power/power_sizing.c /^static double power_count_transistors_levr() {$/;" f file: -power_count_transistors_mux ./power/power_sizing.c /^static double power_count_transistors_mux(t_mux_arch * mux_arch) {$/;" f file: -power_count_transistors_mux_node ./power/power_sizing.c /^static double power_count_transistors_mux_node(t_mux_node * mux_node,$/;" f file: -power_count_transistors_pb_node ./power/power_sizing.c /^static double power_count_transistors_pb_node(t_pb_graph_node * pb_node) {$/;" f file: -power_count_transistors_primitive ./power/power_sizing.c /^static double power_count_transistors_primitive(t_pb_type * pb_type) {$/;" f file: -power_count_transistors_switchbox ./power/power_sizing.c /^static double power_count_transistors_switchbox(t_arch * arch) {$/;" f file: -power_count_transistors_trans_gate ./power/power_sizing.c /^static double power_count_transistors_trans_gate(float size) {$/;" f file: -power_estimation_method_name ./power/power.c /^static char * power_estimation_method_name($/;" f file: -power_find_buffer_sc_levr ./power/power_cmos_tech.c /^void power_find_buffer_sc_levr(t_power_buffer_sc_levr_inf ** lower,$/;" f -power_find_buffer_strength_inf ./power/power_cmos_tech.c /^void power_find_buffer_strength_inf(t_power_buffer_strength_inf ** lower,$/;" f -power_find_mux_volt_inf ./power/power_cmos_tech.c /^void power_find_mux_volt_inf(t_power_mux_volt_pair ** lower,$/;" f -power_find_nmos_leakage ./power/power_cmos_tech.c /^void power_find_nmos_leakage(t_power_nmos_leakage_inf * nmos_leakage_info,$/;" f -power_find_transistor_info ./power/power_cmos_tech.c /^boolean power_find_transistor_info(t_transistor_size_inf ** lower,$/;" f -power_get_mux_arch ./power/power_util.c /^t_mux_arch * power_get_mux_arch(int num_mux_inputs, float transistor_size) {$/;" f -power_init ./power/power.c /^boolean power_init(char * power_out_filepath,$/;" f -power_init_pb_pins_rec ./power/power.c /^void power_init_pb_pins_rec(t_pb_graph_node * pb_node) {$/;" f -power_log_msg ./power/power_util.c /^void power_log_msg(e_power_log_type log_type, char * msg) {$/;" f -power_lowlevel_init ./power/power_lowlevel.c /^void power_lowlevel_init() {$/;" f -power_method_is_recursive ./power/power_util.c /^boolean power_method_is_recursive(e_power_estimation_method method) {$/;" f -power_method_is_transistor_level ./power/power_util.c /^boolean power_method_is_transistor_level($/;" f -power_mux_node_max_inputs ./power/power_sizing.c /^static void power_mux_node_max_inputs(t_mux_node * mux_node,$/;" f file: -power_pb_pins_init ./power/power.c /^void power_pb_pins_init() {$/;" f -power_perc_dynamic ./power/power_util.c /^float power_perc_dynamic(t_power_usage * power_usage) {$/;" f -power_print_breakdown_component ./power/power.c /^static void power_print_breakdown_component(FILE * fp, char * name,$/;" f file: -power_print_breakdown_entry ./power/power.c /^static void power_print_breakdown_entry(FILE * fp, int indent,$/;" f file: -power_print_breakdown_pb ./power/power.c /^static void power_print_breakdown_pb(FILE * fp) {$/;" f file: -power_print_breakdown_pb_rec ./power/power.c /^static void power_print_breakdown_pb_rec(FILE * fp, t_pb_type * pb_type,$/;" f file: -power_print_breakdown_summary ./power/power.c /^static void power_print_breakdown_summary(FILE * fp) {$/;" f file: -power_print_spice_comparison ./power/power_callibrate.c /^void power_print_spice_comparison(void) {$/;" f -power_print_summary ./power/power.c /^static void power_print_summary(FILE * fp, t_vpr_setup vpr_setup) {$/;" f file: -power_print_title ./power/power_util.c /^void power_print_title(FILE * fp, char * title) {$/;" f -power_reset_pb_type ./power/power.c /^static void power_reset_pb_type(t_pb_type * pb_type) {$/;" f file: -power_reset_tile_usage ./power/power.c /^static void power_reset_tile_usage(void) {$/;" f file: -power_routing_init ./power/power.c /^void power_routing_init(t_det_routing_arch * routing_arch) {$/;" f -power_scale_usage ./power/power_util.c /^void power_scale_usage(t_power_usage * power_usage, float scale_factor) {$/;" f -power_size_pb ./power/power_sizing.c /^static void power_size_pb(void) {$/;" f file: -power_size_pb_rec ./power/power_sizing.c /^static void power_size_pb_rec(t_pb_graph_node * pb_node) {$/;" f file: -power_size_pin_buffers_and_wires ./power/power_sizing.c /^static void power_size_pin_buffers_and_wires(t_pb_graph_pin * pin,$/;" f file: -power_size_pin_to_interconnect ./power/power_sizing.c /^static void power_size_pin_to_interconnect(t_interconnect * interc,$/;" f file: -power_sizing_init ./power/power_sizing.c /^void power_sizing_init(t_arch * arch) {$/;" f -power_sum_usage ./power/power_util.c /^float power_sum_usage(t_power_usage * power_usage) {$/;" f -power_tech_init ./power/power_cmos_tech.c /^void power_tech_init(char * cmos_tech_behavior_filepath) {$/;" f -power_tech_load_xml_file ./power/power_cmos_tech.c /^void power_tech_load_xml_file(char * cmos_tech_behavior_filepath) {$/;" f -power_tech_xml_load_component ./power/power_cmos_tech.c /^static void power_tech_xml_load_component(ezxml_t parent,$/;" f file: -power_tech_xml_load_components ./power/power_cmos_tech.c /^static void power_tech_xml_load_components(ezxml_t parent) {$/;" f file: -power_tech_xml_load_multiplexer_info ./power/power_cmos_tech.c /^static void power_tech_xml_load_multiplexer_info(ezxml_t parent) {$/;" f file: -power_tech_xml_load_nmos_st_leakages ./power/power_cmos_tech.c /^static void power_tech_xml_load_nmos_st_leakages(ezxml_t parent) {$/;" f file: -power_total ./power/power.c /^e_power_ret_code power_total(float * run_time_s, t_vpr_setup vpr_setup,$/;" f -power_transistor_area ./power/power_sizing.c /^double power_transistor_area(double num_MTAs) {$/;" f -power_transistors_for_pb_node ./power/power_sizing.c /^static double power_transistors_for_pb_node(t_pb_graph_node * pb_node) {$/;" f file: -power_transistors_per_tile ./power/power_sizing.c /^static double power_transistors_per_tile(t_arch * arch) {$/;" f file: -power_uninit ./power/power.c /^boolean power_uninit(void) {$/;" f -power_usage_MUX2_transmission ./power/power_lowlevel.c /^void power_usage_MUX2_transmission(t_power_usage * power_usage, float size,$/;" f -power_usage_blocks ./power/power.c /^static void power_usage_blocks(t_power_usage * power_usage) {$/;" f file: -power_usage_buf_for_callibration ./power/power_callibrate.c /^float power_usage_buf_for_callibration(int num_inputs, float transistor_size) {$/;" f -power_usage_buf_levr_for_callibration ./power/power_callibrate.c /^float power_usage_buf_levr_for_callibration(int num_inputs,$/;" f -power_usage_buffer ./power/power_components.c /^void power_usage_buffer(t_power_usage * power_usage, float size, float in_prob,$/;" f -power_usage_clock ./power/power.c /^static void power_usage_clock(t_power_usage * power_usage,$/;" f file: -power_usage_clock_single ./power/power.c /^static void power_usage_clock_single(t_power_usage * power_usage,$/;" f file: -power_usage_ff ./power/power_components.c /^void power_usage_ff(t_power_usage * power_usage, float size, float D_prob,$/;" f -power_usage_ff_for_callibration ./power/power_callibrate.c /^float power_usage_ff_for_callibration(int num_inputs, float transistor_size) {$/;" f -power_usage_inverter ./power/power_lowlevel.c /^void power_usage_inverter(t_power_usage * power_usage, float in_dens,$/;" f -power_usage_inverter_irregular ./power/power_lowlevel.c /^void power_usage_inverter_irregular(t_power_usage * power_usage,$/;" f -power_usage_level_restorer ./power/power_lowlevel.c /^void power_usage_level_restorer(t_power_usage * power_usage,$/;" f -power_usage_local_buffers_and_wires ./power/power.c /^static void power_usage_local_buffers_and_wires(t_power_usage * power_usage,$/;" f file: -power_usage_local_interc_mux ./power/power_components.c /^void power_usage_local_interc_mux(t_power_usage * power_usage, t_pb * pb,$/;" f -power_usage_local_pin_buffer_and_wire ./power/power.c /^void power_usage_local_pin_buffer_and_wire(t_power_usage * power_usage,$/;" f -power_usage_local_pin_toggle ./power/power.c /^void power_usage_local_pin_toggle(t_power_usage * power_usage, t_pb * pb,$/;" f -power_usage_lut ./power/power_components.c /^void power_usage_lut(t_power_usage * power_usage, int lut_size,$/;" f -power_usage_lut_for_callibration ./power/power_callibrate.c /^float power_usage_lut_for_callibration(int num_inputs, float transistor_size) {$/;" f -power_usage_mux_for_callibration ./power/power_callibrate.c /^float power_usage_mux_for_callibration(int num_inputs, float transistor_size) {$/;" f -power_usage_mux_multilevel ./power/power_components.c /^void power_usage_mux_multilevel(t_power_usage * power_usage,$/;" f -power_usage_mux_rec ./power/power_components.c /^static void power_usage_mux_rec(t_power_usage * power_usage, float * out_prob,$/;" f file: -power_usage_mux_singlelevel_dynamic ./power/power_lowlevel.c /^void power_usage_mux_singlelevel_dynamic(t_power_usage * power_usage,$/;" f -power_usage_mux_singlelevel_static ./power/power_lowlevel.c /^void power_usage_mux_singlelevel_static(t_power_usage * power_usage,$/;" f -power_usage_pb ./power/power.c /^static void power_usage_pb(t_power_usage * power_usage, t_pb * pb,$/;" f file: -power_usage_primitive ./power/power.c /^static void power_usage_primitive(t_power_usage * power_usage, t_pb * pb,$/;" f file: -power_usage_routing ./power/power.c /^static void power_usage_routing(t_power_usage * power_usage,$/;" f file: -power_usage_wire ./power/power_lowlevel.c /^void power_usage_wire(t_power_usage * power_usage, float capacitance,$/;" f -power_zero_usage ./power/power_util.c /^void power_zero_usage(t_power_usage * power_usage) {$/;" f -prefer_side ./base/vpr_types.h /^ int** prefer_side; \/* [0..num_sinks][0..3] *\/$/;" m struct:s_net -prepacked_data ./base/vpr_types.h /^ t_prepacked_tnode_data * prepacked_data;$/;" m struct:s_tnode -pres_cost ./route/route_common.h /^ float pres_cost;$/;" m struct:__anon15 -pres_fac ./pack/cluster_legality.c /^static float pres_fac;$/;" v file: -pres_fac_mult ./base/ReadOptions.h /^ float pres_fac_mult;$/;" m struct:s_options -pres_fac_mult ./base/vpr_types.h /^ float pres_fac_mult;$/;" m struct:s_router_opts -prev_edge ./base/vpr_types.h /^ int prev_edge;$/;" m struct:s_rr_node -prev_edge ./route/route_common.h /^ int prev_edge;$/;" m struct:s_heap -prev_edge ./route/route_common.h /^ short prev_edge;$/;" m struct:__anon15 -prev_edge_in_pack ./base/vpr_types.h /^ int prev_edge_in_pack;$/;" m struct:s_rr_node -prev_node ./base/vpr_types.h /^ int prev_node;$/;" m struct:s_rr_node -prev_node ./route/route_common.h /^ int prev_node;$/;" m union:s_heap::__anon14 -prev_node ./route/route_common.h /^ int prev_node;$/;" m struct:__anon15 -prev_node_in_pack ./base/vpr_types.h /^ int prev_node_in_pack; $/;" m struct:s_rr_node -prevconnectiongainincr ./base/vpr_types.h /^ std::map prevconnectiongainincr; \/* [0..num_logical_blocks-1] Prev sum to weighted sum of connections to attraction function *\/$/;" m struct:s_pb_stats -primitive_feasible ./pack/cluster.c /^static boolean primitive_feasible(int iblk, t_pb *cur_pb) {$/;" f file: -primitive_type_and_memory_feasible ./pack/cluster.c /^static boolean primitive_type_and_memory_feasible(int iblk,$/;" f file: -primitive_type_feasible ./util/vpr_utils.c /^boolean primitive_type_feasible(int iblk, const t_pb_type *cur_pb_type) {$/;" f -printClusteredNetlistStats ./base/ShowSetup.c /^void printClusteredNetlistStats() {$/;" f -print_array ./place/timing_place_lookup.c /^print_array(float **array_to_print,$/;" f file: -print_autocheck_top_testbench ./base/vpr_types.h /^ boolean print_autocheck_top_testbench;$/;" m struct:s_syn_verilog_opts -print_block_criticalities ./pack/cluster.c /^static void print_block_criticalities(const char * fname) {$/;" f file: -print_clb_placement ./place/place.c /^static void print_clb_placement(const char *fname) {$/;" f file: -print_clustering_timing_info ./timing/path_delay.c /^void print_clustering_timing_info(const char *fname) {$/;" f -print_clusters ./pack/output_blif.c /^static void print_clusters(t_block *clb, int num_clusters, FILE * fpout) {$/;" f file: -print_clusters ./pack/output_clustering.c /^static void print_clusters(t_block *clb, int num_clusters, FILE * fpout) {$/;" f file: -print_complete_net_trace ./base/vpr_api.c /^static void print_complete_net_trace(t_trace* trace, const char *file_name) {$/;" f file: -print_critical_path ./timing/path_delay.c /^void print_critical_path(const char *fname) {$/;" f -print_critical_path_node ./timing/path_delay2.c /^float print_critical_path_node(FILE * fp, t_linked_int * critical_path_node) {$/;" f -print_criticality ./timing/path_delay.c /^void print_criticality(t_slack * slacks, boolean criticality_is_normalized, const char *fname) {$/;" f -print_distribution ./route/rr_graph.c /^print_distribution(FILE * fptr,$/;" f file: -print_formal_verification_top_netlist ./base/vpr_types.h /^ boolean print_formal_verification_top_netlist;$/;" m struct:s_syn_verilog_opts -print_global_criticality_stats ./timing/path_delay.c /^static void print_global_criticality_stats(FILE * fp, float ** criticality, const char * singular_name, const char * capitalized_plural_name) {$/;" f file: -print_input_blif_testbench ./base/vpr_types.h /^ boolean print_input_blif_testbench;$/;" m struct:s_syn_verilog_opts -print_interconnect ./pack/output_clustering.c /^static void print_interconnect(int inode, int *column, int num_tabs,$/;" f file: -print_lambda ./base/stats.c /^void print_lambda(void) {$/;" f -print_lut_remapping ./timing/path_delay.c /^void print_lut_remapping(const char *fname) {$/;" f -print_mirror_connection_block_stats ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void print_mirror_connection_block_stats() {$/;" f -print_mirror_switch_block_stats ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void print_mirror_switch_block_stats() {$/;" f -print_modelsim_autodeck ./base/vpr_types.h /^ boolean print_modelsim_autodeck;$/;" m struct:s_syn_verilog_opts -print_net_delay ./timing/path_delay.c /^void print_net_delay(float **net_delay, const char *fname) {$/;" f -print_net_name ./pack/output_blif.c /^static void print_net_name(int inet, int *column, FILE * fpout) {$/;" f file: -print_net_name ./pack/output_clustering.c /^static void print_net_name(int inet, int *column, int num_tabs, FILE * fpout) {$/;" f file: -print_net_opin_llist ./route/pb_pin_eq_auto_detect.c /^void print_net_opin_llist(t_llist* head) {$/;" f -print_net_opin_occupancy ./route/pb_pin_eq_auto_detect.c /^void print_net_opin_occupancy() {$/;" f -print_netlist ./pack/print_netlist.c /^void print_netlist(char *foutput, char *net_file) {$/;" f -print_open_pb_graph_node ./pack/output_clustering.c /^static void print_open_pb_graph_node(t_pb_graph_node * pb_graph_node,$/;" f file: -print_opt_info_help_desk ./fpga_x2p/shell/read_opt.c /^void print_opt_info_help_desk(t_opt_info* cur_opt_info) {$/;" f -print_pack_molecules ./pack/prepack.c /^static void print_pack_molecules(INP const char *fname,$/;" f file: -print_pb ./pack/output_blif.c /^static void print_pb(FILE *fpout, t_pb * pb, int clb_index) {$/;" f file: -print_pb ./pack/output_clustering.c /^static void print_pb(FILE *fpout, t_pb * pb, int pb_index, int tab_depth) {$/;" f file: -print_pinnum ./pack/print_netlist.c /^static void print_pinnum(FILE * fp, int pinnum) {$/;" f file: -print_place ./base/read_place.c /^void print_place(char *place_file, char *net_file, char *arch_file) {$/;" f -print_primitive ./pack/output_blif.c /^static void print_primitive(FILE *fpout, int iblk) {$/;" f file: -print_primitive_as_blif ./timing/path_delay.c /^static void print_primitive_as_blif (FILE *fpout, int iblk) {$/;" f file: -print_relative_pos_distr ./place/place_stats.c /^print_relative_pos_distr(void)$/;" f -print_report_timing_tcl ./base/vpr_types.h /^ boolean print_report_timing_tcl;$/;" m struct:s_syn_verilog_opts -print_route ./route/route_common.c /^void print_route(char *route_file) {$/;" f -print_rr_indexed_data ./route/rr_graph.c /^void print_rr_indexed_data(FILE * fp, int index) {$/;" f -print_rr_node ./route/rr_graph.c /^void print_rr_node(FILE * fp, t_rr_node * L_rr_node, int inode) {$/;" f -print_sdc_analysis ./base/vpr_types.h /^ boolean print_sdc_analysis;$/;" m struct:s_syn_verilog_opts -print_sdc_pnr ./base/vpr_types.h /^ boolean print_sdc_pnr;$/;" m struct:s_syn_verilog_opts -print_sink_delays ./place/timing_place.c /^void print_sink_delays(const char *fname) {$/;" f -print_slack ./timing/path_delay.c /^void print_slack(float ** slack, boolean slack_is_normalized, const char *fname) {$/;" f -print_spaces ./timing/path_delay.c /^static void print_spaces(FILE * fp, int num_spaces) {$/;" f file: -print_stat_memristor_buffer ./mrfpga/buffer_insertion.c /^int print_stat_memristor_buffer( char* fname, float buffer_size )$/;" f -print_stats ./pack/output_clustering.c /^static void print_stats(t_block *clb, int num_clusters) {$/;" f file: -print_string ./pack/output_blif.c /^static void print_string(const char *str_ptr, int *column, FILE * fpout) {$/;" f file: -print_string ./pack/output_clustering.c /^static void print_string(const char *str_ptr, int *column, int num_tabs, FILE * fpout) {$/;" f file: -print_tabs ./pack/output_clustering.c /^static void print_tabs(FILE *fpout, int num_tabs) {$/;" f file: -print_tabs ./util/vpr_utils.c /^void print_tabs(FILE * fpout, int num_tab) {$/;" f -print_thru_pins ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean print_thru_pins;$/;" m struct:s_trpt_opts file: -print_timing_constraint_info ./timing/path_delay.c /^static void print_timing_constraint_info(const char *fname) {$/;" f file: -print_timing_graph ./timing/path_delay.c /^void print_timing_graph(const char *fname) {$/;" f -print_timing_graph_as_blif ./timing/path_delay.c /^void print_timing_graph_as_blif (const char *fname, t_model *models) {$/;" f -print_timing_stats ./timing/path_delay.c /^void print_timing_stats(void) {$/;" f -print_top_testbench ./base/vpr_types.h /^ boolean print_top_testbench;$/;" m struct:s_syn_verilog_opts -print_user_defined_template ./base/vpr_types.h /^ boolean print_user_defined_template;$/;" m struct:s_syn_verilog_opts -print_wirelen_prob_dist ./base/stats.c /^void print_wirelen_prob_dist(void) {$/;" f -private_cmap ./base/graphics.c /^static Colormap private_cmap; \/* "None" unless a private cmap was allocated. *\/$/;" v file: -probability ./base/vpr_types.h /^ float probability;$/;" m struct:s_net_power -proc_time ./base/place_and_route.h /^ int proc_time;$/;" m struct:s_fmap_cell -proceed ./base/graphics.c /^proceed (void (*drawscreen) (void)) $/;" f file: -processComplexBlock ./base/read_netlist.c /^static void processComplexBlock(INOUTP ezxml_t Parent, INOUTP t_block *cb,$/;" f file: -processPb ./base/read_netlist.c /^static void processPb(INOUTP ezxml_t Parent, INOUTP t_pb* pb,$/;" f file: -processPorts ./base/read_netlist.c /^static void processPorts(INOUTP ezxml_t Parent, INOUTP t_pb* pb,$/;" f file: -process_arg_opt ./fpga_x2p/shell/read_opt.c /^boolean process_arg_opt(INP char** argv,$/;" f -process_constraints ./timing/path_delay.c /^static void process_constraints(void) {$/;" f file: -process_float_arg ./fpga_x2p/shell/read_opt.c /^float process_float_arg(INP char* arg) {$/;" f -process_int_arg ./fpga_x2p/shell/read_opt.c /^int process_int_arg(INP char* arg) {$/;" f -process_settings ./base/read_settings.c /^static int process_settings(ezxml_t Cur, char ** outv)$/;" f file: -process_shell_command ./fpga_x2p/shell/shell_utils.c /^void process_shell_command(char* line, t_shell_env* env) {$/;" f -process_tech_xml_load_transistor_info ./power/power_cmos_tech.c /^static void process_tech_xml_load_transistor_info(ezxml_t parent) {$/;" f file: -propagate_clock_domain_and_skew ./timing/path_delay.c /^static void propagate_clock_domain_and_skew(int inode) {$/;" f file: -ps ./base/graphics.c /^static FILE *ps;$/;" v file: -ps_bot ./base/graphics.c /^static float ps_left, ps_right, ps_top, ps_bot; \/* Figure boundaries for *$/;" v file: -ps_cnames ./base/graphics.c /^static const char *ps_cnames[NUM_COLOR] = {"white", "black", "grey55", "grey75",$/;" v file: -ps_left ./base/graphics.c /^static float ps_left, ps_right, ps_top, ps_bot; \/* Figure boundaries for *$/;" v file: -ps_right ./base/graphics.c /^static float ps_left, ps_right, ps_top, ps_bot; \/* Figure boundaries for *$/;" v file: -ps_top ./base/graphics.c /^static float ps_left, ps_right, ps_top, ps_bot; \/* Figure boundaries for *$/;" v file: -ps_xmult ./base/graphics.c /^static float ps_xmult, ps_ymult; \/* Transformation for PostScript. *\/$/;" v file: -ps_xmult ./base/graphics.h /^ float ps_xmult, ps_ymult;$/;" m struct:__anon6 -ps_ymult ./base/graphics.c /^static float ps_xmult, ps_ymult; \/* Transformation for PostScript. *\/$/;" v file: -ps_ymult ./base/graphics.h /^ float ps_xmult, ps_ymult;$/;" m struct:__anon6 -pt_on_object ./base/graphics.c /^int pt_on_object(float x, float y) { }$/;" f -pt_on_object ./base/graphics.c /^int pt_on_object(int all, float x, float y) {$/;" f -ptc_num ./base/vpr_types.h /^ short ptc_num;$/;" m struct:s_rr_node -ptr ./timing/slre.c /^ const char *ptr; \/\/ Pointer to the substring$/;" m struct:cap file: -quantifier ./timing/slre.c /^static void quantifier(struct slre *r, int prev, int op) {$/;" f file: -quicksort_float ./fpga_x2p/base/quicksort.c /^void quicksort_float(int len, $/;" f -quicksort_float_index ./fpga_x2p/base/quicksort.c /^void quicksort_float_index(int len, $/;" f -quit ./base/graphics.c /^quit (void (*drawscreen) (void)) $/;" f file: -random_top_testbench_verilog_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* random_top_testbench_verilog_file_postfix = "_formal_random_top_tb.v"; $/;" v -rc_node ./timing/net_delay_types.h /^ struct s_rc_node *rc_node;$/;" m struct:s_linked_rc_ptr typeref:struct:s_linked_rc_ptr::s_rc_node -re_expand ./route/route_tree_timing.h /^ short re_expand;$/;" m struct:s_rt_node -read_act_file ./base/vpr_types.h /^ boolean read_act_file;$/;" m struct:s_fpga_spice_opts -read_activity ./base/read_blif.c /^static void read_activity(char * activity_file) {$/;" f file: -read_and_process_blif ./base/read_blif.c /^void read_and_process_blif(char *blif_file,$/;" f -read_blif ./base/read_blif.c /^static void read_blif(char *blif_file, boolean sweep_hanging_nets_and_inputs,$/;" f file: -read_netlist ./base/read_netlist.c /^void read_netlist(INP const char *net_file, INP const t_arch *arch,$/;" f -read_options ./fpga_x2p/shell/read_opt.c /^boolean read_options(INP int argc,$/;" f -read_place ./base/read_place.c /^void read_place(INP const char *place_file, INP const char *arch_file,$/;" f -read_sdc ./timing/read_sdc.c /^void read_sdc(t_timing_inf timing_inf) {$/;" f -read_settings ./base/ReadOptions.h /^ int read_settings;$/;" m struct:s_options -read_settings_file ./base/read_settings.c /^int read_settings_file(char * file_name, char *** outv)$/;" f -read_user_pad_loc ./base/read_place.c /^void read_user_pad_loc(char *pad_loc_file) {$/;" f -realloc_and_load_pb_graph_pin_ptrs_at_var ./pack/pb_type_graph.c /^static boolean realloc_and_load_pb_graph_pin_ptrs_at_var(INP int line_num,$/;" f file: -reassign_rr_node_net_num_from_scratch ./route/pb_pin_eq_auto_detect.c /^void reassign_rr_node_net_num_from_scratch() {$/;" f -rec_add_pb_type_keywords_to_list ./fpga_x2p/base/fpga_x2p_setup.c /^void rec_add_pb_type_keywords_to_list(t_pb_type* cur_pb_type,$/;" f file: -rec_add_rr_graph_wired_lut_rr_edges ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void rec_add_rr_graph_wired_lut_rr_edges(INP t_pb* cur_op_pb,$/;" f -rec_add_unused_rr_graph_wired_lut_rr_edges ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void rec_add_unused_rr_graph_wired_lut_rr_edges(INP t_pb_graph_node* cur_op_pb_graph_node,$/;" f -rec_alloc_phy_pb_children ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_alloc_phy_pb_children(t_pb_graph_node* cur_pb_graph_node, $/;" f -rec_annotate_pb_type_primitive_node_physical_mode_pin ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void rec_annotate_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb_type,$/;" f -rec_annotate_phy_pb_type_primitive_node_physical_mode_pin ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void rec_annotate_phy_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb_type,$/;" f -rec_backannotate_one_pb_wired_luts_and_adapt_graph ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void rec_backannotate_one_pb_wired_luts_and_adapt_graph(t_pb* cur_pb,$/;" f -rec_backannotate_rr_node_net_num ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void rec_backannotate_rr_node_net_num(int LL_num_rr_nodes,$/;" f -rec_connect_rr_graph_for_phy_pb_graph_node ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void rec_connect_rr_graph_for_phy_pb_graph_node(INP t_pb_graph_node* cur_pb_graph_node, $/;" f -rec_copy_name_mux_in_node ./fpga_x2p/verilog/verilog_pbtypes.c /^void rec_copy_name_mux_in_node(t_pb_graph_node* master_node, $/;" f -rec_count_num_conf_bits_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int rec_count_num_conf_bits_pb(t_pb* cur_pb, $/;" f -rec_count_num_conf_bits_pb_type_default_mode ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int rec_count_num_conf_bits_pb_type_default_mode(t_pb_type* cur_pb_type,$/;" f -rec_count_num_conf_bits_pb_type_physical_mode ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type,$/;" f -rec_count_num_iopads_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_count_num_iopads_pb(t_pb* cur_pb) {$/;" f -rec_count_num_iopads_pb_type_default_mode ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_count_num_iopads_pb_type_default_mode(t_pb_type* cur_pb_type) {$/;" f -rec_count_num_iopads_pb_type_physical_mode ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_count_num_iopads_pb_type_physical_mode(t_pb_type* cur_pb_type) {$/;" f -rec_count_num_mode_bits_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_count_num_mode_bits_pb(t_pb* cur_pb) {$/;" f -rec_count_num_mode_bits_pb_type_default_mode ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type) {$/;" f -rec_count_rr_graph_nodes_for_phy_pb_graph_node ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^int rec_count_rr_graph_nodes_for_phy_pb_graph_node(t_pb_graph_node* cur_pb_graph_node) {$/;" f -rec_dump_conf_bits_to_bitstream_file ./fpga_x2p/bitstream/fpga_bitstream.c /^void rec_dump_conf_bits_to_bitstream_file(FILE* fp, $/;" f file: -rec_dump_verilog_spice_model_global_ports ./fpga_x2p/verilog/verilog_utils.c /^int rec_dump_verilog_spice_model_global_ports(FILE* fp, $/;" f -rec_dump_verilog_spice_model_lib_global_ports ./fpga_x2p/verilog/verilog_utils.c /^int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp, $/;" f -rec_fprint_spice_model_global_ports ./fpga_x2p/spice/spice_utils.c /^int rec_fprint_spice_model_global_ports(FILE* fp, $/;" f -rec_get_pb_graph_node_by_pb_type_and_placement_index_in_top_node ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_pb_graph_node* rec_get_pb_graph_node_by_pb_type_and_placement_index_in_top_node(t_pb_graph_node* cur_pb_graph_node, $/;" f -rec_get_pb_type_by_name ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_pb_type* rec_get_pb_type_by_name(t_pb_type* cur_pb_type, $/;" f -rec_get_phy_pb_by_name ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_phy_pb* rec_get_phy_pb_by_name(t_phy_pb* cur_phy_pb, $/;" f -rec_identify_pb_type_idle_mode ./fpga_x2p/base/fpga_x2p_setup.c /^void rec_identify_pb_type_idle_mode(t_pb_type* cur_pb_type) {$/;" f file: -rec_identify_pb_type_phy_mode ./fpga_x2p/base/fpga_x2p_setup.c /^void rec_identify_pb_type_phy_mode(t_pb_type* cur_pb_type) {$/;" f file: -rec_init_rr_graph_for_phy_pb_graph_node ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void rec_init_rr_graph_for_phy_pb_graph_node(INP t_pb_graph_node* cur_pb_graph_node, $/;" f -rec_link_primitive_pb_graph_node_pin_to_phy_pb_graph_pin ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void rec_link_primitive_pb_graph_node_pin_to_phy_pb_graph_pin(t_pb_graph_node* top_pb_graph_node,$/;" f -rec_load_unused_pb_graph_node_temp_net_num_to_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_load_unused_pb_graph_node_temp_net_num_to_pb(t_phy_pb* cur_pb) {$/;" f -rec_mark_one_pb_unused_pb_graph_node_temp_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_mark_one_pb_unused_pb_graph_node_temp_net_num(t_phy_pb* cur_pb) {$/;" f -rec_mark_pb_graph_node_primitive_placement_index_in_top_node ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void rec_mark_pb_graph_node_primitive_placement_index_in_top_node(t_pb_graph_node* cur_pb_graph_node) {$/;" f -rec_mark_pb_graph_node_temp_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_mark_pb_graph_node_temp_net_num(t_pb_graph_node* cur_pb_graph_node) {$/;" f -rec_reset_pb_graph_node_rr_node_index_physical_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_reset_pb_graph_node_rr_node_index_physical_pb(t_pb_graph_node* cur_pb_graph_node) {$/;" f -rec_reset_pb_type_phy_pb_type ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_reset_pb_type_phy_pb_type(t_pb_type* cur_pb_type) {$/;" f -rec_reset_pb_type_temp_placement_index ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_reset_pb_type_temp_placement_index(t_pb_type* cur_pb_type) {$/;" f -rec_stat_pb_type_keywords ./fpga_x2p/base/fpga_x2p_setup.c /^void rec_stat_pb_type_keywords(t_pb_type* cur_pb_type,$/;" f file: -rec_stats_spice_model_global_ports ./fpga_x2p/base/fpga_x2p_utils.c /^void rec_stats_spice_model_global_ports(t_spice_model* cur_spice_model,$/;" f -rec_sync_op_pb_mapping_to_phy_pb_children ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_sync_op_pb_mapping_to_phy_pb_children(t_pb* cur_op_pb, $/;" f -rec_sync_pb_post_routing_vpack_net_num ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void rec_sync_pb_post_routing_vpack_net_num(t_pb* cur_pb) {$/;" f -rec_sync_pb_vpack_net_num_to_phy_pb_rr_graph ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void rec_sync_pb_vpack_net_num_to_phy_pb_rr_graph(t_pb* cur_op_pb,$/;" f -rec_sync_wired_lut_to_one_phy_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void rec_sync_wired_lut_to_one_phy_pb(t_pb_graph_node* cur_pb_graph_node,$/;" f -rec_sync_wired_pb_vpack_net_num_to_phy_pb_rr_graph ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void rec_sync_wired_pb_vpack_net_num_to_phy_pb_rr_graph(t_pb_graph_node* cur_pb_graph_node,$/;" f -rec_update_net_info_local_rr_node_tree ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void rec_update_net_info_local_rr_node_tree(t_pb* src_pb,$/;" f -rec_verilog_generate_sdc_disable_unused_pb_types ./fpga_x2p/verilog/verilog_sdc.c /^void rec_verilog_generate_sdc_disable_unused_pb_types(FILE* fp, $/;" f -recommend_num_sim_clock_cycle ./fpga_x2p/base/fpga_x2p_utils.c /^int recommend_num_sim_clock_cycle(float sim_window_size) {$/;" f -recompute_bb_cost ./place/place.c /^static float recompute_bb_cost(void) {$/;" f file: -recompute_crit_iter ./base/vpr_types.h /^ int recompute_crit_iter;$/;" m struct:s_placer_opts -recompute_occupancy_from_scratch ./route/check_route.c /^static void recompute_occupancy_from_scratch(t_ivec ** clb_opins_used_locally) {$/;" f file: -recompute_timing_after ./base/ReadOptions.h /^ int recompute_timing_after;$/;" m struct:s_options -recompute_timing_after ./base/vpr_types.h /^ int recompute_timing_after;$/;" m struct:s_packer_opts -recover_rr_nodes_ipin_driver_switch ./route/rr_graph_opincb.c /^void recover_rr_nodes_ipin_driver_switch() {$/;" f file: -rect_off_screen ./base/graphics.c /^rect_off_screen (float x1, float y1, float x2, float y2) $/;" f file: -redraw_screen ./base/draw.c /^static void redraw_screen() {$/;" f file: -reference_verilog_benchmark_file ./base/vpr_types.h /^ char* reference_verilog_benchmark_file;$/;" m struct:s_syn_verilog_opts -regex_match ./timing/read_sdc.c /^static boolean regex_match (char * string, char * regular_expression) {$/;" f file: -relapos_rec_s ./place/place_stats.c /^typedef struct relapos_rec_s {$/;" s file: -relapos_rec_t ./place/place_stats.c /^} relapos_rec_t;$/;" t typeref:struct:relapos_rec_s file: -reload_ext_net_rr_terminal_cluster ./pack/cluster_legality.c /^void reload_ext_net_rr_terminal_cluster(void) {$/;" f -reload_intra_cluster_nets ./base/vpr_api.c /^static void reload_intra_cluster_nets(t_pb *pb) {$/;" f file: -relocate ./timing/slre.c /^static void relocate(struct slre *r, int begin, int shift) {$/;" f file: -rename_illegal_port ./base/vpr_types.h /^ boolean rename_illegal_port; \/* Rename illegal port names that is not compatible with verilog\/SPICE syntax *\/$/;" m struct:s_fpga_spice_opts -renaming_report_postfix ./fpga_x2p/base/fpga_x2p_globals.c /^char* renaming_report_postfix = "_io_renaming.rpt";$/;" v -report_cb_timing ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean report_cb_timing;$/;" m struct:s_trpt_opts file: -report_pb_timing ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean report_pb_timing;$/;" m struct:s_trpt_opts file: -report_routing_timing ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean report_routing_timing;$/;" m struct:s_trpt_opts file: -report_sb_timing ./fpga_x2p/verilog/verilog_report_timing.c /^ boolean report_sb_timing;$/;" m struct:s_trpt_opts file: -report_structure ./base/graphics.c /^void report_structure(t_report *report) {$/;" f -report_structure ./base/graphics.c /^void report_structure(t_report*) { }$/;" f -report_timing_path ./base/vpr_types.h /^ char* report_timing_path;$/;" m struct:s_syn_verilog_opts -requeue_primitive ./pack/cluster_placement.c /^static void requeue_primitive($/;" f file: -reserve_locally_used_opins ./route/route_common.c /^void reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins,$/;" f -reserved_syntax_char_head ./fpga_x2p/base/fpga_x2p_globals.c /^t_llist* reserved_syntax_char_head = NULL;$/;" v -reset_cluster_placement_stats ./pack/cluster_placement.c /^void reset_cluster_placement_stats($/;" f -reset_common_state ./base/graphics.c /^static void reset_common_state () {$/;" f file: -reset_flags ./route/check_route.c /^static void reset_flags(int inet, boolean * connected_to_route) {$/;" f file: -reset_legalizer_for_cluster ./pack/cluster_legality.c /^void reset_legalizer_for_cluster(t_block *clb) {$/;" f -reset_lookahead_pins_used ./pack/cluster.c /^static void reset_lookahead_pins_used(t_pb *cur_pb) {$/;" f file: -reset_path_costs ./route/route_common.c /^void reset_path_costs(void) {$/;" f -reset_pin_class_scratch_pad_rec ./pack/cluster_feasibility_filter.c /^static void reset_pin_class_scratch_pad_rec($/;" f file: -reset_placement ./place/timing_place_lookup.c /^static void reset_placement(void) {$/;" f file: -reset_rr_graph_path_costs ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void reset_rr_graph_path_costs(t_rr_graph* local_rr_graph) {$/;" f -reset_rr_graph_rr_node_route_structs ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void reset_rr_graph_rr_node_route_structs(t_rr_graph* local_rr_graph) {$/;" f -reset_rr_node_route_structs ./route/route_common.c /^void reset_rr_node_route_structs(void) {$/;" f -reset_rr_node_to_rc_node ./timing/net_delay.c /^void reset_rr_node_to_rc_node(t_linked_rc_ptr * rr_node_to_rc_node,$/;" f -reset_tried_but_unused_cluster_placements ./pack/cluster_placement.c /^void reset_tried_but_unused_cluster_placements($/;" f -reset_win32_state ./base/graphics.c /^void reset_win32_state () {$/;" f -restore_disable_timing_one_sb_output ./fpga_x2p/verilog/verilog_tcl_utils.c /^void restore_disable_timing_one_sb_output(FILE* fp, $/;" f -restore_original_device ./place/timing_place_lookup.c /^static void restore_original_device(void) {$/;" f file: -restore_routing ./route/route_common.c /^void restore_routing(struct s_trace **best_routing,$/;" f -restore_routing_cluster ./pack/cluster_legality.c /^void restore_routing_cluster(void) {$/;" f -resync_pb_graph_nodes_in_pb ./base/vpr_api.c /^static void resync_pb_graph_nodes_in_pb(t_pb_graph_node *pb_graph_node,$/;" f file: -resync_post_route_netlist ./base/vpr_api.c /^void resync_post_route_netlist() {$/;" f -ret_track_swseg_pattern ./route/rr_graph_swseg.c /^enum ret_track_swseg_pattern {$/;" g file: -revert_place_logical_block ./pack/cluster.c /^static void revert_place_logical_block(INP int iblock, INP int max_models) {$/;" f file: -rising_edge ./timing/read_sdc.c /^ float rising_edge;$/;" m struct:s_sdc_clock file: -root ./base/vpr_types.h /^ int root; \/* root index of molecule, logical_block_ptrs[root] is ptr to root logical block *\/$/;" m struct:s_pack_molecule -root_passes_early_filter ./pack/cluster_placement.c /^static boolean root_passes_early_filter(INP t_pb_graph_node *root, INP t_pack_molecule *molecule, INP int clb_index) {$/;" f file: -rotatable ./base/vpr_types.h /^ t_cb* rotatable; $/;" m struct:s_cb -rotatable ./base/vpr_types.h /^ t_sb* rotatable; $/;" m struct:s_sb -rotate_shift_swseg_pattern ./route/rr_graph_swseg.c /^boolean* rotate_shift_swseg_pattern(int pattern_length,$/;" f file: -route_bb ./fpga_x2p/base/fpga_x2p_types.h /^ t_bb *route_bb; \/* [0..num_nets-1]. Limits area in which each *\/$/;" m struct:fpga_spice_rr_graph -route_bb ./route/route_common.c /^struct s_bb *route_bb = NULL; \/* [0..num_nets-1]. Limits area in which each *\/$/;" v typeref:struct:s_bb -route_type ./base/vpr_types.h /^ enum e_route_type route_type;$/;" m struct:s_router_opts typeref:enum:s_router_opts::e_route_type -router_algorithm ./base/vpr_types.h /^ enum e_router_algorithm router_algorithm;$/;" m struct:s_router_opts typeref:enum:s_router_opts::e_router_algorithm -routing_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* routing_spice_file_name = "routing_header.sp";$/;" v -routing_spice_subckt_file_path_head ./fpga_x2p/spice/spice_globals.c /^t_llist* routing_spice_subckt_file_path_head = NULL;$/;" v -routing_stats ./base/stats.c /^void routing_stats(boolean full_stats, enum e_route_type route_type,$/;" f -routing_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* routing_verilog_file_name = "routing.v";$/;" v -routing_verilog_subckt_file_path_head ./fpga_x2p/verilog/verilog_global.c /^t_llist* routing_verilog_subckt_file_path_head = NULL;$/;" v -rr_blk_source ./base/globals.c /^int **rr_blk_source = NULL; \/* [0..(num_blocks-1)][0..(num_class-1)] *\/$/;" v -rr_blk_source ./base/globals_declare.h /^int **rr_blk_source; \/* [0..num_blocks-1][0..num_class-1] *\/$/;" v -rr_graph ./base/vpr_types.h /^ struct s_rr_node *rr_graph; \/* pointer to rr_graph connecting pbs of cluster *\/$/;" m struct:s_pb typeref:struct:s_pb::s_rr_node -rr_graph ./fpga_x2p/base/fpga_x2p_types.h /^ t_rr_graph* rr_graph;$/;" m struct:fpga_spice_phy_pb -rr_graph_externals ./route/rr_graph.c /^static void rr_graph_externals(t_timing_inf timing_inf,$/;" f file: -rr_indexed_data ./base/globals.c /^t_rr_indexed_data *rr_indexed_data = NULL; \/* [0..(num_rr_indexed_data-1)] *\/$/;" v -rr_indexed_data ./base/globals_declare.h /^t_rr_indexed_data *rr_indexed_data; \/* [0 .. num_rr_indexed_data-1] *\/$/;" v -rr_indexed_data ./fpga_x2p/base/fpga_x2p_types.h /^ t_rr_indexed_data *rr_indexed_data; \/* [0..(num_rr_indexed_data-1)] *\/$/;" m struct:fpga_spice_rr_graph -rr_mem_ch ./fpga_x2p/base/fpga_x2p_types.h /^ t_chunk rr_mem_ch;$/;" m struct:fpga_spice_rr_graph -rr_mem_ch ./pack/cluster_legality.c /^static t_chunk rr_mem_ch = {NULL, 0, NULL};$/;" v file: -rr_mem_ch ./route/rr_graph.c /^static t_chunk rr_mem_ch = {NULL, 0, NULL};$/;" v file: -rr_modified_head ./fpga_x2p/base/fpga_x2p_types.h /^ t_linked_f_pointer *rr_modified_head;$/;" m struct:fpga_spice_rr_graph -rr_modified_head ./route/route_common.c /^static struct s_linked_f_pointer *rr_modified_head = NULL;$/;" v typeref:struct:s_linked_f_pointer file: -rr_node ./base/globals.c /^t_rr_node *rr_node = NULL; \/* [0..(num_rr_nodes-1)] *\/$/;" v -rr_node ./base/globals_declare.h /^t_rr_node *rr_node; \/* [0..num_rr_nodes-1] *\/$/;" v -rr_node ./fpga_x2p/base/fpga_x2p_types.h /^ t_rr_node* rr_node;$/;" m struct:fpga_spice_rr_graph -rr_node_color ./base/draw.c /^static enum color_types *rr_node_color = NULL;$/;" v typeref:enum:color_types file: -rr_node_drive_switch_box ./fpga_x2p/base/fpga_x2p_utils.c /^int rr_node_drive_switch_box(t_rr_node* src_rr_node,$/;" f -rr_node_indices ./base/globals.c /^t_ivec ***rr_node_indices = NULL;$/;" v -rr_node_indices ./base/globals_declare.h /^t_ivec ***rr_node_indices;$/;" v -rr_node_indices ./fpga_x2p/base/fpga_x2p_types.h /^ t_ivec*** rr_node_indices;$/;" m struct:fpga_spice_rr_graph -rr_node_intrinsic_cost ./pack/cluster_legality.c /^static float rr_node_intrinsic_cost(int inode) {$/;" f file: -rr_node_is_global_clb_ipin ./route/check_rr_graph.c /^static boolean rr_node_is_global_clb_ipin(int inode) {$/;" f file: -rr_node_power ./power/power.c /^static t_rr_node_power * rr_node_power;$/;" v file: -rr_node_route_inf ./fpga_x2p/base/fpga_x2p_types.h /^ t_rr_node_route_inf* rr_node_route_inf;$/;" m struct:fpga_spice_rr_graph -rr_node_route_inf ./route/route_common.c /^t_rr_node_route_inf *rr_node_route_inf = NULL; \/* [0..num_rr_nodes-1] *\/$/;" v -rr_node_to_pb_mapping ./base/vpr_types.h /^ struct s_pb **rr_node_to_pb_mapping; \/* [0..num_local_rr_nodes-1] pointer look-up of which pb this rr_node belongs based on index, NULL if pb does not exist *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb -rr_node_to_pb_mapping ./fpga_x2p/base/fpga_x2p_types.h /^ t_phy_pb **rr_node_to_pb_mapping; \/* [0..num_local_rr_nodes-1] pointer look-up of which pb this rr_node belongs based on index, NULL if pb does not exist *\/$/;" m struct:fpga_spice_phy_pb -rr_node_to_rt_node ./route/route_tree_timing.c /^static t_rt_node **rr_node_to_rt_node = NULL; \/* [0..num_rr_nodes-1] *\/$/;" v file: -rram_design_tech ./fpga_x2p/spice/spice_globals.c /^int rram_design_tech = 0;$/;" v -rram_pass_tran_value ./mrfpga/mrfpga_globals.c /^float rram_pass_tran_value = 0;$/;" v -rram_veriloga_file_name ./fpga_x2p/spice/spice_globals.c /^char* rram_veriloga_file_name = "rram_behavior.va";$/;" v -rt_edge_free_list ./route/route_tree_timing.c /^static t_linked_rt_edge *rt_edge_free_list = NULL;$/;" v file: -rt_node_free_list ./route/route_tree_timing.c /^static t_rt_node *rt_node_free_list = NULL;$/;" v file: -rt_node_of_sink ./place/timing_place_lookup.c /^static t_rt_node **rt_node_of_sink;$/;" v file: -run_hspice_shell_script_name ./fpga_x2p/spice/spice_run_scripts.c /^static char* run_hspice_shell_script_name = "run_hspice_sim.sh";$/;" v file: -run_parasitic_net_estimation ./fpga_x2p/base/fpga_x2p_globals.c /^boolean run_parasitic_net_estimation = TRUE;$/;" v -run_shell ./fpga_x2p/shell/mini_shell.c /^void run_shell(int argc, char ** argv) {$/;" f -run_testbench_load_extraction ./fpga_x2p/base/fpga_x2p_globals.c /^boolean run_testbench_load_extraction = TRUE;$/;" v -s_TokenPair ./base/vpr_types.h /^struct s_TokenPair {$/;" s -s_annealing_sched ./base/vpr_types.h /^struct s_annealing_sched {$/;" s -s_bb ./base/vpr_types.h /^struct s_bb {$/;" s -s_bitstream_gen_opts ./base/vpr_types.h /^struct s_bitstream_gen_opts {$/;" s -s_block ./base/vpr_types.h /^struct s_block {$/;" s -s_buffer_plan ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" s file: -s_buffer_plan_list ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list;$/;" s file: -s_buffer_plan_node ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" s file: -s_cb ./base/vpr_types.h /^struct s_cb {$/;" s -s_clb_to_clb_directs ./base/vpr_types.h /^typedef struct s_clb_to_clb_directs {$/;" s -s_clock ./base/vpr_types.h /^typedef struct s_clock {$/;" s -s_cluster_placement_stats ./base/vpr_types.h /^typedef struct s_cluster_placement_stats {$/;" s -s_cmd_category ./fpga_x2p/shell/shell_types.h /^struct s_cmd_category {$/;" s -s_cmd_info ./fpga_x2p/shell/read_opt_types.h /^struct s_cmd_info {$/;" s -s_det_routing_arch ./base/vpr_types.h /^struct s_det_routing_arch {$/;" s -s_file_name_opts ./base/vpr_types.h /^struct s_file_name_opts {$/;" s -s_fmap_cell ./base/place_and_route.h /^typedef struct s_fmap_cell {$/;" s -s_fpga_spice_opts ./base/vpr_types.h /^struct s_fpga_spice_opts {$/;" s -s_grid_tile ./base/vpr_types.h /^typedef struct s_grid_tile {$/;" s -s_hash ./util/hash.h /^struct s_hash {$/;" s -s_hash_iterator ./util/hash.h /^struct s_hash_iterator {$/;" s -s_heap ./route/route_common.h /^struct s_heap {$/;" s -s_io ./base/vpr_types.h /^typedef struct s_io {$/;" s -s_legal_pos ./place/place.c /^typedef struct s_legal_pos {$/;" s file: -s_linked_edge ./route/rr_graph_util.h /^struct s_linked_edge {$/;" s -s_linked_f_pointer ./base/vpr_types.h /^struct s_linked_f_pointer {$/;" s -s_linked_rc_edge ./timing/net_delay_types.h /^struct s_linked_rc_edge {$/;" s -s_linked_rc_ptr ./timing/net_delay_types.h /^struct s_linked_rc_ptr {$/;" s -s_linked_rt_edge ./route/route_tree_timing.h /^struct s_linked_rt_edge {$/;" s -s_log ./power/power.h /^struct s_log {$/;" s -s_logical_block ./base/vpr_types.h /^typedef struct s_logical_block {$/;" s -s_model_stats ./base/read_blif.c /^struct s_model_stats {$/;" s file: -s_molecule_link ./pack/cluster.c /^struct s_molecule_link {$/;" s file: -s_mux ./route/rr_graph.c /^typedef struct s_mux {$/;" s file: -s_mux_arch ./power/power.h /^struct s_mux_arch {$/;" s -s_mux_node ./power/power.h /^struct s_mux_node {$/;" s -s_mux_size_distribution ./route/rr_graph.c /^typedef struct s_mux_size_distribution {$/;" s file: -s_net ./base/vpr_types.h /^typedef struct s_net {$/;" s -s_net_power ./base/vpr_types.h /^struct s_net_power {$/;" s -s_num_mapped_opins_stats ./route/pb_pin_eq_auto_detect.c /^struct s_num_mapped_opins_stats{$/;" s file: -s_opt_info ./fpga_x2p/shell/read_opt_types.h /^struct s_opt_info {$/;" s -s_options ./base/ReadOptions.h /^struct s_options {$/;" s -s_override_constraint ./base/vpr_types.h /^typedef struct s_override_constraint {$/;" s -s_pack_molecule ./base/vpr_types.h /^typedef struct s_pack_molecule {$/;" s -s_packer_opts ./base/vpr_types.h /^struct s_packer_opts {$/;" s -s_pb ./base/vpr_types.h /^typedef struct s_pb {$/;" s -s_pb_stats ./base/vpr_types.h /^typedef struct s_pb_stats {$/;" s -s_pl_blocks_to_be_moved ./place/place.c /^typedef struct s_pl_blocks_to_be_moved {$/;" s file: -s_pl_macro ./place/place_macro.h /^typedef struct s_pl_macro{$/;" s -s_pl_macro_member ./place/place_macro.h /^typedef struct s_pl_macro_member{$/;" s -s_pl_moved_block ./place/place.c /^typedef struct s_pl_moved_block {$/;" s file: -s_place_region ./base/vpr_types.h /^struct s_place_region {$/;" s -s_placer_opts ./base/vpr_types.h /^struct s_placer_opts {$/;" s -s_power_breakdown ./power/power_components.h /^struct s_power_breakdown {$/;" s -s_power_buffer_sc_levr_inf ./power/power.h /^struct s_power_buffer_sc_levr_inf {$/;" s -s_power_buffer_size_inf ./power/power.h /^struct s_power_buffer_size_inf {$/;" s -s_power_buffer_strength_inf ./power/power.h /^struct s_power_buffer_strength_inf {$/;" s -s_power_commonly_used ./power/power.h /^struct s_power_commonly_used {$/;" s -s_power_mux_info ./power/power.h /^struct s_power_mux_info {$/;" s -s_power_mux_volt_inf ./power/power.h /^struct s_power_mux_volt_inf {$/;" s -s_power_mux_volt_pair ./power/power.h /^struct s_power_mux_volt_pair {$/;" s -s_power_nmos_leakage_inf ./power/power.h /^struct s_power_nmos_leakage_inf {$/;" s -s_power_nmos_leakage_pair ./power/power.h /^struct s_power_nmos_leakage_pair {$/;" s -s_power_nmos_mux_inf ./power/power.h /^struct s_power_nmos_mux_inf {$/;" s -s_power_opts ./base/vpr_types.h /^struct s_power_opts {$/;" s -s_power_output ./power/power.h /^struct s_power_output {$/;" s -s_power_tech ./power/power.h /^struct s_power_tech {$/;" s -s_prepacked_tnode_data ./base/vpr_types.h /^typedef struct s_prepacked_tnode_data {$/;" s -s_rc_node ./timing/net_delay_types.h /^struct s_rc_node {$/;" s -s_router_opts ./base/vpr_types.h /^struct s_router_opts {$/;" s -s_rr_indexed_data ./base/vpr_types.h /^typedef struct s_rr_indexed_data {$/;" s -s_rr_node ./base/vpr_types.h /^struct s_rr_node {$/;" s -s_rr_node_power ./power/power.h /^struct s_rr_node_power {$/;" s -s_rt_node ./route/route_tree_timing.h /^struct s_rt_node {$/;" s -s_sb ./base/vpr_types.h /^struct s_sb {$/;" s -s_sdc_clock ./timing/read_sdc.c /^typedef struct s_sdc_clock {$/;" s file: -s_sdc_exclusive_group ./timing/read_sdc.c /^typedef struct s_sdc_exclusive_group {$/;" s file: -s_sdc_opts ./fpga_x2p/verilog/verilog_sdc.c /^struct s_sdc_opts {$/;" s file: -s_seg_details ./base/vpr_types.h /^typedef struct s_seg_details {$/;" s -s_shell_cmd ./fpga_x2p/shell/shell_types.h /^struct s_shell_cmd {$/;" s -s_shell_env ./fpga_x2p/shell/shell_types.h /^struct s_shell_env {$/;" s -s_slack ./base/vpr_types.h /^typedef struct s_slack {$/;" s -s_solution_inf ./power/power.h /^struct s_solution_inf {$/;" s -s_spice_opts ./base/vpr_types.h /^struct s_spice_opts {$/;" s -s_syn_verilog_opts ./base/vpr_types.h /^struct s_syn_verilog_opts {$/;" s -s_tedge ./base/vpr_types.h /^typedef struct s_tedge {$/;" s -s_timing_constraints ./base/vpr_types.h /^typedef struct s_timing_constraints { \/* Container structure for all SDC timing constraints. $/;" s -s_timing_stats ./base/vpr_types.h /^typedef struct s_timing_stats {$/;" s -s_tnode ./base/vpr_types.h /^typedef struct s_tnode {$/;" s -s_token ./util/token.h /^struct s_token {$/;" s -s_trace ./base/vpr_types.h /^typedef struct s_trace {$/;" s -s_transistor_inf ./power/power.h /^struct s_transistor_inf {$/;" s -s_transistor_size_inf ./power/power.h /^struct s_transistor_size_inf {$/;" s -s_trpt_opts ./fpga_x2p/verilog/verilog_report_timing.c /^struct s_trpt_opts {$/;" s file: -s_vpr_setup ./base/vpr_types.h /^typedef struct s_vpr_setup {$/;" s -s_wireL_cnt ./fpga_x2p/verilog/verilog_report_timing.c /^struct s_wireL_cnt {$/;" s file: -sat_blks_pins_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^int sat_blks_pins_prefer_side(int n_nets, t_net* nets, $/;" f -sat_one_blk_pins_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^int sat_one_blk_pins_prefer_side(int n_nets, t_net* nets, $/;" f -save_and_reset_routing_cluster ./pack/cluster_legality.c /^void save_and_reset_routing_cluster(void) {$/;" f -save_best_buffer_list ./mrfpga/buffer_insertion.c /^static void save_best_buffer_list( t_linked_int* best_list )$/;" f file: -save_best_timing ./mrfpga/buffer_insertion.c /^static void save_best_timing( float* sink_delay, t_linked_int* index, float* net_delay )$/;" f file: -save_cluster_solution ./pack/cluster_legality.c /^void save_cluster_solution(void) {$/;" f -save_routing ./route/route_common.c /^void save_routing(struct s_trace **best_routing,$/;" f -saved_base_cost ./base/vpr_types.h /^ float saved_base_cost;$/;" m struct:s_rr_indexed_data -saved_net_rr_terminals ./pack/cluster_legality.c /^static int **saved_net_rr_terminals;$/;" v file: -saved_num_nets_in_cluster ./pack/cluster_legality.c /^static int saved_num_nets_in_cluster;$/;" v file: -saved_xleft ./base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: -saved_xright ./base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: -saved_ybot ./base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: -saved_ytop ./base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: -sb ./base/vpr_types.h /^ boolean *sb;$/;" m struct:s_seg_details -sb_drive_rr_nodes ./base/vpr_types.h /^ t_rr_node** sb_drive_rr_nodes;$/;" m struct:s_rr_node -sb_drive_switches ./base/vpr_types.h /^ int* sb_drive_switches;$/;" m struct:s_rr_node -sb_info ./base/globals.c /^t_sb** sb_info = NULL;$/;" v -sb_num_drive_rr_nodes ./base/vpr_types.h /^ int sb_num_drive_rr_nodes;$/;" m struct:s_rr_node -sb_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* sb_spice_file_name_prefix = "sb_";$/;" v -sb_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* sb_verilog_file_name_prefix = "sb_";$/;" v -sc_levr ./power/power.h /^ float sc_levr;$/;" m struct:s_power_buffer_sc_levr_inf -sc_levr_inf ./power/power.h /^ t_power_buffer_sc_levr_inf * sc_levr_inf;$/;" m struct:s_power_buffer_strength_inf -sc_no_levr ./power/power.h /^ float sc_no_levr;$/;" m struct:s_power_buffer_strength_inf -scale_factor ./power/PowerSpicedComponent.c /^float PowerSpicedComponent::scale_factor(int num_inputs,$/;" f class:PowerSpicedComponent -scan_chain_heads ./fpga_x2p/spice/spice_globals.c /^t_llist* scan_chain_heads = NULL;$/;" v -sched_type ./base/vpr_types.h /^enum sched_type {$/;" g -screen_num ./base/graphics.c /^static int screen_num;$/;" v file: -sdc ./timing/read_sdc.c /^static FILE *sdc;$/;" v file: -sdc_analysis_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_analysis_file_name = "fpga_top_analysis.sdc";$/;" v -sdc_break_loop_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_break_loop_file_name = "break_loop.sdc";$/;" v -sdc_clock_period_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_clock_period_file_name = "clb_clock.sdc";$/;" v -sdc_clocks ./timing/read_sdc.c /^t_sdc_clock * sdc_clocks = NULL; \/* List of clock periods and offsets from create_clock commands *\/$/;" v -sdc_constrain_cb_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_constrain_cb_file_name = "cb.sdc";$/;" v -sdc_constrain_pb_type_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_constrain_pb_type_file_name = "clb_constraints.sdc";$/;" v -sdc_constrain_routing_chan_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_constrain_routing_chan_file_name = "routing_channels.sdc";$/;" v -sdc_constrain_sb_file_name ./fpga_x2p/verilog/verilog_global.c /^char* sdc_constrain_sb_file_name = "sb.sdc";$/;" v -sdc_dir ./fpga_x2p/verilog/verilog_report_timing.c /^ char* sdc_dir;$/;" m struct:s_trpt_opts file: -sdc_dir ./fpga_x2p/verilog/verilog_sdc.c /^ char* sdc_dir;$/;" m struct:s_sdc_opts file: -sdc_dump_all_pb_graph_nodes ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^void sdc_dump_all_pb_graph_nodes(FILE* fp,$/;" f -sdc_dump_annotation ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^void sdc_dump_annotation(char* from_path, \/\/ includes the cell$/;" f -sdc_dump_cur_node_constraints ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^void sdc_dump_cur_node_constraints(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -sdc_file_name ./base/vpr_types.h /^ char *sdc_file_name;$/;" m struct:s_packer_opts -sdc_rec_dump_child_pb_graph_node ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^void sdc_rec_dump_child_pb_graph_node(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -sdf_DFF_delay_printing ./base/verilog_writer.c /^void sdf_DFF_delay_printing(FILE *SDF , t_pb *pb)$/;" f -sdf_LUT_delay_printing ./base/verilog_writer.c /^void sdf_LUT_delay_printing(FILE *SDF , t_pb *pb)$/;" f -search_and_add_num_mapped_opin_llist ./route/pb_pin_eq_auto_detect.c /^t_llist* search_and_add_num_mapped_opin_llist(t_llist* head, $/;" f -search_mapped_block ./fpga_x2p/base/fpga_x2p_utils.c /^t_block* search_mapped_block(int x, int y, int z) {$/;" f -search_mux_linked_list ./fpga_x2p/base/fpga_x2p_mux_utils.c /^t_llist* search_mux_linked_list(t_llist* mux_head,$/;" f -search_swseg_pattern_seg_len ./route/rr_graph_swseg.c /^t_swseg_pattern_inf* search_swseg_pattern_seg_len(INP int num_swseg_pattern,$/;" f file: -search_tapbuf_llist_same_settings ./fpga_x2p/spice/spice_subckt.c /^int search_tapbuf_llist_same_settings(t_llist* head,$/;" f file: -searching_used_latch ./fpga_x2p/verilog/verilog_formality_autodeck.c /^static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chomped_circuit_name, char* inst_name){$/;" f file: -seed ./base/vpr_types.h /^ int seed;$/;" m struct:s_placer_opts -seg_index ./base/vpr_types.h /^ int seg_index;$/;" m struct:s_rr_indexed_data -seg_index_of_cblock ./route/rr_graph_util.c /^int seg_index_of_cblock(t_rr_type from_rr_type, int to_node) {$/;" f -seg_index_of_sblock ./route/rr_graph_util.c /^int seg_index_of_sblock(int from_node, int to_node) {$/;" f -seg_switch ./base/vpr_types.h /^ short seg_switch;$/;" m struct:s_seg_details -segments ./fpga_x2p/spice/spice_mux_testbench.c /^static t_segment_inf* segments;$/;" v file: -segments ./fpga_x2p/spice/spice_routing_testbench.c /^static t_segment_inf* segments;$/;" v file: -selected_input ./power/power.h /^ short selected_input; \/* Input index that is selected *\/$/;" m struct:s_rr_node_power -setAllEchoFileEnabled ./base/ReadOptions.c /^void setAllEchoFileEnabled(boolean value) {$/;" f -setEchoEnabled ./base/ReadOptions.c /^void setEchoEnabled(boolean echo_enabled) {$/;" f -setEchoFileEnabled ./base/ReadOptions.c /^void setEchoFileEnabled(enum e_echo_files echo_option, boolean value) {$/;" f -setEchoFileName ./base/ReadOptions.c /^void setEchoFileName(enum e_echo_files echo_option, const char *name) {$/;" f -setOutputFileName ./base/ReadOptions.c /^void setOutputFileName(enum e_output_files ename, const char *name, const char *default_name) {$/;" f -set_and_balance_arrival_time ./timing/path_delay.c /^static void set_and_balance_arrival_time(int to_node, int from_node, float Tdel, boolean do_lut_input_balancing) {$/;" f file: -set_blk_net_one_sink_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^void set_blk_net_one_sink_prefer_side(int* prefer_side, \/* [0..3] array, should be allocated before *\/$/;" f -set_disable_timing_one_sb_output ./fpga_x2p/verilog/verilog_tcl_utils.c /^void set_disable_timing_one_sb_output(FILE* fp, $/;" f -set_draw_mode ./base/graphics.c /^void set_draw_mode (enum e_draw_mode draw_mode) { }$/;" f -set_draw_mode ./base/graphics.c /^void set_draw_mode (enum e_draw_mode draw_mode) {$/;" f -set_graphics_state ./base/draw.c /^void set_graphics_state(boolean show_graphics_val, int gr_automode_val,$/;" f -set_jump_offset ./timing/slre.c /^static void set_jump_offset(struct slre *r, int pc, int offset) {$/;" f file: -set_keypress_input ./base/graphics.c /^void set_keypress_input (bool enable) {$/;" f -set_keypress_input ./base/graphics.c /^void set_keypress_input (bool) { }$/;" f -set_max_pins_per_side ./base/SetupVPR.c /^static void set_max_pins_per_side() {$/;" f file: -set_mode_cluster_placement_stats ./pack/cluster_placement.c /^void set_mode_cluster_placement_stats(INP t_pb_graph_node *pb_graph_node,$/;" f -set_mouse_move_input ./base/graphics.c /^void set_mouse_move_input (bool enable) {$/;" f -set_mouse_move_input ./base/graphics.c /^void set_mouse_move_input (bool) { }$/;" f -set_one_pb_rr_node_default_prev_node_edge ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void set_one_pb_rr_node_default_prev_node_edge(t_rr_node* pb_rr_graph, $/;" f file: -set_one_pb_rr_node_net_num ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void set_one_pb_rr_node_net_num(t_rr_node* pb_rr_graph, $/;" f file: -set_pb_graph_mode ./pack/cluster_legality.c /^void set_pb_graph_mode(t_pb_graph_node *pb_graph_node, int mode, int isOn) {$/;" f -set_spice_model_counter ./fpga_x2p/base/fpga_x2p_utils.c /^void set_spice_model_counter(int num_spice_models,$/;" f -set_src_bottom_side_net_one_sink_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^void set_src_bottom_side_net_one_sink_prefer_side(int* prefer_side, $/;" f -set_src_left_side_net_one_sink_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^void set_src_left_side_net_one_sink_prefer_side(int* prefer_side, $/;" f -set_src_right_side_net_one_sink_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^void set_src_right_side_net_one_sink_prefer_side(int* prefer_side, $/;" f -set_src_top_side_net_one_sink_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^void set_src_top_side_net_one_sink_prefer_side(int* prefer_side, $/;" f -set_type ./fpga_x2p/base/rr_chan.cpp /^void RRChan::set_type(t_rr_type type) {$/;" f class:RRChan -set_unroute_blk_pins_prefer_sides ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^int set_unroute_blk_pins_prefer_sides(int n_blk, t_block* blk) {$/;" f -setcolor ./base/graphics.c /^void setcolor (int cindex) $/;" f -setcolor ./base/graphics.c /^void setcolor (int cindex) { }$/;" f -setcolor ./base/graphics.c /^void setcolor (string cname) {$/;" f -setfontsize ./base/graphics.c /^void setfontsize (int pointsize) $/;" f -setfontsize ./base/graphics.c /^void setfontsize (int pointsize) { }$/;" f -setlinestyle ./base/graphics.c /^void setlinestyle (int linestyle) $/;" f -setlinestyle ./base/graphics.c /^void setlinestyle (int linestyle) { }$/;" f -setlinewidth ./base/graphics.c /^void setlinewidth (int linewidth) $/;" f -setlinewidth ./base/graphics.c /^void setlinewidth (int linewidth) { }$/;" f -setpoly ./base/graphics.c /^static void setpoly (int bnum, int xc, int yc, int r, float theta) $/;" f file: -setup_blocks_affected ./place/place.c /^static int setup_blocks_affected(int b_from, int x_to, int y_to, int z_to) {$/;" f file: -setup_chan_width ./place/timing_place_lookup.c /^static void setup_chan_width(struct s_router_opts router_opts,$/;" f file: -setup_intracluster_routing_for_logical_block ./pack/cluster_legality.c /^void setup_intracluster_routing_for_logical_block(INP int iblock,$/;" f -setup_intracluster_routing_for_molecule ./pack/cluster_legality.c /^void setup_intracluster_routing_for_molecule(INP t_pack_molecule *molecule,$/;" f -setup_junction_switch ./base/SetupVPR.c /^static void setup_junction_switch(struct s_det_routing_arch *det_routing_arch) {$/;" f file: -setup_vpr_opts ./fpga_x2p/shell/cmd_vpr_setup.h /^t_opt_info setup_vpr_opts[] = {$/;" v -sharinggain ./base/vpr_types.h /^ std::map sharinggain; \/* [0..num_logical_blocks-1]. How many nets on this logical_block are already in the pb under consideration *\/$/;" m struct:s_pb_stats -shell_cmd ./fpga_x2p/shell/shell_cmds.h /^t_shell_cmd shell_cmd[] = {$/;" v -shell_env ./fpga_x2p/shell/mini_shell.c /^t_shell_env shell_env;$/;" v -shell_execute_exit ./fpga_x2p/shell/cmd_exit.c /^void shell_execute_exit(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_execute_fpga_bitstream ./fpga_x2p/shell/cmd_fpga_bitstream.c /^void shell_execute_fpga_bitstream(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_execute_fpga_spice ./fpga_x2p/shell/cmd_fpga_spice.c /^void shell_execute_fpga_spice(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_execute_fpga_verilog ./fpga_x2p/shell/cmd_fpga_verilog.c /^void shell_execute_fpga_verilog(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_execute_fpga_x2p_setup ./fpga_x2p/shell/cmd_fpga_x2p_setup.c /^void shell_execute_fpga_x2p_setup(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_execute_help ./fpga_x2p/shell/cmd_help.c /^void shell_execute_help(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_execute_vpr_pack ./fpga_x2p/shell/cmd_vpr_pack.c /^void shell_execute_vpr_pack(t_shell_env* env, $/;" f -shell_execute_vpr_place_and_route ./fpga_x2p/shell/cmd_vpr_place_and_route.c /^void shell_execute_vpr_place_and_route(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_execute_vpr_setup ./fpga_x2p/shell/cmd_vpr_setup.c /^void shell_execute_vpr_setup(t_shell_env* env, $/;" f -shell_execute_vpr_versapower ./fpga_x2p/shell/cmd_vpr_power.c /^void shell_execute_vpr_versapower(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_init_vpr_place_and_route ./fpga_x2p/shell/cmd_vpr_place_and_route.c /^void shell_init_vpr_place_and_route(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_init_vpr_placer ./fpga_x2p/shell/cmd_vpr_place_and_route.c /^void shell_init_vpr_placer(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_init_vpr_router ./fpga_x2p/shell/cmd_vpr_place_and_route.c /^void shell_init_vpr_router(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_opts ./fpga_x2p/shell/mini_shell.h /^t_opt_info shell_opts[] = {$/;" v -shell_print_usage ./fpga_x2p/shell/shell_utils.c /^void shell_print_usage(t_shell_env* env) {$/;" f -shell_setup_fpga_bitstream ./fpga_x2p/shell/cmd_fpga_bitstream.c /^boolean shell_setup_fpga_bitstream(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_setup_fpga_spice ./fpga_x2p/shell/cmd_fpga_spice.c /^boolean shell_setup_fpga_spice(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_setup_fpga_verilog ./fpga_x2p/shell/cmd_fpga_verilog.c /^boolean shell_setup_fpga_verilog(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_setup_fpga_x2p_setup ./fpga_x2p/shell/cmd_fpga_x2p_setup.c /^boolean shell_setup_fpga_x2p_setup(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_setup_graphics ./fpga_x2p/shell/cmd_vpr_setup.c /^void shell_setup_graphics(t_shell_env* env, $/;" f -shell_setup_read_arch_opts ./fpga_x2p/shell/cmd_vpr_setup.c /^void shell_setup_read_arch_opts(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_setup_vpr_arch ./fpga_x2p/shell/cmd_vpr_setup.c /^void shell_setup_vpr_arch(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_setup_vpr_timing ./fpga_x2p/shell/cmd_vpr_setup.c /^void shell_setup_vpr_timing(t_shell_env* env) {$/;" f -shell_setup_vpr_versa_power ./fpga_x2p/shell/cmd_vpr_power.c /^boolean shell_setup_vpr_versa_power(t_shell_env* env, t_opt_info* opts) {$/;" f -shell_vpr_get_circuit_name ./fpga_x2p/shell/cmd_vpr_setup.c /^char* shell_vpr_get_circuit_name(char* blif_name) {$/;" f -shell_vpr_setup_default_file_names ./fpga_x2p/shell/cmd_vpr_setup.c /^void shell_vpr_setup_default_file_names(t_vpr_setup* vpr_setup, $/;" f -shell_vpr_setup_gen_one_file_name ./fpga_x2p/shell/cmd_vpr_setup.c /^char* shell_vpr_setup_gen_one_file_name(char* circuit_name,$/;" f -show_blif_stats ./base/read_blif.c /^static void show_blif_stats(t_model *user_models, t_model *library_models) {$/;" f file: -show_combinational_cycle_candidates ./timing/path_delay2.c /^static void show_combinational_cycle_candidates() {$/;" f file: -show_congestion ./base/draw.c /^static boolean show_congestion = FALSE;$/;" v file: -show_defects ./base/draw.c /^static boolean show_defects = FALSE; \/* Show defective stuff *\/$/;" v file: -show_graphics ./base/draw.c /^static boolean show_graphics; \/* Graphics enabled or not? *\/$/;" v file: -show_nets ./base/draw.c /^static boolean show_nets = FALSE; \/* Show nets of placement or routing? *\/$/;" v file: -show_opt_list ./fpga_x2p/shell/read_opt.c /^int show_opt_list(t_opt_info* cur) {$/;" f -signal_density_weight ./base/vpr_types.h /^ float signal_density_weight;$/;" m struct:s_fpga_spice_opts -sim_results_dir_name ./fpga_x2p/spice/spice_run_scripts.c /^static char* sim_results_dir_name = "results\/";$/;" v file: -sim_window_size ./base/vpr_types.h /^ float sim_window_size;$/;" m struct:s_fpga_spice_opts -simulator_path ./base/vpr_types.h /^ char* simulator_path;$/;" m struct:s_spice_opts -sink_delay ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: -sink_head ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: -sink_list ./base/vpr_types.h /^ char ** sink_list;$/;" m struct:s_override_constraint -sink_order ./place/timing_place_lookup.c /^static int *sink_order;$/;" v file: -size ./power/power.h /^ float size;$/;" m struct:s_transistor_size_inf -size ./route/rr_graph.c /^ int size;$/;" m struct:s_mux file: -size_inf ./power/power.h /^ t_transistor_size_inf * size_inf; \/* Array of transistor sizes *\/$/;" m struct:s_transistor_inf -skip_clustering ./base/ReadOptions.h /^ boolean skip_clustering;$/;" m struct:s_options -skip_clustering ./base/vpr_types.h /^ boolean skip_clustering;$/;" m struct:s_packer_opts -slack ./base/vpr_types.h /^ float ** slack;$/;" m struct:s_slack -slre ./timing/slre.c /^struct slre {$/;" s file: -slre_capture ./timing/slre.h /^enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT};$/;" g -slre_match ./timing/slre.c /^const char *slre_match(enum slre_option options, const char *re,$/;" f -slre_option ./timing/slre.h /^enum slre_option {SLRE_CASE_INSENSITIVE = 1};$/;" g -snapshot_spice_model_counter ./fpga_x2p/base/fpga_x2p_utils.c /^int* snapshot_spice_model_counter(int num_spice_models,$/;" f -snapshot_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^t_sram_orgz_info* snapshot_sram_orgz_info(t_sram_orgz_info* src_sram_orgz_info) {$/;" f -sort_me ./power/PowerSpicedComponent.c /^void PowerCallibInputs::sort_me() {$/;" f class:PowerCallibInputs -sort_me ./power/PowerSpicedComponent.c /^void PowerSpicedComponent::sort_me(void) {$/;" f class:PowerSpicedComponent -sort_one_class_conflict_pins_by_low_slack ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^int* sort_one_class_conflict_pins_by_low_slack(t_block* target_blk, int class_index,$/;" f -sorted ./power/PowerSpicedComponent.h /^ bool sorted;$/;" m class:PowerCallibInputs -sorted ./power/PowerSpicedComponent.h /^ bool sorted;$/;" m class:PowerSpicedComponent -sorter_PowerCallibInputs ./power/PowerSpicedComponent.c /^bool sorter_PowerCallibInputs(PowerCallibInputs * a, PowerCallibInputs * b) {$/;" f -sorter_PowerCallibSize ./power/PowerSpicedComponent.c /^bool sorter_PowerCallibSize(PowerCallibSize * a, PowerCallibSize * b) {$/;" f -source_list ./base/vpr_types.h /^ char ** source_list; \/* Array of net names of flip-flops or clocks *\/$/;" m struct:s_override_constraint -spice_backannotate_vpr_post_route_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void spice_backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch,$/;" f -spice_cb_mux_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_cb_mux_tb_dir_name = "cb_mux_tb\/";$/;" v file: -spice_cb_mux_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_cb_mux_testbench_postfix = "_cbmux_testbench.sp";$/;" v -spice_cb_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_cb_tb_dir_name = "cb_tb\/";$/;" v file: -spice_cb_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_cb_testbench_postfix = "_cb_testbench.sp";$/;" v -spice_create_one_subckt_file ./fpga_x2p/spice/spice_utils.c /^FILE* spice_create_one_subckt_file(char* subckt_dir,$/;" f -spice_dff_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_dff_testbench_postfix = "_dff_testbench.sp";$/;" v -spice_dir ./base/ReadOptions.h /^ char* spice_dir;$/;" m struct:s_options -spice_dir ./base/vpr_types.h /^ char* spice_dir;$/;" m struct:s_spice_opts -spice_grid_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_grid_tb_dir_name = "grid_tb\/";$/;" v file: -spice_grid_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_grid_testbench_postfix = "_grid_testbench.sp";$/;" v -spice_hardlogic_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_hardlogic_tb_dir_name = "hardlogic_tb\/";$/;" v file: -spice_hardlogic_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_hardlogic_testbench_postfix = "_hardlogic_testbench.sp";$/;" v -spice_io_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_io_tb_dir_name = "io_tb\/";$/;" v file: -spice_io_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_io_testbench_postfix = "_io_testbench.sp";$/;" v -spice_lut_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_lut_tb_dir_name = "lut_tb\/";$/;" v file: -spice_lut_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_lut_testbench_postfix = "_lut_testbench.sp";$/;" v -spice_model ./base/vpr_types.h /^ t_spice_model* spice_model;$/;" m struct:s_clb_to_clb_directs -spice_name_tag ./base/vpr_types.h /^ char* spice_name_tag;$/;" m struct:s_pb -spice_name_tag ./fpga_x2p/base/fpga_x2p_types.h /^ char* spice_name_tag;$/;" m struct:fpga_spice_phy_pb -spice_net_info ./base/vpr_types.h /^ t_spice_net_info* spice_net_info;$/;" m struct:s_net -spice_net_info_add_density_weight ./fpga_x2p/base/fpga_x2p_setup.c /^void spice_net_info_add_density_weight(float signal_density_weight) {$/;" f file: -spice_netlist_file_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_netlist_file_postfix = ".sp";$/;" v -spice_pb_mux_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_pb_mux_tb_dir_name = "pb_mux_tb\/";$/;" v file: -spice_pb_mux_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_pb_mux_testbench_postfix = "_pbmux_testbench.sp";$/;" v -spice_print_cb_testbench ./fpga_x2p/spice/spice_routing_testbench.c /^void spice_print_cb_testbench(char* formatted_spice_dir,$/;" f -spice_print_grid_testbench ./fpga_x2p/spice/spice_grid_testbench.c /^void spice_print_grid_testbench(char* formatted_spice_dir,$/;" f -spice_print_headers ./fpga_x2p/spice/spice_heads.c /^void spice_print_headers(char* include_dir_path,$/;" f -spice_print_mux_testbench ./fpga_x2p/spice/spice_mux_testbench.c /^void spice_print_mux_testbench(char* formatted_spice_dir,$/;" f -spice_print_one_include_subckt_line ./fpga_x2p/spice/spice_utils.c /^void spice_print_one_include_subckt_line(FILE* fp, $/;" f -spice_print_primitive_testbench ./fpga_x2p/spice/spice_primitive_testbench.c /^void spice_print_primitive_testbench(char* formatted_spice_dir,$/;" f -spice_print_sb_testbench ./fpga_x2p/spice/spice_routing_testbench.c /^void spice_print_sb_testbench(char* formatted_spice_dir,$/;" f -spice_print_subckt_header_file ./fpga_x2p/spice/spice_utils.c /^void spice_print_subckt_header_file(t_llist* subckt_llist_head,$/;" f -spice_print_top_netlist ./fpga_x2p/spice/spice_top_netlist.c /^void spice_print_top_netlist(char* circuit_name,$/;" f -spice_sb_mux_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_sb_mux_tb_dir_name = "sb_mux_tb\/";$/;" v file: -spice_sb_mux_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_sb_mux_testbench_postfix = "_sbmux_testbench.sp";$/;" v -spice_sb_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_sb_tb_dir_name = "sb_tb\/";$/;" v file: -spice_sb_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_sb_testbench_postfix = "_sb_testbench.sp";$/;" v -spice_sim_multi_thread_num ./fpga_x2p/spice/spice_globals.c /^int spice_sim_multi_thread_num = 8;$/;" v -spice_tb_global_clock_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_clock_port_name = "gclock";$/;" v -spice_tb_global_config_done_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_config_done_port_name = "gconfig_done";$/;" v -spice_tb_global_gnd_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_gnd_port_name = "ggnd";$/;" v -spice_tb_global_port_inv_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_port_inv_postfix = "_inv";$/;" v -spice_tb_global_reset_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_reset_port_name = "greset";$/;" v -spice_tb_global_set_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_set_port_name = "gset";$/;" v -spice_tb_global_vdd_cb_sram_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_cb_sram_port_name = "gvdd_sram_cbs";$/;" v -spice_tb_global_vdd_direct_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_direct_port_name = "gvdd_direct_interc";$/;" v -spice_tb_global_vdd_hardlogic_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_hardlogic_port_name = "gvdd_hardlogic";$/;" v -spice_tb_global_vdd_hardlogic_sram_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_hardlogic_sram_port_name = "gvdd_sram_hardlogic";$/;" v -spice_tb_global_vdd_io_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_io_port_name = "gvdd_io";$/;" v -spice_tb_global_vdd_io_sram_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_io_sram_port_name = "gvdd_sram_io";$/;" v -spice_tb_global_vdd_load_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_load_port_name = "gvdd_load";$/;" v -spice_tb_global_vdd_localrouting_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_localrouting_port_name = "gvdd_local_interc";$/;" v -spice_tb_global_vdd_localrouting_sram_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_localrouting_sram_port_name = "gvdd_sram_local_routing";$/;" v -spice_tb_global_vdd_lut_sram_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_lut_sram_port_name = "gvdd_sram_luts";$/;" v -spice_tb_global_vdd_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_port_name = "gvdd";$/;" v -spice_tb_global_vdd_sb_sram_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_sb_sram_port_name = "gvdd_sram_sbs";$/;" v -spice_tb_global_vdd_sram_port_name ./fpga_x2p/spice/spice_globals.c /^char* spice_tb_global_vdd_sram_port_name = "gvdd_sram";$/;" v -spice_top_tb_dir_name ./fpga_x2p/spice/spice_api.c /^static char* spice_top_tb_dir_name = "top_tb\/";$/;" v file: -spice_top_testbench_postfix ./fpga_x2p/spice/spice_globals.c /^char* spice_top_testbench_postfix = "_top.sp";$/;" v -split_path_prog_name ./fpga_x2p/base/fpga_x2p_utils.c /^int split_path_prog_name(char* prog_path,$/;" f -spot_blk_position_in_a_macro ./place/place_macro.c /^int spot_blk_position_in_a_macro(t_pl_macro pl_macros,$/;" f -sram_spice_model ./fpga_x2p/spice/spice_globals.c /^t_spice_model* sram_spice_model = NULL;$/;" v -sram_spice_orgz_info ./fpga_x2p/spice/spice_globals.c /^t_sram_orgz_info* sram_spice_orgz_info = NULL;$/;" v -sram_spice_orgz_type ./fpga_x2p/spice/spice_globals.c /^enum e_sram_orgz sram_spice_orgz_type = SPICE_SRAM_STANDALONE;$/;" v typeref:enum:e_sram_orgz -sram_verilog_model ./fpga_x2p/verilog/verilog_global.c /^t_spice_model* sram_verilog_model = NULL;$/;" v -stage_gain ./power/power.h /^ float stage_gain;$/;" m struct:s_power_buffer_strength_inf -start ./base/vpr_types.h /^ int start;$/;" m struct:s_seg_details -start_hash_table_iterator ./util/hash.c /^struct s_hash_iterator start_hash_table_iterator(void) {$/;" f -start_new_cluster ./pack/cluster.c /^static void start_new_cluster($/;" f file: -start_seg_switch ./mrfpga/mrfpga_globals.c /^short start_seg_switch;$/;" v -starting_pin_idx ./power/power.h /^ int starting_pin_idx; \/* Applicable to level 0 only, the overall mux primary input index *\/$/;" m struct:s_mux_node -starting_t ./place/place.c /^static float starting_t(float *cost_ptr, float *bb_cost_ptr,$/;" f file: -stats_lut_spice_mux ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void stats_lut_spice_mux(t_llist** muxes_head,$/;" f -stats_mux_spice_model_pb_node_rec ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void stats_mux_spice_model_pb_node_rec(t_llist** muxes_head,$/;" f -stats_mux_spice_model_pb_type_rec ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void stats_mux_spice_model_pb_type_rec(t_llist** muxes_head,$/;" f -stats_mux_verilog_model_pb_node_rec ./fpga_x2p/verilog/verilog_pbtypes.c /^void stats_mux_verilog_model_pb_node_rec(t_llist** muxes_head,$/;" f -stats_mux_verilog_model_pb_type_rec ./fpga_x2p/verilog/verilog_pbtypes.c /^void stats_mux_verilog_model_pb_type_rec(t_llist** muxes_head,$/;" f -stats_pb_graph_node_port_pin_numbers ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void stats_pb_graph_node_port_pin_numbers(t_pb_graph_node* cur_pb_graph_node,$/;" f -stats_spice_muxes ./fpga_x2p/base/fpga_x2p_mux_utils.c /^t_llist* stats_spice_muxes(int num_switches,$/;" f -stats_spice_muxes_routing_arch ./fpga_x2p/base/fpga_x2p_mux_utils.c /^void stats_spice_muxes_routing_arch(t_llist** muxes_head,$/;" f -statusMessage ./base/graphics.c /^static char statusMessage[BUFSIZE] = ""; \/* User message to display *\/$/;" v file: -std ./base/graphics.c /^using namespace std;$/;" v -std ./power/PowerSpicedComponent.c /^using namespace std;$/;" v -std ./power/power.c /^using namespace std;$/;" v -std ./power/power_cmos_tech.c /^using namespace std;$/;" v -std ./power/power_components.c /^using namespace std;$/;" v -std ./power/power_sizing.c /^using namespace std;$/;" v -std ./power/power_util.c /^using namespace std;$/;" v -stimu_header_file_name ./fpga_x2p/spice/spice_globals.c /^char* stimu_header_file_name = "stimulate_params.sp";$/;" v -store_char_in_data ./timing/slre.c /^static void store_char_in_data(struct slre *r, int ch) {$/;" f file: -strength_inf ./power/power.h /^ t_power_buffer_strength_inf * strength_inf;$/;" m struct:s_power_buffer_size_inf -subckt_dir ./base/vpr_types.h /^ char* subckt_dir;$/;" m struct:s_spice_opts -submodule_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* submodule_verilog_file_name = "sub_module.v";$/;" v -submodule_verilog_subckt_file_path_head ./fpga_x2p/verilog/verilog_global.c /^t_llist* submodule_verilog_subckt_file_path_head = NULL;$/;" v -sum_pin_class ./pack/cluster_feasibility_filter.c /^static void sum_pin_class(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f file: -swap_blk_same_class_2pins ./fpga_x2p/clb_pin_remap/clb_pin_remap_util.c /^void swap_blk_same_class_2pins(t_block* target_blk, int n_nets, t_net* nets,$/;" f -swap_float ./fpga_x2p/base/quicksort.c /^void swap_float(float* int_a, float* int_b) {$/;" f file: -swap_int ./fpga_x2p/base/quicksort.c /^void swap_int(int* int_a, int* int_b) {$/;" f file: -swap_result ./place/place.c /^enum swap_result {$/;" g file: -swapped_to_empty ./place/place.c /^ int swapped_to_empty;$/;" m struct:s_pl_moved_block file: -sweep_hanging_nets_and_inputs ./base/ReadOptions.h /^ boolean sweep_hanging_nets_and_inputs;$/;" m struct:s_options -sweep_hanging_nets_and_inputs ./base/vpr_types.h /^ boolean sweep_hanging_nets_and_inputs;$/;" m struct:s_packer_opts -switch_block_type ./base/vpr_types.h /^ enum e_switch_block_type switch_block_type;$/;" m struct:s_det_routing_arch typeref:enum:s_det_routing_arch::e_switch_block_type -switch_inf ./base/globals.c /^struct s_switch_inf *switch_inf = NULL; \/* [0..(det_routing_arch.num_switch-1)] *\/$/;" v typeref:struct:s_switch_inf -switch_inf ./base/globals_declare.h /^struct s_switch_inf *switch_inf; \/* [0..det_routing_arch.num_switch-1] *\/$/;" v typeref:struct:s_switch_inf -switch_inf ./fpga_x2p/base/fpga_x2p_types.h /^ t_switch_inf* switch_inf;$/;" m struct:fpga_spice_rr_graph -switches ./base/vpr_types.h /^ short *switches;$/;" m struct:s_rr_node -swseg_pattern_change_switch_type ./route/rr_graph_swseg.c /^int swseg_pattern_change_switch_type(int cur_node,$/;" f file: -swseg_patterns ./base/vpr_types.h /^ t_swseg_pattern_inf* swseg_patterns; \/* Xifan TANG: Switch Segment Pattern Support *\/$/;" m struct:s_vpr_setup -syn_verilog_dump_dir ./base/vpr_types.h /^ char* syn_verilog_dump_dir;$/;" m struct:s_syn_verilog_opts -sync_arch_mrfpga_globals ./mrfpga/mrfpga_api.c /^void sync_arch_mrfpga_globals(t_arch_mrfpga arch_mrfpga) {$/;" f -sync_grid_to_blocks ./util/vpr_utils.c /^void sync_grid_to_blocks(INP int L_num_blocks,$/;" f -sync_pb_graph_pin_vpack_net_num_to_phy_pb ./fpga_x2p/router/fpga_x2p_pb_rr_graph.c /^void sync_pb_graph_pin_vpack_net_num_to_phy_pb(t_rr_node* cur_op_pb_rr_graph, $/;" f -szAppName ./base/graphics.c /^static TCHAR szAppName[256], $/;" v file: -szButtonsName ./base/graphics.c /^szButtonsName[] = TEXT("VPR Buttons");$/;" v file: -szGraphicsName ./base/graphics.c /^szGraphicsName[] = TEXT("VPR Graphics"), $/;" v file: -szStatusName ./base/graphics.c /^szStatusName[] = TEXT("VPR Status"),$/;" v file: -t_bb ./base/vpr_types.h /^typedef struct s_bb t_bb;$/;" t typeref:struct:s_bb -t_bitstream_gen_opts ./base/vpr_types.h /^typedef struct s_bitstream_gen_opts t_bitstream_gen_opts;$/;" t typeref:struct:s_bitstream_gen_opts -t_block ./base/vpr_types.h /^typedef struct s_block t_block;$/;" t typeref:struct:s_block -t_buffer_plan ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" t typeref:struct:s_buffer_plan file: -t_buffer_plan_list ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list;$/;" t typeref:struct:s_buffer_plan_list file: -t_buffer_plan_node ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" t typeref:struct:s_buffer_plan_node file: -t_button ./base/graphics.c /^} t_button;$/;" t typeref:struct:__anon4 file: -t_button_type ./base/graphics.c /^} t_button_type;$/;" t typeref:enum:__anon3 file: -t_cb ./base/vpr_types.h /^typedef struct s_cb t_cb;$/;" t typeref:struct:s_cb -t_clb_to_clb_directs ./base/vpr_types.h /^} t_clb_to_clb_directs;$/;" t typeref:struct:s_clb_to_clb_directs -t_clock ./base/vpr_types.h /^} t_clock;$/;" t typeref:struct:s_clock -t_cluster_placement_stats ./base/vpr_types.h /^} t_cluster_placement_stats;$/;" t typeref:struct:s_cluster_placement_stats -t_cmd_category ./fpga_x2p/shell/shell_types.h /^typedef struct s_cmd_category t_cmd_category;$/;" t typeref:struct:s_cmd_category -t_cmd_info ./fpga_x2p/shell/read_opt_types.h /^typedef struct s_cmd_info t_cmd_info;$/;" t typeref:struct:s_cmd_info -t_det_routing_arch ./base/vpr_types.h /^typedef struct s_det_routing_arch t_det_routing_arch;$/;" t typeref:struct:s_det_routing_arch -t_display_type ./base/graphics.c /^} t_display_type;$/;" t typeref:enum:__anon2 file: -t_fmap_cell ./base/place_and_route.h /^} t_fmap_cell;$/;" t typeref:struct:s_fmap_cell -t_fpga_spice_opts ./base/vpr_types.h /^typedef struct s_fpga_spice_opts t_fpga_spice_opts;$/;" t typeref:struct:s_fpga_spice_opts -t_gl_state ./base/graphics.c /^} t_gl_state;$/;" t typeref:struct:__anon5 file: -t_graph_type ./route/rr_graph.h /^typedef enum e_graph_type t_graph_type;$/;" t typeref:enum:e_graph_type -t_grid_tile ./base/vpr_types.h /^} t_grid_tile;$/;" t typeref:struct:s_grid_tile -t_heap ./route/route_common.h /^typedef struct s_heap t_heap;$/;" t typeref:struct:s_heap -t_io ./base/vpr_types.h /^} t_io;$/;" t typeref:struct:s_io -t_legal_pos ./place/place.c /^}t_legal_pos;$/;" t typeref:struct:s_legal_pos file: -t_linked_edge ./route/rr_graph_util.h /^typedef struct s_linked_edge t_linked_edge;$/;" t typeref:struct:s_linked_edge -t_linked_f_pointer ./base/vpr_types.h /^typedef struct s_linked_f_pointer t_linked_f_pointer;$/;" t typeref:struct:s_linked_f_pointer -t_linked_rc_edge ./timing/net_delay_types.h /^typedef struct s_linked_rc_edge t_linked_rc_edge;$/;" t typeref:struct:s_linked_rc_edge -t_linked_rc_ptr ./timing/net_delay_types.h /^typedef struct s_linked_rc_ptr t_linked_rc_ptr;$/;" t typeref:struct:s_linked_rc_ptr -t_linked_rt_edge ./route/route_tree_timing.h /^typedef struct s_linked_rt_edge t_linked_rt_edge;$/;" t typeref:struct:s_linked_rt_edge -t_log ./power/power.h /^typedef struct s_log t_log;$/;" t typeref:struct:s_log -t_logical_block ./base/vpr_types.h /^} t_logical_block;$/;" t typeref:struct:s_logical_block -t_mux ./route/rr_graph.c /^} t_mux;$/;" t typeref:struct:s_mux file: -t_mux_arch ./power/power.h /^typedef struct s_mux_arch t_mux_arch;$/;" t typeref:struct:s_mux_arch -t_mux_node ./power/power.h /^typedef struct s_mux_node t_mux_node;$/;" t typeref:struct:s_mux_node -t_mux_size_distribution ./route/rr_graph.c /^} t_mux_size_distribution;$/;" t typeref:struct:s_mux_size_distribution file: -t_net ./base/vpr_types.h /^} t_net;$/;" t typeref:struct:s_net -t_net_power ./base/vpr_types.h /^typedef struct s_net_power t_net_power;$/;" t typeref:struct:s_net_power -t_num_mapped_opins_stats ./route/pb_pin_eq_auto_detect.c /^typedef struct s_num_mapped_opins_stats t_num_mapped_opins_stats;$/;" t typeref:struct:s_num_mapped_opins_stats file: -t_opt_info ./fpga_x2p/shell/read_opt_types.h /^typedef struct s_opt_info t_opt_info;$/;" t typeref:struct:s_opt_info -t_options ./base/ReadOptions.h /^typedef struct s_options t_options;$/;" t typeref:struct:s_options -t_override_constraint ./base/vpr_types.h /^} t_override_constraint;$/;" t typeref:struct:s_override_constraint -t_pack_molecule ./base/vpr_types.h /^} t_pack_molecule;$/;" t typeref:struct:s_pack_molecule -t_pb ./base/vpr_types.h /^} t_pb;$/;" t typeref:struct:s_pb -t_pb_stats ./base/vpr_types.h /^} t_pb_stats;$/;" t typeref:struct:s_pb_stats -t_phy_pb ./fpga_x2p/base/fpga_x2p_types.h /^typedef struct fpga_spice_phy_pb t_phy_pb;$/;" t typeref:struct:fpga_spice_phy_pb -t_pl_blocks_to_be_moved ./place/place.c /^}t_pl_blocks_to_be_moved;$/;" t typeref:struct:s_pl_blocks_to_be_moved file: -t_pl_macro ./place/place_macro.h /^} t_pl_macro;$/;" t typeref:struct:s_pl_macro -t_pl_macro_member ./place/place_macro.h /^} t_pl_macro_member;$/;" t typeref:struct:s_pl_macro_member -t_pl_moved_block ./place/place.c /^}t_pl_moved_block;$/;" t typeref:struct:s_pl_moved_block file: -t_point ./base/easygl_constants.h /^} t_point; \/* Used in calls to fillpoly *\/$/;" t typeref:struct:__anon1 -t_power_buffer_sc_levr_inf ./power/power.h /^typedef struct s_power_buffer_sc_levr_inf t_power_buffer_sc_levr_inf;$/;" t typeref:struct:s_power_buffer_sc_levr_inf -t_power_buffer_size_inf ./power/power.h /^typedef struct s_power_buffer_size_inf t_power_buffer_size_inf;$/;" t typeref:struct:s_power_buffer_size_inf -t_power_buffer_strength_inf ./power/power.h /^typedef struct s_power_buffer_strength_inf t_power_buffer_strength_inf;$/;" t typeref:struct:s_power_buffer_strength_inf -t_power_commonly_used ./power/power.h /^typedef struct s_power_commonly_used t_power_commonly_used;$/;" t typeref:struct:s_power_commonly_used -t_power_components ./power/power_components.h /^typedef struct s_power_breakdown t_power_components;$/;" t typeref:struct:s_power_breakdown -t_power_mux_info ./power/power.h /^typedef struct s_power_mux_info t_power_mux_info;$/;" t typeref:struct:s_power_mux_info -t_power_mux_volt_inf ./power/power.h /^typedef struct s_power_mux_volt_inf t_power_mux_volt_inf;$/;" t typeref:struct:s_power_mux_volt_inf -t_power_mux_volt_pair ./power/power.h /^typedef struct s_power_mux_volt_pair t_power_mux_volt_pair;$/;" t typeref:struct:s_power_mux_volt_pair -t_power_nmos_leakage_inf ./power/power.h /^typedef struct s_power_nmos_leakage_inf t_power_nmos_leakage_inf;$/;" t typeref:struct:s_power_nmos_leakage_inf -t_power_nmos_leakage_pair ./power/power.h /^typedef struct s_power_nmos_leakage_pair t_power_nmos_leakage_pair;$/;" t typeref:struct:s_power_nmos_leakage_pair -t_power_nmos_leakages ./power/power.h /^typedef struct s_power_nmos_leakages t_power_nmos_leakages;$/;" t typeref:struct:s_power_nmos_leakages -t_power_nmos_mux_inf ./power/power.h /^typedef struct s_power_nmos_mux_inf t_power_nmos_mux_inf;$/;" t typeref:struct:s_power_nmos_mux_inf -t_power_opts ./base/vpr_types.h /^typedef struct s_power_opts t_power_opts;$/;" t typeref:struct:s_power_opts -t_power_output ./power/power.h /^typedef struct s_power_output t_power_output;$/;" t typeref:struct:s_power_output -t_power_tech ./power/power.h /^typedef struct s_power_tech t_power_tech;$/;" t typeref:struct:s_power_tech -t_prepacked_tnode_data ./base/vpr_types.h /^} t_prepacked_tnode_data;$/;" t typeref:struct:s_prepacked_tnode_data -t_rc_node ./timing/net_delay_types.h /^typedef struct s_rc_node t_rc_node;$/;" t typeref:struct:s_rc_node -t_report ./base/graphics.h /^} t_report;$/;" t typeref:struct:__anon6 -t_router_opts ./base/vpr_types.h /^typedef struct s_router_opts t_router_opts;$/;" t typeref:struct:s_router_opts -t_rr_graph ./fpga_x2p/base/fpga_x2p_types.h /^typedef struct fpga_spice_rr_graph t_rr_graph;$/;" t typeref:struct:fpga_spice_rr_graph -t_rr_indexed_data ./base/vpr_types.h /^} t_rr_indexed_data;$/;" t typeref:struct:s_rr_indexed_data -t_rr_node ./base/vpr_types.h /^typedef struct s_rr_node t_rr_node;$/;" t typeref:struct:s_rr_node -t_rr_node_power ./power/power.h /^typedef struct s_rr_node_power t_rr_node_power;$/;" t typeref:struct:s_rr_node_power -t_rr_node_route_inf ./route/route_common.h /^} t_rr_node_route_inf;$/;" t typeref:struct:__anon15 -t_rr_type ./base/vpr_types.h /^} t_rr_type;$/;" t typeref:enum:e_rr_type -t_rt_node ./route/route_tree_timing.h /^typedef struct s_rt_node t_rt_node;$/;" t typeref:struct:s_rt_node -t_sb ./base/vpr_types.h /^typedef struct s_sb t_sb;$/;" t typeref:struct:s_sb -t_sdc_clock ./timing/read_sdc.c /^} t_sdc_clock;$/;" t typeref:struct:s_sdc_clock file: -t_sdc_exclusive_group ./timing/read_sdc.c /^} t_sdc_exclusive_group;$/;" t typeref:struct:s_sdc_exclusive_group file: -t_sdc_opts ./fpga_x2p/verilog/verilog_sdc.c /^typedef struct s_sdc_opts t_sdc_opts;$/;" t typeref:struct:s_sdc_opts file: -t_seg_details ./base/vpr_types.h /^} t_seg_details;$/;" t typeref:struct:s_seg_details -t_shell_cmd ./fpga_x2p/shell/shell_types.h /^typedef struct s_shell_cmd t_shell_cmd;$/;" t typeref:struct:s_shell_cmd -t_shell_env ./fpga_x2p/shell/shell_types.h /^typedef struct s_shell_env t_shell_env;$/;" t typeref:struct:s_shell_env -t_slack ./base/vpr_types.h /^} t_slack;$/;" t typeref:struct:s_slack -t_solution_inf ./power/power.h /^typedef struct s_solution_inf t_solution_inf;$/;" t typeref:struct:s_solution_inf -t_spice_opts ./base/vpr_types.h /^typedef struct s_spice_opts t_spice_opts;$/;" t typeref:struct:s_spice_opts -t_syn_verilog_opts ./base/vpr_types.h /^typedef struct s_syn_verilog_opts t_syn_verilog_opts;$/;" t typeref:struct:s_syn_verilog_opts -t_tedge ./base/vpr_types.h /^} t_tedge;$/;" t typeref:struct:s_tedge -t_timing_constraints ./base/vpr_types.h /^} t_timing_constraints;$/;" t typeref:struct:s_timing_constraints -t_timing_stats ./base/vpr_types.h /^} t_timing_stats;$/;" t typeref:struct:s_timing_stats -t_tnode ./base/vpr_types.h /^} t_tnode;$/;" t typeref:struct:s_tnode -t_token ./util/token.h /^typedef struct s_token t_token;$/;" t typeref:struct:s_token -t_trace ./base/vpr_types.h /^} t_trace;$/;" t typeref:struct:s_trace -t_transistor_inf ./power/power.h /^typedef struct s_transistor_inf t_transistor_inf;$/;" t typeref:struct:s_transistor_inf -t_transistor_size_inf ./power/power.h /^typedef struct s_transistor_size_inf t_transistor_size_inf;$/;" t typeref:struct:s_transistor_size_inf -t_trpt_opts ./fpga_x2p/verilog/verilog_report_timing.c /^typedef struct s_trpt_opts t_trpt_opts;$/;" t typeref:struct:s_trpt_opts file: -t_vpr_setup ./base/vpr_types.h /^} t_vpr_setup;$/;" t typeref:struct:s_vpr_setup -t_wireL_cnt ./fpga_x2p/verilog/verilog_report_timing.c /^typedef struct s_wireL_cnt t_wireL_cnt;$/;" t typeref:struct:s_wireL_cnt file: -tag ./fpga_x2p/shell/read_opt_types.h /^ char* tag; \/* tag of option *\/$/;" m struct:s_opt_info -target_flag ./route/route_common.h /^ short target_flag;$/;" m struct:__anon15 -tb_head ./fpga_x2p/spice/spice_globals.c /^t_llist* tb_head = NULL;$/;" v -tb_num_grid ./fpga_x2p/spice/spice_grid_testbench.c /^static int tb_num_grid = 0;$/;" v file: -tb_num_primitive ./fpga_x2p/spice/spice_primitive_testbench.c /^static int tb_num_primitive = 0;$/;" v file: -td_place_exp_first ./base/vpr_types.h /^ float td_place_exp_first;$/;" m struct:s_placer_opts -td_place_exp_last ./base/vpr_types.h /^ float td_place_exp_last;$/;" m struct:s_placer_opts -tech_size ./power/power.h /^ float tech_size; \/* Tech size in nm, for example 90e-9 for 90nm *\/$/;" m struct:s_power_tech -tedge_ch ./timing/path_delay.c /^static t_chunk tedge_ch = {NULL, 0, NULL};$/;" v file: -temp_net_cost ./place/place.c /^static float *net_cost = NULL, *temp_net_cost = NULL; \/* [0..num_nets-1] *\/$/;" v file: -temp_num_pins ./base/read_blif.c /^static int *num_driver, *temp_num_pins;$/;" v file: -temp_point_to_point_delay_cost ./place/place.c /^static float **temp_point_to_point_delay_cost = NULL;$/;" v file: -temp_point_to_point_timing_cost ./place/place.c /^static float **temp_point_to_point_timing_cost = NULL;$/;" v file: -temp_used ./base/vpr_types.h /^ int temp_used;$/;" m struct:s_logical_block -temperature ./power/power.h /^ float temperature; \/* Temp in C *\/$/;" m struct:s_power_tech -test_if_exposed ./base/graphics.c /^static Bool test_if_exposed (Display *disp, XEvent *event_ptr, XPointer dummy) $/;" f file: -testbench_cb_mux_cnt ./fpga_x2p/spice/spice_mux_testbench.c /^static int testbench_cb_mux_cnt = 0;$/;" v file: -testbench_load_cnt ./fpga_x2p/spice/spice_grid_testbench.c /^static int testbench_load_cnt = 0;$/;" v file: -testbench_load_cnt ./fpga_x2p/spice/spice_mux_testbench.c /^static int testbench_load_cnt = 0;$/;" v file: -testbench_load_cnt ./fpga_x2p/spice/spice_primitive_testbench.c /^static int testbench_load_cnt = 0;$/;" v file: -testbench_load_cnt ./fpga_x2p/spice/spice_routing_testbench.c /^static int testbench_load_cnt = 0;$/;" v file: -testbench_mux_cnt ./fpga_x2p/spice/spice_mux_testbench.c /^static int testbench_mux_cnt = 0;$/;" v file: -testbench_muxes_head ./fpga_x2p/spice/spice_mux_testbench.c /^static t_llist* testbench_muxes_head = NULL; $/;" v file: -testbench_pb_mux_cnt ./fpga_x2p/spice/spice_mux_testbench.c /^static int testbench_pb_mux_cnt = 0;$/;" v file: -testbench_sb_mux_cnt ./fpga_x2p/spice/spice_mux_testbench.c /^static int testbench_sb_mux_cnt = 0;$/;" v file: -testbench_sram_cnt ./fpga_x2p/spice/spice_mux_testbench.c /^static int testbench_sram_cnt = 0;$/;" v file: -text ./base/graphics.c /^ char text[BUTTON_TEXT_LEN]; $/;" m struct:__anon4 file: -textarea ./base/graphics.c /^static Window toplevel, menu, textarea; \/* various windows *\/$/;" v file: -tie_break_high_fanout_net ./base/vpr_types.h /^ int tie_break_high_fanout_net; \/* If no marked candidate atoms, use this high fanout net to determine the next candidate atom *\/$/;" m struct:s_pb_stats -tile_length ./power/power.h /^ float tile_length;$/;" m struct:s_power_commonly_used -tile_width ./base/draw.c /^static float tile_width, pin_size;$/;" v file: -tile_x ./base/draw.c /^static float *tile_x, *tile_y;$/;" v file: -tile_y ./base/draw.c /^static float *tile_x, *tile_y;$/;" v file: -timing_criticality ./base/vpr_types.h /^ float ** timing_criticality;$/;" m struct:s_slack -timing_driven ./base/ReadOptions.h /^ boolean timing_driven;$/;" m struct:s_options -timing_driven ./base/vpr_types.h /^ boolean timing_driven;$/;" m struct:s_packer_opts -timing_driven_check_net_delays ./route/route_timing.c /^static void timing_driven_check_net_delays(float **net_delay) {$/;" f file: -timing_driven_expand_neighbours ./route/route_timing.c /^static void timing_driven_expand_neighbours(struct s_heap *current, int inet,$/;" f file: -timing_driven_route_net ./route/route_timing.c /^boolean timing_driven_route_net(int inet, float pres_fac, float max_criticality,$/;" f -timing_nets ./timing/path_delay.c /^static struct s_net *timing_nets = NULL;$/;" v typeref:struct:s_net file: -timing_place_crit ./place/timing_place.c /^float **timing_place_crit; \/*available externally *\/$/;" v -timing_place_crit_ch ./place/timing_place.c /^static t_chunk timing_place_crit_ch = {NULL, 0, NULL};$/;" v file: -timing_tradeoff ./base/vpr_types.h /^ float timing_tradeoff;$/;" m struct:s_placer_opts -timinggain ./base/vpr_types.h /^ std::map timinggain; \/* [0..num_logical_blocks-1]. The timing criticality score of this logical_block. $/;" m struct:s_pb_stats -tnode ./base/vpr_types.h /^ t_tnode *tnode;$/;" m struct:s_rr_node -tnode ./timing/path_delay.c /^t_tnode *tnode = NULL; \/* [0..num_tnodes - 1] *\/$/;" v -tnodes_at_level ./timing/path_delay2.c /^struct s_ivec *tnodes_at_level;$/;" v typeref:struct:s_ivec -to_clb_pin_end_index ./base/vpr_types.h /^ int to_clb_pin_end_index;$/;" m struct:s_clb_to_clb_directs -to_clb_pin_start_index ./base/vpr_types.h /^ int to_clb_pin_start_index;$/;" m struct:s_clb_to_clb_directs -to_clb_type ./base/vpr_types.h /^ t_type_descriptor *to_clb_type;$/;" m struct:s_clb_to_clb_directs -to_node ./base/vpr_types.h /^ int to_node; \/* index of node at the sink end of this edge *\/$/;" m struct:s_tedge -toggle_congestion ./base/draw.c /^static void toggle_congestion(void (*drawscreen_ptr)(void)) {$/;" f file: -toggle_defects ./base/draw.c /^static void toggle_defects(void (*drawscreen_ptr)(void)) {$/;" f file: -toggle_nets ./base/draw.c /^static void toggle_nets(void (*drawscreen_ptr)(void)) {$/;" f file: -toggle_rr ./base/draw.c /^static void toggle_rr(void (*drawscreen_ptr)(void)) {$/;" f file: -top_height ./base/graphics.c /^static int top_width, top_height; \/* window size *\/$/;" v file: -top_height ./base/graphics.h /^ int top_width, top_height;$/;" m struct:__anon6 -top_netlist_addr_bl_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_addr_bl_port_name = "addr_bl";$/;" v -top_netlist_addr_wl_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_addr_wl_port_name = "addr_wl";$/;" v -top_netlist_array_bl_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_array_bl_port_name = "bl_bus";$/;" v -top_netlist_array_blb_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_array_blb_port_name = "blb_bus";$/;" v -top_netlist_array_wl_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_array_wl_port_name = "wl_bus";$/;" v -top_netlist_array_wlb_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_array_wlb_port_name = "wlb_bus";$/;" v -top_netlist_bl_data_in_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_bl_data_in_port_name = "data_in";$/;" v -top_netlist_bl_enable_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_bl_enable_port_name = "en_bl";$/;" v -top_netlist_normal_bl_port_postfix ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_normal_bl_port_postfix = "_bl";$/;" v -top_netlist_normal_blb_port_postfix ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_normal_blb_port_postfix = "_blb";$/;" v -top_netlist_normal_wl_port_postfix ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_normal_wl_port_postfix = "_wl";$/;" v -top_netlist_normal_wlb_port_postfix ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_normal_wlb_port_postfix = "_wlb";$/;" v -top_netlist_reserved_bl_port_postfix ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_reserved_bl_port_postfix = "_reserved_bl";$/;" v -top_netlist_reserved_wl_port_postfix ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_reserved_wl_port_postfix = "_reserved_wl";$/;" v -top_netlist_scan_chain_head_prefix ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_scan_chain_head_prefix = "sc_in";$/;" v -top_netlist_wl_enable_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_netlist_wl_enable_port_name = "en_wl";$/;" v -top_tb_clock_reg_postfix ./fpga_x2p/verilog/verilog_global.c /^char* top_tb_clock_reg_postfix = "_reg";$/;" v -top_tb_config_done_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_tb_config_done_port_name = "config_done";$/;" v -top_tb_inout_reg_postfix ./fpga_x2p/verilog/verilog_global.c /^char* top_tb_inout_reg_postfix = "_reg";$/;" v -top_tb_op_clock_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_tb_op_clock_port_name = "op_clock";$/;" v -top_tb_prog_clock_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_tb_prog_clock_port_name = "prog_clock";$/;" v -top_tb_prog_reset_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_tb_prog_reset_port_name = "prog_reset";$/;" v -top_tb_prog_set_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_tb_prog_set_port_name = "prog_set";$/;" v -top_tb_reset_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_tb_reset_port_name = "greset";$/;" v -top_tb_set_port_name ./fpga_x2p/verilog/verilog_global.c /^char* top_tb_set_port_name = "gset";$/;" v -top_testbench_verilog_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* top_testbench_verilog_file_postfix = "_top_tb.v"; \/* !!! must be consist with the modelsim_testbench_module_postfix *\/ $/;" v -top_width ./base/graphics.c /^static int top_width, top_height; \/* window size *\/$/;" v file: -top_width ./base/graphics.h /^ int top_width, top_height;$/;" m struct:__anon6 -toplevel ./base/graphics.c /^static Window toplevel, menu, textarea; \/* various windows *\/$/;" v file: -total_cb_buffer_size ./power/power.h /^ float total_cb_buffer_size;$/;" m struct:s_power_commonly_used -total_cb_mux_input_density ./fpga_x2p/spice/spice_mux_testbench.c /^static float total_cb_mux_input_density = 0.;$/;" v file: -total_pb_mux_input_density ./fpga_x2p/spice/spice_mux_testbench.c /^static float total_pb_mux_input_density = 0.;$/;" v file: -total_sb_buffer_size ./power/power.h /^ float total_sb_buffer_size;$/;" m struct:s_power_commonly_used -total_sb_mux_input_density ./fpga_x2p/spice/spice_mux_testbench.c /^static float total_sb_mux_input_density = 0.;$/;" v file: -trace_ch ./fpga_x2p/base/fpga_x2p_types.h /^ t_chunk trace_ch;$/;" m struct:fpga_spice_rr_graph -trace_ch ./route/route_common.c /^static t_chunk trace_ch = {NULL, 0, NULL};$/;" v file: -trace_free_head ./fpga_x2p/base/fpga_x2p_types.h /^ t_trace *trace_free_head;$/;" m struct:fpga_spice_rr_graph -trace_free_head ./route/route_common.c /^static struct s_trace *trace_free_head = NULL;$/;" v typeref:struct:s_trace file: -trace_head ./base/globals.c /^struct s_trace **trace_head = NULL; \/* [0..(num_nets-1)] *\/$/;" v typeref:struct:s_trace -trace_head ./base/globals_declare.h /^struct s_trace **trace_head, **trace_tail;$/;" v typeref:struct:s_trace -trace_head ./fpga_x2p/base/fpga_x2p_types.h /^ t_trace **trace_head; \/* [0..(num_nets-1)] *\/$/;" m struct:fpga_spice_rr_graph -trace_tail ./base/globals.c /^struct s_trace **trace_tail = NULL; \/* [0..(num_nets-1)] *\/$/;" v typeref:struct:s_trace -trace_tail ./base/globals_declare.h /^struct s_trace **trace_head, **trace_tail;$/;" v typeref:struct: -trace_tail ./fpga_x2p/base/fpga_x2p_types.h /^ t_trace **trace_tail; \/* [0..(num_nets-1)] *\/$/;" m struct:fpga_spice_rr_graph -trans_per_R ./route/rr_graph_area.c /^static float trans_per_R(float Rtrans, float R_minW_trans) {$/;" f file: -trans_per_buf ./route/rr_graph_area.c /^float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos) {$/;" f -trans_per_mux ./route/rr_graph_area.c /^static float trans_per_mux(int num_inputs, float trans_sram_bit,$/;" f file: -transistor_size ./power/PowerSpicedComponent.h /^ float transistor_size;$/;" m class:PowerCallibSize -transistor_size ./power/power.h /^ float transistor_size;$/;" m struct:s_mux_arch -transistor_type_name ./power/power_util.c /^char * transistor_type_name(e_tx_type type) {$/;" f -translate_down ./base/graphics.c /^translate_down (void (*drawscreen) (void)) $/;" f file: -translate_left ./base/graphics.c /^translate_left (void (*drawscreen) (void)) $/;" f file: -translate_right ./base/graphics.c /^translate_right (void (*drawscreen) (void)) $/;" f file: -translate_up ./base/graphics.c /^translate_up (void (*drawscreen) (void)) $/;" f file: -traverse_clb ./base/verilog_writer.c /^pb_list *traverse_clb(t_pb *pb , pb_list *prim_list)$/;" f -traverse_linked_list ./base/verilog_writer.c /^void traverse_linked_list(pb_list *list)$/;" f -traverse_linked_list_conn ./base/verilog_writer.c /^void traverse_linked_list_conn(conn_list *list)$/;" f -tree_mux_last_level_input_num ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int tree_mux_last_level_input_num(int num_level,$/;" f -tried ./base/vpr_types.h /^ t_cluster_placement_primitive *tried; \/* ptrs to primitives that are open but current logic block unable to pack to *\/$/;" m struct:s_cluster_placement_stats -trigger_type ./base/vpr_types.h /^ char* trigger_type;$/;" m struct:s_logical_block -trpt_routing_file_name ./fpga_x2p/verilog/verilog_global.c /^char* trpt_routing_file_name = "report_timing_routing.tcl";$/;" v -trpt_sb_file_name ./fpga_x2p/verilog/verilog_global.c /^char* trpt_sb_file_name = "report_timing_sb.tcl";$/;" v -truth_table ./base/vpr_types.h /^ struct s_linked_vptr *truth_table; \/* If this is a LUT (.names), then this is the logic that the LUT implements *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_linked_vptr -try_access_dir ./fpga_x2p/base/fpga_x2p_utils.c /^enum e_dir_err try_access_dir(char* dir_path) {$/;" f -try_access_file ./fpga_x2p/base/fpga_x2p_utils.c /^int try_access_file(char* file_path) {$/;" f -try_breadth_first_route ./route/route_breadth_first.c /^boolean try_breadth_first_route(struct s_router_opts router_opts,$/;" f -try_breadth_first_route_cluster ./pack/cluster_legality.c /^boolean try_breadth_first_route_cluster(void) {$/;" f -try_breadth_first_route_pb_rr_graph ./fpga_x2p/router/fpga_x2p_router.c /^boolean try_breadth_first_route_pb_rr_graph(t_rr_graph* local_rr_graph) {$/;" f -try_buffer_for_net ./mrfpga/buffer_insertion.c /^void try_buffer_for_net( int inet, t_rc_node** rc_node_free_list, t_linked_rc_edge** rc_edge_free_list, t_linked_rc_ptr* rr_node_to_rc_node, float* net_delay ) {$/;" f -try_buffer_for_routing ./mrfpga/buffer_insertion.c /^void try_buffer_for_routing ( float** net_delay ) {$/;" f -try_buffer_rc_tree ./mrfpga/buffer_insertion.c /^static t_buffer_plan_list try_buffer_rc_tree (t_rc_node *rc_node, int num_pins, int* isink_to_inode) {$/;" f file: -try_clb_pin_remap_after_placement ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^void try_clb_pin_remap_after_placement(t_det_routing_arch det_routing_arch,$/;" f -try_create_molecule ./pack/prepack.c /^static t_pack_molecule *try_create_molecule($/;" f file: -try_expand_molecule ./pack/prepack.c /^static boolean try_expand_molecule(INOUTP t_pack_molecule *molecule,$/;" f file: -try_pack ./pack/pack.c /^void try_pack(INP struct s_packer_opts *packer_opts, INP const t_arch * arch,$/;" f -try_pack_molecule ./pack/cluster.c /^static enum e_block_pack_status try_pack_molecule($/;" f file: -try_place ./place/place.c /^void try_place(struct s_placer_opts placer_opts,$/;" f -try_place_logical_block_rec ./pack/cluster.c /^static enum e_block_pack_status try_place_logical_block_rec($/;" f file: -try_place_macro ./place/place.c /^static int try_place_macro(int itype, int ichoice, int imacro, int * free_locations){$/;" f file: -try_place_molecule ./pack/cluster_placement.c /^static float try_place_molecule(INP t_pack_molecule *molecule,$/;" f file: -try_remap_blk_class_one_conflict_pin ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^int try_remap_blk_class_one_conflict_pin(t_block* target_blk, int class_index, int pin_index,$/;" f -try_route ./route/route_common.c /^boolean try_route(int width_fac, struct s_router_opts router_opts,$/;" f -try_sat_one_blk_pin_class_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^int try_sat_one_blk_pin_class_prefer_side(t_block* target_blk,$/;" f -try_swap ./place/place.c /^static enum swap_result try_swap(float t, float *cost, float *bb_cost, float *timing_cost,$/;" f file: -try_timing_driven_route ./route/route_timing.c /^boolean try_timing_driven_route(struct s_router_opts router_opts,$/;" f -try_update_lookahead_pins_used ./pack/cluster.c /^static void try_update_lookahead_pins_used(t_pb *cur_pb) {$/;" f file: -try_update_sram_orgz_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void try_update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -ts_bb_coord_new ./place/place.c /^static struct s_bb *ts_bb_coord_new = NULL;$/;" v typeref:struct:s_bb file: -ts_bb_edge_new ./place/place.c /^static struct s_bb *ts_bb_edge_new = NULL;$/;" v typeref:struct:s_bb file: -ts_nets_to_update ./place/place.c /^static int *ts_nets_to_update = NULL;$/;" v file: -turn_on_off ./base/graphics.c /^static void turn_on_off (int pressed) {$/;" f file: -twisted ./base/vpr_types.h /^ boolean twisted;$/;" m struct:s_seg_details -type ./base/graphics.c /^ t_button_type type;$/;" m struct:__anon4 file: -type ./base/vpr_types.h /^ e_tnode_type type; \/* see the above enum *\/$/;" m struct:s_tnode -type ./base/vpr_types.h /^ enum e_pack_pattern_molecule_type type; \/* what kind of molecule is this? *\/$/;" m struct:s_pack_molecule typeref:enum:s_pack_molecule::e_pack_pattern_molecule_type -type ./base/vpr_types.h /^ enum logical_block_types type; \/* I\/O, combinational logic, or latch *\/$/;" m struct:s_logical_block typeref:enum:s_logical_block::logical_block_types -type ./base/vpr_types.h /^ enum sched_type type;$/;" m struct:s_annealing_sched typeref:enum:s_annealing_sched::sched_type -type ./base/vpr_types.h /^ t_rr_type type;$/;" m struct:s_rr_node -type ./base/vpr_types.h /^ t_type_ptr type;$/;" m struct:s_block -type ./base/vpr_types.h /^ t_type_ptr type;$/;" m struct:s_grid_tile -type ./base/vpr_types.h /^ t_rr_type type;$/;" m struct:s_cb -type ./util/token.h /^ enum e_token_type type;$/;" m struct:s_token typeref:enum:s_token::e_token_type -type_ ./fpga_x2p/base/rr_chan.h /^ t_rr_type type_; \/* channel type: CHANX or CHANY *\/$/;" m class:RRChan -type_descriptors ./base/globals.c /^struct s_type_descriptor *type_descriptors = NULL;$/;" v typeref:struct:s_type_descriptor -type_descriptors_backup ./place/timing_place_lookup.c /^static t_type_descriptor *type_descriptors_backup;$/;" v file: -u ./route/route_common.h /^ } u;$/;" m struct:s_heap typeref:union:s_heap::__anon14 -u ./route/route_tree_timing.h /^ } u;$/;" m struct:s_rt_node typeref:union:s_rt_node::__anon16 -u ./timing/net_delay_types.h /^ } u;$/;" m struct:s_rc_node typeref:union:s_rc_node::__anon18 -unbuf_switched ./base/vpr_types.h /^ int unbuf_switched; \/* Xifan TANG: Switch Segment Pattern Support*\/$/;" m struct:s_rr_node -unclustered_list_head ./pack/cluster.c /^static struct s_molecule_link *unclustered_list_head;$/;" v typeref:struct:s_molecule_link file: -unclustered_list_head_size ./pack/cluster.c /^int unclustered_list_head_size;$/;" v -unmap_button ./base/graphics.c /^static void unmap_button (int bnum) $/;" f file: -unmark_fanout_intermediate_nodes ./pack/cluster_feasibility_filter.c /^static void unmark_fanout_intermediate_nodes($/;" f file: -upbound_sim_num_clock_cycles ./fpga_x2p/spice/spice_grid_testbench.c /^static int upbound_sim_num_clock_cycles = 2;$/;" v file: -upbound_sim_num_clock_cycles ./fpga_x2p/spice/spice_mux_testbench.c /^static int upbound_sim_num_clock_cycles = 2;$/;" v file: -upbound_sim_num_clock_cycles ./fpga_x2p/spice/spice_primitive_testbench.c /^static int upbound_sim_num_clock_cycles = 2;$/;" v file: -upbound_sim_num_clock_cycles ./fpga_x2p/spice/spice_routing_testbench.c /^static int upbound_sim_num_clock_cycles = 2;$/;" v file: -updateRect ./base/graphics.c /^static RECT adjustRect, updateRect;$/;" v file: -update_bb ./place/place.c /^static void update_bb(int inet, struct s_bb *bb_coord_new,$/;" f file: -update_cluster_stats ./pack/cluster.c /^static void update_cluster_stats( INP t_pack_molecule *molecule,$/;" f file: -update_connection_gain_values ./pack/cluster.c /^static void update_connection_gain_values(int inet, int clustered_block,$/;" f file: -update_grid_pb_pins_parasitic_nets ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_grid_pb_pins_parasitic_nets() {$/;" f -update_grid_pbs_post_route_rr_graph ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_grid_pbs_post_route_rr_graph() {$/;" f -update_mem_bank_info_num_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void update_mem_bank_info_num_blwl(t_mem_bank_info* cur_mem_bank_info,$/;" f -update_mem_bank_info_num_mem_bit ./fpga_x2p/base/fpga_x2p_utils.c /^void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info,$/;" f -update_mem_bank_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void update_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info,$/;" f -update_message ./base/graphics.c /^update_message (const char *msg) $/;" f -update_message ./base/graphics.c /^void update_message (const char *msg) { }$/;" f -update_mirror_connection_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void update_mirror_connection_blocks() {$/;" f -update_mirror_switch_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void update_mirror_switch_blocks() {$/;" f -update_net_delays_from_route_tree ./route/route_tree_timing.c /^void update_net_delays_from_route_tree(float *net_delay,$/;" f -update_normalized_costs ./timing/path_delay.c /^static void update_normalized_costs(float criticality_denom, long max_critical_input_paths,$/;" f file: -update_one_connection_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void update_one_connection_block_mirror(t_cb* cur_cb) {$/;" f -update_one_grid_pack_net_num ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_grid_pack_net_num(int x, int y) {$/;" f -update_one_grid_pb_pins_parasitic_nets ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_grid_pb_pins_parasitic_nets(int ix, int iy) {$/;" f -update_one_io_grid_pack_net_num ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_io_grid_pack_net_num(int x, int y) {$/;" f -update_one_spice_model_grid_index_high ./fpga_x2p/base/fpga_x2p_utils.c /^void update_one_spice_model_grid_index_high(int x, int y, $/;" f -update_one_spice_model_grid_index_low ./fpga_x2p/base/fpga_x2p_utils.c /^void update_one_spice_model_grid_index_low(int x, int y, $/;" f -update_one_spice_model_routing_index_high ./fpga_x2p/base/fpga_x2p_utils.c /^void update_one_spice_model_routing_index_high(int x, int y, t_rr_type chan_type,$/;" f -update_one_spice_model_routing_index_low ./fpga_x2p/base/fpga_x2p_utils.c /^void update_one_spice_model_routing_index_low(int x, int y, t_rr_type chan_type,$/;" f -update_one_switch_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^void update_one_switch_block_mirror(t_sb* cur_sb) {$/;" f -update_one_unused_grid_output_pins_parasitic_nets ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_unused_grid_output_pins_parasitic_nets(int ix, int iy) {$/;" f -update_one_used_grid_pb_pins_parasitic_nets ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void update_one_used_grid_pb_pins_parasitic_nets(t_phy_pb* cur_pb,$/;" f -update_pb_graph_node_temp_net_num_to_pb ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void update_pb_graph_node_temp_net_num_to_pb(t_pb_graph_node* cur_pb_graph_node,$/;" f -update_pb_vpack_net_num_from_temp_net_num ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void update_pb_vpack_net_num_from_temp_net_num(t_phy_pb* cur_pb, $/;" f -update_primitive_cost_or_status ./pack/cluster_placement.c /^static void update_primitive_cost_or_status(INP t_pb_graph_node *pb_graph_node,$/;" f file: -update_ps_transform ./base/graphics.c /^update_ps_transform (void) $/;" f file: -update_rlim ./place/place.c /^static void update_rlim(float *rlim, float success_rat) {$/;" f file: -update_route_tree ./route/route_tree_timing.c /^update_route_tree(struct s_heap * hptr) {$/;" f -update_rr_base_costs ./route/route_timing.c /^static void update_rr_base_costs(int inet, float largest_criticality) {$/;" f file: -update_rr_graph_traceback ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^t_trace* update_rr_graph_traceback(t_rr_graph* local_rr_graph,$/;" f -update_rr_nodes_driver_switch ./route/rr_graph_swseg.c /^void update_rr_nodes_driver_switch(enum e_directionality directionality) {$/;" f -update_scff_info_num_mem_bit ./fpga_x2p/base/fpga_x2p_utils.c /^void update_scff_info_num_mem_bit(t_scff_info* cur_scff_info,$/;" f -update_screen ./base/draw.c /^void update_screen(int priority, char *msg, enum pic_type pic_on_screen_val,$/;" f -update_slacks ./timing/path_delay.c /^static void update_slacks(t_slack * slacks, int source_clock_domain, int sink_clock_domain, float criticality_denom,$/;" f file: -update_spice_models_grid_index_high ./fpga_x2p/base/fpga_x2p_utils.c /^void update_spice_models_grid_index_high(int x, int y, $/;" f -update_spice_models_grid_index_low ./fpga_x2p/base/fpga_x2p_utils.c /^void update_spice_models_grid_index_low(int x, int y, $/;" f -update_spice_models_routing_index_high ./fpga_x2p/base/fpga_x2p_utils.c /^void update_spice_models_routing_index_high(int x, int y, t_rr_type chan_type,$/;" f -update_spice_models_routing_index_low ./fpga_x2p/base/fpga_x2p_utils.c /^void update_spice_models_routing_index_low(int x, int y, t_rr_type chan_type, $/;" f -update_sram_orgz_info_mem_model ./fpga_x2p/base/fpga_x2p_utils.c /^void update_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -update_sram_orgz_info_num_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void update_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -update_sram_orgz_info_num_mem_bit ./fpga_x2p/base/fpga_x2p_utils.c /^void update_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -update_sram_orgz_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -update_standalone_sram_info_num_mem_bit ./fpga_x2p/base/fpga_x2p_utils.c /^void update_standalone_sram_info_num_mem_bit(t_standalone_sram_info* cur_standalone_sram_info,$/;" f -update_t ./place/place.c /^static void update_t(float *t, float std_dev, float rlim, float success_rat,$/;" f file: -update_td_cost ./place/place.c /^static void update_td_cost(void) {$/;" f file: -update_timing_gain_values ./pack/cluster.c /^static void update_timing_gain_values(int inet, int clustered_block,$/;" f file: -update_total_gain ./pack/cluster.c /^static void update_total_gain(float alpha, float beta, boolean timing_driven,$/;" f file: -update_traceback ./route/route_common.c /^update_traceback(struct s_heap *hptr, int inet) {$/;" f -update_transform ./base/graphics.c /^update_transform (void) $/;" f file: -update_unbuffered_ancestors_C_downstream ./route/route_tree_timing.c /^update_unbuffered_ancestors_C_downstream(t_rt_node * start_of_new_path_rt_node) {$/;" f file: -update_win ./base/graphics.c /^update_win (int x[2], int y[2], void (*drawscreen)(void)) $/;" f file: -update_wire_L_counter_in_llist ./fpga_x2p/verilog/verilog_report_timing.c /^void update_wire_L_counter_in_llist(t_llist* rr_path_cnt, $/;" f -usage ./base/vpr_types.h /^ int usage;$/;" m struct:s_grid_tile -use_default_timing_constraints ./timing/read_sdc.c /^static void use_default_timing_constraints(void) {$/;" f file: -used_input_pins ./base/vpr_types.h /^ int used_input_pins; \/* Number of used input pins *\/$/;" m struct:s_logical_block -user_defined_template_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* user_defined_template_verilog_file_name = "user_defined_templates.v";$/;" v -user_models ./base/vpr_types.h /^ t_model * user_models; \/* blif models defined by the user *\/$/;" m struct:s_vpr_setup -v_ds ./power/power.h /^ float v_ds;$/;" m struct:s_power_nmos_leakage_pair -v_in ./power/power.h /^ float v_in;$/;" m struct:s_power_mux_volt_pair -v_out_max ./power/power.h /^ float v_out_max;$/;" m struct:s_power_mux_volt_pair -v_out_min ./power/power.h /^ float v_out_min;$/;" m struct:s_power_mux_volt_pair -val ./fpga_x2p/shell/read_opt_types.h /^ char* val; \/*The value*\/$/;" m struct:s_opt_info -val_type ./fpga_x2p/shell/read_opt_types.h /^ enum opt_val_type val_type; $/;" m struct:s_opt_info typeref:enum:s_opt_info::opt_val_type -valid ./base/vpr_types.h /^ boolean valid; \/* Whether or not this molecule is still valid *\/$/;" m struct:s_pack_molecule -valid_chan_type ./fpga_x2p/base/rr_chan.cpp /^bool DeviceRRChan::valid_chan_type(t_rr_type chan_type) const {$/;" f class:DeviceRRChan -valid_coordinator ./fpga_x2p/base/rr_chan.cpp /^bool DeviceRRChan::valid_coordinator(t_rr_type chan_type, size_t x, size_t y) const {$/;" f class:DeviceRRChan -valid_module_id ./fpga_x2p/base/rr_chan.cpp /^bool DeviceRRChan::valid_module_id(t_rr_type chan_type, size_t module_id) const {$/;" f class:DeviceRRChan -valid_node_id ./fpga_x2p/base/rr_chan.cpp /^bool RRChan::valid_node_id(size_t node_id) const {$/;" f class:RRChan -valid_primitives ./base/vpr_types.h /^ t_cluster_placement_primitive **valid_primitives; \/* [0..num_pb_types-1] ptrs to linked list of valid primitives, for convenience, each linked list head is empty *\/$/;" m struct:s_cluster_placement_stats -valid_type ./fpga_x2p/base/rr_chan.cpp /^bool RRChan::valid_type(t_rr_type type) const {$/;" f class:RRChan -validate_mirror_connection_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_mirror_connection_blocks() {$/;" f -validate_mirror_switch_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_mirror_switch_blocks() {$/;" f -validate_one_connection_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_one_connection_block_mirror(t_cb* cur_cb) {$/;" f -validate_one_switch_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_one_switch_block_mirror(t_sb* cur_sb) {$/;" f -value ./mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" m struct:s_buffer_plan_node file: -verify_binary_search ./base/vpr_types.h /^ boolean verify_binary_search;$/;" m struct:s_router_opts -verilog_compact_generate_fake_xy_for_io_border_side ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void verilog_compact_generate_fake_xy_for_io_border_side(int border_side, $/;" f -verilog_config_peripheral_prefix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_config_peripheral_prefix = "config_peripheral";$/;" v -verilog_convert_port_type_to_string ./fpga_x2p/verilog/verilog_utils.c /^char* verilog_convert_port_type_to_string(enum e_spice_model_port_type port_type) {$/;" f -verilog_create_one_subckt_file ./fpga_x2p/verilog/verilog_utils.c /^FILE* verilog_create_one_subckt_file(char* subckt_dir,$/;" f -verilog_default_signal_init_value ./fpga_x2p/verilog/verilog_global.c /^int verilog_default_signal_init_value = 0;$/;" v -verilog_determine_src_chan_coordinate_switch_box ./fpga_x2p/verilog/verilog_routing.c /^void verilog_determine_src_chan_coordinate_switch_box(t_rr_node* src_rr_node,$/;" f -verilog_find_interc_fan_in_des_pb_graph_pin ./fpga_x2p/verilog/verilog_pbtypes.c /^void verilog_find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin,$/;" f -verilog_find_pb_graph_pin_in_edges_interc_type ./fpga_x2p/verilog/verilog_pbtypes.c /^enum e_interconnect verilog_find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) {$/;" f -verilog_formal_verification_preproc_flag ./fpga_x2p/verilog/verilog_global.c /^char* verilog_formal_verification_preproc_flag = "ENABLE_FORMAL_VERIFICATION"; \/\/ the flag to enable formal verification during compilation$/;" v -verilog_generate_one_report_timing_sb_to_cb ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_one_report_timing_sb_to_cb(FILE* fp,$/;" f -verilog_generate_one_report_timing_sb_to_sb ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_one_report_timing_sb_to_sb(FILE* fp,$/;" f -verilog_generate_one_report_timing_within_sb ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_one_report_timing_within_sb(FILE* fp,$/;" f -verilog_generate_one_routing_segmental_report_timing ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_one_routing_segmental_report_timing(FILE* fp, $/;" f -verilog_generate_one_routing_wire_report_timing ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_one_routing_wire_report_timing(FILE* fp, $/;" f -verilog_generate_report_timing ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_report_timing(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_report_timing_one_sb_ending_segments ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_report_timing_one_sb_ending_segments(FILE* fp, $/;" f -verilog_generate_report_timing_one_sb_thru_segments ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_report_timing_one_sb_thru_segments(FILE* fp, $/;" f -verilog_generate_routing_report_timing ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_routing_report_timing(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_routing_wires_report_timing ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_routing_wires_report_timing(FILE* fp, $/;" f -verilog_generate_sb_report_timing ./fpga_x2p/verilog/verilog_report_timing.c /^void verilog_generate_sb_report_timing(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_sdc_analysis ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_analysis(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_sdc_break_loop_mux ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_break_loop_mux(FILE* fp,$/;" f -verilog_generate_sdc_break_loop_sb ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_break_loop_sb(FILE* fp,$/;" f -verilog_generate_sdc_break_loop_sram ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_break_loop_sram(FILE* fp, $/;" f -verilog_generate_sdc_break_loops ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_break_loops(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_sdc_clock_period ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_clock_period(t_sdc_opts sdc_opts,$/;" f -verilog_generate_sdc_constrain_cbs ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_cbs(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_sdc_constrain_one_cb ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_one_cb(FILE* fp,$/;" f -verilog_generate_sdc_constrain_one_cb_path ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,$/;" f -verilog_generate_sdc_constrain_one_chan ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_one_chan(FILE* fp, $/;" f -verilog_generate_sdc_constrain_one_sb_mux ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_one_sb_mux(FILE* fp,$/;" f -verilog_generate_sdc_constrain_one_sb_path ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_one_sb_path(FILE* fp,$/;" f -verilog_generate_sdc_constrain_pb_types ./fpga_x2p/verilog/verilog_sdc_pb_types.c /^void verilog_generate_sdc_constrain_pb_types(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_sdc_constrain_routing_channels ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_routing_channels(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_sdc_constrain_sbs ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_constrain_sbs(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_generate_sdc_disable_global_ports ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_global_ports(FILE* fp) {$/;" f -verilog_generate_sdc_disable_one_unused_block ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_one_unused_block(FILE* fp,$/;" f -verilog_generate_sdc_disable_one_unused_cb ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, $/;" f -verilog_generate_sdc_disable_one_unused_chan ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_one_unused_chan(FILE* fp, $/;" f -verilog_generate_sdc_disable_one_unused_grid ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_one_unused_grid(FILE* fp,$/;" f -verilog_generate_sdc_disable_sram_orgz ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_sram_orgz(FILE* fp, $/;" f -verilog_generate_sdc_disable_unused_cbs ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_unused_cbs(FILE* fp,$/;" f -verilog_generate_sdc_disable_unused_cbs_muxs ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_unused_cbs_muxs(FILE* fp) {$/;" f -verilog_generate_sdc_disable_unused_grids ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_unused_grids(FILE* fp, $/;" f -verilog_generate_sdc_disable_unused_grids_muxs ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_unused_grids_muxs(FILE* fp,$/;" f -verilog_generate_sdc_disable_unused_routing_channels ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_unused_routing_channels(FILE* fp, $/;" f -verilog_generate_sdc_disable_unused_sbs ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_unused_sbs(FILE* fp,$/;" f -verilog_generate_sdc_disable_unused_sbs_muxs ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp, int LL_nx, int LL_ny) {$/;" f -verilog_generate_sdc_input_output_delays ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_input_output_delays(FILE* fp,$/;" f -verilog_generate_sdc_pnr ./fpga_x2p/verilog/verilog_sdc.c /^void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info,$/;" f -verilog_get_grid_block_subckt_name ./fpga_x2p/verilog/verilog_pbtypes.c /^char* verilog_get_grid_block_subckt_name(int x, int y, int z,$/;" f -verilog_get_grid_phy_block_subckt_name ./fpga_x2p/verilog/verilog_pbtypes.c /^char* verilog_get_grid_phy_block_subckt_name(int x, int y, int z,$/;" f -verilog_get_grid_side_pin_rr_nodes ./fpga_x2p/verilog/verilog_routing.c /^t_rr_node** verilog_get_grid_side_pin_rr_nodes(int* num_pin_rr_nodes,$/;" f -verilog_include_defines_preproc_file ./fpga_x2p/verilog/verilog_utils.c /^void verilog_include_defines_preproc_file(FILE* fp, $/;" f -verilog_include_simulation_defines_file ./fpga_x2p/verilog/verilog_utils.c /^void verilog_include_simulation_defines_file(FILE* fp, $/;" f -verilog_mem_posfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_mem_posfix = "_mem";$/;" v -verilog_mux_basis_posfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_mux_basis_posfix = "_basis";$/;" v -verilog_mux_special_basis_posfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_mux_special_basis_posfix = "_special_basis";$/;" v -verilog_netlist_file_postfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_netlist_file_postfix = ".v";$/;" v -verilog_signal_init_preproc_flag ./fpga_x2p/verilog/verilog_global.c /^char* verilog_signal_init_preproc_flag = "ENABLE_SIGNAL_INITIALIZATION"; \/\/ the flag to enable signal initialization during compilation$/;" v -verilog_sim_timescale ./fpga_x2p/verilog/verilog_global.c /^float verilog_sim_timescale = 1e-9; \/\/ Verilog Simulation time scale (minimum time unit) : 1ns$/;" v -verilog_timing_preproc_flag ./fpga_x2p/verilog/verilog_global.c /^char* verilog_timing_preproc_flag = "ENABLE_TIMING"; \/\/ the flag to enable timing definition during compilation$/;" v -verilog_top_postfix ./fpga_x2p/verilog/verilog_global.c /^char* verilog_top_postfix = "_top.v";$/;" v -verilog_writer ./base/verilog_writer.c /^void verilog_writer(void)$/;" f -view_mux_size_distribution ./route/rr_graph.c /^view_mux_size_distribution(t_ivec *** L_rr_node_indices,$/;" f file: -visited ./power/power.h /^ boolean visited; \/* When traversing netlist, need to track whether the node has been processed *\/$/;" m struct:s_rr_node_power -vpack_net ./base/globals.c /^struct s_net *vpack_net = NULL;$/;" v typeref:struct:s_net -vpack_net_num ./base/vpr_types.h /^ int vpack_net_num;$/;" m struct:s_rr_node -vpack_net_num_changed ./base/vpr_types.h /^ boolean vpack_net_num_changed;$/;" m struct:s_rr_node -vpack_to_clb_net_mapping ./base/globals.c /^int *vpack_to_clb_net_mapping = NULL; \/* [0..num_vpack_nets - 1] *\/$/;" v -vpr_alloc_and_load_output_file_names ./base/vpr_api.c /^void vpr_alloc_and_load_output_file_names(const char* default_name) {$/;" f -vpr_check_arch ./base/vpr_api.c /^void vpr_check_arch(INP t_arch Arch, INP boolean TimingEnabled) {$/;" f -vpr_check_options ./base/vpr_api.c /^void vpr_check_options(INP t_options Options, INP boolean TimingEnabled) {$/;" f -vpr_check_setup ./base/vpr_api.c /^void vpr_check_setup(INP enum e_operation Operation,$/;" f -vpr_fpga_bitstream_generator ./fpga_x2p/bitstream/fpga_bitstream.c /^void vpr_fpga_bitstream_generator(t_vpr_setup vpr_setup,$/;" f -vpr_fpga_generate_bitstream ./fpga_x2p/bitstream/fpga_bitstream.c /^void vpr_fpga_generate_bitstream(t_vpr_setup vpr_setup,$/;" f -vpr_fpga_spice ./fpga_x2p/spice/spice_api.c /^void vpr_fpga_spice(t_vpr_setup vpr_setup,$/;" f -vpr_fpga_verilog ./fpga_x2p/verilog/verilog_api.c /^void vpr_fpga_verilog(t_vpr_setup vpr_setup,$/;" f -vpr_fpga_x2p_tool_suites ./fpga_x2p/base/fpga_x2p_api.c /^void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,$/;" f -vpr_free_all ./base/vpr_api.c /^void vpr_free_all(INOUTP t_arch Arch, INOUTP t_options options,$/;" f -vpr_free_vpr_data_structures ./base/vpr_api.c /^void vpr_free_vpr_data_structures(INOUTP t_arch Arch, INOUTP t_options options,$/;" f -vpr_get_output_file_name ./base/vpr_api.c /^char *vpr_get_output_file_name(enum e_output_files ename) {$/;" f -vpr_init ./base/vpr_api.c /^void vpr_init(INP int argc, INP char **argv, OUTP t_options *options,$/;" f -vpr_init_file_handler ./base/vpr_api.c /^void vpr_init_file_handler() {$/;" f -vpr_init_pre_place_and_route ./base/vpr_api.c /^void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {$/;" f -vpr_pack ./base/vpr_api.c /^void vpr_pack(INP t_vpr_setup vpr_setup, INP t_arch arch) {$/;" f -vpr_pack_opts ./fpga_x2p/shell/cmd_vpr_pack.h /^t_opt_info vpr_pack_opts[] = {$/;" v -vpr_place_and_route ./base/vpr_api.c /^void vpr_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch arch) {$/;" f -vpr_place_and_route_opts ./fpga_x2p/shell/cmd_vpr_place_and_route.h /^t_opt_info vpr_place_and_route_opts[] = {$/;" v -vpr_power_estimation ./base/vpr_api.c /^void vpr_power_estimation(t_vpr_setup vpr_setup, t_arch Arch) {$/;" f -vpr_print_title ./base/vpr_api.c /^void vpr_print_title(void) {$/;" f -vpr_print_usage ./base/vpr_api.c /^void vpr_print_usage(void) {$/;" f -vpr_read_and_process_blif ./base/vpr_api.c /^void vpr_read_and_process_blif(INP char *blif_file,$/;" f -vpr_read_options ./base/vpr_api.c /^void vpr_read_options(INP int argc, INP char **argv, OUTP t_options * options) {$/;" f -vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture ./base/vpr_api.c /^t_trace* vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture($/;" f -vpr_run_interactive_mode ./fpga_x2p/shell/mini_shell.c /^void vpr_run_interactive_mode() {$/;" f -vpr_run_script_mode ./fpga_x2p/shell/mini_shell.c /^void vpr_run_script_mode(char* script_file_name) {$/;" f -vpr_set_output_file_name ./base/vpr_api.c /^void vpr_set_output_file_name(enum e_output_files ename, const char *name,$/;" f -vpr_setup ./fpga_x2p/shell/shell_types.h /^ t_vpr_setup vpr_setup;$/;" m struct:s_shell_env -vpr_setup_vpr ./base/vpr_api.c /^void vpr_setup_vpr(INP t_options *Options, INP boolean TimingEnabled,$/;" f -vpr_shell_prefix ./fpga_x2p/shell/mini_shell.c /^char* vpr_shell_prefix = "VPR7-OpenFPGA> ";$/;" v -vpr_show_setup ./base/vpr_api.c /^void vpr_show_setup(INP t_options options, INP t_vpr_setup vpr_setup) {$/;" f -vpr_to_phy_track ./route/rr_graph2.c /^static int vpr_to_phy_track(INP int itrack, INP int chan_num, INP int seg_num,$/;" f file: -vpr_versapower_opts ./fpga_x2p/shell/cmd_vpr_power.h /^t_opt_info vpr_versapower_opts[] = {$/;" v -watch_edges ./route/rr_graph.c /^void watch_edges(int inode, t_linked_edge * edge_list_head) {$/;" f -which_button ./base/graphics.c /^static int which_button (Window win) $/;" f file: -width ./base/graphics.c /^ int width; $/;" m struct:__anon4 file: -win ./base/graphics.c /^ Window win; $/;" m struct:__anon4 file: -win32_colors ./base/graphics.c /^static const COLORREF win32_colors[NUM_COLOR] = { RGB(255, 255, 255),$/;" v file: -win32_drain_message_queue ./base/graphics.c /^void win32_drain_message_queue () {$/;" f -win32_line_styles ./base/graphics.c /^static const int win32_line_styles[2] = { PS_SOLID, PS_DASH };$/;" v file: -windowAdjustFlag ./base/graphics.c /^static int windowAdjustFlag = 0, adjustButton = -1;$/;" v file: -wire_buffer_inf ./mrfpga/mrfpga_globals.c /^t_buffer_inf wire_buffer_inf;$/;" v -wire_switch ./base/vpr_types.h /^ short wire_switch;$/;" m struct:s_seg_details -wire_to_ipin_switch ./base/vpr_types.h /^ short wire_to_ipin_switch;$/;" m struct:s_det_routing_arch -wirelength ./base/place_and_route.h /^ int wirelength; \/* corresponding wirelength of successful routing at wneed *\/$/;" m struct:s_fmap_cell -wires_spice_file_name ./fpga_x2p/spice/spice_globals.c /^char* wires_spice_file_name = "wires.sp";$/;" v -wires_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* wires_verilog_file_name = "wires.v";$/;" v -with_val ./fpga_x2p/shell/read_opt_types.h /^ enum opt_with_val with_val;$/;" m struct:s_opt_info typeref:enum:s_opt_info::opt_with_val -wneed ./base/place_and_route.h /^ int wneed; \/* need wneed to route *\/$/;" m struct:s_fmap_cell -write_formality_script ./fpga_x2p/verilog/verilog_formality_autodeck.c /^void write_formality_script (t_syn_verilog_opts fpga_verilog_opts,$/;" f -write_include_netlists ./fpga_x2p/verilog/verilog_include_netlists.c /^void write_include_netlists (char* src_dir_formatted,$/;" f -x ./base/easygl_constants.h /^ float x; $/;" m struct:__anon1 -x ./base/vpr_types.h /^ int x;$/;" m struct:s_block -x ./base/vpr_types.h /^ int x;$/;" m struct:s_cb -x ./base/vpr_types.h /^ int x;$/;" m struct:s_sb -x ./place/place.c /^ int x;$/;" m struct:s_legal_pos file: -x_offset ./base/vpr_types.h /^ int x_offset;$/;" m struct:s_clb_to_clb_directs -x_offset ./place/place_macro.h /^ int x_offset;$/;" m struct:s_pl_macro_member -x_rr_node_left ./base/draw.c /^static float *x_rr_node_left = NULL;$/;" v file: -x_rr_node_right ./base/draw.c /^static float *x_rr_node_right = NULL;$/;" v file: -xcoord ./base/graphics.c /^static int xcoord (float worldx) $/;" f file: -xdiv ./base/graphics.c /^static float xdiv, ydiv;$/;" v file: -xhigh ./base/vpr_types.h /^ short xhigh;$/;" m struct:s_rr_node -xleft ./base/graphics.c /^ int xleft; $/;" m struct:__anon4 file: -xleft ./base/graphics.c /^static float xleft, xright, ytop, ybot; \/* world coordinates *\/$/;" v file: -xleft ./base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 -xlow ./base/vpr_types.h /^ short xlow;$/;" m struct:s_rr_node -xmax ./base/vpr_types.h /^ int xmax;$/;" m struct:s_bb -xmin ./base/vpr_types.h /^ int xmin;$/;" m struct:s_bb -xmult ./base/graphics.c /^static float xmult, ymult; \/* Transformation factors *\/$/;" v file: -xmult ./base/graphics.h /^ float xmult, ymult;$/;" m struct:__anon6 -xnew ./place/place.c /^ int xnew;$/;" m struct:s_pl_moved_block file: -xold ./place/place.c /^ int xold;$/;" m struct:s_pl_moved_block file: -xright ./base/graphics.c /^static float xleft, xright, ytop, ybot; \/* world coordinates *\/$/;" v file: -xright ./base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 -y ./base/easygl_constants.h /^ float y;$/;" m struct:__anon1 -y ./base/vpr_types.h /^ int y;$/;" m struct:s_block -y ./base/vpr_types.h /^ int y;$/;" m struct:s_cb -y ./base/vpr_types.h /^ int y;$/;" m struct:s_sb -y ./place/place.c /^ int y;$/;" m struct:s_legal_pos file: -y_offset ./base/vpr_types.h /^ int y_offset;$/;" m struct:s_clb_to_clb_directs -y_offset ./place/place_macro.h /^ int y_offset; $/;" m struct:s_pl_macro_member -y_rr_node_bottom ./base/draw.c /^static float *y_rr_node_bottom = NULL;$/;" v file: -y_rr_node_top ./base/draw.c /^static float *y_rr_node_top = NULL;$/;" v file: -ybot ./base/graphics.c /^static float xleft, xright, ytop, ybot; \/* world coordinates *\/$/;" v file: -ybot ./base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 -ycoord ./base/graphics.c /^static int ycoord (float worldy) $/;" f file: -ydiv ./base/graphics.c /^static float xdiv, ydiv;$/;" v file: -yhigh ./base/vpr_types.h /^ short yhigh;$/;" m struct:s_rr_node -ylow ./base/vpr_types.h /^ short ylow;$/;" m struct:s_rr_node -ymax ./base/vpr_types.h /^ int ymax;$/;" m struct:s_bb -ymin ./base/vpr_types.h /^ int ymin;$/;" m struct:s_bb -ymult ./base/graphics.c /^static float xmult, ymult; \/* Transformation factors *\/$/;" v file: -ymult ./base/graphics.h /^ float xmult, ymult;$/;" m struct:__anon6 -ynew ./place/place.c /^ int ynew;$/;" m struct:s_pl_moved_block file: -yold ./place/place.c /^ int yold;$/;" m struct:s_pl_moved_block file: -ytop ./base/graphics.c /^ int ytop;$/;" m struct:__anon4 file: -ytop ./base/graphics.c /^static float xleft, xright, ytop, ybot; \/* world coordinates *\/$/;" v file: -ytop ./base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 -z ./base/vpr_types.h /^ int z; \/* For IPIN, source, and sink nodes, helps identify which location this rr_node belongs to *\/$/;" m struct:s_rr_node -z ./base/vpr_types.h /^ int z;$/;" m struct:s_block -z ./place/place.c /^ int z;$/;" m struct:s_legal_pos file: -z_offset ./base/vpr_types.h /^ int z_offset;$/;" m struct:s_clb_to_clb_directs -z_offset ./place/place_macro.h /^ int z_offset;$/;" m struct:s_pl_macro_member -zero_one_spice_model_grid_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void zero_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) {$/;" f -zero_one_spice_model_routing_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void zero_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) {$/;" f -zero_spice_model_grid_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void zero_spice_model_grid_index_low_high(int num_spice_models, $/;" f -zero_spice_models_cnt ./fpga_x2p/base/fpga_x2p_utils.c /^void zero_spice_models_cnt(int num_spice_models, t_spice_model* spice_model) {$/;" f -zero_spice_models_routing_index_low_high ./fpga_x2p/base/fpga_x2p_utils.c /^void zero_spice_models_routing_index_low_high(int num_spice_models, $/;" f -znew ./place/place.c /^ int znew;$/;" m struct:s_pl_moved_block file: -zold ./place/place.c /^ int zold;$/;" m struct:s_pl_moved_block file: -zoom_fit ./base/graphics.c /^zoom_fit (void (*drawscreen) (void)) $/;" f file: -zoom_in ./base/graphics.c /^zoom_in (void (*drawscreen) (void)) $/;" f file: -zoom_out ./base/graphics.c /^zoom_out (void (*drawscreen) (void)) $/;" f file: