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[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF

This commit is contained in:
tangxifan 2021-10-30 14:46:12 -07:00
parent 0b770f3330
commit ec184ef532
1 changed files with 17 additions and 1 deletions
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18
openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
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@ -8,7 +8,23 @@ proc
techmap -D NO_LUT -map +/adff2dff.v techmap -D NO_LUT -map +/adff2dff.v
# Synthesis # Synthesis
synth -top ${TOP_MODULE} -flatten opt_expr
opt_clean
check
opt -nodffe -nosdff
fsm
opt -nodffe -nosdff
wreduce
peepopt
opt_clean
opt -nodffe -nosdff
memory -nomap
opt_clean
opt -fast -full -nodffe -nosdff
memory_map
opt -full -nodffe -nosdff
techmap
opt -fast -nodffe -nosdff
clean clean
# LUT mapping # LUT mapping