Merge branch 'tangxifan-patch-2' of github.com:lnis-uofu/OpenFPGA into tangxifan-patch-2

libs/libpcf/src/base/repack_design_constraints.h

@@ -36,7 +36,11 @@ constexpr const char* REPACK_DESIGN_CONSTRAINT_OPEN_NET = "OPEN";
  *******************************************************************/
 class RepackDesignConstraints {
  public: /* Type of design constraints */
-  enum e_design_constraint_type { PIN_ASSIGNMENT, NUM_DESIGN_CONSTRAINT_TYPES };
+  enum e_design_constraint_type {
+    PIN_ASSIGNMENT,
+    IGNORE_NET,
+    NUM_DESIGN_CONSTRAINT_TYPES
+  };
 
  public: /* Types */
   typedef vtr::vector<RepackDesignConstraintId,

libs/libpcf/src/io/read_xml_repack_design_constraints.cpp

@@ -11,6 +11,7 @@
 
 /* Headers from vtr util library */
 #include "vtr_assert.h"
+#include "vtr_log.h"
 #include "vtr_time.h"
 
 /* Headers from libopenfpga util library */
@@ -52,6 +53,49 @@ static void read_xml_pin_constraint(
     get_attribute(xml_pin_constraint, "net", loc_data).as_string());
 }
 
+static void read_xml_ignore_net_constraint(
+  pugi::xml_node& xml_pin_constraint, const pugiutil::loc_data& loc_data,
+  RepackDesignConstraints& repack_design_constraints) {
+  /* Create a new design constraint in the storage */
+  RepackDesignConstraintId design_constraint_id =
+    repack_design_constraints.create_design_constraint(
+      RepackDesignConstraints::IGNORE_NET);
+
+  if (false == repack_design_constraints.valid_design_constraint_id(
+                 design_constraint_id)) {
+    archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint),
+                   "Fail to create design constraint!\n");
+  }
+
+  std::string pin_ctx_to_parse =
+    get_attribute(xml_pin_constraint, "pin", loc_data).as_string();
+  openfpga::StringToken pin_tokenizer(pin_ctx_to_parse);
+  std::vector<std::string> pin_info = pin_tokenizer.split('.');
+  /* Expect two contents, otherwise error out */
+  if (pin_info.size() != 2) {
+    std::string err_msg =
+      std::string("Invalid content '") + pin_ctx_to_parse +
+      std::string("' to skip, expect <pb_type_name>.<pin>\n");
+    VTR_LOG_ERROR(err_msg.c_str());
+    VTR_ASSERT(pin_info.size() == 2);
+  }
+  std::string pb_type_name = pin_info[0];
+  openfpga::PortParser port_parser(pin_info[1]);
+  openfpga::BasicPort curr_port = port_parser.port();
+  if (!curr_port.is_valid()) {
+    std::string err_msg =
+      std::string("Invalid pin definition '") + pin_ctx_to_parse +
+      std::string("', expect <pb_type_name>.<pin_name>[int:int]\n");
+    VTR_LOG_ERROR(err_msg.c_str());
+    VTR_ASSERT(curr_port.is_valid());
+  }
+  repack_design_constraints.set_pb_type(design_constraint_id, pb_type_name);
+  repack_design_constraints.set_pin(design_constraint_id, curr_port);
+  repack_design_constraints.set_net(
+    design_constraint_id,
+    get_attribute(xml_pin_constraint, "name", loc_data).as_string());
+}
+
 /********************************************************************
  * Parse XML codes about <repack_design_constraints> to an object of
  *RepackDesignConstraints
@@ -80,11 +124,16 @@ RepackDesignConstraints read_xml_repack_design_constraints(
 
     for (pugi::xml_node xml_design_constraint : xml_root.children()) {
       /* Error out if the XML child has an invalid name! */
-      if (xml_design_constraint.name() != std::string("pin_constraint")) {
+      if (xml_design_constraint.name() == std::string("pin_constraint")) {
-        bad_tag(xml_design_constraint, loc_data, xml_root, {"pin_constraint"});
+        read_xml_pin_constraint(xml_design_constraint, loc_data,
+                                repack_design_constraints);
+      } else if (xml_design_constraint.name() == std::string("ignore_net")) {
+        read_xml_ignore_net_constraint(xml_design_constraint, loc_data,
+                                       repack_design_constraints);
+      } else {
+        bad_tag(xml_design_constraint, loc_data, xml_root,
+                {"pin_constraint", "ignore_net"});
       }
-      read_xml_pin_constraint(xml_design_constraint, loc_data,
-                              repack_design_constraints);
     }
   } catch (pugiutil::XmlError& e) {
     archfpga_throw(design_constraint_fname, e.line(), "%s", e.what());

openfpga/src/repack/repack.cpp

@@ -575,10 +575,13 @@ static void add_lb_router_nets(
     /* Only for global net which should be ignored, cache the sink nodes */
     BasicPort curr_pin(std::string(source_pb_pin->port->name),
                        source_pb_pin->pin_number, source_pb_pin->pin_number);
-    if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id)) &&
+    if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id) &&
-        (clustering_ctx.clb_nlist.net_is_global(cluster_net_id)) &&
+         clustering_ctx.clb_nlist.net_is_global(cluster_net_id) &&
-        (options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name),
+         options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name),
-                                           curr_pin))) {
+                                           curr_pin)) ||
+        (options.net_is_specified_to_be_ignored(
+          atom_ctx.nlist.net_name(pb_pin_mapped_nets[source_pb_pin]),
+          std::string(lb_type->pb_type->name), curr_pin))) {
       /* Find the net mapped to this pin in clustering results*/
       AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin];
 

openfpga/src/repack/repack_option.cpp

@@ -46,6 +46,24 @@ bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name,
   return false;
 }
 
+bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name,
+                                                  std::string pb_type_name,
+                                                  const BasicPort& pin) const {
+  const RepackDesignConstraints& design_constraint = design_constraints();
+  /* If found a constraint, record the net name */
+  for (const RepackDesignConstraintId id_ :
+       design_constraint.design_constraints()) {
+    if (design_constraint.type(id_) == RepackDesignConstraints::IGNORE_NET &&
+        design_constraint.pb_type(id_) == pb_type_name &&
+        design_constraint.net(id_) == cluster_net_name) {
+      if (design_constraint.pin(id_).mergeable(pin) &&
+          design_constraint.pin(id_).contained(pin))
+        return true;
+    }
+  }
+  return false;
+}
+
 bool RepackOption::verbose_output() const { return verbose_output_; }
 
 /******************************************************************************

openfpga/src/repack/repack_option.h

@@ -25,6 +25,9 @@ class RepackOption {
   /* Identify if a pin should ignore all the global nets */
   bool is_pin_ignore_global_nets(const std::string& pb_type_name,
                                  const BasicPort& pin) const;
+  bool net_is_specified_to_be_ignored(std::string cluster_net_name,
+                                      std::string pb_type_name,
+                                      const BasicPort& pin) const;
   bool verbose_output() const;
 
  public: /* Public mutators */

openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml

@@ -0,0 +1,5 @@
+<pin_constraints>
+  <set_io pin="op_clk[0]" net="clk_i"/>
+  <set_io pin="op_reset[0]" net="rst_i"/>
+</pin_constraints>
+

openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml

@@ -0,0 +1,7 @@
+<repack_design_constraints>
+  <pin_constraint pb_type="clb" pin="clk[0]" net="clk_i"/>
+  <pin_constraint pb_type="clb" pin="reset[0]" net="rst_i"/>
+  <ignore_net name="rst_i" pin="clb.I[0:11]"/>
+
+</repack_design_constraints>
+

openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml

@@ -0,0 +1,5 @@
+<pin_constraints>
+  <set_io pin="op_clk[0]" net="clk"/>
+  <set_io pin="op_reset[0]" net="rst"/>
+</pin_constraints>
+

openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml

@@ -0,0 +1,8 @@
+<repack_design_constraints>
+  <pin_constraint pb_type="clb" pin="clk[0]" net="clk"/>
+  <pin_constraint pb_type="clb" pin="reset[0]" net="rst"/>
+  <ignore_net name="rst" pin="clb.I[0:11]"/>
+  <reset />
+  <!-- Leave lreset unconstrained as it may be mapped to any internal reset signals -->
+</repack_design_constraints>
+

openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf

@@ -0,0 +1,50 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 3*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
+openfpga_vpr_device_layout=2x2
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localRstGen_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/two_dff_inv_rst/two_dff_inv_rst.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = two_dff_inv_rst
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
+bench0_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
+
+bench1_top = rst_on_lut
+bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml
+bench1_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

yosys

@@ -1 +1 @@
-Subproject commit 2ffea67b043fcde3854618aca01a8aed0f41ec56
+Subproject commit 8bd681acfc3b0913e57f6312ed357b2334cf19cb