From eb056e2afdc0c703b17710effaae943aa21fdae6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 22 Mar 2021 12:50:17 -0600
Subject: [PATCH] [Benchmark] Add missing DPRAM module to or1200

---
 .../benchmarks/vtr_benchmark/or1200.v         | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/openfpga_flow/benchmarks/vtr_benchmark/or1200.v b/openfpga_flow/benchmarks/vtr_benchmark/or1200.v
index e6f75b38e..df164e27a 100755
--- a/openfpga_flow/benchmarks/vtr_benchmark/or1200.v
+++ b/openfpga_flow/benchmarks/vtr_benchmark/or1200.v
@@ -5234,3 +5234,49 @@ end
 wire[8:0] unused_signal;
 assign unused_signal = lsu_op;
 endmodule
+
+//---------------------------------------
+// A dual-port RAM 
+// This module is tuned for VTR's benchmarks
+//---------------------------------------
+module dual_port_ram (
+	input clk,
+	input we1,
+	input we2,
+	input [`OR1200_REGFILE_ADDR_WIDTH - 1 : 0] addr1,
+	input [`OR1200_OPERAND_WIDTH - 1 : 0] data1,
+	output [`OR1200_OPERAND_WIDTH - 1 : 0] out1,
+	input [`OR1200_REGFILE_ADDR_WIDTH - 1 : 0] addr2,
+	input [`OR1200_OPERAND_WIDTH - 1 : 0] data2,
+	output [`OR1200_OPERAND_WIDTH - 1 : 0] out2
+);
+
+	reg [`OR1200_OPERAND_WIDTH - 1 : 0] ram[2**`OR1200_REGFILE_ADDR_WIDTH - 1 : 0];
+	reg [`OR1200_OPERAND_WIDTH - 1 : 0] data_out1;
+	reg [`OR1200_OPERAND_WIDTH - 1 : 0] data_out2;
+
+	assign out1 = data_out1;
+	assign out2 = data_out2;
+
+    // If writen enable 1 is activated,
+    // data1 will be loaded through addr1
+    // Otherwise, data will be read out through addr1
+	always @(posedge clk) begin
+		if (we1) begin
+			ram[addr1] <= data1;
+        end else begin
+			data_out1 <= ram[addr1];
+		end
+	end
+
+    // If writen enable 2 is activated,
+    // data1 will be loaded through addr2
+    // Otherwise, data will be read out through addr2
+	always @(posedge clk) begin
+		if (we2) begin
+			ram[addr2] <= data2;
+		end else begin
+			data_out2 <= ram[addr2];
+		end
+	end
+endmodule