diff --git a/examples/example_1.act b/examples/example_1.act
new file mode 100644
index 000000000..19fd43010
--- /dev/null
+++ b/examples/example_1.act
@@ -0,0 +1,4 @@
+I0 0.478200 0.190600
+clk 0.493600 0.194000
+Q0 0.521800 0.190600
+n7 0.521800 0.099455
diff --git a/examples/example_1.blif b/examples/example_1.blif
index b696e7312..eaf9b1fdb 100644
--- a/examples/example_1.blif
+++ b/examples/example_1.blif
@@ -1,13 +1,10 @@
-# Baudouin Chauviere University of Utah 30 September 2018
-# Benchmark doing an inverter
-
+# Benchmark "inverter.bench" written by ABC on Wed Nov 14 13:52:06 2018
 .model inverter.bench
 .inputs I0 clk
 .outputs Q0
 
-.latch        n0        Q0 re        clk  0
+.latch         n7         Q0 re        clk  0
 
-.names I0 n0
+.names I0 n7
 0 1
-
-.end
\ No newline at end of file
+.end
diff --git a/examples/example_1.sh b/examples/example_1.sh
index 5e6256400..0a3d284e5 100755
--- a/examples/example_1.sh
+++ b/examples/example_1.sh
@@ -3,7 +3,7 @@
 
 # Pack, place, and route a heterogeneous FPGA
 # Packing uses the AAPack algorithm
-../vpr7_x2p/vpr/vpr ./example_1.xml ./example_1.blif --full_stats --nodisp --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test
+../vpr7_x2p/vpr/vpr ./example_1.xml ./example_1.blif --full_stats --nodisp --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_example_1 --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_example_1
 
 
 
diff --git a/examples/example_1.xml b/examples/example_1.xml
index 0bf993ffc..79c3c940f 100644
--- a/examples/example_1.xml
+++ b/examples/example_1.xml
@@ -25,7 +25,8 @@
 
   <!-- Physical descriptions begin -->
   <layout auto="1.0"/>
-
+<!-- <layout width="3" height="3"/> -->
+  
   <spice_settings>
     <parameters>
       <options sim_temp="25" post="off" captab="off" fast="on"/>
@@ -63,13 +64,23 @@
       <io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
       <io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
     </transistors> 
-    <module_spice_models>
-      <spice_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
+    <module_circuit_models>
+      <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
         <design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
-      </spice_model>
-      <spice_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
+      </circuit_model>
+	<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
+        	<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
+        	<port type="input" prefix="in" size="1"/>
+        	<port type="output" prefix="out" size="1"/>
+      </circuit_model>
+	<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
+		<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
+		<port type="input" prefix="in" size="1"/>
+		<port type="output" prefix="out" size="1"/>
+      </circuit_model>
+      <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
         <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
         <input_buffer exist="off"/>
         <output_buffer exist="off"/>
@@ -77,86 +88,106 @@
         <port type="input" prefix="sel" size="1"/>
         <port type="input" prefix="selb" size="1"/>
         <port type="output" prefix="out" size="1"/>
-      </spice_model>
-      <spice_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
+      </circuit_model>
+      <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
         <design_technology type="cmos"/>
         <input_buffer exist="off"/>
         <output_buffer exist="off"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
         <wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-      </spice_model>
-      <spice_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
+      </circuit_model>
+      <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
         <design_technology type="cmos"/>
         <input_buffer exist="off"/>
         <output_buffer exist="off"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
         <wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-      </spice_model>
-      <spice_model type="mux" name="mux_2level" prefix="mux_2level" is_default="1" dump_structural_verilog="true">
+      </circuit_model>
+	<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" dump_structural_verilog="true">
+		<design_technology type="cmos" structure="one-level"/>
+		<input_buffer exist="on" circuit_model_name="INVTX1"/>
+		<output_buffer exist="on" circuit_model_name="tap_buf4"/>
+		<!--mux2to1 subckt_name="mux2to1"/-->
+		<pass_gate_logic circuit_model_name="TGATE"/>
+		<port type="input" prefix="in" size="1"/>
+		<port type="output" prefix="out" size="1"/>
+		<port type="sram" prefix="sram" size="1"/>
+      	</circuit_model>
+      <circuit_model type="mux" name="mux_2level" prefix="mux_2level" is_default="1" dump_structural_verilog="true">
         <design_technology type="cmos" structure="multi-level" num_level="2"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVTX1"/>
         <!--mux2to1 subckt_name="mux2to1"/-->
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
         <port type="sram" prefix="sram" size="1"/>
-      </spice_model>
+      </circuit_model>
+	<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+		<design_technology type="cmos" structure="multi-level" num_level="2"/>
+		<input_buffer exist="on" circuit_model_name="INVTX1"/>
+		<output_buffer exist="on" circuit_model_name="tap_buf4"/>
+		<!--mux2to1 subckt_name="mux2to1"/-->
+		<pass_gate_logic circuit_model_name="TGATE"/>
+		<port type="input" prefix="in" size="1"/>
+		<port type="output" prefix="out" size="1"/>
+		<port type="sram" prefix="sram" size="1"/>
+      </circuit_model>
 
-      <spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/ff.v">
+      <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/ff.v">
          <design_technology type="cmos"/>
-         <input_buffer exist="on" spice_model_name="INVTX1"/>
-         <output_buffer exist="on" spice_model_name="INVTX1"/>
-         <pass_gate_logic spice_model_name="TGATE"/>
+         <input_buffer exist="on" circuit_model_name="INVTX1"/>
+         <output_buffer exist="on" circuit_model_name="INVTX1"/>
+         <pass_gate_logic circuit_model_name="TGATE"/>
          <port type="input" prefix="D" size="1"/>
          <port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
          <port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
          <port type="output" prefix="Q" size="1"/>
          <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
-      </spice_model>
-      <spice_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      </circuit_model>
+      <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
-        <lut_input_buffer exist="on" spice_model_name="buf4"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVTX1"/>
+        <lut_input_buffer exist="on" circuit_model_name="buf4"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="4"/>
         <port type="output" prefix="out" size="1"/>
         <port type="sram" prefix="sram" size="16"/>
-      </spice_model>
-      <spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v" >
+      </circuit_model>
+      <circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v" >
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVTX1"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="2"/>
-      </spice_model>
-      <spice_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v">
+      </circuit_model>
+      <circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVTX1"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="2"/>
-        <port type="bl" prefix="bl" size="1" default_val="0" inv_spice_model_name="INVTX1"/>
-        <port type="blb" prefix="blb" size="1" default_val="1" inv_spice_model_name="INVTX1"/>
-        <port type="wl" prefix="wl" size="1" default_val="0" inv_spice_model_name="INVTX1"/>
-      </spice_model>
-      <spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/io.v">
+        <port type="bl" prefix="bl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
+        <port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
+        <port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
+      </circuit_model>
+      <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/io.v">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVTX1"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="inout" prefix="pad" size="1"/>
-        <port type="sram" prefix="en" size="1" mode_select="true" spice_model_name="sram6T_blwl" default_val="1"/>
+        <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_blwl" default_val="1"/>
         <port type="input" prefix="outpad" size="1"/>
         <port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
         <port type="output" prefix="inpad" size="1"/>
-      </spice_model>
-    </module_spice_models>
+      </circuit_model>
+    </module_circuit_models>
   </spice_settings>
   <device>
     <sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
@@ -164,8 +195,8 @@
 
     <area grid_logic_tile_area="0"/> 
     <sram area="6">
-      <verilog organization="memory_bank" spice_model_name="sram6T_blwl"/>
-      <spice organization="standalone" spice_model_name="sram6T" />
+      <verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
+      <spice organization="standalone" circuit_model_name="sram6T" />
     </sram>
     <chan_width_distr>
       <io width="1.000000"/>
@@ -176,25 +207,25 @@
   </device>
 
   <cblocks>
-    <switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
+    <switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
     </switch>
   </cblocks>
   <switchlist>
-	<switch type="mux" name="sb_mux_L4" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
+	<switch type="mux" name="sb_mux_L4" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
     </switch>
   </switchlist>
   <segmentlist>
-    <segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
+    <segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
       <mux name="sb_mux_L4"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>
     </segment>
-    <segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
+    <segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
       <mux name="sb_mux_L4"/>
       <sb type="pattern">1 1 1</sb>
       <cb type="pattern">1 1 </cb>
     </segment>
-    <segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
+    <segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
       <mux name="sb_mux_L4"/>
       <sb type="pattern">1 1</sb>
       <cb type="pattern">1</cb>
@@ -208,7 +239,7 @@
 
       <!-- physical design description -->
       <mode name="io_phy" disabled_in_packing="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1" spice_model_name="iopad">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
         </pb_type>
@@ -223,7 +254,7 @@
       </mode>
 
       <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1" spice_model_name="iopad" mode_bits="1">
+        <pb_type name="inpad" blif_model=".input" num_pb="1" circuit_model_name="iopad" mode_bits="1">
           <output name="inpad" num_pins="1"/>
         </pb_type>
         <interconnect>
@@ -233,7 +264,7 @@
         </interconnect>
       </mode>
       <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1" spice_model_name="iopad" mode_bits="0">
+        <pb_type name="outpad" blif_model=".output" num_pb="1" circuit_model_name="iopad" mode_bits="0">
           <input name="outpad" num_pins="1"/>
         </pb_type>
         <interconnect>
@@ -289,7 +320,7 @@
             <clock name="clk" num_pins="1"/> 
 
             <!-- Define LUT -->
-            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut" spice_model_name="lut4">
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut4">
               <input name="in" num_pins="4" port_class="lut_in"/>
               <output name="out" num_pins="1" port_class="lut_out"/>
               <!-- LUT timing using delay matrix, one delay per input -->
@@ -302,7 +333,7 @@
             </pb_type>
 
             <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" spice_model_name="static_dff">
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
@@ -317,7 +348,7 @@
                 <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> -->
               </direct>
               <direct name="direct3" input="ble4.clk" output="ff.clk"/>                    
-              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out" spice_model_name="mux_1level_tapbuf">
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out" circuit_model_name="mux_1level_tapbuf">
                 <delay_constant max="42.06e-12" in_port="lut4.out" out_port="ble4.out" />
                 <delay_constant max="42.06e-12" in_port="ff.Q" out_port="ble4.out" />
               </mux>
@@ -332,7 +363,7 @@
         <!-- 4-LUT mode definition end -->
       </pb_type>
       <interconnect>
-        <complete name="crossbar" input="clb.I fle[0:0].out" output="fle[0:0].in" spice_model_name="mux_2level">
+        <complete name="crossbar" input="clb.I fle[0:0].out" output="fle[0:0].in" circuit_model_name="mux_2level">
           <delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[0:0].in" />
           <delay_constant max="53.44e-12" in_port="fle[0:0].out" out_port="fle[0:0].in" />
         </complete>
@@ -369,4 +400,4 @@
   <clocks>
     <clock buffer_size="auto" C_wire="0"/>
   </clocks>
-</architecture>
\ No newline at end of file
+</architecture>
diff --git a/examples/example_2.act b/examples/example_2.act
new file mode 100644
index 000000000..e59326b48
--- /dev/null
+++ b/examples/example_2.act
@@ -0,0 +1,4 @@
+I0 0.501800 0.202600
+clk 0.488800 0.199600
+Q0 0.498200 0.202600
+n7 0.498200 0.100935
diff --git a/examples/example_2.blif b/examples/example_2.blif
index aeb37025b..de9f0eeb8 100644
--- a/examples/example_2.blif
+++ b/examples/example_2.blif
@@ -1,13 +1,10 @@
-# Baudouin Chauviere University of Utah 30 September 2018
-# Benchmark doing an inverter
-
+# Benchmark "example_2.bench" written by ABC on Wed Nov 14 11:42:18 2018
 .model example_2.bench
 .inputs I0 clk
 .outputs Q0
 
-.latch        n0        Q0 re        clk  0
+.latch         n7         Q0 re        clk  0
 
-.names I0 n0
+.names I0 n7
 0 1
-
-.end
\ No newline at end of file
+.end
diff --git a/examples/example_2.sh b/examples/example_2.sh
index 403736f7d..74041f62e 100755
--- a/examples/example_2.sh
+++ b/examples/example_2.sh
@@ -3,7 +3,6 @@
 
 # Pack, place, and route a heterogeneous FPGA
 # Packing uses the AAPack algorithm
-../vpr7_x2p/vpr/vpr ./example_2.xml ./example_2.blif --full_stats --nodisp --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test
-
+../vpr7_x2p/vpr/vpr ./example_2.xml ./example_2.blif --full_stats --nodisp --route_chan_width 100 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_example_2 --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_example_2
 
 
diff --git a/examples/example_2.xml b/examples/example_2.xml
index c5b479a56..846f9dc4c 100644
--- a/examples/example_2.xml
+++ b/examples/example_2.xml
@@ -24,8 +24,8 @@
   
 
   <!-- Physical descriptions begin -->
-  <!-- <layout auto="1.0"/> --> <!-- Takes the smallest square possible that fits the number of LUTs needed -->
-  <layout width="3" height="3"/>
+  <layout auto="1.0"/> <!-- Takes the smallest square possible that fits the number of LUTs needed -->
+  <!-- <layout width="3" height="3"/> -->
   
   <spice_settings>
     <parameters>
@@ -42,7 +42,6 @@
           <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
         </slew>
         <delay>
-          <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
           <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
         </delay>
       </measure>
@@ -64,13 +63,23 @@
       <io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
       <io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
     </transistors> 
-    <module_spice_models>
-      <spice_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
+    <module_circuit_models>
+      <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
         <design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
-      </spice_model>
-      <spice_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
+      </circuit_model>
+	<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+      </circuit_model>
+	<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
+		<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
+		<port type="input" prefix="in" size="1"/>
+		<port type="output" prefix="out" size="1"/>
+      </circuit_model>
+      <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
         <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
         <input_buffer exist="off"/>
         <output_buffer exist="off"/>
@@ -78,86 +87,106 @@
         <port type="input" prefix="sel" size="1"/>
         <port type="input" prefix="selb" size="1"/>
         <port type="output" prefix="out" size="1"/>
-      </spice_model>
-      <spice_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
+      </circuit_model>
+      <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
         <design_technology type="cmos"/>
         <input_buffer exist="off"/>
         <output_buffer exist="off"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
         <wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-      </spice_model>
-      <spice_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
+      </circuit_model>
+      <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
         <design_technology type="cmos"/>
         <input_buffer exist="off"/>
         <output_buffer exist="off"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
         <wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-      </spice_model>
-      <spice_model type="mux" name="mux_2level" prefix="mux_2level" is_default="1" dump_structural_verilog="true">
+      </circuit_model>
+	<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" dump_structural_verilog="true">
+		<design_technology type="cmos" structure="one-level"/>
+		<input_buffer exist="on" circuit_model_name="INVTX1"/>
+		<output_buffer exist="on" circuit_model_name="tap_buf4"/>
+		<!--mux2to1 subckt_name="mux2to1"/-->
+		<pass_gate_logic circuit_model_name="TGATE"/>
+		<port type="input" prefix="in" size="1"/>
+		<port type="output" prefix="out" size="1"/>
+		<port type="sram" prefix="sram" size="1"/>
+      	</circuit_model>
+	<circuit_model type="mux" name="mux_2level" prefix="mux_2level" is_default="1" dump_structural_verilog="true">
+		<design_technology type="cmos" structure="multi-level" num_level="2"/>
+		<input_buffer exist="on" circuit_model_name="INVTX1"/>
+		<output_buffer exist="on" circuit_model_name="INVTX1"/>
+		<!--mux2to1 subckt_name="mux2to1"/-->
+		<pass_gate_logic circuit_model_name="TGATE"/>
+		<port type="input" prefix="in" size="1"/>
+		<port type="output" prefix="out" size="1"/>
+		<port type="sram" prefix="sram" size="1"/>
+      	</circuit_model>
+      <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
         <design_technology type="cmos" structure="multi-level" num_level="2"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="tap_buf4"/>
         <!--mux2to1 subckt_name="mux2to1"/-->
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
         <port type="sram" prefix="sram" size="1"/>
-      </spice_model>
+      </circuit_model>
 
-      <spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/ff.v">
+      <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/ff.v">
          <design_technology type="cmos"/>
-         <input_buffer exist="on" spice_model_name="INVTX1"/>
-         <output_buffer exist="on" spice_model_name="INVTX1"/>
-         <pass_gate_logic spice_model_name="TGATE"/>
+         <input_buffer exist="on" circuit_model_name="INVTX1"/>
+         <output_buffer exist="on" circuit_model_name="INVTX1"/>
+         <pass_gate_logic circuit_model_name="TGATE"/>
          <port type="input" prefix="D" size="1"/>
          <port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
          <port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
          <port type="output" prefix="Q" size="1"/>
          <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
-      </spice_model>
-      <spice_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
+      </circuit_model>
+      <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
-        <lut_input_buffer exist="on" spice_model_name="buf4"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVTX1"/>
+        <lut_input_buffer exist="on" circuit_model_name="buf4"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="6"/>
         <port type="output" prefix="out" size="1"/>
         <port type="sram" prefix="sram" size="64"/>
-      </spice_model>
-      <spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v" >
+      </circuit_model>
+      <circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v" >
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVTX1"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="2"/>
-      </spice_model>
-      <spice_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v">
+      </circuit_model>
+      <circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVTX1"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="2"/>
-        <port type="bl" prefix="bl" size="1" default_val="0" inv_spice_model_name="INVTX1"/>
-        <port type="blb" prefix="blb" size="1" default_val="1" inv_spice_model_name="INVTX1"/>
-        <port type="wl" prefix="wl" size="1" default_val="0" inv_spice_model_name="INVTX1"/>
-      </spice_model>
-      <spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/io.v">
+        <port type="bl" prefix="bl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
+        <port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
+        <port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
+      </circuit_model>
+      <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/io.v">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVTX1"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVTX1"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="inout" prefix="pad" size="1"/>
-        <port type="sram" prefix="en" size="1" mode_select="true" spice_model_name="sram6T_blwl" default_val="1"/>
+        <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_blwl" default_val="1"/>
         <port type="input" prefix="outpad" size="1"/>
         <port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
         <port type="output" prefix="inpad" size="1"/>
-      </spice_model>
-    </module_spice_models>
+      </circuit_model>
+    </module_circuit_models>
   </spice_settings>
   <device>
     <sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
@@ -165,8 +194,8 @@
 
     <area grid_logic_tile_area="0"/> 
     <sram area="6">
-      <verilog organization="memory_bank" spice_model_name="sram6T_blwl"/>
-      <spice organization="standalone" spice_model_name="sram6T" />
+      <verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
+      <spice organization="standalone" circuit_model_name="sram6T" />
     </sram>
     <chan_width_distr>
       <io width="1.000000"/>
@@ -177,25 +206,25 @@
   </device>
 
   <cblocks>
-    <switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
+    <switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
     </switch>
   </cblocks>
   <switchlist>
-	<switch type="mux" name="sb_mux_L4" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
+	<switch type="mux" name="sb_mux_L4" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
     </switch>
   </switchlist>
   <segmentlist>
-    <segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
+    <segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
       <mux name="sb_mux_L4"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>
     </segment>
-    <segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
+    <segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
       <mux name="sb_mux_L4"/>
       <sb type="pattern">1 1 1</sb>
       <cb type="pattern">1 1 </cb>
     </segment>
-    <segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
+    <segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
       <mux name="sb_mux_L4"/>
       <sb type="pattern">1 1</sb>
       <cb type="pattern">1</cb>
@@ -209,7 +238,7 @@
 
       <!-- physical design description -->
       <mode name="io_phy" disabled_in_packing="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1" spice_model_name="iopad">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
         </pb_type>
@@ -224,7 +253,7 @@
       </mode>
 
       <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1" spice_model_name="iopad" mode_bits="1">
+        <pb_type name="inpad" blif_model=".input" num_pb="1" circuit_model_name="iopad" mode_bits="1">
           <output name="inpad" num_pins="1"/>
         </pb_type>
         <interconnect>
@@ -234,7 +263,7 @@
         </interconnect>
       </mode>
       <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1" spice_model_name="iopad" mode_bits="0">
+        <pb_type name="outpad" blif_model=".output" num_pb="1" circuit_model_name="iopad" mode_bits="0">
           <input name="outpad" num_pins="1"/>
         </pb_type>
         <interconnect>
@@ -270,13 +299,13 @@
 	
     <pb_type name="clb" area="53894" opin_to_cb="false">
       <pin_equivalence_auto_detect input_ports ="off" output_ports="off"/>
-      <input name="I" num_pins="20" equivalent="true"/> <!-- Each slice will have 6 inputs but we pass the output of a slice to the next one hence 4x(6-1)= 20 inputs (one input from the first slice is hanging)   -->
-      <output name="O" num_pins="1" equivalent="false"/>
+      <input name="I" num_pins="40" equivalent="true"/> <!-- Each slice will have 6 inputs but we pass the output of a slice to the next one hence 4x(6-1)= 20 inputs (one input from the first slice is hanging)   -->
+      <output name="O" num_pins="10" equivalent="false"/>
       <clock name="clk" num_pins="1"/>
       
 	  <!-- fle basically refers to a slice. In this example, we just want one of them but we 
 	  leave it in so that we know this architecture can and should be used -->
-      <pb_type name="fle" num_pb="4" idle_mode_name="n1_lut6" physical_mode_name="n1_lut6">
+      <pb_type name="fle" num_pb="10" idle_mode_name="n1_lut6" physical_mode_name="n1_lut6">
         <input name="in" num_pins="6"/>
         <output name="out" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
@@ -289,7 +318,7 @@
             <clock name="clk" num_pins="1"/> 
 
             <!-- Define LUT -->
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" spice_model_name="lut6">
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut6">
               <input name="in" num_pins="6" port_class="lut_in"/>
               <output name="out" num_pins="1" port_class="lut_out"/>
               <!-- LUT timing using delay matrix, one delay per input -->
@@ -304,7 +333,7 @@
             </pb_type>
 
             <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" spice_model_name="static_dff">
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
@@ -319,7 +348,7 @@
                 <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> 
               </direct>
               <direct name="direct3" input="ble6.clk" output="ff.clk"/>                    
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out" spice_model_name="mux_1level_tapbuf">
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out" circuit_model_name="mux_1level_tapbuf">
                 <delay_constant max="42.06e-12" in_port="lut6.out" out_port="ble6.out" />
                 <delay_constant max="42.06e-12" in_port="ff.Q" out_port="ble6.out" />
               </mux>
@@ -334,13 +363,13 @@
         <!-- 6-LUT mode definition end -->
       </pb_type>
       <interconnect>
-        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" spice_model_name="mux_2level">
-          <delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[3:0].in" />
-          <delay_constant max="53.44e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in" circuit_model_name="mux_2level">
+          <delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[9:0].in" />
+          <delay_constant max="53.44e-12" in_port="fle[9:0].out" out_port="fle[9:0].in" />
         </complete>
-        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
-		<complete/>
-		<direct name="clbouts1" input="fle[3:0].out" output="clb.O[3:0]"/>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+	</complete>
+	<direct name="clbouts1" input="fle[9:0].out" output="clb.O[9:0]"/>
       </interconnect>
 
       <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
@@ -365,4 +394,4 @@
   <clocks>
     <clock buffer_size="auto" C_wire="0"/>
   </clocks>
-</architecture>
\ No newline at end of file
+</architecture>