From ea4aee8cb257705e0844bd8a38d0416b844220fd Mon Sep 17 00:00:00 2001
From: Lalit Sharma <lsharma@quicklogic.com>
Date: Sun, 28 Feb 2021 22:07:23 -0800
Subject: [PATCH] For time-being yosys script running in no_adder mode.

---
 openfpga_flow/misc/qlf_yosys.ys                                 | 2 +-
 .../quicklogic_flow_example_script.openfpga                     | 2 +-
 openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys
index b5169287e..131bddd3c 100644
--- a/openfpga_flow/misc/qlf_yosys.ys
+++ b/openfpga_flow/misc/qlf_yosys.ys
@@ -2,5 +2,5 @@
 # Read verilog files
 ${READ_VERILOG_FILE}
 
-synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -top ${TOP_MODULE}
+synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -no_adder -top ${TOP_MODULE}
 
diff --git a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
index c9ae60b56..414fd8d47 100644
--- a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} 
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
index 38c047162..71529c23b 100644
--- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
@@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_vpr_circuit_format=eblif
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml