diff --git a/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
index cc0701390..afcf5d68d 100644
--- a/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
@@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+link_openfpga_arch --sort_gsb_chan_node_in_edges
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
index d3400b268..cf2b6ae51 100755
--- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
@@ -182,6 +182,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@
 run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@
 run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@
 run-task basic_tests/tile_organization/homo_fabric_tile_global_tile_clock $@
+run-task basic_tests/tile_organization/homo_fabric_tile_adder_chain $@
 
 echo -e "Testing global port definition from tiles";
 run-task basic_tests/global_tile_ports/global_tile_clock $@
diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile/config/task.conf
index c07a08d33..7fb9e0265 100644
--- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile/config/task.conf
@@ -9,7 +9,7 @@
 [GENERAL]
 run_engine=openfpga_shell
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
+power_analysis = false
 spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
@@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_full_testbench_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
 
 [ARCHITECTURES]
diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/task.conf
index 4df4c7014..94c457cf5 100644
--- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/task.conf
@@ -9,7 +9,7 @@
 [GENERAL]
 run_engine=openfpga_shell
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
+power_analysis = false
 spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
@@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_vpr_device=2x2
 openfpga_vpr_route_chan_width=20
 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/task.conf
index dc95f9ab2..9d306ecb5 100644
--- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/task.conf
@@ -9,7 +9,7 @@
 [GENERAL]
 run_engine=openfpga_shell
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
+power_analysis = false
 spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
@@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_vpr_device=4x4
 openfpga_vpr_route_chan_width=20
 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/task.conf
new file mode 100644
index 000000000..077f1b560
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/task.conf
@@ -0,0 +1,45 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_vpr_device=auto
+openfpga_vpr_route_chan_width=20
+openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v
+bench_yosys_adder_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+# Benchmark information
+bench0_top = adder_8
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/tile_config.xml
new file mode 100644
index 000000000..1a1f3f6e8
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/tile_config.xml
@@ -0,0 +1 @@
+<tiles style="top_left"/>
diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/task.conf
index b9950dab2..3e7e3f542 100644
--- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/task.conf
@@ -9,7 +9,7 @@
 [GENERAL]
 run_engine=openfpga_shell
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
+power_analysis = false
 spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
@@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_vpr_device=auto
 openfpga_vpr_route_chan_width=20
 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml