riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[engine] update vtr and enable more debugging info

This commit is contained in:
tangxifan 2022-08-27 19:12:43 -07:00
parent 83c233022f
commit e9d6e7e38a
5 changed files with 11 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga/src/annotation/openfpga_annotate_routing.cpp
View File

@ -143,7 +143,7 @@ void annotate_rr_node_previous_nodes(const DeviceContext& device_ctx,
/* Only update mapped nodes */
if (prev_node) {
vpr_routing_annotation.set_rr_node_prev_node(rr_node, prev_node);
vpr_routing_annotation.set_rr_node_prev_node(device_ctx.rr_graph, rr_node, prev_node);
counter++;
}

9
openfpga/src/annotation/vpr_routing_annotation.cpp
View File

@ -52,15 +52,18 @@ void VprRoutingAnnotation::set_rr_node_net(const RRNodeId& rr_node,
rr_node_nets_[rr_node] = net_id;
}
void VprRoutingAnnotation::set_rr_node_prev_node(const RRNodeId& rr_node,
void VprRoutingAnnotation::set_rr_node_prev_node(const RRGraphView& rr_graph,
const RRNodeId& rr_node,
const RRNodeId& prev_node) {
/* Ensure that the node_id is in the list */
VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size());
/* Warn any override attempt */
if ( (RRNodeId::INVALID() != rr_node_prev_nodes_[rr_node])
&& (prev_node != rr_node_prev_nodes_[rr_node])) {
VTR_LOG_WARN("Override the previous node '%ld' by previous node '%ld' for node '%ld' with in routing context annotation!\n",
size_t(rr_node_prev_nodes_[rr_node]), size_t(prev_node), size_t(rr_node));
VTR_LOG_WARN("Override the previous node '%s' by previous node '%s' for node '%s' with in routing context annotation!\n",
rr_graph.node_coordinate_to_string(rr_node_prev_nodes_[rr_node]).c_str(),
rr_graph.node_coordinate_to_string(prev_node).c_str(),
rr_graph.node_coordinate_to_string(rr_node).c_str());
}
rr_node_prev_nodes_[rr_node] = prev_node;

3
openfpga/src/annotation/vpr_routing_annotation.h
View File

@ -33,7 +33,8 @@ class VprRoutingAnnotation {
void init(const RRGraphView& rr_graph);
void set_rr_node_net(const RRNodeId& rr_node,
const ClusterNetId& net_id);
void set_rr_node_prev_node(const RRNodeId& rr_node,
void set_rr_node_prev_node(const RRGraphView& rr_graph,
const RRNodeId& rr_node,
const RRNodeId& prev_node);
private: /* Internal data */
/* Clustered net ids mapped to each rr_node */

2
openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
View File

@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT}
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit f0cf714da1048671841b4bbfa0c457e2cd36ea9e
Subproject commit b5d4f8ca41bc65ce35eae6ef3ec8ce1bf7f6a5a3