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[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs

This commit is contained in:
tangxifan 2023-01-18 18:31:36 -08:00
parent acc905fa11
commit e974e5ddf7
4 changed files with 4 additions and 1 deletions
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2
openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
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@ -1,6 +1,6 @@
# Run VPR for the 'and' design # Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml #--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

1
openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf
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@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
openfpga_vpr_device_layout=2x2
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml

1
openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/task.conf
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@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
openfpga_vpr_device_layout=2x2
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml

1
openfpga_flow/tasks/basic_tests/k4_series/k4n4_rst_gen/config/task.conf
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@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
openfpga_vpr_device_layout=2x2
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localRstGen_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localRstGen_40nm.xml