From 6480b06a2dd851f64ec66b8237f54359b38f4b33 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 11:01:53 -0600 Subject: [PATCH 001/114] [OpenFPGA tool] Remove out-of-data test blif, architecture and scripts --- openfpga/test_blif/and.act | 3 - openfpga/test_blif/and.blif | 8 - openfpga/test_blif/and.v | 14 - openfpga/test_blif/and_latch.act | 6 - openfpga/test_blif/and_latch.blif | 14 - openfpga/test_blif/and_latch.v | 23 - .../k6_N10_40nm_openfpga.xml | 228 ----- .../k6_frac_N10_40nm_openfpga.xml | 260 ------ .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 285 ------- ...c_N10_adder_chain_mem16K_40nm_openfpga.xml | 302 ------- ...0_adder_chain_mem16K_aib_40nm_openfpga.xml | 314 ------- ...c_N10_adder_column_chain_40nm_openfpga.xml | 285 ------- ...N10_adder_register_chain_40nm_openfpga.xml | 288 ------- ...dder_register_scan_chain_40nm_openfpga.xml | 294 ------- .../k6_frac_N10_spyio_40nm_openfpga.xml | 264 ------ .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 252 ------ .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 251 ------ openfpga/test_script/and_k6_frac.openfpga | 62 -- .../and_k6_frac_adder_chain.openfpga | 62 -- .../and_k6_frac_adder_chain_mem16K.openfpga | 62 -- .../test_script/and_k6_frac_tileable.openfpga | 59 -- .../and_k6_frac_tileable_adder_chain.openfpga | 64 -- ..._frac_tileable_adder_chain_mem16K.openfpga | 62 -- ...c_tileable_adder_chain_mem16K_aib.openfpga | 62 -- ...er_chain_mem16K_multi_io_capacity.openfpga | 62 -- ...ble_adder_chain_mem16K_reduced_io.openfpga | 62 -- ..._tileable_adder_chain_wide_mem16K.openfpga | 62 -- ..._frac_tileable_adder_column_chain.openfpga | 62 -- ...ileable_adder_register_scan_chain.openfpga | 63 -- .../and_k6_frac_tileable_spyio.openfpga | 59 -- ...and_k6_frac_tileable_stdcell_mux2.openfpga | 59 -- ...e_thru_channel_adder_chain_mem16K.openfpga | 62 -- .../and_k6_frac_tileable_tree_mux.openfpga | 59 -- .../test_script/and_latch_k6_frac.openfpga | 59 -- .../and_latch_k6_frac_tileable.openfpga | 59 -- ...atch_k6_frac_tileable_adder_chain.openfpga | 62 -- ..._frac_tileable_adder_chain_mem16K.openfpga | 62 -- openfpga/test_vpr_arch/k6_N10_40nm.xml | 299 ------- .../test_vpr_arch/k6_N10_tileable_40nm.xml | 299 ------- openfpga/test_vpr_arch/k6_frac_N10_40nm.xml | 441 ---------- .../k6_frac_N10_adder_chain_40nm.xml | 644 -------------- .../k6_frac_N10_adder_chain_mem16K_40nm.xml | 739 ---------------- .../k6_frac_N10_tileable_40nm.xml | 441 ---------- .../k6_frac_N10_tileable_adder_chain_40nm.xml | 644 -------------- ...c_N10_tileable_adder_chain_mem16K_40nm.xml | 739 ---------------- ...0_tileable_adder_chain_mem16K_aib_40nm.xml | 805 ------------------ ...er_chain_mem16K_multi_io_capacity_40nm.xml | 773 ----------------- ...ble_adder_chain_mem16K_reduced_io_40nm.xml | 742 ---------------- ..._tileable_adder_chain_wide_mem16K_40nm.xml | 739 ---------------- ...N10_tileable_adder_register_chain_40nm.xml | 696 --------------- ...ileable_adder_register_scan_chain_40nm.xml | 734 ---------------- ...e_thru_channel_adder_chain_mem16K_40nm.xml | 734 ---------------- 52 files changed, 13785 deletions(-) delete mode 100644 openfpga/test_blif/and.act delete mode 100644 openfpga/test_blif/and.blif delete mode 100644 openfpga/test_blif/and.v delete mode 100644 openfpga/test_blif/and_latch.act delete mode 100644 openfpga/test_blif/and_latch.blif delete mode 100644 openfpga/test_blif/and_latch.v delete mode 100644 openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml delete mode 100644 openfpga/test_script/and_k6_frac.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_adder_chain.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_spyio.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga delete mode 100644 openfpga/test_script/and_latch_k6_frac.openfpga delete mode 100644 openfpga/test_script/and_latch_k6_frac_tileable.openfpga delete mode 100644 openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga delete mode 100644 openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga delete mode 100644 openfpga/test_vpr_arch/k6_N10_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml diff --git a/openfpga/test_blif/and.act b/openfpga/test_blif/and.act deleted file mode 100644 index 0f77bc6b3..000000000 --- a/openfpga/test_blif/and.act +++ /dev/null @@ -1,3 +0,0 @@ -a 0.5 0.5 -b 0.5 0.5 -c 0.25 0.25 diff --git a/openfpga/test_blif/and.blif b/openfpga/test_blif/and.blif deleted file mode 100644 index 67d978741..000000000 --- a/openfpga/test_blif/and.blif +++ /dev/null @@ -1,8 +0,0 @@ -.model top -.inputs a b -.outputs c - -.names a b c -11 1 - -.end diff --git a/openfpga/test_blif/and.v b/openfpga/test_blif/and.v deleted file mode 100644 index 876f1c6fe..000000000 --- a/openfpga/test_blif/and.v +++ /dev/null @@ -1,14 +0,0 @@ -`timescale 1ns / 1ps - -module top( - a, - b, - c); - -input wire a; -input wire b; -output wire c; - -assign c = a & b; - -endmodule diff --git a/openfpga/test_blif/and_latch.act b/openfpga/test_blif/and_latch.act deleted file mode 100644 index 61bbe1fe8..000000000 --- a/openfpga/test_blif/and_latch.act +++ /dev/null @@ -1,6 +0,0 @@ -a 0.492800 0.201000 -b 0.502000 0.197200 -clk 0.500000 2.000000 -d 0.240200 0.171200 -c 0.240200 0.044100 -n1 0.240200 0.044100 diff --git a/openfpga/test_blif/and_latch.blif b/openfpga/test_blif/and_latch.blif deleted file mode 100644 index dbd863d9c..000000000 --- a/openfpga/test_blif/and_latch.blif +++ /dev/null @@ -1,14 +0,0 @@ -# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020 -.model top -.inputs a b clk -.outputs c d - -.latch n1 d re clk 0 - -.names a b c -11 1 - -.names c n1 -1 1 - -.end diff --git a/openfpga/test_blif/and_latch.v b/openfpga/test_blif/and_latch.v deleted file mode 100644 index 893cdf7a4..000000000 --- a/openfpga/test_blif/and_latch.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps - -module top( - clk, - a, - b, - c, - d); - -input wire clk; - -input wire a; -input wire b; -output wire c; -output reg d; - -assign c = a & b; - -always @(posedge clk) begin - d <= c; -end - -endmodule diff --git a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml deleted file mode 100644 index de0602e1e..000000000 --- a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml +++ /dev/null @@ -1,228 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml deleted file mode 100644 index 51e250a8a..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ /dev/null @@ -1,260 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml deleted file mode 100644 index cb145e06d..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ /dev/null @@ -1,302 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml deleted file mode 100644 index 621847439..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ /dev/null @@ -1,294 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml deleted file mode 100644 index 159214507..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ /dev/null @@ -1,264 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml deleted file mode 100644 index 59f493a13..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ /dev/null @@ -1,252 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml deleted file mode 100644 index d04318510..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ /dev/null @@ -1,251 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga deleted file mode 100644 index 90f20b2b7..000000000 --- a/openfpga/test_script/and_k6_frac.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges --verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/and.bitstream - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --hierarchical --file /var/tmp/xtang/openfpga_test_src/SDC_hie -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga deleted file mode 100644 index 3cdebb2b1..000000000 --- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga deleted file mode 100644 index 34ec11181..000000000 --- a/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable.openfpga b/openfpga/test_script/and_k6_frac_tileable.openfpga deleted file mode 100644 index 0731e6543..000000000 --- a/openfpga/test_script/and_k6_frac_tileable.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga deleted file mode 100644 index 05ea64bce..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga +++ /dev/null @@ -1,64 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist - write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC \ - --explicit_port_mapping --include_timing --include_signal_init \ - --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga deleted file mode 100644 index ed0d8cc5a..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga deleted file mode 100644 index 492c70ea6..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga deleted file mode 100644 index 29830f1db..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga deleted file mode 100644 index 22a658a73..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga deleted file mode 100644 index 466c3bcd0..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga deleted file mode 100644 index fbcdda185..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga deleted file mode 100644 index 864fea78d..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga +++ /dev/null @@ -1,63 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc \ - --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga b/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga deleted file mode 100644 index 7b9fa407c..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga b/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga deleted file mode 100644 index 04ff99d8c..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga deleted file mode 100644 index 5b1177586..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga b/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga deleted file mode 100644 index 95cd2a3c3..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac.openfpga b/openfpga/test_script/and_latch_k6_frac.openfpga deleted file mode 100644 index b41ac4450..000000000 --- a/openfpga/test_script/and_latch_k6_frac.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and_latch' design -vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack --verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable.openfpga deleted file mode 100644 index c89174d2d..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and_latch' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack --verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga deleted file mode 100644 index ef49426d0..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga deleted file mode 100644 index 87c69c880..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_vpr_arch/k6_N10_40nm.xml b/openfpga/test_vpr_arch/k6_N10_40nm.xml deleted file mode 100644 index 83b4948a8..000000000 --- a/openfpga/test_vpr_arch/k6_N10_40nm.xml +++ /dev/null @@ -1,299 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml deleted file mode 100644 index ceacbb3f2..000000000 --- a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml +++ /dev/null @@ -1,299 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml deleted file mode 100644 index 8476a5155..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml +++ /dev/null @@ -1,441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml deleted file mode 100644 index e0d7ce812..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml deleted file mode 100644 index 146a170e5..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml +++ /dev/null @@ -1,441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml deleted file mode 100644 index 8f1dfd10e..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml +++ /dev/null @@ -1,644 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml deleted file mode 100644 index 8254a0583..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml deleted file mode 100644 index 35eedb327..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml +++ /dev/null @@ -1,805 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - aib.tx_clk aib.tx_data aib.rx_clk aib.rx_data - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - 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- - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml deleted file mode 100644 index d23c34960..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml +++ /dev/null @@ -1,773 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io_top.outpad io_top.inpad - - - - - - - - - - - io_right.outpad io_right.inpad - - - - - - - - - - - io_bottom.outpad io_bottom.inpad - - - - - - - - - - - io_left.outpad io_left.inpad - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml deleted file mode 100644 index bb06c5f39..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml +++ /dev/null @@ -1,742 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - 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io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin clb.regin - clb.O[9:0] clb.I[19:0] - clb.cout clb.regout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml deleted file mode 100644 index f83919c7c..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml +++ /dev/null @@ -1,734 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin clb.regin clb.scin - clb.O[9:0] clb.I[19:0] - clb.cout clb.regout clb.scout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml deleted file mode 100644 index 7e4cf8e7a..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,734 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - From 951a47b19cb34fabbf215365bcb4ddff2434f1b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:05:39 -0600 Subject: [PATCH 002/114] [Architecture] Add k4 series architecture using pattern-based local routing --- ...N5_tileable_pattern_local_routing_40nm.xml | 355 ++++++++++++++++++ 1 file changed, 355 insertions(+) create mode 100644 openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml diff --git a/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml new file mode 100644 index 000000000..29c20f59a --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml @@ -0,0 +1,355 @@ + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 1aab691e9d795b4e40408df5aed0d1c73e42b046 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:06:16 -0600 Subject: [PATCH 003/114] [Architecture] Add openfpga architecture using pattern based local routing --- ...tern_local_routing_40nm_frame_openfpga.xml | 213 ++++++++++++++++++ 1 file changed, 213 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml new file mode 100644 index 000000000..2916fb658 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -0,0 +1,213 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 33506958061eaa6538f27b01e93775a5fe9b2977 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:06:47 -0600 Subject: [PATCH 004/114] [Regression test] Add test case for pattern based local routing architecture --- .../config/task.conf | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf new file mode 100644 index 000000000..2a94ee552 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif + +[SYNTHESIS_PARAM] +bench0_top = and2_latch +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 6ed05d380be1b807623298a713e713a167f4f709 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:08:01 -0600 Subject: [PATCH 005/114] [Regression Test] Deploy pattern based local routing test case to CI --- .travis/basic_reg_test.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 85cb514e4..515dc3b1d 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -51,5 +51,7 @@ echo -e "Testing K4N4 with multiple lengths of routing segments"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs echo -e "Testing K4N4 with 32-bit fracturable multiplier"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs +echo -e "Testing K4N5 with pattern based local routing"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs end_section "OpenFPGA.TaskTun" From c92cf71891989fcdbce2c9e5c9907d29886048a7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:46:41 -0600 Subject: [PATCH 006/114] [Regression Test] Add a new template script for fixed device support --- ...e_route_chan_width_example_script.openfpga | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga new file mode 100644 index 000000000..5bac56d00 --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From 149d5b20bd7d27a340570419721bd75ba042073f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:47:11 -0600 Subject: [PATCH 007/114] [Regression Test] Add test case for fixed device support --- .../fixed_device_support/config/task.conf | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf new file mode 100644 index 000000000..364962203 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 5c62bafa7ff780215d8b5ed535281c50320dcb7f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:48:45 -0600 Subject: [PATCH 008/114] [Regression Test] Deploy the fix device test case to CI --- .travis/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 515dc3b1d..04ed06fe2 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -29,6 +29,9 @@ echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FP python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs +echo -e "Testing fixed device layout and routing channel width"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs + echo -e "Testing fabric Verilog generation only"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs From b242ab79bd4125bd5cb2742c25b7a373a5814901 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:19:02 -0600 Subject: [PATCH 009/114] [OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset --- .../VerilogNetlists/config_latch_neg_rst.v | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_rst.v diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v new file mode 100644 index 000000000..917bf88ce --- /dev/null +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v @@ -0,0 +1,39 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Function : A Configurable Latch where data storage +// can be updated at rising clock edge +// when wl is enabled +// Reset is active low +// Coder : Xifan TANG +//----------------------------------------------------- +module config_latch ( + input resetb, // Reset input + input clk, // Clock Input + input wl, // Data Enable + input bl, // Data Input + output Q, // Q output + output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge clk or posedge resetb) begin + if (~resetb) begin + q_reg <= 1'b0; + end else if (1'b1 == wl) begin + q_reg <= bl; + end +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule From 893859be370c45a149e4bfc9af9252cfefe3b07e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:21:00 -0600 Subject: [PATCH 010/114] [Architecture] Add openfpga architecture using active-low configurable latch --- .../k4_N4_40nm_frame_resetb_openfpga.xml | 200 ++++++++++++++++++ 1 file changed, 200 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml new file mode 100644 index 000000000..27df66764 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From a94c2655c2863e194785fe75d5e3ebaeb7616e75 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:21:30 -0600 Subject: [PATCH 011/114] [Architecture] Patch Verilog HDL for configurable latch --- openfpga_flow/VerilogNetlists/config_latch.v | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v index 6cbe5657e..ec52510d6 100644 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ b/openfpga_flow/VerilogNetlists/config_latch.v @@ -4,6 +4,7 @@ // Function : A Configurable Latch where data storage // can be updated at rising clock edge // when wl is enabled +// Reset is active high // Coder : Xifan TANG //----------------------------------------------------- module config_latch ( From f23c25e1234b99ea88bf95a2b520a78bf207d77d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:25:17 -0600 Subject: [PATCH 012/114] [Regression Test] Add test case for configurable latch with active-low reset --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf new file mode 100644 index 000000000..755b9ec94 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From a3c982a83f896061b008865b689c5c5080897e95 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:27:16 -0600 Subject: [PATCH 013/114] [Architecture] Patch the openfpga architecture using active-low configurable latch --- .../openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml index 27df66764..efefbf581 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml @@ -146,7 +146,7 @@ - + From f0d31f50f4b5df23e6e7f3f366e5f0abd1406251 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:28:36 -0600 Subject: [PATCH 014/114] [Regression Test] Deploy active-low configurable latch test case to CI --- .travis/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 04ed06fe2..f61ddb698 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -19,6 +19,7 @@ echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs From 1a2c66f07de63cfcc1a827200d5a51ae1827fdf3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:34:49 -0600 Subject: [PATCH 015/114] [Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell --- .../k4_N4_40nm_frame_sram_openfpga.xml | 198 ++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml new file mode 100644 index 000000000..a21f2a520 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml @@ -0,0 +1,198 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From ad385c6d69de01d16ee5de736f8cc3a87cf43d7f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:39:36 -0600 Subject: [PATCH 016/114] [Regression Test] Add test case for using SRAM cell in frame-based configuration --- .../configuration_frame_sram/config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf new file mode 100644 index 000000000..1e7322490 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 092ada39f4a77b85f2f4eff69ddfa71ec34a88ed Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:49:30 -0600 Subject: [PATCH 017/114] [Architecture] Add Verilog HDL for DFF with write enable --- openfpga_flow/VerilogNetlists/ff_en.v | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/ff_en.v diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v new file mode 100644 index 000000000..fa0ed47d4 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/ff_en.v @@ -0,0 +1,33 @@ +//----------------------------------------------------- +// Design Name : D-type Flip-flop with Write Enable +// File Name : ff_en.v +// Function : D flip-flop with asyn reset and set +// Coder : Xifan TANG +//----------------------------------------------------- +module DFF_EN ( +/* Global ports go first */ +input SET, // set input +input RST, // Reset input +input WE, // Write Enable +input CK, // Clock Input +/* Local ports follow */ +input D, // Data Input +output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RESET) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (WE) begin + q_reg <= D; +end + +// Wire q_reg to Q +assign Q = q_reg; + +endmodule //End Of Module From 645db17168268a300e78d57a26191c54a16c78a7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:52:59 -0600 Subject: [PATCH 018/114] [Architecture] Patch DFF Verilog HDL --- openfpga_flow/VerilogNetlists/ff_en.v | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v index fa0ed47d4..c7a063ce7 100644 --- a/openfpga_flow/VerilogNetlists/ff_en.v +++ b/openfpga_flow/VerilogNetlists/ff_en.v @@ -13,6 +13,7 @@ input CK, // Clock Input /* Local ports follow */ input D, // Data Input output Q // Q output +output QB // QB output ); //------------Internal Variables-------- reg q_reg; @@ -27,7 +28,13 @@ end else if (WE) begin q_reg <= D; end +`ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q assign Q = q_reg; +assign QB = ~q_reg; +`else +assign Q = 1'bZ; +assign QB = !Q; +`endif endmodule //End Of Module From 906191e9310faeb9d3c87613c1f306f9c137f0d2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:58:13 -0600 Subject: [PATCH 019/114] [Architecture] Use strict latch Verilog HDL in frame-based procotol --- openfpga_flow/VerilogNetlists/config_latch.v | 6 ++---- .../VerilogNetlists/config_latch_neg_rst.v | 6 ++---- ...xml => k4_N4_40nm_frame_ccff_openfpga.xml} | 19 +++++++++++-------- .../k4_N4_40nm_frame_openfpga.xml | 1 - .../k4_N4_40nm_frame_resetb_openfpga.xml | 1 - .../k4_N4_40nm_powergate_frame_openfpga.xml | 1 - ...4_no_local_routing_40nm_frame_openfpga.xml | 1 - ...tern_local_routing_40nm_frame_openfpga.xml | 1 - ..._adder_chain_mem1K_40nm_frame_openfpga.xml | 1 - ...r_chain_mem1K_L124_40nm_frame_openfpga.xml | 1 - ...n_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 1 - .../config/task.conf | 2 +- 12 files changed, 16 insertions(+), 25 deletions(-) rename openfpga_flow/openfpga_arch/{k4_N4_40nm_frame_sram_openfpga.xml => k4_N4_40nm_frame_ccff_openfpga.xml} (90%) rename openfpga_flow/tasks/basic_tests/full_testbench/{configuration_frame_sram => configuration_frame_ccff}/config/task.conf (97%) diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v index ec52510d6..e0732ac47 100644 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ b/openfpga_flow/VerilogNetlists/config_latch.v @@ -2,14 +2,12 @@ // Design Name : config_latch // File Name : config_latch.v // Function : A Configurable Latch where data storage -// can be updated at rising clock edge -// when wl is enabled +// can be updated when wl is enabled // Reset is active high // Coder : Xifan TANG //----------------------------------------------------- module config_latch ( input reset, // Reset input - input clk, // Clock Input input wl, // Data Enable input bl, // Data Input output Q, // Q output @@ -19,7 +17,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset) begin +always @ ( posedge reset) begin if (reset) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v index 917bf88ce..836012259 100644 --- a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v @@ -2,14 +2,12 @@ // Design Name : config_latch // File Name : config_latch.v // Function : A Configurable Latch where data storage -// can be updated at rising clock edge -// when wl is enabled +// can be updated when wl is enabled // Reset is active low // Coder : Xifan TANG //----------------------------------------------------- module config_latch ( input resetb, // Reset input - input clk, // Clock Input input wl, // Data Enable input bl, // Data Input output Q, // Q output @@ -19,7 +17,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge clk or posedge resetb) begin +always @ ( posedge resetb) begin if (~resetb) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml similarity index 90% rename from openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml rename to openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index a21f2a520..48fc4157c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -145,28 +145,31 @@ - + + - - - - - + + + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index b89a23644..b370c1f3d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -155,7 +155,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml index efefbf581..f1894c9a5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml @@ -155,7 +155,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index bf96e1aa0..402331b6f 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -161,7 +161,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index 9ba39b3ce..c579e4f49 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -155,7 +155,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index 2916fb658..7ca1ba958 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -155,7 +155,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 508ceab90..45d660d95 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -173,7 +173,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 8bba60744..6a3aba09e 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -173,7 +173,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index eb5e3c659..0cd86c659 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -173,7 +173,6 @@ - diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf similarity index 97% rename from openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf rename to openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf index 1e7322490..399be683b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] From ebb866d04a55c200f3b69a90ed709ca5fbc0c008 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:04:14 -0600 Subject: [PATCH 020/114] [Architecture] Patch frame based using ccff --- openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 48fc4157c..286b20f38 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,7 +146,7 @@ - + From 341a7578310b7e9eb71f50e91ea1f6205e1bd2f3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:05:55 -0600 Subject: [PATCH 021/114] [Regression Test] Deploy configuration frame using ccff test case to CI --- .travis/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index f61ddb698..efca9e376 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -19,6 +19,7 @@ echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; From 9adeb550dc60d25aa9e9caa9b4ab9d996200c067 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:28:00 -0600 Subject: [PATCH 022/114] [OpenFPGA Tool] Bug fix in fabric builder --- openfpga/src/fabric/build_memory_modules.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp index b9b83508a..32d1c93b2 100644 --- a/openfpga/src/fabric/build_memory_modules.cpp +++ b/openfpga/src/fabric/build_memory_modules.cpp @@ -636,13 +636,13 @@ void build_frame_memory_module(ModuleManager& module_manager, module_manager.add_configurable_child(mem_module, sram_mem_module, sram_instance); /* Wire data_in port to SRAM BL port */ - ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_bl_ports[0])); + ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_bl_ports[0])); add_module_bus_nets(module_manager, mem_module, mem_module, 0, mem_data_port, sram_mem_module, sram_instance, sram_bl_port); /* Wire decoder data_out port to sram WL ports */ - ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_wl_ports[0])); + ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_wl_ports[0])); ModulePortId decoder_data_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); ModuleNetId wl_net = module_manager.create_module_net(mem_module); /* Source node of the input net is the input of memory module */ From 1864b080a23ad10a26ab2e1eb44933904757300d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:28:45 -0600 Subject: [PATCH 023/114] [Architecture] Bug fix in configurable latch Verilog HDL --- openfpga_flow/VerilogNetlists/config_latch.v | 2 +- openfpga_flow/VerilogNetlists/ff_en.v | 4 ++-- .../openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v index e0732ac47..e08ea2153 100644 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ b/openfpga_flow/VerilogNetlists/config_latch.v @@ -17,7 +17,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge reset) begin +always @ (reset or bl or wl) begin if (reset) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v index c7a063ce7..11b657a9f 100644 --- a/openfpga_flow/VerilogNetlists/ff_en.v +++ b/openfpga_flow/VerilogNetlists/ff_en.v @@ -12,7 +12,7 @@ input WE, // Write Enable input CK, // Clock Input /* Local ports follow */ input D, // Data Input -output Q // Q output +output Q, // Q output output QB // QB output ); //------------Internal Variables-------- @@ -20,7 +20,7 @@ reg q_reg; //-------------Code Starts Here--------- always @ ( posedge CK or posedge RST or posedge SET) -if (RESET) begin +if (RST) begin q_reg <= 1'b0; end else if (SET) begin q_reg <= 1'b1; diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 286b20f38..7ccada510 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,7 +146,7 @@ - + From 129caea38cb93afe977358a7a065cdb1ff87ec6f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:30:48 -0600 Subject: [PATCH 024/114] [Architecture] Patch configurable latch Verilog HDL with resetb --- openfpga_flow/VerilogNetlists/config_latch_neg_rst.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v index 836012259..cb24769d5 100644 --- a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v @@ -17,7 +17,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge resetb) begin +always @ (resetb or wl or bl) begin if (~resetb) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin From ad881ea4dc1a43404187ba4c6159ae35d8ea324b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:59:25 -0600 Subject: [PATCH 025/114] [OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank --- .../src/fpga_verilog/verilog_top_testbench.cpp | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 27f714957..8a5ec3721 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -136,15 +136,15 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED programming clock to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----")); + /* Wire the INVERTED configuration done signal to the enable signal !!! */ + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + print_verilog_wire_connection(fp, en_port, config_done_port, true); } @@ -173,15 +173,16 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED programming clock to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----")); + /* Wire the INVERTED configuration done signal to the enable signal !!! */ + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + print_verilog_wire_connection(fp, en_port, config_done_port, true); + } /******************************************************************** From 437ef544313ec88439eff88d6a35911cd63f128f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 19:20:41 -0600 Subject: [PATCH 026/114] [Regression Test] Bug fix for CI --- .travis/basic_reg_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index efca9e376..e0ee4685b 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -19,7 +19,7 @@ echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame_ccff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; From 8e4e66038a532867722bc71c034eba87d0a82112 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 19:32:48 -0600 Subject: [PATCH 027/114] [Architecture] Bug fix for standalone memory --- openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml | 1 - 1 file changed, 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 035732d35..0781e6caa 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -155,7 +155,6 @@ - From 064678fe32c455222acd19763036b2b97f778cd9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:27:52 -0600 Subject: [PATCH 028/114] [OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol --- .../libarchopenfpga/src/circuit_library.cpp | 15 ++++++ .../libarchopenfpga/src/circuit_library.h | 23 +++++---- .../src/read_xml_circuit_library.cpp | 3 ++ .../src/write_xml_circuit_library.cpp | 4 ++ openfpga/src/base/openfpga_verilog.cpp | 2 +- openfpga/src/fpga_verilog/verilog_api.cpp | 6 +-- openfpga/src/fpga_verilog/verilog_api.h | 3 +- .../fpga_verilog/verilog_top_testbench.cpp | 51 ++++++++++++++----- .../src/fpga_verilog/verilog_top_testbench.h | 3 +- 9 files changed, 81 insertions(+), 29 deletions(-) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index bbf9c50c4..1bc6e840e 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -942,6 +942,12 @@ bool CircuitLibrary::port_is_config_enable(const CircuitPortId& circuit_port_id) return port_is_config_enable_[circuit_port_id]; } +bool CircuitLibrary::port_is_edge_triggered(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_edge_triggered_[circuit_port_id]; +} + /* Return a flag if the port is used during programming a FPGA in a circuit model */ bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ @@ -1493,6 +1499,15 @@ void CircuitLibrary::set_port_is_config_enable(const CircuitPortId& circuit_port return; } +/* Set the is_edge_triggered for a port of a circuit model */ +void CircuitLibrary::set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, + const bool& is_edge_triggered) { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_edge_triggered_[circuit_port_id] = is_edge_triggered; + return; +} + /* Set the is_prog for a port of a circuit model */ void CircuitLibrary::set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog) { diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index bd082f738..f4b742a27 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -91,15 +91,16 @@ * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches - * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 13. port_tri_state_model_name: the name of circuit model linked to tri-state the port - * 14. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port - * 15. port_inv_model_names_: the name of inverter circuit model linked to the port - * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port - * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port - * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used - * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used - * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * 12. port_is_edge_triggered: specify if this port is triggerd by edges like the clock signal of a D-type flip-flop + * 13. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 14. port_tri_state_model_name: the name of circuit model linked to tri-state the port + * 15. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port + * 16. port_inv_model_names_: the name of inverter circuit model linked to the port + * 17. port_inv_model_ids_: the Id of inverter circuit model linked to the port + * 18. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 19. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 20. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 21. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains * * ------ Delay information ------ * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge @@ -284,6 +285,7 @@ class CircuitLibrary { bool port_is_reset(const CircuitPortId& circuit_port_id) const; bool port_is_set(const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; + bool port_is_edge_triggered(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; std::vector port_lut_output_mask(const CircuitPortId& circuit_port_id) const; @@ -364,6 +366,8 @@ class CircuitLibrary { const bool& is_set); void set_port_is_config_enable(const CircuitPortId& circuit_port_id, const bool& is_config_enable); + void set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, + const bool& is_edge_triggered); void set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog); void set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, @@ -550,6 +554,7 @@ class CircuitLibrary { vtr::vector port_is_reset_; vtr::vector port_is_set_; vtr::vector port_is_config_enable_; + vtr::vector port_is_edge_triggered_; vtr::vector port_is_prog_; vtr::vector port_tri_state_model_names_; vtr::vector port_tri_state_model_ids_; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index 36e837814..4136b0463 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -564,6 +564,9 @@ void read_xml_circuit_port(pugi::xml_node& xml_port, /* Identify if the port is to enable programming for FPGAs, by default it is NOT */ circuit_lib.set_port_is_config_enable(port, get_attribute(xml_port, "is_config_enable", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + /* Identify if the port is to triggered by edges, by default it is NOT */ + circuit_lib.set_port_is_edge_triggered(port, get_attribute(xml_port, "is_edge_triggered", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + /* Find the name of circuit model that this port is linked to */ circuit_lib.set_port_tri_state_model_name(port, get_attribute(xml_port, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string()); diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp index b141b0fe2..9165725e2 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -207,6 +207,10 @@ void write_xml_circuit_port(std::fstream& fp, write_xml_attribute(fp, "is_config_enable", "true"); } + if (true == circuit_lib.port_is_edge_triggered(port)) { + write_xml_attribute(fp, "is_edge_triggered", "true"); + } + /* Output the name of circuit model that this port is linked to */ if (!circuit_lib.port_tri_state_model_name(port).empty()) { write_xml_attribute(fp, "circuit_model_name", circuit_lib.port_tri_state_model_name(port).c_str()); diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 58ea20f2e..0c6367fc5 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -97,7 +97,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.simulation_setting(), - openfpga_ctx.arch().config_protocol.type(), + openfpga_ctx.arch().config_protocol, options); /* TODO: should identify the error code from internal function execution */ diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index 940d78953..fe5b76196 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -156,7 +156,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, const VprNetlistAnnotation &netlist_annotation, const CircuitLibrary &circuit_lib, const SimulationSetting &simulation_setting, - const e_config_protocol_type &config_protocol_type, + const ConfigProtocol &config_protocol, const VerilogTestbenchOption &options) { vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for FPGA fabric\n"); @@ -205,7 +205,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream, - config_protocol_type, + config_protocol, circuit_lib, global_ports, atom_ctx, place_ctx, io_location_map, netlist_annotation, @@ -225,7 +225,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, src_dir_path, atom_ctx, place_ctx, io_location_map, module_manager, - config_protocol_type, + config_protocol.type(), bitstream_manager.num_bits(), simulation_setting.num_clock_cycles(), simulation_setting.programming_clock_frequency(), diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h index 94fbf3a29..1af656d7d 100644 --- a/openfpga/src/fpga_verilog/verilog_api.h +++ b/openfpga/src/fpga_verilog/verilog_api.h @@ -10,6 +10,7 @@ #include "mux_library.h" #include "decoder_library.h" #include "circuit_library.h" +#include "config_protocol.h" #include "vpr_context.h" #include "vpr_device_annotation.h" #include "device_rr_gsb.h" @@ -49,7 +50,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager, const VprNetlistAnnotation& netlist_annotation, const CircuitLibrary& circuit_lib, const SimulationSetting& simulation_parameters, - const e_config_protocol_type& config_protocol_type, + const ConfigProtocol& config_protocol, const VerilogTestbenchOption& options); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 8a5ec3721..763f7800e 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -153,6 +153,8 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, + const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { /* Validate the file stream */ @@ -174,15 +176,32 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; /* Wire the INVERTED configuration done signal to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); - fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, config_done_port, true); + /* Find the circuit model of configurable memory + * Spot its BL port and generate stimuli based on BL port's attribute: + * - If the BL port is triggered by edge, use the inverted programming clock signal + * - If the BL port is a regular port, use the inverted configuration done signal + */ + const CircuitModelId& mem_model = config_protocol.memory_model(); + VTR_ASSERT(true == circuit_lib.valid_model_id(mem_model)); + std::vector mem_model_bl_ports = circuit_lib.model_ports_by_type(mem_model, CIRCUIT_MODEL_PORT_BL); + VTR_ASSERT(1 == mem_model_bl_ports.size()); + if (true == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])) { + VTR_ASSERT_SAFE(false == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])); + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock signal -----")); + fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; + print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + } else { + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); + fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; + print_verilog_wire_connection(fp, en_port, config_done_port, true); + } } /******************************************************************** @@ -190,10 +209,11 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { - switch(sram_orgz_type) { + switch(config_protocol.type()) { case CONFIG_MEM_STANDALONE: print_verilog_top_testbench_flatten_memory_port(fp, module_manager, top_module); break; @@ -204,7 +224,8 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, print_verilog_top_testbench_memory_bank_port(fp, module_manager, top_module); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_port(fp, module_manager, top_module); + print_verilog_top_testbench_frame_decoder_port(fp, config_protocol, circuit_lib, + module_manager, top_module); break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -435,7 +456,8 @@ void print_verilog_top_testbench_ports(std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const std::vector& clock_port_names, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const std::string& circuit_name){ /* Validate the file stream */ valid_file_stream(fp); @@ -509,7 +531,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl; /* Configuration ports depend on the organization of SRAMs */ - print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type, + print_verilog_top_testbench_config_protocol_port(fp, config_protocol, circuit_lib, module_manager, top_module); /* Create a clock port if the benchmark have one but not in the default name! @@ -1459,7 +1481,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, void print_verilog_top_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const AtomContext& atom_ctx, @@ -1498,13 +1520,14 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Start of testbench */ print_verilog_top_testbench_ports(fp, module_manager, top_module, atom_ctx, netlist_annotation, clock_port_names, - sram_orgz_type, circuit_name); + config_protocol, circuit_lib, + circuit_name); /* Find the clock period */ float prog_clock_period = (1./simulation_parameters.programming_clock_frequency()); float op_clock_period = (1./simulation_parameters.operating_clock_frequency()); /* Estimate the number of configuration clock cycles */ - size_t num_config_clock_cycles = calculate_num_config_clock_cycles(sram_orgz_type, + size_t num_config_clock_cycles = calculate_num_config_clock_cycles(config_protocol.type(), fast_configuration, bitstream_manager, fabric_bitstream); @@ -1543,11 +1566,11 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Print tasks used for loading bitstreams */ print_verilog_top_testbench_load_bitstream_task(fp, - sram_orgz_type, + config_protocol.type(), module_manager, top_module); /* load bitstream to FPGA fabric in a configuration phase */ - print_verilog_top_testbench_bitstream(fp, sram_orgz_type, + print_verilog_top_testbench_bitstream(fp, config_protocol.type(), fast_configuration, module_manager, top_module, bitstream_manager, fabric_bitstream); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h index cbafc6dc4..64d0e0b26 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h @@ -10,6 +10,7 @@ #include "bitstream_manager.h" #include "fabric_bitstream.h" #include "circuit_library.h" +#include "config_protocol.h" #include "vpr_context.h" #include "io_location_map.h" #include "vpr_netlist_annotation.h" @@ -25,7 +26,7 @@ namespace openfpga { void print_verilog_top_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const AtomContext& atom_ctx, From 3d234d840b051322479e4b132238e121b65eb5d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:31:11 -0600 Subject: [PATCH 029/114] [Documentation] Update documentation for the edge triggered attribute --- docs/source/manual/arch_lang/circuit_library.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 59e5f055f..9e8466c09 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -143,7 +143,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in .. option:: + is_global="" is_set="" is_reset="" + is_edge_triggered="" is_config_enable=""/> Define the attributes for a port of a circuit model. @@ -190,6 +191,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. + - ``is_edge_triggered="true|false"`` Specify if this port is edge sensitive, like the clock port of a D-type flip-flop. This attribute is used to create stimuli in testbenches when flip-flops are used as configurable memory in frame-based configuration protocol. + .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. .. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details. From 8b8ce22fd1fda5d5bf16be3003561bb4fd774d8b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:37:28 -0600 Subject: [PATCH 030/114] [OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library --- libopenfpga/libarchopenfpga/src/circuit_library.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index 1bc6e840e..d8069f903 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -1380,6 +1380,7 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, port_is_reset_.push_back(false); port_is_set_.push_back(false); port_is_config_enable_.push_back(false); + port_is_edge_triggered_.push_back(false); port_is_prog_.push_back(false); port_tri_state_model_names_.emplace_back(); port_tri_state_model_ids_.push_back(CircuitModelId::INVALID()); From fc60b181914a7169b8af801d773de6dfa9160665 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:41:49 -0600 Subject: [PATCH 031/114] [Architecture] Now a regular flip-flop can be used in frame-based configuration --- .../k4_N4_40nm_frame_ccff_openfpga.xml | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 7ccada510..f6313bc22 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,30 +146,28 @@ - + - - + - + - - + - + - + From 2869eae8a94958322b84471408278152693665f8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:43:15 -0600 Subject: [PATCH 032/114] [Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol --- .../k4_N4_40nm_frame_scff_openfpga.xml | 201 ++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml new file mode 100644 index 000000000..7ccada510 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -0,0 +1,201 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 05c2e652a44e0f236c21e86d4a3b5a04c78ce365 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:44:06 -0600 Subject: [PATCH 033/114] [Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol --- .../configuration_frame_scff/config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf new file mode 100644 index 000000000..2be6528e4 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 709a20a3499f07c34a86bc1c918ce7839dfeff52 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:45:19 -0600 Subject: [PATCH 034/114] [Regression Test] Deploy new test to CI --- .travis/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index e0ee4685b..609c60749 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -20,6 +20,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; From a3abf81afec540cf908002546eb462ec5b40407a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:25:06 -0600 Subject: [PATCH 035/114] [OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration --- .../fpga_verilog/verilog_top_testbench.cpp | 135 ++++++++++++++++-- 1 file changed, 127 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 763f7800e..d6f7d1075 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1135,6 +1135,89 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); } +/******************************************************************** + * Decide if we should use reset or set signal to acheive fast configuration + * - If only one type signal is specified, we use that type + * For example, only reset signal is defined, we will use reset + * - If both are defined, pick the one that will bring bigger reduction + * i.e., larger number of configuration bits can be skipped + *******************************************************************/ +static +bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& config_protocol_type, + const bool& fast_configuration, + const std::vector& global_prog_reset_ports, + const std::vector& global_prog_set_ports, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream) { + + /* Early exit conditions */ + if (!global_prog_reset_ports.empty() && global_prog_set_ports.empty()) { + return false; + } else if (!global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { + return true; + } else if (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { + /* If both types of ports are not defined, the fast configuration should be turned off */ + VTR_ASSERT(false == fast_configuration); + return false; + } + + VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty()); + bool bit_value_to_skip = false; + + size_t num_ones_to_skip = 0; + size_t num_zeros_to_skip = 0; + + /* Branch on the type of configuration protocol */ + switch (config_protocol_type) { + case CONFIG_MEM_STANDALONE: + break; + case CONFIG_MEM_SCAN_CHAIN: { + /* We can only skip the ones/zeros at the beginning of the bitstream */ + /* Count how many logic '1' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + break; + } + VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_ones_to_skip++; + } + /* Count how many logic '0' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + break; + } + VTR_ASSERT(false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_zeros_to_skip++; + } + break; + } + case CONFIG_MEM_MEMORY_BANK: + case CONFIG_MEM_FRAME_BASED: { + /* Count how many logic '1' and logic '0' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + num_zeros_to_skip++; + } else { + VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_ones_to_skip++; + } + } + break; + } + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid SRAM organization type!\n"); + exit(1); + } + + /* By default, we prefer to skip zeros (when the numbers are the same */ + if (num_ones_to_skip > num_zeros_to_skip) { + bit_value_to_skip = true; + } + + return bit_value_to_skip; +} + /******************************************************************** * Print stimulus for a FPGA fabric with a configuration chain protocol * where configuration bits are programming in serial (one by one) @@ -1150,6 +1233,7 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, static void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, const bool& fast_configuration, + const bool& bit_value_to_skip, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { /* Validate the file stream */ @@ -1174,13 +1258,14 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, fp << std::endl; + /* Attention: when the fast configuration is enabled, we will start from the first bit '1' * This requires a reset signal (as we forced in the first clock cycle) */ bool start_config = false; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { if ( (false == start_config) - && (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) { + && (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) { start_config = true; } @@ -1221,6 +1306,7 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, static void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, const bool& fast_configuration, + const bool& bit_value_to_skip, const ModuleManager& module_manager, const ModuleId& top_module, const FabricBitstream& fabric_bitstream) { @@ -1272,7 +1358,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, for (const FabricBitId& bit_id : fabric_bitstream.bits()) { /* When fast configuration is enabled, we skip zero data_in values */ if ((true == fast_configuration) - && (false == fabric_bitstream.bit_din(bit_id))) { + && (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) { continue; } @@ -1326,6 +1412,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, static void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, const bool& fast_configuration, + const bool& bit_value_to_skip, const ModuleManager& module_manager, const ModuleId& top_module, const FabricBitstream& fabric_bitstream) { @@ -1368,7 +1455,7 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, for (const FabricBitId& bit_id : fabric_bitstream.bits()) { /* When fast configuration is enabled, we skip zero data_in values */ if ((true == fast_configuration) - && (false == fabric_bitstream.bit_din(bit_id))) { + && (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) { continue; } @@ -1424,30 +1511,61 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_bitstream(std::fstream& fp, - const e_config_protocol_type& sram_orgz_type, + const e_config_protocol_type& config_protocol_type, const bool& fast_configuration, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, const ModuleManager& module_manager, const ModuleId& top_module, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { + /* Try to find global reset/set ports for programming */ + std::vector global_prog_reset_ports; + std::vector global_prog_set_ports; + for (const CircuitPortId& global_port : global_ports) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) + || (false == circuit_lib.port_is_reset(global_port))); + if (true == circuit_lib.port_is_reset(global_port)) { + global_prog_reset_ports.push_back(global_port); + } + if (true == circuit_lib.port_is_set(global_port)) { + global_prog_set_ports.push_back(global_port); + } + } + + bool apply_fast_configuration = fast_configuration; + if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) + && (true == fast_configuration)) { + VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off"); + } + bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol_type, + apply_fast_configuration, + global_prog_reset_ports, + global_prog_set_ports, + bitstream_manager, fabric_bitstream); + /* Branch on the type of configuration protocol */ - switch (sram_orgz_type) { + switch (config_protocol_type) { case CONFIG_MEM_STANDALONE: print_verilog_top_testbench_vanilla_bitstream(fp, module_manager, top_module, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_SCAN_CHAIN: - print_verilog_top_testbench_configuration_chain_bitstream(fp, fast_configuration, + print_verilog_top_testbench_configuration_chain_bitstream(fp, apply_fast_configuration, + bit_value_to_skip, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_MEMORY_BANK: - print_verilog_top_testbench_memory_bank_bitstream(fp, fast_configuration, + print_verilog_top_testbench_memory_bank_bitstream(fp, apply_fast_configuration, + bit_value_to_skip, module_manager, top_module, fabric_bitstream); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_bitstream(fp, fast_configuration, + print_verilog_top_testbench_frame_decoder_bitstream(fp, apply_fast_configuration, + bit_value_to_skip, module_manager, top_module, fabric_bitstream); break; @@ -1572,6 +1690,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* load bitstream to FPGA fabric in a configuration phase */ print_verilog_top_testbench_bitstream(fp, config_protocol.type(), fast_configuration, + circuit_lib, global_ports, module_manager, top_module, bitstream_manager, fabric_bitstream); From f57fd273afb14d766ad77a8de495c60e648b89b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:28:06 -0600 Subject: [PATCH 036/114] [Documentation] Update documentation for smart fast configuration --- .../openfpga_shell/openfpga_commands/fpga_verilog_commands.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index c2044cf57..24dc3a603 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -33,6 +33,8 @@ write_verilog_testbench - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. + .. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration. + - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification From c2c37d7555944a0daca30b7083b104ba990e8e72 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:34:23 -0600 Subject: [PATCH 037/114] [OpenFPGA Tool] Add more print-out for smart fast configuration --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index d6f7d1075..28200696e 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1164,6 +1164,8 @@ bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty()); bool bit_value_to_skip = false; + VTR_LOG("Both reset and set ports are defined for programming controls, selecting the best-fit one...\n"); + size_t num_ones_to_skip = 0; size_t num_zeros_to_skip = 0; @@ -1210,9 +1212,20 @@ bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& exit(1); } + VTR_LOG("Using reset will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_zeros_to_skip / (float) fabric_bitstream.num_bits(), + num_zeros_to_skip, fabric_bitstream.num_bits()); + + VTR_LOG("Using set will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_ones_to_skip / (float) fabric_bitstream.num_bits(), + num_ones_to_skip, fabric_bitstream.num_bits()); + /* By default, we prefer to skip zeros (when the numbers are the same */ if (num_ones_to_skip > num_zeros_to_skip) { + VTR_LOG("Will use set signal in fast configuration\n"); bit_value_to_skip = true; + } else { + VTR_LOG("Will use reset signal in fast configuration\n"); } return bit_value_to_skip; From 154c9045f6aa53f2567d7165ba87b32d7d3137fc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:38:42 -0600 Subject: [PATCH 038/114] [OpoenFPGA Tool] Bug fix for smart fast configuration --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 28200696e..481d01ae4 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1536,10 +1536,13 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, std::vector global_prog_reset_ports; std::vector global_prog_set_ports; for (const CircuitPortId& global_port : global_ports) { + if (false == circuit_lib.port_is_reset(global_port)) { + continue; + } VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) || (false == circuit_lib.port_is_reset(global_port))); - if (true == circuit_lib.port_is_reset(global_port)) { + if (true == circuit_lib.port_is_prog(global_port)) { global_prog_reset_ports.push_back(global_port); } if (true == circuit_lib.port_is_set(global_port)) { From 8fa4fa1125a37fcd13af15265369056b0c8b6c11 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:39:31 -0600 Subject: [PATCH 039/114] [Architecture] Add openfpga architecture using set signals for configurable latch --- .../k4_N4_40nm_frame_use_set_openfpga.xml | 199 ++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml new file mode 100644 index 000000000..a3ea99857 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 7591060fbd24bde23552be77fb269b298efa3a24 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:45:06 -0600 Subject: [PATCH 040/114] [Architecture] Add configurable latch Verilog designs and assoicated architectures --- .../VerilogNetlists/config_latch_set.v | 37 +++++++++++++++++ .../VerilogNetlists/config_latch_set_reset.v | 41 +++++++++++++++++++ .../k4_N4_40nm_frame_use_set_openfpga.xml | 6 +-- 3 files changed, 81 insertions(+), 3 deletions(-) create mode 100644 openfpga_flow/VerilogNetlists/config_latch_set.v create mode 100644 openfpga_flow/VerilogNetlists/config_latch_set_reset.v diff --git a/openfpga_flow/VerilogNetlists/config_latch_set.v b/openfpga_flow/VerilogNetlists/config_latch_set.v new file mode 100644 index 000000000..945df2377 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/config_latch_set.v @@ -0,0 +1,37 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Function : A Configurable Latch where data storage +// can be updated when wl is enabled +// Set is active high +// Coder : Xifan TANG +//----------------------------------------------------- +module config_latch_set ( + input set, // Reset input + input wl, // Data Enable + input bl, // Data Input + output Q, // Q output + output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (set or bl or wl) begin + if (set) begin + q_reg <= 1'b1; + end else if (1'b1 == wl) begin + q_reg <= bl; + end +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_set_reset.v b/openfpga_flow/VerilogNetlists/config_latch_set_reset.v new file mode 100644 index 000000000..ad9f75322 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/config_latch_set_reset.v @@ -0,0 +1,41 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Function : A Configurable Latch where data storage +// can be updated when wl is enabled +// Reset is active high +// Set is active high +// Coder : Xifan TANG +//----------------------------------------------------- +module config_latch_set_reset ( + input reset, // Reset input + input set, // Set input + input wl, // Data Enable + input bl, // Data Input + output Q, // Q output + output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (reset or set or bl or wl) begin + if (reset) begin + q_reg <= 1'b0; + end else if (set) begin + q_reg <= 1'b1; + end else if (1'b1 == wl) begin + q_reg <= bl; + end +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index a3ea99857..2785712a8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -146,7 +146,7 @@ - + @@ -161,13 +161,13 @@ - + - + From 9331ef941d81dd3ea8f96a302571700be35acae2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:46:04 -0600 Subject: [PATCH 041/114] [Architecture] Add architecture that use both set and reset signals --- ...40nm_frame_use_both_set_reset_openfpga.xml | 200 ++++++++++++++++++ 1 file changed, 200 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml new file mode 100644 index 000000000..1f4108593 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 349aa79069ee79feadad2915c74f0c60f0c350f9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:49:38 -0600 Subject: [PATCH 042/114] [Regression test] Add test case for smart fast configuration --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf new file mode 100644 index 000000000..1cdffa78f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 73e59d67afeb4551256c31d62fbe9ece9ce240b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:50:23 -0600 Subject: [PATCH 043/114] [Architecture] Add test case for fast configuration using set signals --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf new file mode 100644 index 000000000..4b5763f69 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From fcf1ff418fa949e7512f0f4b16478df944f80d1c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:53:38 -0600 Subject: [PATCH 044/114] [Architecture] Add Verilog for SRAM using set/reset --- openfpga_flow/VerilogNetlists/sram.v | 80 +++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v index c27dbeebe..0cd5862c1 100644 --- a/openfpga_flow/VerilogNetlists/sram.v +++ b/openfpga_flow/VerilogNetlists/sram.v @@ -17,7 +17,7 @@ output outb // Data output reg data; //----- when wl is enabled, we can read in data from bl - always @(bl, wl) + always @(bl or wl) begin if (1'b1 == reset) begin data <= 1'b0; @@ -42,6 +42,84 @@ output outb // Data output endmodule +module sram_blwl_set( +input set, // Word line control signal +input wl, // Word line control signal +input bl, // Bit line control signal +output out, // Data output +output outb // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(bl or wl) + begin + if (1'b1 == set) begin + data <= 1'b1; + end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign out = data; + assign outb = ~data; +`else + assign out = 1'bZ; + assign outb = !out; +`endif + +endmodule + +module sram_blwl_set_reset( +input reset, // Word line control signal +input set, // Word line control signal +input wl, // Word line control signal +input bl, // Bit line control signal +output out, // Data output +output outb // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(bl or wl) + begin + if (1'b1 == reset) begin + data <= 1'b0; + end else if (1'b1 == set) begin + data <= 1'b1; + end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign out = data; + assign outb = ~data; +`else + assign out = 1'bZ; + assign outb = !out; +`endif + +endmodule + + //------ Module: sram6T_blwl -----// //------ Verilog file: sram.v -----// From 46b12611a9f4ed950951bc1baf49a8cbf29439cd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:04:07 -0600 Subject: [PATCH 045/114] [OpenFPGA Tool] Bug fix for smart fast configuration --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 481d01ae4..e76c198e9 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1536,13 +1536,14 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, std::vector global_prog_reset_ports; std::vector global_prog_set_ports; for (const CircuitPortId& global_port : global_ports) { - if (false == circuit_lib.port_is_reset(global_port)) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + if (false == circuit_lib.port_is_prog(global_port)) { continue; } - VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) - || (false == circuit_lib.port_is_reset(global_port))); - if (true == circuit_lib.port_is_prog(global_port)) { + || (false == circuit_lib.port_is_set(global_port))); + if (true == circuit_lib.port_is_reset(global_port)) { global_prog_reset_ports.push_back(global_port); } if (true == circuit_lib.port_is_set(global_port)) { @@ -1553,7 +1554,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, bool apply_fast_configuration = fast_configuration; if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) && (true == fast_configuration)) { - VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off"); + VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n"); } bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol_type, apply_fast_configuration, From 77a1f995648792903da3087a004b29f39b31b8ab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:04:24 -0600 Subject: [PATCH 046/114] [Architecture] Bug fix for architecture using set only --- .../openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index 2785712a8..96073d685 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -146,7 +146,7 @@ - + From 707300a6e4507bce0f0d5bf84de64c0269748101 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:07:40 -0600 Subject: [PATCH 047/114] [Architecture] Bug fix for using both reset and set architecture --- .../k4_N4_40nm_frame_use_both_set_reset_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index 1f4108593..2b695027a 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -146,7 +146,7 @@ - + From 07198f63960d2897af2e3bfdd1a2d94b4bb07091 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:08:30 -0600 Subject: [PATCH 048/114] [Regression Test] Deploy smart configuration tests to CI --- .travis/basic_reg_test.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 609c60749..04b36b885 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -17,7 +17,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/c echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs From c7fc0178b0b5f513b3f9a8a26d895c9166ade80f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:57:06 -0600 Subject: [PATCH 049/114] [Architecture] Rename to be consist with other architectures --- .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 199 ++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml new file mode 100644 index 000000000..f1894c9a5 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From d0cef6824265b274b8b570a4fd4025c8a96cdf3b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:58:59 -0600 Subject: [PATCH 050/114] [Regression test] Add test case for using resetb --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf new file mode 100644 index 000000000..24751ed47 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 8e780635df5781eb5a92cafcfa9b5ca59d53adb8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:59:46 -0600 Subject: [PATCH 051/114] [Regression Test] Rename test case in CI --- .travis/basic_reg_test.sh | 2 +- .../k4_N4_40nm_frame_resetb_openfpga.xml | 199 ------------------ .../config/task.conf | 34 --- 3 files changed, 1 insertion(+), 234 deletions(-) delete mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml delete mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 04b36b885..d22568aee 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -23,7 +23,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_c python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml deleted file mode 100644 index f1894c9a5..000000000 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml +++ /dev/null @@ -1,199 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf deleted file mode 100644 index 755b9ec94..000000000 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf +++ /dev/null @@ -1,34 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 -bench0_chan_width = 300 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= From 5d60b4ef8c27b7088008d7e596354a25ca1e6a95 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 23:02:49 -0600 Subject: [PATCH 052/114] [Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set --- .../VerilogNetlists/config_latch_neg_set.v | 37 ++++ .../k4_N4_40nm_frame_use_setb_openfpga.xml | 199 ++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_set.v create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_set.v b/openfpga_flow/VerilogNetlists/config_latch_neg_set.v new file mode 100644 index 000000000..2c23a73d1 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_set.v @@ -0,0 +1,37 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Function : A Configurable Latch where data storage +// can be updated when wl is enabled +// Reset is active low +// Coder : Xifan TANG +//----------------------------------------------------- +module config_latch_neg_set ( + input setb, // Reset input + input wl, // Data Enable + input bl, // Data Input + output Q, // Q output + output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (setb or wl or bl) begin + if (~setb) begin + q_reg <= 1'b1; + end else if (1'b1 == wl) begin + q_reg <= bl; + end +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml new file mode 100644 index 000000000..670339321 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 5b0d451f0fec4418390d0ee3fb4245c2fb2c6686 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 23:04:10 -0600 Subject: [PATCH 053/114] [Regression Test] Add test case for configurable latch with active-low set --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf new file mode 100644 index 000000000..793854774 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 10b6e1dc0dd5731b05b2e1d3d1c7c0077ccb715f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 23:06:46 -0600 Subject: [PATCH 054/114] [Architecture] bug fix for active-low --- .../openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index 670339321..0a08f0b83 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -161,13 +161,13 @@ - + - + From 70a8c6dc29b350fe6a9c68c0a68f6f3f193595dc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 23:07:19 -0600 Subject: [PATCH 055/114] [Regression Test] Add test case using active-low set to CI --- .travis/basic_reg_test.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index d22568aee..5ffbcf6b2 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -20,10 +20,11 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs From 6bb30ab33c53b174f02f095352f922deb5b2d445 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:02:51 -0600 Subject: [PATCH 056/114] [Architecture] Enrich SRAM Verilog HDL for flexible set/reset support --- openfpga_flow/VerilogNetlists/sram.v | 261 +++++++++++++++++++++------ 1 file changed, 201 insertions(+), 60 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v index 0cd5862c1..847e1a90a 100644 --- a/openfpga_flow/VerilogNetlists/sram.v +++ b/openfpga_flow/VerilogNetlists/sram.v @@ -42,27 +42,32 @@ output outb // Data output endmodule -module sram_blwl_set( -input set, // Word line control signal -input wl, // Word line control signal -input bl, // Bit line control signal -output out, // Data output -output outb // Data output +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-high set +// - a write-enable +//----------------------------------------------------- +module SRAMS( + input SET, // active-high set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output ); //----- local variable need to be registered reg data; //----- when wl is enabled, we can read in data from bl - always @(bl or wl) + always @(D or WE) begin - if (1'b1 == set) begin + if (1'b1 == SET) begin data <= 1'b1; - end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + end else if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 data <= 1'b1; - end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 data <= 1'b0; end @@ -70,39 +75,83 @@ output outb // Data output `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q - assign out = data; - assign outb = ~data; + assign Q = data; + assign QN = ~data; `else - assign out = 1'bZ; - assign outb = !out; + assign Q = 1'bZ; + assign QN = !out; `endif endmodule -module sram_blwl_set_reset( -input reset, // Word line control signal -input set, // Word line control signal -input wl, // Word line control signal -input bl, // Bit line control signal -output out, // Data output -output outb // Data output +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-low set +// - a write-enable +//----------------------------------------------------- +module SRAMSN( + input SETN, // active-low set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output ); //----- local variable need to be registered reg data; //----- when wl is enabled, we can read in data from bl - always @(bl or wl) + always @(D or WE) begin - if (1'b1 == reset) begin + if (1'b0 == SETN) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !out; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-high reset +// - a write-enable +//----------------------------------------------------- +module SRAMR( + input RST, // active-high reset signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b1 == RST) begin data <= 1'b0; - end else if (1'b1 == set) begin - data <= 1'b1; - end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + end else if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 data <= 1'b1; - end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 data <= 1'b0; end @@ -110,58 +159,150 @@ output outb // Data output `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q - assign out = data; - assign outb = ~data; + assign Q = data; + assign QN = ~data; `else - assign out = 1'bZ; - assign outb = !out; + assign Q = 1'bZ; + assign QN = !out; `endif endmodule - - -//------ Module: sram6T_blwl -----// -//------ Verilog file: sram.v -----// -//------ Author: Xifan TANG -----// -module sram6T_blwl( -//input read, -//input nequalize, -input din, // Data input -output dout, // Data output -output doutb, // Data output -input bl, // Bit line control signal -input wl, // Word line control signal -input blb // Inverted Bit line control signal +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-low reset +// - a write-enable +//----------------------------------------------------- +module SRAMRN( + input RSTN, // active-low reset signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output ); + //----- local variable need to be registered - reg a; + reg data; //----- when wl is enabled, we can read in data from bl - always @(bl, wl) + always @(D or WE) begin + if (1'b0 == RSTN) begin + data <= 1'b0; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 - if ((1'b1 == bl)&&(1'b1 == wl)) begin - a <= 1'b1; - end + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 - if ((1'b0 == bl)&&(1'b1 == wl)) begin - a <= 1'b0; + data <= 1'b0; end end - // dout is short-wired to din - assign dout = a; - //---- doutb is always opposite to dout - assign doutb = ~dout; -`ifdef ENABLE_SIGNAL_INITIALIZATION - initial begin - $deposit(a, $random); - end +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !out; `endif + endmodule +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-high reset +// - an active-high set +// - a write-enable +//----------------------------------------------------- +module SRAMSR( + input RST, // active-high reset signal + input SET, // active-high set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b1 == RST) begin + data <= 1'b0; + end else if (1'b1 == SET) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !out; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-low reset +// - an active-low set +// - a write-enable +//----------------------------------------------------- +module SRAMSNRN( + input RSTN, // active-low reset signal + input SETN, // active-low set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b0 == RSTN) begin + data <= 1'b0; + end else if (1'b0 == SETN) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !out; +`endif + +endmodule + + module sram6T_rram( input read, input nequalize, From 56c9aab190d1772fcabe28af22dfcd5cc931a093 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:15:08 -0600 Subject: [PATCH 057/114] [Architecture] Add architecture to use different SRAM cells for memory bank --- ..._40nm_bank_use_both_set_reset_openfpga.xml | 200 ++++++++++++++++++ .../k4_N4_40nm_bank_use_reset_openfpga.xml | 199 +++++++++++++++++ .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 199 +++++++++++++++++ .../k4_N4_40nm_bank_use_set_openfpga.xml | 199 +++++++++++++++++ .../k4_N4_40nm_bank_use_setb_openfpga.xml | 199 +++++++++++++++++ 5 files changed, 996 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml new file mode 100644 index 000000000..95c93a6db --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml new file mode 100644 index 000000000..33581d64a --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml new file mode 100644 index 000000000..184c5b14c --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml new file mode 100644 index 000000000..904ee811a --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml new file mode 100644 index 000000000..68a29312a --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 186f00edfcddc7f9c1c1a5097af5059c936c8350 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:25:03 -0600 Subject: [PATCH 058/114] [Regression Test] Add test cases for memory bank using different SRAM cells --- .../memory_bank_use_reset/config/task.conf | 34 +++++++++++++++++++ .../memory_bank_use_resetb/config/task.conf | 34 +++++++++++++++++++ .../memory_bank_use_set/config/task.conf | 34 +++++++++++++++++++ .../memory_bank_use_setb/config/task.conf | 34 +++++++++++++++++++ .../smart_fast_memory_bank/config/task.conf | 34 +++++++++++++++++++ 5 files changed, 170 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf new file mode 100644 index 000000000..cb9ddbee7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf new file mode 100644 index 000000000..87ef8b32b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf new file mode 100644 index 000000000..cf4341928 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf new file mode 100644 index 000000000..55af9d7cc --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf new file mode 100644 index 000000000..26e5b6239 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From e454467799392dea4bd62e5e59a73d52c11a8fb1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:26:10 -0600 Subject: [PATCH 059/114] [Regression Test] Deploy memory bank test cases to CI --- .travis/basic_reg_test.sh | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 5ffbcf6b2..c10ae3a66 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -28,7 +28,12 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/c echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; From 83971bba41021b8f69ac4ff37fa49e65241b3ed8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:31:31 -0600 Subject: [PATCH 060/114] [Architecture] Update cell ports for native SRAM cell --- openfpga_flow/VerilogNetlists/sram.v | 34 +++++++++---------- .../k4_N4_40nm_bank_openfpga.xml | 15 ++++---- 2 files changed, 24 insertions(+), 25 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v index 847e1a90a..8cd50c46e 100644 --- a/openfpga_flow/VerilogNetlists/sram.v +++ b/openfpga_flow/VerilogNetlists/sram.v @@ -1,31 +1,31 @@ //----------------------------------------------------- // Design Name : sram_blwl // File Name : sram.v -// Function : A SRAM cell is is accessible -// when wl is enabled // Coder : Xifan TANG //----------------------------------------------------- -module sram_blwl( -input reset, // Word line control signal -input wl, // Word line control signal -input bl, // Bit line control signal -output out, // Data output -output outb // Data output + + +//----------------------------------------------------- +// Function : A SRAM cell with write enable +//----------------------------------------------------- +module SRAM( + input WE, // Word line control signal as write enable + input D, // Bit line control signal + output Q, // Data output + output QN // Data output ); //----- local variable need to be registered reg data; //----- when wl is enabled, we can read in data from bl - always @(bl or wl) + always @(WE or D) begin - if (1'b1 == reset) begin - data <= 1'b0; - end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 data <= 1'b1; - end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 data <= 1'b0; end @@ -33,11 +33,11 @@ output outb // Data output `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q - assign out = data; - assign outb = ~data; + assign Q = data; + assign QN = ~data; `else - assign out = 1'bZ; - assign outb = !out; + assign Q = 1'bZ; + assign QN = !out; `endif endmodule diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index 110ea66a9..45fa552d0 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -146,28 +146,27 @@ - + - - - - - + + + + - + - + From 48083d2276badd369ad8f163c6cecf40823202a2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:32:03 -0600 Subject: [PATCH 061/114] [Regression Test] Adapt fast memory bank test case --- .../full_testbench/fast_memory_bank/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf index e669edf34..05e3f475b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] From 7238a2be03314bf984c1de59b570ff32ca406c5a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 11:02:01 -0600 Subject: [PATCH 062/114] [Architecture] Merge latch Verilog HDL to a unique file --- openfpga_flow/VerilogNetlists/config_latch.v | 37 --- .../VerilogNetlists/config_latch_neg_rst.v | 37 --- .../VerilogNetlists/config_latch_neg_set.v | 37 --- .../VerilogNetlists/config_latch_set.v | 37 --- .../VerilogNetlists/config_latch_set_reset.v | 41 --- openfpga_flow/VerilogNetlists/latch.v | 255 ++++++++++++++++++ 6 files changed, 255 insertions(+), 189 deletions(-) delete mode 100644 openfpga_flow/VerilogNetlists/config_latch.v delete mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_rst.v delete mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_set.v delete mode 100644 openfpga_flow/VerilogNetlists/config_latch_set.v delete mode 100644 openfpga_flow/VerilogNetlists/config_latch_set_reset.v create mode 100644 openfpga_flow/VerilogNetlists/latch.v diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v deleted file mode 100644 index e08ea2153..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ /dev/null @@ -1,37 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Reset is active high -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch ( - input reset, // Reset input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (reset or bl or wl) begin - if (reset) begin - q_reg <= 1'b0; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v deleted file mode 100644 index cb24769d5..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v +++ /dev/null @@ -1,37 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Reset is active low -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch ( - input resetb, // Reset input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (resetb or wl or bl) begin - if (~resetb) begin - q_reg <= 1'b0; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_set.v b/openfpga_flow/VerilogNetlists/config_latch_neg_set.v deleted file mode 100644 index 2c23a73d1..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch_neg_set.v +++ /dev/null @@ -1,37 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Reset is active low -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch_neg_set ( - input setb, // Reset input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (setb or wl or bl) begin - if (~setb) begin - q_reg <= 1'b1; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_set.v b/openfpga_flow/VerilogNetlists/config_latch_set.v deleted file mode 100644 index 945df2377..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch_set.v +++ /dev/null @@ -1,37 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Set is active high -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch_set ( - input set, // Reset input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (set or bl or wl) begin - if (set) begin - q_reg <= 1'b1; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_set_reset.v b/openfpga_flow/VerilogNetlists/config_latch_set_reset.v deleted file mode 100644 index ad9f75322..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch_set_reset.v +++ /dev/null @@ -1,41 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Reset is active high -// Set is active high -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch_set_reset ( - input reset, // Reset input - input set, // Set input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (reset or set or bl or wl) begin - if (reset) begin - q_reg <= 1'b0; - end else if (set) begin - q_reg <= 1'b1; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/latch.v b/openfpga_flow/VerilogNetlists/latch.v new file mode 100644 index 000000000..f2b0f2f09 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/latch.v @@ -0,0 +1,255 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +//----------------------------------------------------- +module LATCH ( + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (WE or D) begin + if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high reset signal +//----------------------------------------------------- +module LATCHR ( + input RST, // Reset signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RST or WE or D) begin + if (RST) begin + q_reg <= 1'b0; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-low reset signal +//----------------------------------------------------- +module LATCHRN ( + input RSTN, // Reset signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RSTN or WE or D) begin + if (~RSTN) begin + q_reg <= 1'b0; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high set signal +//----------------------------------------------------- +module LATCHS ( + input SET, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (SET or WE or D) begin + if (SET) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-low set signal +//----------------------------------------------------- +module LATCHSN ( + input SETN, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (SETN or WE or D) begin + if (~SETN) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high reset signal +// - an active-high set signal +//----------------------------------------------------- +module LATCHSR ( + input RST, // Reset signal + input SET, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RST or SET or WE or D) begin + if (RST) begin + q_reg <= 1'b0; + end else if (SET) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high reset signal +// - an active-high set signal +//----------------------------------------------------- +module LATCHSNRN ( + input RSTN, // Reset signal + input SETN, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RSTN or SETN or WE or D) begin + if (~RSTN) begin + q_reg <= 1'b0; + end else if (~SETN) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + From fde15c4f8842612133e24f61beac76d6bb379353 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:13:35 -0600 Subject: [PATCH 063/114] [Regression Test] Add test for fast memory bank configuration using set signals --- .../fast_memory_bank_use_set/config/task.conf | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf new file mode 100644 index 000000000..44494baf6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 2add0406a7339a8f93e872592d27f06c435d006a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:14:03 -0600 Subject: [PATCH 064/114] [Architecture] Update architecture files for new latch naming --- .../k4_N4_40nm_frame_openfpga.xml | 15 +++++++------- ...40nm_frame_use_both_set_reset_openfpga.xml | 18 ++++++++--------- .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 16 +++++++-------- .../k4_N4_40nm_frame_use_set_openfpga.xml | 16 +++++++-------- .../k4_N4_40nm_frame_use_setb_openfpga.xml | 16 +++++++-------- .../k4_N4_40nm_powergate_frame_openfpga.xml | 16 +++++++-------- ...4_no_local_routing_40nm_frame_openfpga.xml | 16 +++++++-------- ...tern_local_routing_40nm_frame_openfpga.xml | 16 +++++++-------- ..._adder_chain_mem1K_40nm_frame_openfpga.xml | 18 ++++++++--------- ...r_chain_mem1K_L124_40nm_frame_openfpga.xml | 18 ++++++++--------- ...n_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 20 +++++++++---------- 11 files changed, 92 insertions(+), 93 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index b370c1f3d..681c67cae 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -146,28 +146,27 @@ - + - - - - - + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index 2b695027a..298b49e30 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -146,29 +146,29 @@ - + - - - - - - + + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml index f1894c9a5..1866e8ec1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index 96073d685..e92172048 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index 0a08f0b83..c2001aa5e 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index 402331b6f..37292c40e 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -152,28 +152,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index c579e4f49..2f6a960d1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index 7ca1ba958..d0b63dd2b 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 45d660d95..118f082b4 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -161,25 +161,25 @@ - + - + - - - - - + + + + + - + @@ -207,7 +207,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 6a3aba09e..4e9e16e79 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -161,25 +161,25 @@ - + - + - - - - - + + + + + - + @@ -207,7 +207,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 0cd86c659..5124e11a1 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -161,25 +161,25 @@ - + - + - - - - - + + + + + - + @@ -213,11 +213,11 @@ - + - + From 539bb617f99c72ccca3687d3d21c3c985e99b582 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:17:18 -0600 Subject: [PATCH 065/114] [Architecture] Add reset test case for frame based configuration --- .../k4_N4_40nm_frame_use_reset_openfpga.xml | 199 ++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml new file mode 100644 index 000000000..5ee20c2e1 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From ffd1a72d22a73d6e48584d0d45d4321bd51350ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:18:26 -0600 Subject: [PATCH 066/114] [Architecture] Add regression tests for the frame-based configuration using reset and set signals --- .../config/task.conf | 42 +++++++++++++++++++ .../config/task.conf | 42 +++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf new file mode 100644 index 000000000..b5e82f32b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf new file mode 100644 index 000000000..1f2a9bd45 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 9d9cf6ee71c21325517a034b0edae0f6ac8584cb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:20:18 -0600 Subject: [PATCH 067/114] [Regression Test] Deploy new tests to CI --- .travis/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index c10ae3a66..d326e03a6 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -22,7 +22,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_c python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs @@ -33,6 +35,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs From 1b13e8ecb1b4bd2e34c398e20ea35bb7e33435c8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:26:13 -0600 Subject: [PATCH 068/114] [Architecture] Bug fix in the SRAM Verilog --- openfpga_flow/VerilogNetlists/sram.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v index 8cd50c46e..86f3ddf99 100644 --- a/openfpga_flow/VerilogNetlists/sram.v +++ b/openfpga_flow/VerilogNetlists/sram.v @@ -37,7 +37,7 @@ module SRAM( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -79,7 +79,7 @@ module SRAMS( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -121,7 +121,7 @@ module SRAMSN( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -163,7 +163,7 @@ module SRAMR( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -205,7 +205,7 @@ module SRAMRN( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -251,7 +251,7 @@ module SRAMSR( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -297,7 +297,7 @@ module SRAMSNRN( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule From e832d806c728fea56aa99cc238693da745d0fa9f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 13:50:59 -0600 Subject: [PATCH 069/114] [Architecture] Add DFF Verilog netlist using standard naming convention --- openfpga_flow/VerilogNetlists/dff.v | 247 ++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/dff.v diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v new file mode 100644 index 000000000..2314cae0f --- /dev/null +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -0,0 +1,247 @@ +//----------------------------------------------------- +// Design Name : D-type Flip-flops +// File Name : ff.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A native D-type flip-flop +//----------------------------------------------------- +module DFF ( + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK) + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +//----------------------------------------------------- +module DFFR ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST) +if (RST) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active low reset +//----------------------------------------------------- +module DFFRN ( + input RSTN, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or negedge RSTN) +if (~RSTN) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high set +//----------------------------------------------------- +module DFFS ( + input SET, // Set input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge SET) +if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active low set +//----------------------------------------------------- +module DFFSN ( + input SETN, // Set input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or negedge SETN) +if (~SETN) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +//----------------------------------------------------- +module DFFSR ( + input SET, // set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFSR ( + input SET, // Set input + input RST, // Reset input + input SE, // Scan-chain Enable + input SI, // Scan-chain input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module From e7906899ddabd68ef7e2c3277b3b4b2cdc6cf04c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 13:53:12 -0600 Subject: [PATCH 070/114] [Regression test] Bug fix for fast configuration frame. Now should use a latch with reset --- .../full_testbench/fast_configuration_frame/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf index 3626d3e85..0ab4871ca 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] From efad0402c2df041fba13eb2d2332063307b0c5d3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 13:55:41 -0600 Subject: [PATCH 071/114] [Regression Test] Bug fix for CI errors --- .../load_external_architecture_bitstream/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf index 89ba177b6..f88536f37 100644 --- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=vpr_blif [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml openfpga_vpr_device_layout=2x2 From 98d88dc68647c32b1beebb1aebb02c747eba33df Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:13:48 -0600 Subject: [PATCH 072/114] [Architecture] Bug fix for vanilla memory organization --- .../k4_N4_40nm_standalone_openfpga.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 0781e6caa..43dd1e3f1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + From 178afb3c7f68c8453b10ad30e8e8cbfa36afb360 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:23:27 -0600 Subject: [PATCH 073/114] [Architecture] Add configuration chain architectures using different DFF cells --- .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 11 +- ...N4_40nm_cc_use_both_set_reset_openfpga.xml | 191 ++++++++++++++++++ .../k4_N4_40nm_cc_use_reset_openfpga.xml | 190 +++++++++++++++++ .../k4_N4_40nm_cc_use_resetb_openfpga.xml | 190 +++++++++++++++++ .../k4_N4_40nm_cc_use_set_openfpga.xml | 190 +++++++++++++++++ .../k4_N4_40nm_cc_use_setb_openfpga.xml | 190 +++++++++++++++++ 6 files changed, 956 insertions(+), 6 deletions(-) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index f1db02ad1..acf0311f1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -137,28 +137,27 @@ - + - - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml new file mode 100644 index 000000000..e6f35ab03 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -0,0 +1,191 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml new file mode 100644 index 000000000..6554e98a0 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml new file mode 100644 index 000000000..bd18bffce --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml new file mode 100644 index 000000000..290c36e9c --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml new file mode 100644 index 000000000..1700117d9 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 7fbccdd1026fe35af8bccdc83b16546299ac7c28 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:34:12 -0600 Subject: [PATCH 074/114] [Regression Tests] Add test cases for configuration chain using different DFF cells --- .../config/task.conf | 34 +++++++++++++++ .../config/task.conf | 34 +++++++++++++++ .../config/task.conf | 34 +++++++++++++++ .../config/task.conf | 34 +++++++++++++++ .../fast_configuration_chain/config/task.conf | 3 +- .../config/task.conf | 42 +++++++++++++++++++ .../config/task.conf | 34 +++++++++++++++ 7 files changed, 213 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf new file mode 100644 index 000000000..b96d8f648 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf new file mode 100644 index 000000000..379ae0404 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf new file mode 100644 index 000000000..6c7ae7c75 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf new file mode 100644 index 000000000..4a8222d91 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf index 0d98afa11..04e7fef1b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf @@ -8,7 +8,6 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false @@ -18,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf new file mode 100644 index 000000000..d3879a68f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf new file mode 100644 index 000000000..fb8de2067 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 08838c4957fad72cfcd8c55b4a3a9921bfd17186 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:36:39 -0600 Subject: [PATCH 075/114] [Regression Test] Deploy new configuration chain test cases to CI --- .travis/basic_reg_test.sh | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index d326e03a6..2eb3da47a 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -12,7 +12,13 @@ echo -e "Basic regression tests"; echo -e "Testing configuration chain of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; From 3b42fe94d6d3bc5cdb45896b4b1322e3309504df Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:41:44 -0600 Subject: [PATCH 076/114] [Architecture] Update external bitstream file --- .../and2_k4_N4_tileable_40nm_bitstream.xml | 338 +++++++++--------- 1 file changed, 169 insertions(+), 169 deletions(-) diff --git a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml index f1f0a7362..7b6e5d3cd 100644 --- a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml +++ b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Mon Jul 27 15:47:36 2020 + - Date: Thu Sep 24 14:40:51 2020 --> @@ -11,7 +11,7 @@ - + @@ -19,7 +19,7 @@ - + @@ -64,7 +64,7 @@ - + @@ -72,7 +72,7 @@ - + @@ -117,7 +117,7 @@ - + @@ -125,7 +125,7 @@ - + @@ -170,7 +170,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -563,7 +563,7 @@ - + @@ -571,7 +571,7 @@ - + @@ -616,7 +616,7 @@ - + @@ -624,7 +624,7 @@ - + @@ -669,7 +669,7 @@ - + @@ -677,7 +677,7 @@ - + @@ -722,7 +722,7 @@ - + @@ -730,7 +730,7 @@ - + @@ -1115,7 +1115,7 @@ - + @@ -1123,7 +1123,7 @@ - + @@ -1168,7 +1168,7 @@ - + @@ -1176,7 +1176,7 @@ - + @@ -1221,7 +1221,7 @@ - + @@ -1229,7 +1229,7 @@ - + @@ -1274,7 +1274,7 @@ - + @@ -1282,24 +1282,24 @@ - + - + - + - + - - + + - + - + - + @@ -1703,7 +1703,7 @@ - + @@ -1711,7 +1711,7 @@ - + @@ -1756,7 +1756,7 @@ - + @@ -1764,7 +1764,7 @@ - + @@ -1809,7 +1809,7 @@ - + @@ -1817,7 +1817,7 @@ - + @@ -1862,7 +1862,7 @@ - + @@ -1870,7 +1870,7 @@ - + @@ -2253,13 +2253,13 @@ - + - + @@ -2269,13 +2269,13 @@ - + - + @@ -2285,13 +2285,13 @@ - + - + @@ -2301,13 +2301,13 @@ - + - + @@ -2317,13 +2317,13 @@ - + - + @@ -2333,13 +2333,13 @@ - + - + @@ -2349,13 +2349,13 @@ - + - + @@ -2365,13 +2365,13 @@ - + - + @@ -2383,13 +2383,13 @@ - + - + @@ -2399,13 +2399,13 @@ - + - + @@ -2415,13 +2415,13 @@ - + - + @@ -2431,13 +2431,13 @@ - + - + @@ -2447,13 +2447,13 @@ - + - + @@ -2463,13 +2463,13 @@ - + - + @@ -2479,13 +2479,13 @@ - + - + @@ -2495,13 +2495,13 @@ - + - + @@ -2513,13 +2513,13 @@ - + - + @@ -2529,13 +2529,13 @@ - + - + @@ -2545,13 +2545,13 @@ - + - + @@ -2561,13 +2561,13 @@ - + - + @@ -2577,13 +2577,13 @@ - + - + @@ -2593,13 +2593,13 @@ - + - + @@ -2609,13 +2609,13 @@ - + - + @@ -2625,13 +2625,13 @@ - + - + @@ -2643,13 +2643,13 @@ - + - + @@ -2659,13 +2659,13 @@ - + - + @@ -2675,13 +2675,13 @@ - + - + @@ -2691,13 +2691,13 @@ - + - + @@ -2707,13 +2707,13 @@ - + - + @@ -2723,13 +2723,13 @@ - + - + @@ -2739,13 +2739,13 @@ - + - + @@ -2755,13 +2755,13 @@ - + - + @@ -2773,13 +2773,13 @@ - + - + @@ -2789,13 +2789,13 @@ - + - + @@ -2805,13 +2805,13 @@ - + - + @@ -2821,13 +2821,13 @@ - + - + @@ -2837,13 +2837,13 @@ - + - + @@ -2853,13 +2853,13 @@ - + - + @@ -2869,13 +2869,13 @@ - + - + @@ -2885,13 +2885,13 @@ - + - + @@ -2903,13 +2903,13 @@ - + - + @@ -2919,13 +2919,13 @@ - + - + @@ -2935,13 +2935,13 @@ - + - + @@ -2951,13 +2951,13 @@ - + - + @@ -2967,13 +2967,13 @@ - + - + @@ -2983,13 +2983,13 @@ - + - + @@ -2999,13 +2999,13 @@ - + - + @@ -3015,13 +3015,13 @@ - + - + @@ -3033,13 +3033,13 @@ - + - + @@ -3049,13 +3049,13 @@ - + - + @@ -3065,13 +3065,13 @@ - + - + @@ -3081,13 +3081,13 @@ - + - + @@ -3097,13 +3097,13 @@ - + - + @@ -3113,13 +3113,13 @@ - + - + @@ -3129,13 +3129,13 @@ - + - + @@ -3145,13 +3145,13 @@ - + - + @@ -3163,13 +3163,13 @@ - + - + @@ -3179,13 +3179,13 @@ - + - + @@ -3195,13 +3195,13 @@ - + - + @@ -3211,13 +3211,13 @@ - + - + @@ -3227,13 +3227,13 @@ - + - + @@ -3243,13 +3243,13 @@ - + - + @@ -3259,13 +3259,13 @@ - + - + @@ -3275,13 +3275,13 @@ - + - + From 81965e75f6a9f71061ea8178a8cf405ba0ae1138 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:53:21 -0600 Subject: [PATCH 077/114] [Architecture] Bug fix in DFF Verilog HDL --- openfpga_flow/VerilogNetlists/dff.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 2314cae0f..5a8fcb8c2 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -17,7 +17,7 @@ module DFF ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge CK) +always @ (posedge CK) begin q_reg <= D; end From 9cb67e6097d2d75e64be2718d2aa1ceea5bccb63 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 15:19:37 -0600 Subject: [PATCH 078/114] [Architecture] Now all the configuration chain architecture use the DFFR cell by default --- .../k4_N4_40nm_fixed_sim_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_ccff_openfpga.xml | 6 +++--- .../k4_frac_N4_40nm_cc_openfpga.xml | 14 +++++++------- ...k4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 14 +++++++------- .../openfpga_arch/k6_N10_40nm_openfpga.xml | 12 ++++++------ ...6_N10_intermediate_buffer_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 14 +++++++------- ...in_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 18 +++++++++--------- ...ac_N10_adder_chain_mem16K_40nm_openfpga.xml | 14 +++++++------- ...10_adder_chain_mem16K_aib_40nm_openfpga.xml | 14 +++++++------- ...ac_N10_adder_column_chain_40nm_openfpga.xml | 14 +++++++------- ..._N10_adder_register_chain_40nm_openfpga.xml | 14 +++++++------- ...adder_register_scan_chain_40nm_openfpga.xml | 14 +++++++------- ...gister_scan_chain_depop50_40nm_openfpga.xml | 14 +++++++------- ...scan_chain_depop50_spypad_40nm_openfpga.xml | 16 ++++++++-------- .../k6_frac_N10_behavioral_40nm_openfpga.xml | 14 +++++++------- ...k6_frac_N10_local_encoder_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N10_spyio_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 14 +++++++------- .../openfpga_arch/k6_frac_N8_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N8_debuf_mux_40nm_openfpga.xml | 14 +++++++------- ...k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N8_local_encoder_40nm_openfpga.xml | 14 +++++++------- ...6_frac_N8_outbuf_only_mux_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N8_stdcell_mux_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N8_tree_mux_40nm_openfpga.xml | 14 +++++++------- 28 files changed, 192 insertions(+), 192 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml index 95359f565..dafbe687c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml @@ -146,28 +146,28 @@ - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index f6313bc22..176316e56 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,7 +146,7 @@ - + @@ -161,13 +161,13 @@ - + - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index ee5c4df5f..3e7ed7b81 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 7033f1eda..44dffdef3 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -161,25 +161,25 @@ - + - + - + - - + + - + @@ -195,7 +195,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index 81e60ee3a..f660718ed 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -146,28 +146,28 @@ - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml index 06ef4506d..e6abb5517 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -147,28 +147,28 @@ - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml index ae4e5d1e1..5b32cd890 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 6d5df7467..33d440fa3 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -196,7 +196,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 6ddb0d681..e61e0666c 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -202,7 +202,7 @@ - + @@ -218,11 +218,11 @@ - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index b8c99a382..0f0437c96 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -208,7 +208,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index c0c1aa581..f29657610 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -218,7 +218,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index 26af034f5..b881e140f 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -196,7 +196,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index e10c12d27..081b6c7a8 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -196,7 +196,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 8537cfc18..d892db3ad 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -167,25 +167,25 @@ - + - + - + - - + + - + @@ -201,7 +201,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index b815842e7..01c4db307 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -167,25 +167,25 @@ - + - + - + - - + + - + @@ -201,7 +201,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index c74625e33..ec6ce1b0e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -167,7 +167,7 @@ - + @@ -182,25 +182,25 @@ - + - + - + - - + + - + @@ -216,7 +216,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml index e4a721acb..6d1244fc4 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml index 51e8fca53..83849f927 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index 9ce18bc81..ad7e28916 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -161,18 +161,18 @@ - + - + - + - - + + @@ -183,13 +183,13 @@ - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml index cfda3061f..e134efbde 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml @@ -153,31 +153,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml index e8980c6c3..a89ef925f 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml @@ -152,31 +152,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index 74d1d9933..0dc25624d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml index b0c8c6ba0..cb84da0f3 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml index 1cb12f465..879b54a07 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml index 721fb6663..2136f24a1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml index 07b4e93d8..18abbc824 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml index da7c4b76b..a1a3de80b 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -153,31 +153,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml index b39c7a999..a5b266d3e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -152,31 +152,31 @@ - + - + - + - - + + - + - + From 79875d5a91c68f4e975dcef42b1eb2896b05b1fc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 15:27:26 -0600 Subject: [PATCH 079/114] [Architecture] Bug fix in the configuration chain arch using both reset and set --- .../k4_N4_40nm_cc_use_both_set_reset_openfpga.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml index e6f35ab03..9014b991b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -141,8 +141,8 @@ - - + + From 8468f25b238401daaf020c926f00674ace33453a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 16:31:55 -0600 Subject: [PATCH 080/114] [OpenFPGA Tool] Bug fix in the smart fast configuration strategy --- .../fpga_verilog/verilog_top_testbench.cpp | 185 +++++++++++++----- 1 file changed, 135 insertions(+), 50 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index e76c198e9..c4250bdcc 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -60,6 +60,54 @@ constexpr char* TOP_TB_CLOCK_REG_POSTFIX = "_reg"; constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX = "_autocheck_top_tb"; +/******************************************************************** + * Identify global reset ports for programming + *******************************************************************/ +static +std::vector find_global_programming_reset_ports(const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + /* Try to find global reset ports for programming */ + std::vector global_prog_reset_ports; + for (const CircuitPortId& global_port : global_ports) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + if (false == circuit_lib.port_is_prog(global_port)) { + continue; + } + VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); + VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) + || (false == circuit_lib.port_is_set(global_port))); + if (true == circuit_lib.port_is_reset(global_port)) { + global_prog_reset_ports.push_back(global_port); + } + } + + return global_prog_reset_ports; +} + +/******************************************************************** + * Identify global set ports for programming + *******************************************************************/ +static +std::vector find_global_programming_set_ports(const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + /* Try to find global set ports for programming */ + std::vector global_prog_set_ports; + for (const CircuitPortId& global_port : global_ports) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + if (false == circuit_lib.port_is_prog(global_port)) { + continue; + } + VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); + VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) + || (false == circuit_lib.port_is_set(global_port))); + if (true == circuit_lib.port_is_set(global_port)) { + global_prog_set_ports.push_back(global_port); + } + } + + return global_prog_set_ports; +} + /******************************************************************** * Print local wires for flatten memory (standalone) configuration protocols *******************************************************************/ @@ -242,7 +290,9 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, - const std::vector& global_ports) { + const std::vector& global_ports, + const bool& active_global_prog_reset, + const bool& active_global_prog_set) { /* Validate the file stream */ valid_file_stream(fp); @@ -324,10 +374,13 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + /* For global programming reset port, we will active only when specified */ BasicPort stimuli_reset_port; + bool activate = true; if (true == circuit_lib.port_is_prog(model_global_port)) { stimuli_reset_port.set_name(std::string(TOP_TB_PROG_RESET_PORT_NAME)); stimuli_reset_port.set_width(1); + activate = active_global_prog_reset; } else { VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); stimuli_reset_port.set_name(std::string(TOP_TB_RESET_PORT_NAME)); @@ -337,9 +390,15 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, * The wiring will be inverted if the default value of the global port is 1 * Otherwise, the wiring will not be inverted! */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_reset_port, - 1 == circuit_lib.port_default_value(model_global_port)); + if (true == activate) { + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_reset_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } else { + VTR_ASSERT_SAFE(false == activate); + print_verilog_wire_constant_values(fp, module_manager.module_port(top_module, module_global_port), + std::vector(1, circuit_lib.port_default_value(model_global_port))); + } } /* Connect global set ports to operating or programming set signal */ @@ -366,10 +425,13 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + /* For global programming set port, we will active only when specified */ BasicPort stimuli_set_port; + bool activate = true; if (true == circuit_lib.port_is_prog(model_global_port)) { stimuli_set_port.set_name(std::string(TOP_TB_PROG_SET_PORT_NAME)); stimuli_set_port.set_width(1); + activate = active_global_prog_set; } else { VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); stimuli_set_port.set_name(std::string(TOP_TB_SET_PORT_NAME)); @@ -379,9 +441,15 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, * The wiring will be inverted if the default value of the global port is 1 * Otherwise, the wiring will not be inverted! */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_set_port, - 1 == circuit_lib.port_default_value(model_global_port)); + if (true == activate) { + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_set_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } else { + VTR_ASSERT_SAFE(false == activate); + print_verilog_wire_constant_values(fp, module_manager.module_port(top_module, module_global_port), + std::vector(1, circuit_lib.port_default_value(model_global_port))); + } } /* For the rest of global ports, wire them to constant signals */ @@ -584,6 +652,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, static size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz_type, const bool& fast_configuration, + const bool& bit_value_to_skip, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { size_t num_config_clock_cycles = 1 + fabric_bitstream.num_bits(); @@ -602,7 +671,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz size_t full_num_config_clock_cycles = num_config_clock_cycles; size_t num_bits_to_skip = 0; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + if (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { break; } num_bits_to_skip++; @@ -623,7 +692,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz size_t full_num_config_clock_cycles = num_config_clock_cycles; num_config_clock_cycles = 1; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (true == fabric_bitstream.bit_din(bit_id)) { + if (bit_value_to_skip != fabric_bitstream.bit_din(bit_id)) { num_config_clock_cycles++; } } @@ -1008,11 +1077,11 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp, fp << std::endl; /* Programming set signal for configuration circuit : always disabled */ - print_verilog_comment(fp, "----- Begin programming set signal generation: always disabled -----"); + print_verilog_comment(fp, "----- Begin programming set signal generation -----"); print_verilog_pulse_stimuli(fp, prog_set_port, - 0, /* Initial value */ + 1, /* Initial value */ prog_clock_period / timescale, 0); - print_verilog_comment(fp, "----- End programming set signal generation: always disabled -----"); + print_verilog_comment(fp, "----- End programming set signal generation -----"); fp << std::endl; @@ -1526,41 +1595,11 @@ static void print_verilog_top_testbench_bitstream(std::fstream& fp, const e_config_protocol_type& config_protocol_type, const bool& fast_configuration, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, + const bool& bit_value_to_skip, const ModuleManager& module_manager, const ModuleId& top_module, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { - /* Try to find global reset/set ports for programming */ - std::vector global_prog_reset_ports; - std::vector global_prog_set_ports; - for (const CircuitPortId& global_port : global_ports) { - VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); - if (false == circuit_lib.port_is_prog(global_port)) { - continue; - } - VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); - VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) - || (false == circuit_lib.port_is_set(global_port))); - if (true == circuit_lib.port_is_reset(global_port)) { - global_prog_reset_ports.push_back(global_port); - } - if (true == circuit_lib.port_is_set(global_port)) { - global_prog_set_ports.push_back(global_port); - } - } - - bool apply_fast_configuration = fast_configuration; - if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) - && (true == fast_configuration)) { - VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n"); - } - bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol_type, - apply_fast_configuration, - global_prog_reset_ports, - global_prog_set_ports, - bitstream_manager, fabric_bitstream); /* Branch on the type of configuration protocol */ switch (config_protocol_type) { @@ -1570,18 +1609,18 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_SCAN_CHAIN: - print_verilog_top_testbench_configuration_chain_bitstream(fp, apply_fast_configuration, + print_verilog_top_testbench_configuration_chain_bitstream(fp, fast_configuration, bit_value_to_skip, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_MEMORY_BANK: - print_verilog_top_testbench_memory_bank_bitstream(fp, apply_fast_configuration, + print_verilog_top_testbench_memory_bank_bitstream(fp, fast_configuration, bit_value_to_skip, module_manager, top_module, fabric_bitstream); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_bitstream(fp, apply_fast_configuration, + print_verilog_top_testbench_frame_decoder_bitstream(fp, fast_configuration, bit_value_to_skip, module_manager, top_module, fabric_bitstream); @@ -1652,6 +1691,23 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Preparation: find all the clock ports */ std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); + /* Preparation: find all the reset/set ports for programming usage */ + std::vector global_prog_reset_ports = find_global_programming_reset_ports(circuit_lib, global_ports); + std::vector global_prog_set_ports = find_global_programming_set_ports(circuit_lib, global_ports); + + /* Identify if we can apply fast configuration */ + bool apply_fast_configuration = fast_configuration; + if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) + && (true == fast_configuration)) { + VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n"); + apply_fast_configuration = false; + } + bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(), + apply_fast_configuration, + global_prog_reset_ports, + global_prog_set_ports, + bitstream_manager, fabric_bitstream); + /* Start of testbench */ print_verilog_top_testbench_ports(fp, module_manager, top_module, atom_ctx, netlist_annotation, clock_port_names, @@ -1663,7 +1719,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, float op_clock_period = (1./simulation_parameters.operating_clock_frequency()); /* Estimate the number of configuration clock cycles */ size_t num_config_clock_cycles = calculate_num_config_clock_cycles(config_protocol.type(), - fast_configuration, + apply_fast_configuration, + bit_value_to_skip, bitstream_manager, fabric_bitstream); @@ -1674,10 +1731,38 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, op_clock_period, VERILOG_SIM_TIMESCALE); + /* Identify the stimulus for global reset/set for programming purpose: + * - If only reset port is seen we turn on Reset + * - If only set port is seen we turn on Reset + * - If both reset and set port is defined, + * we pick the one which is consistent with the bit value to be skipped + */ + bool active_global_prog_reset = false; + bool active_global_prog_set = false; + + if (!global_prog_reset_ports.empty()) { + active_global_prog_reset = true; + } + + if (!global_prog_set_ports.empty()) { + active_global_prog_set = true; + } + + /* Ensure that at most only one of the two switches is activated */ + if ( (true == active_global_prog_reset) + && (true == active_global_prog_set) ) { + /* If we will skip logic '0', we will activate programming reset */ + active_global_prog_reset = !bit_value_to_skip; + /* If we will skip logic '1', we will activate programming set */ + active_global_prog_set = bit_value_to_skip; + } + /* Generate stimuli for global ports or connect them to existed signals */ print_verilog_top_testbench_global_ports_stimuli(fp, module_manager, top_module, - circuit_lib, global_ports); + circuit_lib, global_ports, + active_global_prog_reset, + active_global_prog_set); /* Instanciate FPGA top-level module */ print_verilog_testbench_fpga_instance(fp, module_manager, top_module, @@ -1706,8 +1791,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* load bitstream to FPGA fabric in a configuration phase */ print_verilog_top_testbench_bitstream(fp, config_protocol.type(), - fast_configuration, - circuit_lib, global_ports, + apply_fast_configuration, + bit_value_to_skip, module_manager, top_module, bitstream_manager, fabric_bitstream); From 4d94fcb2982935f65a387ab662fd712659ed01d9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 16:38:34 -0600 Subject: [PATCH 081/114] [Regression Test] Bug fix in calling test cases --- .travis/basic_reg_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 2eb3da47a..53dd98393 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -18,7 +18,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; From fc154b8560a2f30c44b4e6bc1d3c659106069c54 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 16:45:56 -0600 Subject: [PATCH 082/114] [Architecture] Bug fix due to switching CCFF cell --- .../openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 176316e56..ca630da7e 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,15 +146,15 @@ - + - + - + - + From 2d81ff90121b9984f9e022ec7133b33a510e0554 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 16:59:52 -0600 Subject: [PATCH 083/114] [Regression test] Add configuration chain test case where both set and reset are used --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf new file mode 100644 index 000000000..288a3564a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 335f5b78c12c7495e86e8505bc930d01a6f98430 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:02:28 -0600 Subject: [PATCH 084/114] [Regression Test] Add test case to use both set and reset for configuration frame --- .../config/task.conf | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf new file mode 100644 index 000000000..548e37cb8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 19dd3778d9a5a0237350751d9bd851f113d63be9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:04:24 -0600 Subject: [PATCH 085/114] [Architecture] Add test case for memory bank to use both reset and set --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf new file mode 100644 index 000000000..855e3156e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From a30255b2a441e92c70ec1b7f347e714010de2cae Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:04:43 -0600 Subject: [PATCH 086/114] [Regression Test] Deploy new test cases to CI --- .travis/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 53dd98393..f84af4b37 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -16,6 +16,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs @@ -32,6 +33,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; @@ -40,6 +42,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs From 0a5369f919a4e0fd9ebdae51213ce6f47e8d2851 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:26:48 -0600 Subject: [PATCH 087/114] [Architecture] Adapt all the architecture files to use standard DFF cell --- openfpga_flow/VerilogNetlists/dff.v | 34 +++++++++++++++++++ .../k4_N4_40nm_bank_openfpga.xml | 14 ++++---- ..._40nm_bank_use_both_set_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_bank_use_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 10 +++--- .../k4_N4_40nm_bank_use_set_openfpga.xml | 10 +++--- .../k4_N4_40nm_bank_use_setb_openfpga.xml | 10 +++--- .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 10 +++--- ...N4_40nm_cc_use_both_set_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_cc_use_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_cc_use_resetb_openfpga.xml | 10 +++--- .../k4_N4_40nm_cc_use_set_openfpga.xml | 10 +++--- .../k4_N4_40nm_cc_use_setb_openfpga.xml | 10 +++--- .../k4_N4_40nm_fixed_sim_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_ccff_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_scff_openfpga.xml | 10 +++--- ...40nm_frame_use_both_set_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_use_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_use_set_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_use_setb_openfpga.xml | 10 +++--- .../k4_N4_40nm_powergate_frame_openfpga.xml | 10 +++--- .../k4_N4_40nm_standalone_openfpga.xml | 10 +++--- ...4_no_local_routing_40nm_frame_openfpga.xml | 10 +++--- ...tern_local_routing_40nm_frame_openfpga.xml | 10 +++--- .../k4_frac_N4_40nm_cc_openfpga.xml | 10 +++--- ...4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 10 +++--- ..._adder_chain_mem1K_40nm_frame_openfpga.xml | 12 +++---- ...r_chain_mem1K_L124_40nm_frame_openfpga.xml | 12 +++---- ...n_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 12 +++---- .../openfpga_arch/k6_N10_40nm_openfpga.xml | 10 +++--- ..._N10_intermediate_buffer_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 10 +++--- ...n_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 12 +++---- ...c_N10_adder_chain_mem16K_40nm_openfpga.xml | 12 +++---- ...0_adder_chain_mem16K_aib_40nm_openfpga.xml | 12 +++---- ...c_N10_adder_column_chain_40nm_openfpga.xml | 10 +++--- ...N10_adder_register_chain_40nm_openfpga.xml | 10 +++--- ...dder_register_scan_chain_40nm_openfpga.xml | 8 ++--- ...ister_scan_chain_depop50_40nm_openfpga.xml | 8 ++--- ...can_chain_depop50_spypad_40nm_openfpga.xml | 8 ++--- .../k6_frac_N10_behavioral_40nm_openfpga.xml | 10 +++--- ...6_frac_N10_local_encoder_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_spyio_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 10 +++--- .../k6_frac_N8_40nm_openfpga.xml | 10 +++--- .../k6_frac_N8_debuf_mux_40nm_openfpga.xml | 10 +++--- ...6_frac_N8_inbuf_only_mux_40nm_openfpga.xml | 10 +++--- ...k6_frac_N8_local_encoder_40nm_openfpga.xml | 10 +++--- ..._frac_N8_outbuf_only_mux_40nm_openfpga.xml | 10 +++--- .../k6_frac_N8_stdcell_mux_40nm_openfpga.xml | 10 +++--- .../k6_frac_N8_tree_mux_40nm_openfpga.xml | 10 +++--- 55 files changed, 309 insertions(+), 275 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 5a8fcb8c2..25701e694 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -203,6 +203,40 @@ end endmodule //End Of Module +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +//----------------------------------------------------- +module DFFSRQ ( + input SET, // set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; +`else + assign Q = 1'bZ; +`endif + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index 45fa552d0..fd4379b60 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -124,15 +124,15 @@ - + - - - - - + + + + + @@ -192,7 +192,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index 95c93a6db..7a03fcefd 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -194,7 +194,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml index 33581d64a..349d71e0d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml index 184c5b14c..2c0705f83 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml index 904ee811a..296593272 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml index 68a29312a..69267a999 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index acf0311f1..b137b5f74 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -183,7 +183,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml index 9014b991b..566fb305d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -185,7 +185,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml index 6554e98a0..85787e154 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml index bd18bffce..95f33581c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml index 290c36e9c..1e0a9a422 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml index 1700117d9..23ba4e1f3 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml index dafbe687c..e9ccfdbe5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index ca630da7e..0419f0f3d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index 681c67cae..a21fa751c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -192,7 +192,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index 7ccada510..ccaa8b66c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -195,7 +195,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index 298b49e30..e6f401309 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -194,7 +194,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml index 5ee20c2e1..449ed1740 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml index 1866e8ec1..e2f838905 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index e92172048..a2315d5a1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index c2001aa5e..20189c8a5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index 37292c40e..118a12b5a 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -130,15 +130,15 @@ - + - - + + - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 43dd1e3f1..0d9a0e85d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index 2f6a960d1..24a296aa3 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -189,7 +189,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index d0b63dd2b..aa04235c4 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -206,7 +206,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index 3e7ed7b81..61280345a 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 44dffdef3..70896f503 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -225,7 +225,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 118f082b4..20a91779d 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + @@ -237,7 +237,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 4e9e16e79..89eb8d37f 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + @@ -241,7 +241,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 5124e11a1..6dffbfd2c 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + @@ -247,7 +247,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index f660718ed..1f6370321 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml index e6abb5517..750ff9fac 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -194,7 +194,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml index 5b32cd890..6dc828cc6 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 33d440fa3..6c30d6381 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index e61e0666c..937dd27f1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -216,7 +216,7 @@ - + @@ -252,7 +252,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 0f0437c96..12117aad3 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -204,7 +204,7 @@ - + @@ -238,7 +238,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index f29657610..f3a821c95 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -204,7 +204,7 @@ - + @@ -250,7 +250,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index b881e140f..2253f034d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 081b6c7a8..63c47f5d6 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -227,7 +227,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index d892db3ad..9d1185882 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -142,17 +142,17 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - + + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 01c4db307..3303e65b8 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -142,17 +142,17 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - + + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index ec6ce1b0e..df6418450 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -142,17 +142,17 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - + + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml index 6d1244fc4..6fb6bc2c8 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml index 83849f927..75387fa12 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index ad7e28916..9d8a77ee4 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -216,7 +216,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml index e134efbde..1aa072294 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml @@ -131,15 +131,15 @@ - + - - + + - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml index a89ef925f..d2e505db0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml @@ -130,15 +130,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index 0dc25624d..fee0b0f2d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml index cb84da0f3..ab2309ec1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml index 879b54a07..dd13e5003 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml index 2136f24a1..8ce4a01a1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml index 18abbc824..395a166f0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml index a1a3de80b..2821a6f36 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -131,15 +131,15 @@ - + - - + + - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml index a5b266d3e..d7bf58889 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -130,15 +130,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + From 49d6863641909c2f13f4c7d5f82c1a9281f8b602 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:33:14 -0600 Subject: [PATCH 088/114] [Architecture] Bug fix for scan-chain FF cell renaming --- openfpga_flow/VerilogNetlists/dff.v | 9 +++------ ...rac_N10_adder_register_scan_chain_40nm_openfpga.xml | 8 ++++---- ...adder_register_scan_chain_depop50_40nm_openfpga.xml | 6 +++--- ...egister_scan_chain_depop50_spypad_40nm_openfpga.xml | 10 +++++----- 4 files changed, 15 insertions(+), 18 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 25701e694..3e767d8c4 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -244,15 +244,14 @@ endmodule //End Of Module // - scan-chain input // - a scan-chain enable //----------------------------------------------------- -module SDFFSR ( +module SDFFSRQ ( input SET, // Set input input RST, // Reset input - input SE, // Scan-chain Enable - input SI, // Scan-chain input input CK, // Clock Input + input SE, // Scan-chain Enable input D, // Data Input + input SI, // Scan-chain input output Q, // Q output - output QN // QB output ); //------------Internal Variables-------- reg q_reg; @@ -272,10 +271,8 @@ end `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q assign Q = q_reg; - assign QN = ~q_reg; `else assign Q = 1'bZ; - assign QN = !Q; `endif endmodule //End Of Module diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 9d1185882..41867db36 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -142,13 +142,13 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - + + @@ -233,7 +233,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 3303e65b8..1aa06737b 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -142,13 +142,13 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - + @@ -228,7 +228,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index df6418450..f288f47ef 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -142,13 +142,13 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - + @@ -243,7 +243,7 @@ - + @@ -278,7 +278,7 @@ - + @@ -311,7 +311,7 @@ - + From 54b3f244d3bddefb3c2c26ac9d08c9f60dc480f6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:35:02 -0600 Subject: [PATCH 089/114] [Architecture] Remove obsolete Verilog netlists --- openfpga_flow/VerilogNetlists/ff.v | 146 -------------------------- openfpga_flow/VerilogNetlists/ff_en.v | 40 ------- 2 files changed, 186 deletions(-) delete mode 100644 openfpga_flow/VerilogNetlists/ff.v delete mode 100644 openfpga_flow/VerilogNetlists/ff_en.v diff --git a/openfpga_flow/VerilogNetlists/ff.v b/openfpga_flow/VerilogNetlists/ff.v deleted file mode 100644 index 2f2477f24..000000000 --- a/openfpga_flow/VerilogNetlists/ff.v +++ /dev/null @@ -1,146 +0,0 @@ -//----------------------------------------------------- -// Design Name : static_dff -// File Name : ff.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -//------ Include defines: preproc flags ----- -// `include "./SRC/fpga_defines.v" -module static_dff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; - -endmodule //End Of Module static_dff - -module scan_chain_ff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -input TESTEN, // Clock Input -/* Local ports follow */ -input D, // Data Input -input DI, // Scan Chain Data Input -output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else if (TESTEN) begin - q_reg <= DI; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; - -endmodule //End Of Module static_dff - - -//----------------------------------------------------- -// Design Name : scan_chain_dff -// File Name : ff.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -module sc_dff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~Q; - -endmodule //End Of Module static_dff - -//----------------------------------------------------- -// Design Name : scan_chain_dff compact -// File Name : ff.v -// Function : Scan-chain D flip-flop without reset and set //Modified to fit Edouards architecture -// Coder : Xifan TANG -//----------------------------------------------------- -module sc_dff_compact ( -/* Global ports go first */ -input reset, // Reset input -//input set, // set input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset /*or posedge set*/) -if (reset) begin - q_reg <= 1'b0; -//end else if (set) begin -// q_reg <= 1'b1; -end else begin - q_reg <= D; -end -/* -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~Q; -*/ - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule //End Of Module static_dff diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v deleted file mode 100644 index 11b657a9f..000000000 --- a/openfpga_flow/VerilogNetlists/ff_en.v +++ /dev/null @@ -1,40 +0,0 @@ -//----------------------------------------------------- -// Design Name : D-type Flip-flop with Write Enable -// File Name : ff_en.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -module DFF_EN ( -/* Global ports go first */ -input SET, // set input -input RST, // Reset input -input WE, // Write Enable -input CK, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output QB // QB output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST or posedge SET) -if (RST) begin - q_reg <= 1'b0; -end else if (SET) begin - q_reg <= 1'b1; -end else if (WE) begin - q_reg <= D; -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign QB = ~q_reg; -`else -assign Q = 1'bZ; -assign QB = !Q; -`endif - -endmodule //End Of Module From 749455631670ccea28c5da4a9905e14d9a9dfd3f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:38:16 -0600 Subject: [PATCH 090/114] [Architecture] Bug fix for scan-chain FF cell --- openfpga_flow/VerilogNetlists/dff.v | 43 +++++++++++++++++++ .../k4_N4_40nm_frame_scff_openfpga.xml | 7 +-- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 3e767d8c4..6f62e627c 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -237,6 +237,49 @@ end endmodule //End Of Module +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFSR ( + input SET, // Set input + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q + assign Q = q_reg; + assign QN = !Q; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index ccaa8b66c..3ed8a652b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -146,17 +146,18 @@ - + - + - + + From 3e7c88eac85091de439ac3152540eddfaa6eebf6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:41:03 -0600 Subject: [PATCH 091/114] [Architecture] Bug fix in Verilog netlist for scan-chain DFF --- openfpga_flow/VerilogNetlists/dff.v | 4 ++-- .../openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 6f62e627c..6ed1428d4 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -213,7 +213,7 @@ module DFFSRQ ( input RST, // Reset input input CK, // Clock Input input D, // Data Input - output Q, // Q output + output Q // Q output ); //------------Internal Variables-------- reg q_reg; @@ -294,7 +294,7 @@ module SDFFSRQ ( input SE, // Scan-chain Enable input D, // Data Input input SI, // Scan-chain input - output Q, // Q output + output Q // Q output ); //------------Internal Variables-------- reg q_reg; diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index 3ed8a652b..53b5e2ebd 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -155,7 +155,7 @@ - + @@ -164,13 +164,13 @@ - + - + From 3ade6d6ff5ba7e3118f28edf11d61b3940d5ea39 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:53:30 -0600 Subject: [PATCH 092/114] [Architecture] Bug fix for dff that are used in data path --- openfpga_flow/VerilogNetlists/dff.v | 14 ++------------ ...k4_N4_40nm_bank_use_both_set_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_set_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_setb_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 6 +++--- 7 files changed, 20 insertions(+), 30 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 6ed1428d4..8803e1239 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -228,12 +228,7 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; -`else - assign Q = 1'bZ; -`endif +assign Q = q_reg; endmodule //End Of Module @@ -311,11 +306,6 @@ end else begin q_reg <= D; end -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q - assign Q = q_reg; -`else - assign Q = 1'bZ; -`endif +assign Q = q_reg; endmodule //End Of Module diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index 7a03fcefd..e5ce87852 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml index 349d71e0d..86fc2e5fc 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml index 2c0705f83..c6c589f66 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml index 296593272..b1b339401 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml index 69267a999..d84703d52 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index b137b5f74..c119e0b9a 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -120,10 +120,10 @@ - - + + - + From d51efd397ffcfb40667d13f7b56257dd32640b98 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 18:02:42 -0600 Subject: [PATCH 093/114] [Architecture] Bug fix for architectures using DFF cells --- openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index fd4379b60..a6b32fdd9 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + @@ -192,7 +192,7 @@ - + From 60a14ccbd21184ce04ce170497f0591572db42fa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 18:20:55 -0600 Subject: [PATCH 094/114] [Architecture] Bug fix in architectures that use BRAM --- .../k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml | 2 +- .../k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml | 2 +- ...frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 2 +- ...rac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 2 +- .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml | 2 +- .../k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 20a91779d..09fe2c681 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 89eb8d37f..79980dacc 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 6dffbfd2c..d5c6fff86 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 937dd27f1..3b1ab1732 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -216,7 +216,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 12117aad3..92f56df47 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index f3a821c95..2543f9096 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -204,7 +204,7 @@ - + From eb5fd1f44eba9f7225ceb26aeb27011d31bd5cef Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 18:37:25 -0600 Subject: [PATCH 095/114] [Architecture] Bug fix for architectures using scan-chain DFF cell --- ...frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml | 2 +- ...0_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 1aa06737b..a3d5b3bb7 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index f288f47ef..ac7547e57 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -147,7 +147,7 @@ - + From e0f9547f5b9e5c23238eb294047c3b16b9e99552 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 19:53:54 -0600 Subject: [PATCH 096/114] [Architecture] Rework the i/o cell Verilog HDL --- openfpga_flow/VerilogNetlists/gpio.v | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/gpio.v diff --git a/openfpga_flow/VerilogNetlists/gpio.v b/openfpga_flow/VerilogNetlists/gpio.v new file mode 100644 index 000000000..5fb318f3d --- /dev/null +++ b/openfpga_flow/VerilogNetlists/gpio.v @@ -0,0 +1,20 @@ +//----------------------------------------------------- +// Design Name : General Purpose I/Os +// File Name : gpio.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A minimum general purpose I/O +//----------------------------------------------------- +module GPIO ( + input A, // Data output + output Y, // Data input + inout PAD, // bi-directional pad + input DIR // direction control +); + //----- when direction enabled, the signal is propagated from PAD to data input + assign Y = DIR ? PAD : 1'bz; + //----- when direction is disabled, the signal is propagated from data out to pad + assign PAD = DIR ? 1'bz : A; +endmodule From 4a0a4481710ef04f247b8e003e0cec550a451d22 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 19:56:01 -0600 Subject: [PATCH 097/114] [Architecture] Rename openfpga architecture for the I/O cell --- openfpga_flow/VerilogNetlists/io.v | 16 ---------------- .../openfpga_arch/k4_N4_40nm_bank_openfpga.xml | 12 ++++++------ ..._N4_40nm_bank_use_both_set_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_bank_use_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_bank_use_set_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_bank_use_setb_openfpga.xml | 12 ++++++------ .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 12 ++++++------ ...k4_N4_40nm_cc_use_both_set_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_cc_use_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_cc_use_resetb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_cc_use_set_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_cc_use_setb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_fixed_sim_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_ccff_openfpga.xml | 12 ++++++------ .../openfpga_arch/k4_N4_40nm_frame_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_scff_openfpga.xml | 12 ++++++------ ...N4_40nm_frame_use_both_set_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_use_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_use_set_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_use_setb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_powergate_frame_openfpga.xml | 14 +++++++------- .../k4_N4_40nm_standalone_openfpga.xml | 12 ++++++------ ...4_N4_no_local_routing_40nm_frame_openfpga.xml | 12 ++++++------ ...pattern_local_routing_40nm_frame_openfpga.xml | 12 ++++++------ .../k4_frac_N4_40nm_cc_openfpga.xml | 12 ++++++------ .../k4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 12 ++++++------ ..._N4_adder_chain_mem1K_40nm_frame_openfpga.xml | 12 ++++++------ ...dder_chain_mem1K_L124_40nm_frame_openfpga.xml | 12 ++++++------ ...hain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 12 ++++++------ .../openfpga_arch/k6_N10_40nm_openfpga.xml | 12 ++++++------ .../k6_N10_intermediate_buffer_40nm_openfpga.xml | 12 ++++++------ .../openfpga_arch/k6_frac_N10_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 12 ++++++------ ...hain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 12 ++++++------ ...frac_N10_adder_chain_mem16K_40nm_openfpga.xml | 12 ++++++------ ..._N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 14 +++++++------- ...frac_N10_adder_column_chain_40nm_openfpga.xml | 12 ++++++------ ...ac_N10_adder_register_chain_40nm_openfpga.xml | 12 ++++++------ ...0_adder_register_scan_chain_40nm_openfpga.xml | 12 ++++++------ ...register_scan_chain_depop50_40nm_openfpga.xml | 12 ++++++------ ...r_scan_chain_depop50_spypad_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_behavioral_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_local_encoder_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_spyio_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 12 ++++++------ .../openfpga_arch/k6_frac_N8_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_debuf_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_local_encoder_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_stdcell_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_tree_mux_40nm_openfpga.xml | 12 ++++++------ 55 files changed, 326 insertions(+), 342 deletions(-) delete mode 100644 openfpga_flow/VerilogNetlists/io.v diff --git a/openfpga_flow/VerilogNetlists/io.v b/openfpga_flow/VerilogNetlists/io.v deleted file mode 100644 index 9fccdd23d..000000000 --- a/openfpga_flow/VerilogNetlists/io.v +++ /dev/null @@ -1,16 +0,0 @@ -//------ Module: iopad -----// -//------ Verilog file: io.v -----// -//------ Author: Xifan TANG -----// -module iopad( -//input zin, // Set output to be Z -input outpad, // Data output -output inpad, // Data input -inout pad, // bi-directional pad -input en // enable signal to control direction of iopad -//input direction_inv // enable signal to control direction of iopad -); - //----- when direction enabled, the signal is propagated from pad to din - assign inpad = en ? pad : 1'bz; - //----- when direction is disabled, the signal is propagated from dout to pad - assign pad = en ? 1'bz : outpad; -endmodule diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index a6b32fdd9..e2ce76956 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -155,14 +155,14 @@ - + - - - - + + + + @@ -180,7 +180,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index e5ce87852..d8f97ba41 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -157,14 +157,14 @@ - + - - - - + + + + @@ -182,7 +182,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml index 86fc2e5fc..427889368 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml index c6c589f66..d03b2d2be 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml index b1b339401..fec761135 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml index d84703d52..dc3c89739 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index c119e0b9a..a36a863fd 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -146,14 +146,14 @@ - + - - - - + + + + @@ -171,7 +171,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml index 566fb305d..762fc1af3 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -148,14 +148,14 @@ - + - - - - + + + + @@ -173,7 +173,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml index 85787e154..c74d0aedb 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml @@ -147,14 +147,14 @@ - + - - - - + + + + @@ -172,7 +172,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml index 95f33581c..3e453fb3f 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml @@ -147,14 +147,14 @@ - + - - - - + + + + @@ -172,7 +172,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml index 1e0a9a422..78461fadc 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml @@ -147,14 +147,14 @@ - + - - - - + + + + @@ -172,7 +172,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml index 23ba4e1f3..ee990043b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml @@ -147,14 +147,14 @@ - + - - - - + + + + @@ -172,7 +172,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml index e9ccfdbe5..dced448a2 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 0419f0f3d..5d9aee9eb 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index a21fa751c..92b7930c7 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -155,14 +155,14 @@ - + - - - - + + + + @@ -180,7 +180,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index 53b5e2ebd..ff3f2e1b0 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -159,14 +159,14 @@ - + - - - - + + + + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index e6f401309..7495f9c3b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -157,14 +157,14 @@ - + - - - - + + + + @@ -182,7 +182,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml index 449ed1740..0b7f14a25 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml index e2f838905..f43436de5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index a2315d5a1..cee0fbc79 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index 20189c8a5..7ba360992 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index 118a12b5a..0d03dc6d6 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -36,7 +36,7 @@ - + @@ -162,14 +162,14 @@ - + - - - - + + + + @@ -187,7 +187,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 0d9a0e85d..3392eef23 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index 24a296aa3..cf0502130 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index aa04235c4..6366425e0 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index 61280345a..ceef842c0 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 70896f503..d293c206e 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 09fe2c681..57ba20070 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -224,7 +224,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 79980dacc..45614dd10 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -228,7 +228,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index d5c6fff86..8746805da 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -234,7 +234,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index 1f6370321..9c8e66a87 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml index 750ff9fac..e0e8cd461 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -157,14 +157,14 @@ - + - - - - + + + + @@ -182,7 +182,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml index 6dc828cc6..3afe5a693 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 6c30d6381..66f172080 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -213,7 +213,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 3b1ab1732..f883dc1d2 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -239,7 +239,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 92f56df47..b83c1c63a 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -225,7 +225,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index 2543f9096..08d2ca9ed 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -214,7 +214,7 @@ - + @@ -237,7 +237,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index 2253f034d..1a7b74700 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -213,7 +213,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 63c47f5d6..6305544b2 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -214,7 +214,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 41867db36..93589b263 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -180,14 +180,14 @@ - + - - - - + + + + @@ -220,7 +220,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index a3d5b3bb7..da3e8ec60 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -180,14 +180,14 @@ - + - - - - + + + + @@ -219,7 +219,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index ac7547e57..1f07c79dc 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -195,14 +195,14 @@ - + - - - - + + + + @@ -234,7 +234,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml index 6fb6bc2c8..a0d9be879 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml index 75387fa12..ef3bf9f21 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index 9d8a77ee4..f9fcfe148 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -174,18 +174,18 @@ - + - + - - - + + + @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml index 1aa072294..588e88620 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml @@ -166,14 +166,14 @@ - + - - - - + + + + @@ -191,7 +191,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml index d2e505db0..da9767f10 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml @@ -165,14 +165,14 @@ - + - - - - + + + + @@ -190,7 +190,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index fee0b0f2d..098e7ba2e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml index ab2309ec1..53dda3357 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml index dd13e5003..f050bd8a7 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml index 8ce4a01a1..ec3f99c4d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml index 395a166f0..cab4ef22b 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml index 2821a6f36..e367ff8bb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -166,14 +166,14 @@ - + - - - - + + + + @@ -191,7 +191,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml index d7bf58889..0585bf591 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -165,14 +165,14 @@ - + - - - - + + + + @@ -190,7 +190,7 @@ - + From 53187044e6a2e22846efeacb22f90abb4da7813d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:07:57 -0600 Subject: [PATCH 098/114] [Architecture] Rename adder cell --- openfpga_flow/VerilogNetlists/adder.v | 33 ++++++++++++++------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/adder.v b/openfpga_flow/VerilogNetlists/adder.v index da288c9b9..fa13384d9 100644 --- a/openfpga_flow/VerilogNetlists/adder.v +++ b/openfpga_flow/VerilogNetlists/adder.v @@ -1,19 +1,20 @@ -//------ Module: sram6T_blwl -----// -//------ Verilog file: sram.v -----// -//------ Author: Xifan TANG -----// -module adder( -input [0:0] a, // Input a -input [0:0] b, // Input b -input [0:0] cin, // Input cin -output [0:0] cout, // Output carry -output [0:0] sumout // Output sum -); -//wire[1:0] int_calc; +//----------------------------------------------------- +// Design Name : Multi-bit Full Adder +// File Name : adder.v +// Coder : Xifan TANG +//----------------------------------------------------- -//assign int_calc = a + b + cin; -//assign cout = int_calc[1]; -//assign sumout = int_calc[0]; - assign sumout = a ^ b ^ cin; - assign cout = (a & b) | (a & cin) | (b & cin); +//----------------------------------------------------- +// Function : A 1-bit full adder +//----------------------------------------------------- +module ADDF( + input [0:0] A, // Input a + input [0:0] B, // Input b + input [0:0] CI, // Input cin + output [0:0] CO, // Output carry + output [0:0] SUM // Output sum +); + assign SUM = A ^ B ^ CI; + assign CO = (A & B) | (A & CI) | (B & CI); endmodule From 4ada793c84c9bb34a84295667fc60178400e582c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:09:29 -0600 Subject: [PATCH 099/114] [Architecture] Adapt openfpga architecture to follow the renamed adder cell --- ...4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 18 +++++++-------- ..._adder_chain_mem1K_40nm_frame_openfpga.xml | 18 +++++++-------- ...r_chain_mem1K_L124_40nm_frame_openfpga.xml | 18 +++++++-------- ...n_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 22 +++++++++---------- .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 18 +++++++-------- ...n_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 22 +++++++++---------- ...c_N10_adder_chain_mem16K_40nm_openfpga.xml | 18 +++++++-------- ...0_adder_chain_mem16K_aib_40nm_openfpga.xml | 18 +++++++-------- ...c_N10_adder_column_chain_40nm_openfpga.xml | 18 +++++++-------- ...N10_adder_register_chain_40nm_openfpga.xml | 18 +++++++-------- ...dder_register_scan_chain_40nm_openfpga.xml | 18 +++++++-------- ...ister_scan_chain_depop50_40nm_openfpga.xml | 18 +++++++-------- ...can_chain_depop50_spypad_40nm_openfpga.xml | 22 +++++++++---------- 13 files changed, 123 insertions(+), 123 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index d293c206e..114ffecad 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -183,15 +183,15 @@ - + - - - - - + + + + + @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 57ba20070..56b3a3b0d 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -183,15 +183,15 @@ - + - - - - - + + + + + @@ -238,7 +238,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 45614dd10..e44bfbff4 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -183,15 +183,15 @@ - + - - - - - + + + + + @@ -242,7 +242,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 8746805da..d51bd7215 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -183,15 +183,15 @@ - + - - - - - + + + + + @@ -209,8 +209,8 @@ - - + + @@ -248,7 +248,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 66f172080..4fec07c77 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -227,7 +227,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index f883dc1d2..cc50bf9ed 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,22 +184,22 @@ - + - - - - - + + + + + - - + + @@ -253,7 +253,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index b83c1c63a..e9b25c714 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -239,7 +239,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index 08d2ca9ed..34474e19e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -251,7 +251,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index 1a7b74700..2e82fedfc 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -227,7 +227,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 6305544b2..10b8f2ba4 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -228,7 +228,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 93589b263..4d7ba7fd0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -189,15 +189,15 @@ - + - - - - - + + + + + @@ -234,7 +234,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index da3e8ec60..455688737 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -189,15 +189,15 @@ - + - - - - - + + + + + @@ -229,7 +229,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 1f07c79dc..6f0b235ba 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -204,15 +204,15 @@ - + - - - - - + + + + + @@ -244,7 +244,7 @@ - + @@ -279,7 +279,7 @@ - + @@ -312,7 +312,7 @@ - + From 8edfc79f53b76751e0dc25373c5767794fe2c121 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:11:21 -0600 Subject: [PATCH 100/114] [Architecture] Rename AIB cell --- openfpga_flow/VerilogNetlists/aib.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/VerilogNetlists/aib.v index 2ebfd5cea..86ea4f671 100644 --- a/openfpga_flow/VerilogNetlists/aib.v +++ b/openfpga_flow/VerilogNetlists/aib.v @@ -5,12 +5,12 @@ // Coder : Xifan Tang //----------------------------------------------------- -module aib ( - input tx_clk, - input rx_clk, - inout[0:79] pad, - input[0:79] tx_data, - output[0:79] rx_data); +module AIB ( + input TXCLK, + input RXCLK, + inout[0:79] PAD, + input[0:79] TXDATA, + output[0:79] RXDATA); // May add the logic function of a real AIB // Refer to the offical AIB github From bd0f0144a0724ffcfe4dd0fd514f00c077cb2750 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:14:16 -0600 Subject: [PATCH 101/114] [Architecture] Rename AIB architecture for the new cell naming --- openfpga_flow/VerilogNetlists/aib.v | 8 ++++---- ...frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/VerilogNetlists/aib.v index 86ea4f671..8d1b9e6da 100644 --- a/openfpga_flow/VerilogNetlists/aib.v +++ b/openfpga_flow/VerilogNetlists/aib.v @@ -6,11 +6,11 @@ //----------------------------------------------------- module AIB ( - input TXCLK, - input RXCLK, + input TX_CLK, + input RX_CLK, inout[0:79] PAD, - input[0:79] TXDATA, - output[0:79] RXDATA); + input[0:79] TX_DATA, + output[0:79] RX_DATA); // May add the logic function of a real AIB // Refer to the offical AIB github diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index 34474e19e..c1a7d8d3d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -206,14 +206,14 @@ - + - - - - + + + + @@ -234,7 +234,7 @@ - + From e4bfa2ef51ad54432b51f735ec4851bb2b489088 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:16:50 -0600 Subject: [PATCH 102/114] [Architecture] Update external bitstream file --- .../and2_k4_N4_tileable_40nm_bitstream.xml | 258 +++++++++--------- 1 file changed, 129 insertions(+), 129 deletions(-) diff --git a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml index 7b6e5d3cd..07a874f86 100644 --- a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml +++ b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Thu Sep 24 14:40:51 2020 + - Date: Thu Sep 24 20:16:32 2020 --> @@ -2253,13 +2253,13 @@ - + - + @@ -2269,13 +2269,13 @@ - + - + @@ -2285,13 +2285,13 @@ - + - + @@ -2301,13 +2301,13 @@ - + - + @@ -2317,13 +2317,13 @@ - + - + @@ -2333,13 +2333,13 @@ - + - + @@ -2349,13 +2349,13 @@ - + - + @@ -2365,13 +2365,13 @@ - + - + @@ -2383,13 +2383,13 @@ - + - + @@ -2399,13 +2399,13 @@ - + - + @@ -2415,13 +2415,13 @@ - + - + @@ -2431,13 +2431,13 @@ - + - + @@ -2447,13 +2447,13 @@ - + - + @@ -2463,13 +2463,13 @@ - + - + @@ -2479,13 +2479,13 @@ - + - + @@ -2495,13 +2495,13 @@ - + - + @@ -2513,13 +2513,13 @@ - + - + @@ -2529,13 +2529,13 @@ - + - + @@ -2545,13 +2545,13 @@ - + - + @@ -2561,13 +2561,13 @@ - + - + @@ -2577,13 +2577,13 @@ - + - + @@ -2593,13 +2593,13 @@ - + - + @@ -2609,13 +2609,13 @@ - + - + @@ -2625,13 +2625,13 @@ - + - + @@ -2643,13 +2643,13 @@ - + - + @@ -2659,13 +2659,13 @@ - + - + @@ -2675,13 +2675,13 @@ - + - + @@ -2691,13 +2691,13 @@ - + - + @@ -2707,13 +2707,13 @@ - + - + @@ -2723,13 +2723,13 @@ - + - + @@ -2739,13 +2739,13 @@ - + - + @@ -2755,13 +2755,13 @@ - + - + @@ -2773,13 +2773,13 @@ - + - + @@ -2789,13 +2789,13 @@ - + - + @@ -2805,13 +2805,13 @@ - + - + @@ -2821,13 +2821,13 @@ - + - + @@ -2837,13 +2837,13 @@ - + - + @@ -2853,13 +2853,13 @@ - + - + @@ -2869,13 +2869,13 @@ - + - + @@ -2885,13 +2885,13 @@ - + - + @@ -2903,13 +2903,13 @@ - + - + @@ -2919,13 +2919,13 @@ - + - + @@ -2935,13 +2935,13 @@ - + - + @@ -2951,13 +2951,13 @@ - + - + @@ -2967,13 +2967,13 @@ - + - + @@ -2983,13 +2983,13 @@ - + - + @@ -2999,13 +2999,13 @@ - + - + @@ -3015,13 +3015,13 @@ - + - + @@ -3033,13 +3033,13 @@ - + - + @@ -3049,13 +3049,13 @@ - + - + @@ -3065,13 +3065,13 @@ - + - + @@ -3081,13 +3081,13 @@ - + - + @@ -3097,13 +3097,13 @@ - + - + @@ -3113,13 +3113,13 @@ - + - + @@ -3129,13 +3129,13 @@ - + - + @@ -3145,13 +3145,13 @@ - + - + @@ -3163,13 +3163,13 @@ - + - + @@ -3179,13 +3179,13 @@ - + - + @@ -3195,13 +3195,13 @@ - + - + @@ -3211,13 +3211,13 @@ - + - + @@ -3227,13 +3227,13 @@ - + - + @@ -3243,13 +3243,13 @@ - + - + @@ -3259,13 +3259,13 @@ - + - + @@ -3275,13 +3275,13 @@ - + - + From 0a53a719bdab86936b717cf6958dea7b7f04d65f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:42:24 -0600 Subject: [PATCH 103/114] [Architecture] Bug fix due to adder renaming --- .../openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 4 ++-- .../k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml | 4 ++-- .../k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml | 4 ++-- ...ac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 4 ++-- .../openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml | 4 ++-- ...c_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_column_chain_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_register_chain_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml | 4 ++-- ...ac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml | 4 ++-- ...adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml | 4 ++-- 13 files changed, 26 insertions(+), 26 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 114ffecad..beeb811e1 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 56b3a3b0d..aed95c588 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index e44bfbff4..f5efbc285 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index d51bd7215..3a53d9aa4 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 4fec07c77..adc3da01e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index cc50bf9ed..1b2d8ffcb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index e9b25c714..2733b0317 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index c1a7d8d3d..d900f0edb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index 2e82fedfc..b5439a151 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 10b8f2ba4..b22057acb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 4d7ba7fd0..748f8ec48 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 455688737..4335c3ae4 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 6f0b235ba..765bd94a1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 From 00bf775971132343be5aa5857a8c73641a5dea5b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:54:18 -0600 Subject: [PATCH 104/114] [Architecture] Bug fix for adder renaming --- ...ac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 3a53d9aa4..af193a385 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -209,8 +209,8 @@ - - + + From 20d6b2bf84fd971295149a45260d2ac7e7475d24 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 21:14:13 -0600 Subject: [PATCH 105/114] [Architecture] Remove out-of-date Verilog testbench --- openfpga_flow/VerilogNetlists/lb_tb.v | 199 -------------------------- 1 file changed, 199 deletions(-) delete mode 100644 openfpga_flow/VerilogNetlists/lb_tb.v diff --git a/openfpga_flow/VerilogNetlists/lb_tb.v b/openfpga_flow/VerilogNetlists/lb_tb.v deleted file mode 100644 index 705970fd6..000000000 --- a/openfpga_flow/VerilogNetlists/lb_tb.v +++ /dev/null @@ -1,199 +0,0 @@ -//----------------------------------------------------- -// Design Name : testbench for logic blocks -// File Name : lb_tb.v -// Function : Configurable logic block -// Coder : Xifan TANG -//----------------------------------------------------- -//----- Time scale: simulation time step and accuracy ----- -`timescale 1ns / 1ps - -module lb_tb; -// Parameters -parameter SIZE_IN = 40; //---- MUX input size -parameter SIZE_OUT = 10; //---- MUX input size -parameter SIZE_RESERV_BLWL = 49 + 1; //---- MUX input size -parameter SIZE_BLWL = 1019 - 310 + 1; //---- MUX input size -parameter prog_clk_period = 1; // [ns] half clock period -parameter op_clk_period = 1; // [ns] half clock period -parameter config_period = 2 * prog_clk_period; // [ns] One full clock period -parameter operating_period = SIZE_IN * 2 * op_clk_period; // [ns] One full clock period - -// Ports -wire [0:SIZE_IN-1] lb_in; -wire [0:SIZE_IN-1] lb_out; -wire lb_clk; -wire [0:SIZE_RESERV_BLWL-1] reserv_bl; -wire [0:SIZE_RESERV_BLWL-1] reserv_wl; -wire [0:SIZE_BLWL-1] bl; -wire [0:SIZE_BLWL-1] wl; -wire prog_EN; -wire prog_ENb; -wire zin; -wire nequalize; -wire read; -wire clk; -wire Reset; -wire Set; -// Clocks -wire prog_clock; -wire op_clock; - -// Registered port -reg [0:SIZE_IN-1] lb_in_reg; -reg [0:SIZE_RESERV_BLWL-1] reserv_bl_reg; -reg [0:SIZE_RESERV_BLWL-1] reserv_wl_reg; -reg [0:SIZE_BLWL-1] bl_reg; -reg [0:SIZE_BLWL-1] wl_reg; -reg prog_clock_reg; -reg op_clock_reg; - -// Config done signal; -reg config_done; -// Temp register for rotating shift -reg temp; - -// Unit under test -grid_1__1_ U0 ( -zin, -nequalize, -read, -clk, -Reset, -Set, -prog_ENb, -prog_EN, -// Top inputs -lb_in[0], lb_in[4], lb_in[8], lb_in[12], lb_in[16], -lb_in[20], lb_in[24], lb_in[28], lb_in[32], lb_in[36], -// Top outputs -lb_out[0], lb_out[4], lb_out[8], -// Right inputs -lb_in[1], lb_in[5], lb_in[9], lb_in[13], lb_in[17], -lb_in[21], lb_in[25], lb_in[29], lb_in[33], lb_in[37], -// Right outputs -lb_out[1], lb_out[5], lb_out[9], -// Bottom inputs -lb_in[2], lb_in[6], lb_in[10], lb_in[14], lb_in[18], -lb_in[22], lb_in[26], lb_in[30], lb_in[34], lb_in[38], -// Bottom outputs -lb_out[2], lb_out[6], -// Bottom inputs -lb_clk, -// left inputs -lb_in[3], lb_in[7], lb_in[11], lb_in[15], lb_in[19], -lb_in[23], lb_in[27], lb_in[31], lb_in[35], lb_in[39], -// left outputs -lb_out[3], lb_out[7], -reserv_bl, reserv_wl, -bl, wl -); - -// Task: assign BL and WL values -task prog_lb_blwl; - begin - @(posedge prog_clock); - // Rotate left shift - temp = reserv_bl_reg[SIZE_RESERV_BLWL-1]; - //bl_reg = bl_reg >> 1; - reserv_bl_reg[1:SIZE_RESERV_BLWL-1] = reserv_bl_reg[0:SIZE_RESERV_BLWL-2]; - reserv_bl_reg[0] = temp; - end -endtask - -// Task: assign inputs -task op_lb_in; - begin - @(posedge op_clock); - temp = lb_in_reg[SIZE_IN-1]; - lb_in_reg[1:SIZE_IN-1] = lb_in_reg[0:SIZE_IN-2]; - lb_in_reg[0] = temp; - end -endtask - -// Configuration done signal -initial -begin - config_done = 1'b0; -end -// Enabled during config_period, Disabled during op_period -always -begin - #config_period config_done = ~config_done; - #operating_period config_done = ~config_done; -end - -// Programming clocks -initial -begin - prog_clock_reg = 1'b0; -end -always -begin - #prog_clk_period prog_clock_reg = ~prog_clock_reg; -end - -// Operating clocks -initial -begin - op_clock_reg = 1'b0; -end -always -begin - #op_clk_period op_clock_reg = ~op_clock_reg; -end - -// Programming and Operating clocks -assign prog_clock = prog_clock_reg & (~config_done); -assign op_clock = op_clock_reg & config_done; - -// Programming Enable signals -assign prog_EN = prog_clock & (~config_done); -assign prog_ENb = ~prog_EN; - -// Programming phase: BL/WL -initial -begin - // Initialize BL/WL registers - reserv_bl_reg = {SIZE_RESERV_BLWL {1'b0}}; - reserv_bl_reg[0] = 1'b1; - reserv_wl_reg = {SIZE_RESERV_BLWL {1'b0}}; - // Reserved BL/WL - bl_reg = {SIZE_BLWL {1'b0}}; - wl_reg = {SIZE_BLWL {1'b1}}; - //wl_reg[SIZE_BLWL-1] = 1'b1; -end -always wait (~config_done) // Only invoked when config_done is 0 -begin - // Propagate input 1 to the output - // BL[0] = 1, WL[4] = 1 - prog_lb_blwl; -end - -// Operating Phase -initial -begin - lb_in_reg = {SIZE_IN {1'b0}}; - lb_in_reg[0] = 1'b1; // Last bit is 1 initially -end -always wait (config_done) // Only invoked when config_done is 1 -begin - /* Update inputs */ - op_lb_in; -end - -// Wire ports -assign lb_in = lb_in_reg; -assign reserv_bl = reserv_bl_reg; -assign reserv_wl = reserv_wl_reg; -assign bl = bl_reg; -assign wl = wl_reg; - -// Constant ports -assign zin = 1'b0; -assign nequalize = 1'b1; -assign read = 1'b0; -assign clk = op_clock; -assign Reset = ~config_done; -assign Set = 1'b0; - -endmodule From 019208ec0f195f609d0a85f65cdabe36274b0b98 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 11:55:28 -0600 Subject: [PATCH 106/114] [Architecture] Reorganize the cell netlists and update architecture files accordingly --- .../openfpga_arch/k4_N4_40nm_bank_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_both_set_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_set_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_setb_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 6 +++--- .../k4_N4_40nm_cc_use_both_set_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_cc_use_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_cc_use_resetb_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml | 6 +++--- .../k4_N4_40nm_cc_use_setb_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_frame_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_both_set_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_set_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_setb_openfpga.xml | 6 +++--- .../k4_N4_40nm_powergate_frame_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_standalone_openfpga.xml | 6 +++--- .../k4_N4_no_local_routing_40nm_frame_openfpga.xml | 6 +++--- ..._N5_pattern_local_routing_40nm_frame_openfpga.xml | 6 +++--- .../openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml | 6 +++--- .../k4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 8 ++++---- ...frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml | 10 +++++----- ...N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml | 10 +++++----- ...er_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 12 ++++++------ openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml | 6 +++--- .../k6_N10_intermediate_buffer_40nm_openfpga.xml | 6 +++--- .../openfpga_arch/k6_frac_N10_40nm_openfpga.xml | 6 +++--- .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 8 ++++---- ...er_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml | 10 +++++----- ...frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_adder_column_chain_40nm_openfpga.xml | 8 ++++---- ...6_frac_N10_adder_register_chain_40nm_openfpga.xml | 8 ++++---- ...c_N10_adder_register_scan_chain_40nm_openfpga.xml | 8 ++++---- ...der_register_scan_chain_depop50_40nm_openfpga.xml | 8 ++++---- ...ister_scan_chain_depop50_spypad_40nm_openfpga.xml | 8 ++++---- .../k6_frac_N10_behavioral_40nm_openfpga.xml | 6 +++--- .../k6_frac_N10_local_encoder_40nm_openfpga.xml | 6 +++--- .../k6_frac_N10_spyio_40nm_openfpga.xml | 6 +++--- .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 8 ++++---- .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 6 +++--- .../openfpga_arch/k6_frac_N8_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_debuf_mux_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_local_encoder_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_stdcell_mux_40nm_openfpga.xml | 8 ++++---- .../k6_frac_N8_tree_mux_40nm_openfpga.xml | 6 +++--- .../spice}/adder.sp | 0 .../spice}/ff.sp | 0 .../spice}/gate.sp | 0 .../spice}/io.sp | 0 .../spice}/sram.sp | 0 .../spice_testbench}/ff_tb.sp | 0 .../verilog}/adder.v | 0 .../verilog}/aib.v | 0 .../verilog}/dff.v | 0 .../verilog}/dpram.v | 0 .../verilog}/dpram16k.v | 0 .../verilog}/dpram1k.v | 0 .../verilog}/frac_mem_32k.v | 0 .../verilog}/gpio.v | 0 .../verilog}/latch.v | 0 .../verilog}/lut6.v | 0 .../verilog}/mult_32x32.v | 0 .../verilog}/mult_36x36.v | 0 .../verilog}/mux2.v | 0 .../verilog}/sram.v | 0 .../verilog_testbench}/dpram_tb.v | 0 .../verilog_testbench}/ff_tb.v | 0 .../verilog_testbench}/mux_tb.v | 0 .../verilog_testbench}/sram_tb.v | 0 78 files changed, 186 insertions(+), 186 deletions(-) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/adder.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/ff.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/gate.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/io.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/sram.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice_testbench}/ff_tb.sp (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/adder.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/aib.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/dff.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/dpram.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/dpram16k.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/dpram1k.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/frac_mem_32k.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/gpio.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/latch.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/lut6.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/mult_32x32.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/mult_36x36.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/mux2.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/sram.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog_testbench}/dpram_tb.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog_testbench}/ff_tb.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog_testbench}/mux_tb.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog_testbench}/sram_tb.v (100%) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index e2ce76956..3acfc387c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -155,7 +155,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index d8f97ba41..0fde86957 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -157,7 +157,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml index 427889368..54b7dd8cc 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml index d03b2d2be..22fcb70da 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml index fec761135..8ef6b9cf8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml index dc3c89739..477a013e2 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index a36a863fd..5d368c49d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -146,7 +146,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml index 762fc1af3..7cb74e9c2 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -148,7 +148,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml index c74d0aedb..56ce2b305 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml index 3e453fb3f..0afb065d8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml index 78461fadc..a99cb0cfa 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml index ee990043b..42dc751d2 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml index dced448a2..8dce74596 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 5d9aee9eb..bf7cad751 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index 92b7930c7..52e3a7091 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -155,7 +155,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index ff3f2e1b0..c2d66f866 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -159,7 +159,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index 7495f9c3b..9b54531dd 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -157,7 +157,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml index 0b7f14a25..93ba74c10 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml index f43436de5..634b95f7b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index cee0fbc79..8c0c8c692 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index 7ba360992..2e4d554f8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index 0d03dc6d6..71629daf3 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -130,7 +130,7 @@ - + @@ -152,7 +152,7 @@ - + @@ -162,7 +162,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 3392eef23..3f1ebecad 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index cf0502130..0264a8862 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index 6366425e0..3d4434c43 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index ceef842c0..1c5b5a300 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index beeb811e1..47db8c70a 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + @@ -183,7 +183,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index aed95c588..b800c806a 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + @@ -183,7 +183,7 @@ - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index f5efbc285..0a5d0be89 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + @@ -183,7 +183,7 @@ - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index af193a385..c41a0e40c 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + @@ -183,7 +183,7 @@ - + @@ -193,7 +193,7 @@ - + @@ -205,7 +205,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index 9c8e66a87..cd348a131 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml index e0e8cd461..1e10c1f05 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -147,7 +147,7 @@ - + @@ -157,7 +157,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml index 3afe5a693..a91b9eb01 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index adc3da01e..ad2bb7df9 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 1b2d8ffcb..70001d8e0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + @@ -194,7 +194,7 @@ - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 2733b0317..f7c69d96a 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + @@ -194,7 +194,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index d900f0edb..49832b5f9 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + @@ -194,7 +194,7 @@ - + @@ -206,7 +206,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index b5439a151..d39983bbe 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index b22057acb..54e07fdae 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 748f8ec48..299649ff0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -142,7 +142,7 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + @@ -170,7 +170,7 @@ - + @@ -180,7 +180,7 @@ - + @@ -189,7 +189,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 4335c3ae4..e0825a04e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -142,7 +142,7 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + @@ -170,7 +170,7 @@ - + @@ -180,7 +180,7 @@ - + @@ -189,7 +189,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 765bd94a1..30b76c135 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -142,7 +142,7 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + @@ -185,7 +185,7 @@ - + @@ -195,7 +195,7 @@ - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml index a0d9be879..a5c49fc75 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml index ef3bf9f21..b9aece61a 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index f9fcfe148..53e9ecc79 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml index 588e88620..8dc34b2c5 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml @@ -86,7 +86,7 @@ If your standard cell provider does not offer the exact truth table, you can simply swap the inputs as shown in the example below --> - + @@ -131,7 +131,7 @@ - + @@ -156,7 +156,7 @@ - + @@ -166,7 +166,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml index da9767f10..1b001691d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml @@ -130,7 +130,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -165,7 +165,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index 098e7ba2e..0abab4c71 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml index 53dda3357..566968e41 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml index f050bd8a7..a56d378b7 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml index ec3f99c4d..febd52470 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml index cab4ef22b..48eacc3ba 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml index e367ff8bb..9e027bd22 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -86,7 +86,7 @@ If your standard cell provider does not offer the exact truth table, you can simply swap the inputs as shown in the example below --> - + @@ -131,7 +131,7 @@ - + @@ -156,7 +156,7 @@ - + @@ -166,7 +166,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml index 0585bf591..486b8cd43 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -130,7 +130,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -165,7 +165,7 @@ - + diff --git a/openfpga_flow/SpiceNetlists/adder.sp b/openfpga_flow/openfpga_cell_library/spice/adder.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/adder.sp rename to openfpga_flow/openfpga_cell_library/spice/adder.sp diff --git a/openfpga_flow/SpiceNetlists/ff.sp b/openfpga_flow/openfpga_cell_library/spice/ff.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/ff.sp rename to openfpga_flow/openfpga_cell_library/spice/ff.sp diff --git a/openfpga_flow/SpiceNetlists/gate.sp b/openfpga_flow/openfpga_cell_library/spice/gate.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/gate.sp rename to openfpga_flow/openfpga_cell_library/spice/gate.sp diff --git a/openfpga_flow/SpiceNetlists/io.sp b/openfpga_flow/openfpga_cell_library/spice/io.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/io.sp rename to openfpga_flow/openfpga_cell_library/spice/io.sp diff --git a/openfpga_flow/SpiceNetlists/sram.sp b/openfpga_flow/openfpga_cell_library/spice/sram.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/sram.sp rename to openfpga_flow/openfpga_cell_library/spice/sram.sp diff --git a/openfpga_flow/SpiceNetlists/ff_tb.sp b/openfpga_flow/openfpga_cell_library/spice_testbench/ff_tb.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/ff_tb.sp rename to openfpga_flow/openfpga_cell_library/spice_testbench/ff_tb.sp diff --git a/openfpga_flow/VerilogNetlists/adder.v b/openfpga_flow/openfpga_cell_library/verilog/adder.v similarity index 100% rename from openfpga_flow/VerilogNetlists/adder.v rename to openfpga_flow/openfpga_cell_library/verilog/adder.v diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/openfpga_cell_library/verilog/aib.v similarity index 100% rename from openfpga_flow/VerilogNetlists/aib.v rename to openfpga_flow/openfpga_cell_library/verilog/aib.v diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dff.v rename to openfpga_flow/openfpga_cell_library/verilog/dff.v diff --git a/openfpga_flow/VerilogNetlists/dpram.v b/openfpga_flow/openfpga_cell_library/verilog/dpram.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dpram.v rename to openfpga_flow/openfpga_cell_library/verilog/dpram.v diff --git a/openfpga_flow/VerilogNetlists/dpram16k.v b/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dpram16k.v rename to openfpga_flow/openfpga_cell_library/verilog/dpram16k.v diff --git a/openfpga_flow/VerilogNetlists/dpram1k.v b/openfpga_flow/openfpga_cell_library/verilog/dpram1k.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dpram1k.v rename to openfpga_flow/openfpga_cell_library/verilog/dpram1k.v diff --git a/openfpga_flow/VerilogNetlists/frac_mem_32k.v b/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v similarity index 100% rename from openfpga_flow/VerilogNetlists/frac_mem_32k.v rename to openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v diff --git a/openfpga_flow/VerilogNetlists/gpio.v b/openfpga_flow/openfpga_cell_library/verilog/gpio.v similarity index 100% rename from openfpga_flow/VerilogNetlists/gpio.v rename to openfpga_flow/openfpga_cell_library/verilog/gpio.v diff --git a/openfpga_flow/VerilogNetlists/latch.v b/openfpga_flow/openfpga_cell_library/verilog/latch.v similarity index 100% rename from openfpga_flow/VerilogNetlists/latch.v rename to openfpga_flow/openfpga_cell_library/verilog/latch.v diff --git a/openfpga_flow/VerilogNetlists/lut6.v b/openfpga_flow/openfpga_cell_library/verilog/lut6.v similarity index 100% rename from openfpga_flow/VerilogNetlists/lut6.v rename to openfpga_flow/openfpga_cell_library/verilog/lut6.v diff --git a/openfpga_flow/VerilogNetlists/mult_32x32.v b/openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v similarity index 100% rename from openfpga_flow/VerilogNetlists/mult_32x32.v rename to openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v diff --git a/openfpga_flow/VerilogNetlists/mult_36x36.v b/openfpga_flow/openfpga_cell_library/verilog/mult_36x36.v similarity index 100% rename from openfpga_flow/VerilogNetlists/mult_36x36.v rename to openfpga_flow/openfpga_cell_library/verilog/mult_36x36.v diff --git a/openfpga_flow/VerilogNetlists/mux2.v b/openfpga_flow/openfpga_cell_library/verilog/mux2.v similarity index 100% rename from openfpga_flow/VerilogNetlists/mux2.v rename to openfpga_flow/openfpga_cell_library/verilog/mux2.v diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/openfpga_cell_library/verilog/sram.v similarity index 100% rename from openfpga_flow/VerilogNetlists/sram.v rename to openfpga_flow/openfpga_cell_library/verilog/sram.v diff --git a/openfpga_flow/VerilogNetlists/dpram_tb.v b/openfpga_flow/openfpga_cell_library/verilog_testbench/dpram_tb.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dpram_tb.v rename to openfpga_flow/openfpga_cell_library/verilog_testbench/dpram_tb.v diff --git a/openfpga_flow/VerilogNetlists/ff_tb.v b/openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v similarity index 100% rename from openfpga_flow/VerilogNetlists/ff_tb.v rename to openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v diff --git a/openfpga_flow/VerilogNetlists/mux_tb.v b/openfpga_flow/openfpga_cell_library/verilog_testbench/mux_tb.v similarity index 100% rename from openfpga_flow/VerilogNetlists/mux_tb.v rename to openfpga_flow/openfpga_cell_library/verilog_testbench/mux_tb.v diff --git a/openfpga_flow/VerilogNetlists/sram_tb.v b/openfpga_flow/openfpga_cell_library/verilog_testbench/sram_tb.v similarity index 100% rename from openfpga_flow/VerilogNetlists/sram_tb.v rename to openfpga_flow/openfpga_cell_library/verilog_testbench/sram_tb.v From 6bea712db0989ddc0d541954e35e631aa389bf59 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 14:54:51 -0600 Subject: [PATCH 107/114] [OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name --- .../src/fabric/build_essential_modules.cpp | 10 +++++- .../fpga_verilog/verilog_essential_gates.cpp | 36 +++++++++---------- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/openfpga/src/fabric/build_essential_modules.cpp b/openfpga/src/fabric/build_essential_modules.cpp index 19e1a10ea..3623ed259 100644 --- a/openfpga/src/fabric/build_essential_modules.cpp +++ b/openfpga/src/fabric/build_essential_modules.cpp @@ -256,7 +256,15 @@ void rename_primitive_module_port_names(ModuleManager& module_manager, /* We only care about user-defined models */ if ( (true == circuit_lib.model_verilog_netlist(model).empty()) && (true == circuit_lib.model_spice_netlist(model).empty()) ) { - continue; + /* Exception circuit models as primitive cells + * - Inverter, buffer, pass-gate logic, logic gate + * which should be renamed even when auto-generated + */ + if ( (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(model)) + && (CIRCUIT_MODEL_PASSGATE != circuit_lib.model_type(model)) + && (CIRCUIT_MODEL_GATE != circuit_lib.model_type(model)) ) { + continue; + } } /* Skip Routing channel wire models because they need a different name. Do it later */ if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index d33407071..ca3d38734 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -43,7 +43,7 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, print_verilog_comment(fp, std::string("----- Verilog codes of a power-gated inverter -----")); /* Create a sensitive list */ - fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl; + fp << "\treg " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; fp << "\talways @("; /* Power-gate port first*/ @@ -52,10 +52,10 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, if (false == circuit_lib.port_is_config_enable(power_gate_port)) { continue; } - fp << circuit_lib.port_prefix(power_gate_port); + fp << circuit_lib.port_lib_name(power_gate_port); fp << ", "; } - fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl; + fp << circuit_lib.port_lib_name(input_port) << ") begin" << std::endl; /* Dump the case of power-gated */ fp << "\t\tif ("; @@ -79,14 +79,14 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, fp << "~"; } - fp << circuit_lib.port_prefix(power_gate_port) << "[" << power_gate_pin << "])"; + fp << circuit_lib.port_lib_name(power_gate_port) << "[" << power_gate_pin << "])"; port_cnt++; /* Update port counter*/ } } fp << ") begin" << std::endl; - fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = "; + fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = "; /* Branch on the type of inverter/buffer: * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, @@ -101,12 +101,12 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, fp << "~"; } - fp << circuit_lib.port_prefix(input_port) << ";" << std::endl; + fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl; fp << "\t\tend else begin" << std::endl; - fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = 1'bz;" << std::endl; + fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = 1'bz;" << std::endl; fp << "\t\tend" << std::endl; fp << "\tend" << std::endl; - fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl; + fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; } /************************************************ @@ -124,7 +124,7 @@ void print_verilog_invbuf_body(std::fstream& fp, print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----")); - fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = (" << circuit_lib.port_prefix(input_port) << " === 1'bz)? $random : "; + fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " === 1'bz)? $random : "; /* Branch on the type of inverter/buffer: * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, @@ -139,7 +139,7 @@ void print_verilog_invbuf_body(std::fstream& fp, fp << "~"; } - fp << circuit_lib.port_prefix(input_port) << ";" << std::endl; + fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl; } /************************************************ @@ -264,8 +264,8 @@ void print_verilog_passgate_module(const ModuleManager& module_manager, /* Dump logics: we propagate input to the output when the gate is '1' * the input is blocked from output when the gate is '0' */ - fp << "\tassign " << circuit_lib.port_prefix(output_ports[0]) << " = "; - fp << circuit_lib.port_prefix(input_ports[1]) << " ? " << circuit_lib.port_prefix(input_ports[0]); + fp << "\tassign " << circuit_lib.port_lib_name(output_ports[0]) << " = "; + fp << circuit_lib.port_lib_name(input_ports[1]) << " ? " << circuit_lib.port_lib_name(input_ports[0]); fp << " : 1'bz;" << std::endl; /* Print timing info */ @@ -311,7 +311,7 @@ void print_verilog_and_or_gate_body(std::fstream& fp, for (const auto& output_port : output_ports) { for (const auto& output_pin : circuit_lib.pins(output_port)) { - BasicPort output_port_info(circuit_lib.port_prefix(output_port), output_pin, output_pin); + BasicPort output_port_info(circuit_lib.port_lib_name(output_port), output_pin, output_pin); fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port_info); fp << " = "; @@ -323,7 +323,7 @@ void print_verilog_and_or_gate_body(std::fstream& fp, fp << " " << gate_verilog_operator << " "; } - BasicPort input_port_info(circuit_lib.port_prefix(input_port), input_pin, input_pin); + BasicPort input_port_info(circuit_lib.port_lib_name(input_port), input_pin, input_pin); fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); /* Increment the counter for port */ @@ -395,10 +395,10 @@ void print_verilog_mux2_gate_body(std::fstream& fp, * the third input is the select port */ fp << "\tassign "; - BasicPort out_port_info(circuit_lib.port_prefix(output_ports[0]), 0, 0); - BasicPort sel_port_info(circuit_lib.port_prefix(input_ports[2]), 0, 0); - BasicPort in0_port_info(circuit_lib.port_prefix(input_ports[0]), 0, 0); - BasicPort in1_port_info(circuit_lib.port_prefix(input_ports[1]), 0, 0); + BasicPort out_port_info(circuit_lib.port_lib_name(output_ports[0]), 0, 0); + BasicPort sel_port_info(circuit_lib.port_lib_name(input_ports[2]), 0, 0); + BasicPort in0_port_info(circuit_lib.port_lib_name(input_ports[0]), 0, 0); + BasicPort in1_port_info(circuit_lib.port_lib_name(input_ports[1]), 0, 0); fp << generate_verilog_port(VERILOG_PORT_CONKT, out_port_info); fp << " = "; From 1b4e4491799d4eed93bfa5e18c15d69d2b725e47 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 21:05:20 -0600 Subject: [PATCH 108/114] [OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol --- .../fpga_verilog/verilog_top_testbench.cpp | 132 ++++++++++++------ .../src/fpga_verilog/verilog_writer_utils.cpp | 51 +++++++ .../src/fpga_verilog/verilog_writer_utils.h | 6 + 3 files changed, 148 insertions(+), 41 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index c4250bdcc..a63ef38ef 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -178,21 +178,34 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_REG, wl_addr_port) << ";" << std::endl; /* Print the data-input port for the frame-based decoder here */ - print_verilog_comment(fp, std::string("---- Data input port for frame-based decoder -----")); + print_verilog_comment(fp, std::string("---- Data input port for memory decoders -----")); ModulePortId din_port_id = module_manager.find_module_port(top_module, std::string(DECODER_DATA_IN_PORT_NAME)); BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED configuration done signal to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); + /* Generate enable signal waveform here: + * which is a 90 degree phase shift than the programming clock + */ + print_verilog_comment(fp, std::string("---- Wire enable port of memory decoders -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort en_register_port(std::string(en_port.get_name() + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, config_done_port, true); + fp << generate_verilog_port(VERILOG_PORT_REG, en_register_port) << ";" << std::endl; + + write_tab_to_file(fp, 1); + fp << "assign "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, en_port); + fp << "= "; + fp << "~" << generate_verilog_port(VERILOG_PORT_CONKT, en_register_port); + fp << " & "; + fp << "~" << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); + fp << ";" << std::endl; } @@ -201,8 +214,6 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, - const ConfigProtocol& config_protocol, - const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { /* Validate the file stream */ @@ -223,33 +234,28 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED configuration done signal to the enable signal !!! */ + /* Generate enable signal waveform here: + * which is a 90 degree phase shift than the programming clock + */ + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoders -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort en_register_port(std::string(en_port.get_name() + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1); - /* Find the circuit model of configurable memory - * Spot its BL port and generate stimuli based on BL port's attribute: - * - If the BL port is triggered by edge, use the inverted programming clock signal - * - If the BL port is a regular port, use the inverted configuration done signal - */ - const CircuitModelId& mem_model = config_protocol.memory_model(); - VTR_ASSERT(true == circuit_lib.valid_model_id(mem_model)); - std::vector mem_model_bl_ports = circuit_lib.model_ports_by_type(mem_model, CIRCUIT_MODEL_PORT_BL); - VTR_ASSERT(1 == mem_model_bl_ports.size()); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); - if (true == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])) { - VTR_ASSERT_SAFE(false == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock signal -----")); - fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); - } else { - BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); - fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, config_done_port, true); - } + fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_REG, en_register_port) << ";" << std::endl; + + write_tab_to_file(fp, 1); + fp << "assign "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, en_port); + fp << "= "; + fp << "~" << generate_verilog_port(VERILOG_PORT_CONKT, en_register_port); + fp << " & "; + fp << "~" << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); + fp << ";" << std::endl; } /******************************************************************** @@ -258,7 +264,6 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, static void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, const ConfigProtocol& config_protocol, - const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { switch(config_protocol.type()) { @@ -272,7 +277,7 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, print_verilog_top_testbench_memory_bank_port(fp, module_manager, top_module); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_port(fp, config_protocol, circuit_lib, + print_verilog_top_testbench_frame_decoder_port(fp, module_manager, top_module); break; default: @@ -525,7 +530,6 @@ void print_verilog_top_testbench_ports(std::fstream& fp, const VprNetlistAnnotation& netlist_annotation, const std::vector& clock_port_names, const ConfigProtocol& config_protocol, - const CircuitLibrary& circuit_lib, const std::string& circuit_name){ /* Validate the file stream */ valid_file_stream(fp); @@ -599,7 +603,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl; /* Configuration ports depend on the organization of SRAMs */ - print_verilog_top_testbench_config_protocol_port(fp, config_protocol, circuit_lib, + print_verilog_top_testbench_config_protocol_port(fp, config_protocol, module_manager, top_module); /* Create a clock port if the benchmark have one but not in the default name! @@ -816,9 +820,7 @@ void print_verilog_top_testbench_load_bitstream_task_memory_bank(std::fstream& f /* Validate the file stream */ valid_file_stream(fp); - ModulePortId en_port_id = module_manager.find_module_port(top_module, - std::string(DECODER_ENABLE_PORT_NAME)); - BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME)); @@ -851,7 +853,7 @@ void print_verilog_top_testbench_load_bitstream_task_memory_bank(std::fstream& f fp << generate_verilog_port(VERILOG_PORT_INPUT, wl_addr_value) << ";" << std::endl; fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl; fp << "\tbegin" << std::endl; - fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, en_port) << ");" << std::endl; + fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; fp << "\t\t\t"; fp << generate_verilog_port(VERILOG_PORT_CONKT, bl_addr_port); @@ -898,9 +900,7 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream& /* Validate the file stream */ valid_file_stream(fp); - ModulePortId en_port_id = module_manager.find_module_port(top_module, - std::string(DECODER_ENABLE_PORT_NAME)); - BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); ModulePortId addr_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ADDRESS_PORT_NAME)); @@ -926,7 +926,7 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream& fp << generate_verilog_port(VERILOG_PORT_INPUT, addr_value) << ";" << std::endl; fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl; fp << "\tbegin" << std::endl; - fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, en_port) << ");" << std::endl; + fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; fp << "\t\t\t"; fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_port); @@ -1113,6 +1113,49 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp, fp << std::endl; } +/******************************************************************** + * Print input stimuli for configuration protocol + * include: + * - memory bank + * 1. the enable signal + * - frame-based + * 1. the enable signal + *******************************************************************/ +static +void print_verilog_top_testbench_configuration_protocol_stimulus(std::fstream& fp, + const e_config_protocol_type& config_protocol_type, + const ModuleManager& module_manager, + const ModuleId& top_module, + const float& prog_clock_period, + const float& timescale) { + /* Validate the file stream */ + valid_file_stream(fp); + + /* Branch on the type of configuration protocol */ + switch (config_protocol_type) { + case CONFIG_MEM_STANDALONE: + break; + case CONFIG_MEM_SCAN_CHAIN: + break; + case CONFIG_MEM_MEMORY_BANK: + case CONFIG_MEM_FRAME_BASED: { + ModulePortId en_port_id = module_manager.find_module_port(top_module, + std::string(DECODER_ENABLE_PORT_NAME)); + BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort en_register_port(std::string(en_port.get_name() + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1); + print_verilog_comment(fp, std::string("---- Generate enable signal waveform -----")); + print_verilog_shifted_clock_stimuli(fp, en_register_port, + 0.25 * prog_clock_period / timescale, + 0.5 * prog_clock_period / timescale, 0); + break; + } + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid SRAM organization type!\n"); + exit(1); + } +} + /******************************************************************** * Print stimulus for a FPGA fabric with a flatten memory (standalone) configuration protocol * We will load the bitstream in the second clock cycle, right after the first reset cycle @@ -1711,7 +1754,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Start of testbench */ print_verilog_top_testbench_ports(fp, module_manager, top_module, atom_ctx, netlist_annotation, clock_port_names, - config_protocol, circuit_lib, + config_protocol, circuit_name); /* Find the clock period */ @@ -1731,6 +1774,13 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, op_clock_period, VERILOG_SIM_TIMESCALE); + /* Generate stimuli for programming interface */ + print_verilog_top_testbench_configuration_protocol_stimulus(fp, + config_protocol.type(), + module_manager, top_module, + prog_clock_period, + VERILOG_SIM_TIMESCALE); + /* Identify the stimulus for global reset/set for programming purpose: * - If only reset port is seen we turn on Reset * - If only set port is seen we turn on Reset diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index 2817ccbaf..bc41f1cab 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -1294,6 +1294,57 @@ void print_verilog_pulse_stimuli(std::fstream& fp, fp << std::endl; } + +/******************************************************************** + * Print stimuli for a clock pulse generation + * This function supports the delay at the beginning of the waveform + * + * |<-- Initial delay -->|<--- pulse width --->| + * +------ flip_value + * | + * initial_value --------------------------------------------+ + * + *******************************************************************/ +void print_verilog_shifted_clock_stimuli(std::fstream& fp, + const BasicPort& port, + const float& initial_delay, + const float& pulse_width, + const size_t& initial_value) { + /* Validate the file stream */ + VTR_ASSERT(true == valid_file_stream(fp)); + + /* Config_done signal: indicate when configuration is finished */ + fp << "initial" << std::endl; + + write_tab_to_file(fp, 1); + fp << "begin" << std::endl; + + write_tab_to_file(fp, 1); + std::vector initial_values(port.get_width(), initial_value); + + write_tab_to_file(fp, 1); + fp << generate_verilog_port_constant_values(port, initial_values); + fp << ";" << std::endl; + + write_tab_to_file(fp, 2); + fp << "#" << std::setprecision(10) << initial_delay; + fp << ";" << std::endl; + + write_tab_to_file(fp, 2); + fp << "forever "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, port); + fp << " = "; + fp << "#" << std::setprecision(10) << pulse_width; + fp << " ~" << generate_verilog_port(VERILOG_PORT_CONKT, port); + fp << ";" << std::endl; + + write_tab_to_file(fp, 1); + fp << "end" << std::endl; + + /* Print an empty line as splitter */ + fp << std::endl; +} + /******************************************************************** * Print stimuli for a pulse generation * This function supports multiple signal switching under different pulse width diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h index 21c12509b..fd1c9b1a5 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.h +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h @@ -161,6 +161,12 @@ void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, const size_t& num_conf_bits, const BasicPort& fm_config_bus); +void print_verilog_shifted_clock_stimuli(std::fstream& fp, + const BasicPort& port, + const float& initial_delay, + const float& pulse_width, + const size_t& initial_value); + void print_verilog_pulse_stimuli(std::fstream& fp, const BasicPort& port, const size_t& initial_value, From dcbd6a06140701a3ad40052db746f6de87e6754f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 21:08:12 -0600 Subject: [PATCH 109/114] [Architecture] Add lib name to TGATE to test compatibility --- .../openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index 1c5b5a300..b33049ae7 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -84,10 +84,10 @@ - - - - + + + + 10e-12 5e-12 5e-12 From ffd926d68679b782561dfc867dc5886b9ed702b6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 21:30:59 -0600 Subject: [PATCH 110/114] [Architecture] Update external bitstream --- .../and2_k4_N4_tileable_40nm_bitstream.xml | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml index 07a874f86..28d1265f6 100644 --- a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml +++ b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Thu Sep 24 20:16:32 2020 + - Date: Fri Sep 25 21:30:07 2020 --> @@ -1286,20 +1286,20 @@ - + - + - + - - + + - + - + - + From 154f23b108a8e646db07d79a27d04a679eea0054 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 26 Sep 2020 11:54:06 -0600 Subject: [PATCH 111/114] [OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches --- .../fpga_verilog/verilog_top_testbench.cpp | 48 ++++++++++++++++++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index a63ef38ef..2d957b6b6 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -641,8 +641,8 @@ void print_verilog_top_testbench_ports(std::fstream& fp, /* Instantiate an integer to count the number of error and * determine if the simulation succeed or failed */ - print_verilog_comment(fp, std::string("----- Error counter -----")); - fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 0;" << std::endl; + print_verilog_comment(fp, std::string("----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----")); + fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 1;" << std::endl; } /******************************************************************** @@ -1675,6 +1675,44 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, } } +/******************************************************************** + * Add auto-check codes for the full testbench + * in particular for the configuration phase: + * - Check that the configuration done signal is raised, indicating + * that the configuration phase is finished + *******************************************************************/ +static +void print_verilog_top_testbench_check(std::fstream& fp, + const std::string& autochecked_preprocessing_flag, + const std::string& config_done_port_name, + const std::string& error_counter_name) { + + /* Validate the file stream */ + valid_file_stream(fp); + + /* Add output autocheck conditionally: only when a preprocessing flag is enable */ + print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag); + + print_verilog_comment(fp, std::string("----- Configuration done must be raised in the end -------")); + + BasicPort config_done_port(config_done_port_name, 1); + + write_tab_to_file(fp, 1); + fp << "always@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port) << ") begin" << std::endl; + + write_tab_to_file(fp, 2); + fp << error_counter_name << " = " << error_counter_name << " - 1;" << std::endl; + + write_tab_to_file(fp, 1); + fp << "end" << std::endl; + + /* Condition ends */ + print_verilog_endif(fp); + + /* Add an empty line as splitter */ + fp << std::endl; +} + /******************************************************************** * The top-level function to generate a testbench, in order to verify: * 1. Configuration phase of the FPGA fabric, where the bitstream is @@ -1866,6 +1904,12 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, clock_port_names, std::string(TOP_TB_OP_CLOCK_PORT_NAME)); + /* Add autocheck for configuration phase */ + print_verilog_top_testbench_check(fp, + std::string(AUTOCHECKED_SIMULATION_FLAG), + std::string(TOP_TB_CONFIG_DONE_PORT_NAME), + std::string(TOP_TESTBENCH_ERROR_COUNTER)); + /* Find simulation time */ float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE, num_config_clock_cycles, From 51d96244c616d0338894ea95babf307edc17dae2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 26 Sep 2020 14:30:57 -0600 Subject: [PATCH 112/114] [OpenFPGA Tool] Remove deprecated XML syntax --- .../libarchopenfpga/src/circuit_library.cpp | 15 ------------ .../libarchopenfpga/src/circuit_library.h | 23 ++++++++----------- .../src/read_xml_circuit_library.cpp | 3 --- .../src/write_xml_circuit_library.cpp | 4 ---- 4 files changed, 9 insertions(+), 36 deletions(-) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index d8069f903..55dfe8130 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -942,11 +942,6 @@ bool CircuitLibrary::port_is_config_enable(const CircuitPortId& circuit_port_id) return port_is_config_enable_[circuit_port_id]; } -bool CircuitLibrary::port_is_edge_triggered(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_edge_triggered_[circuit_port_id]; -} /* Return a flag if the port is used during programming a FPGA in a circuit model */ bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { @@ -1380,7 +1375,6 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, port_is_reset_.push_back(false); port_is_set_.push_back(false); port_is_config_enable_.push_back(false); - port_is_edge_triggered_.push_back(false); port_is_prog_.push_back(false); port_tri_state_model_names_.emplace_back(); port_tri_state_model_ids_.push_back(CircuitModelId::INVALID()); @@ -1500,15 +1494,6 @@ void CircuitLibrary::set_port_is_config_enable(const CircuitPortId& circuit_port return; } -/* Set the is_edge_triggered for a port of a circuit model */ -void CircuitLibrary::set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, - const bool& is_edge_triggered) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_edge_triggered_[circuit_port_id] = is_edge_triggered; - return; -} - /* Set the is_prog for a port of a circuit model */ void CircuitLibrary::set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog) { diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index f4b742a27..bd082f738 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -91,16 +91,15 @@ * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches - * 12. port_is_edge_triggered: specify if this port is triggerd by edges like the clock signal of a D-type flip-flop - * 13. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 14. port_tri_state_model_name: the name of circuit model linked to tri-state the port - * 15. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port - * 16. port_inv_model_names_: the name of inverter circuit model linked to the port - * 17. port_inv_model_ids_: the Id of inverter circuit model linked to the port - * 18. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port - * 19. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used - * 20. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used - * 21. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 13. port_tri_state_model_name: the name of circuit model linked to tri-state the port + * 14. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port + * 15. port_inv_model_names_: the name of inverter circuit model linked to the port + * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port + * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains * * ------ Delay information ------ * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge @@ -285,7 +284,6 @@ class CircuitLibrary { bool port_is_reset(const CircuitPortId& circuit_port_id) const; bool port_is_set(const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; - bool port_is_edge_triggered(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; std::vector port_lut_output_mask(const CircuitPortId& circuit_port_id) const; @@ -366,8 +364,6 @@ class CircuitLibrary { const bool& is_set); void set_port_is_config_enable(const CircuitPortId& circuit_port_id, const bool& is_config_enable); - void set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, - const bool& is_edge_triggered); void set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog); void set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, @@ -554,7 +550,6 @@ class CircuitLibrary { vtr::vector port_is_reset_; vtr::vector port_is_set_; vtr::vector port_is_config_enable_; - vtr::vector port_is_edge_triggered_; vtr::vector port_is_prog_; vtr::vector port_tri_state_model_names_; vtr::vector port_tri_state_model_ids_; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index 4136b0463..36e837814 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -564,9 +564,6 @@ void read_xml_circuit_port(pugi::xml_node& xml_port, /* Identify if the port is to enable programming for FPGAs, by default it is NOT */ circuit_lib.set_port_is_config_enable(port, get_attribute(xml_port, "is_config_enable", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); - /* Identify if the port is to triggered by edges, by default it is NOT */ - circuit_lib.set_port_is_edge_triggered(port, get_attribute(xml_port, "is_edge_triggered", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); - /* Find the name of circuit model that this port is linked to */ circuit_lib.set_port_tri_state_model_name(port, get_attribute(xml_port, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string()); diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp index 9165725e2..b141b0fe2 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -207,10 +207,6 @@ void write_xml_circuit_port(std::fstream& fp, write_xml_attribute(fp, "is_config_enable", "true"); } - if (true == circuit_lib.port_is_edge_triggered(port)) { - write_xml_attribute(fp, "is_edge_triggered", "true"); - } - /* Output the name of circuit model that this port is linked to */ if (!circuit_lib.port_tri_state_model_name(port).empty()) { write_xml_attribute(fp, "circuit_model_name", circuit_lib.port_tri_state_model_name(port).c_str()); From 94a1324f0527276546c3b2571b1a1b7700a473f7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 26 Sep 2020 14:31:57 -0600 Subject: [PATCH 113/114] [Documentation] Remove deprecated XML syntax --- docs/source/manual/arch_lang/circuit_library.rst | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 9e8466c09..59e5f055f 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -143,8 +143,7 @@ A circuit model may consist of a number of ports. The port list is mandatory in .. option:: + is_global="" is_set="" is_reset="" is_config_enable=""/> Define the attributes for a port of a circuit model. @@ -191,8 +190,6 @@ A circuit model may consist of a number of ports. The port list is mandatory in - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. - - ``is_edge_triggered="true|false"`` Specify if this port is edge sensitive, like the clock port of a D-type flip-flop. This attribute is used to create stimuli in testbenches when flip-flops are used as configurable memory in frame-based configuration protocol. - .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. .. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details. From 94047037c570b6a432fea8f363a5147df9bc918d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Sep 2020 14:33:14 -0600 Subject: [PATCH 114/114] [OpenFPGA Tool] Streamline codes in openfpga arch parser --- .../src/read_xml_circuit_library.cpp | 166 ++++-------------- .../src/read_xml_config_protocol.cpp | 19 +- .../src/read_xml_simulation_setting.cpp | 10 +- .../src/read_xml_technology_library.cpp | 20 +-- 4 files changed, 53 insertions(+), 162 deletions(-) diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index 36e837814..86b1de94e 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -26,52 +26,10 @@ *******************************************************************/ static e_circuit_model_type string_to_circuit_model_type(const std::string& type_string) { - if (std::string("chan_wire") == type_string) { - return CIRCUIT_MODEL_CHAN_WIRE; - } - - if (std::string("wire") == type_string) { - return CIRCUIT_MODEL_WIRE; - } - - if (std::string("mux") == type_string) { - return CIRCUIT_MODEL_MUX; - } - - if (std::string("lut") == type_string) { - return CIRCUIT_MODEL_LUT; - } - - if (std::string("ff") == type_string) { - return CIRCUIT_MODEL_FF; - } - - if (std::string("sram") == type_string) { - return CIRCUIT_MODEL_SRAM; - } - - if (std::string("hard_logic") == type_string) { - return CIRCUIT_MODEL_HARDLOGIC; - } - - if (std::string("ccff") == type_string) { - return CIRCUIT_MODEL_CCFF; - } - - if (std::string("iopad") == type_string) { - return CIRCUIT_MODEL_IOPAD; - } - - if (std::string("inv_buf") == type_string) { - return CIRCUIT_MODEL_INVBUF; - } - - if (std::string("pass_gate") == type_string) { - return CIRCUIT_MODEL_PASSGATE; - } - - if (std::string("gate") == type_string) { - return CIRCUIT_MODEL_GATE; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } /* Reach here, we have an invalid value, error out */ @@ -83,12 +41,10 @@ e_circuit_model_type string_to_circuit_model_type(const std::string& type_string *******************************************************************/ static e_circuit_model_design_tech string_to_design_tech_type(const std::string& type_string) { - if (std::string("cmos") == type_string) { - return CIRCUIT_MODEL_DESIGN_CMOS; - } - - if (std::string("rram") == type_string) { - return CIRCUIT_MODEL_DESIGN_RRAM; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_DESIGN_TECH_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES; @@ -99,12 +55,10 @@ e_circuit_model_design_tech string_to_design_tech_type(const std::string& type_s *******************************************************************/ static e_circuit_model_buffer_type string_to_buffer_type(const std::string& type_string) { - if (std::string("inverter") == type_string) { - return CIRCUIT_MODEL_BUF_INV; - } - - if (std::string("buffer") == type_string) { - return CIRCUIT_MODEL_BUF_BUF; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_BUF_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_BUFFER_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_BUF_TYPES; @@ -115,12 +69,10 @@ e_circuit_model_buffer_type string_to_buffer_type(const std::string& type_string *******************************************************************/ static e_circuit_model_pass_gate_logic_type string_to_passgate_type(const std::string& type_string) { - if (std::string("transmission_gate") == type_string) { - return CIRCUIT_MODEL_PASS_GATE_TRANSMISSION; - } - - if (std::string("pass_transistor") == type_string) { - return CIRCUIT_MODEL_PASS_GATE_TRANSISTOR; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_PASS_GATE_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_PASSGATE_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_PASS_GATE_TYPES; @@ -131,16 +83,10 @@ e_circuit_model_pass_gate_logic_type string_to_passgate_type(const std::string& *******************************************************************/ static e_circuit_model_structure string_to_mux_structure_type(const std::string& type_string) { - if (std::string("tree") == type_string) { - return CIRCUIT_MODEL_STRUCTURE_TREE; - } - - if (std::string("one_level") == type_string) { - return CIRCUIT_MODEL_STRUCTURE_ONELEVEL; - } - - if (std::string("multi_level") == type_string) { - return CIRCUIT_MODEL_STRUCTURE_MULTILEVEL; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_STRUCTURE_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_STRUCTURE_TYPES; @@ -151,16 +97,10 @@ e_circuit_model_structure string_to_mux_structure_type(const std::string& type_s *******************************************************************/ static e_circuit_model_gate_type string_to_gate_type(const std::string& type_string) { - if (std::string("AND") == type_string) { - return CIRCUIT_MODEL_GATE_AND; - } - - if (std::string("OR") == type_string) { - return CIRCUIT_MODEL_GATE_OR; - } - - if (std::string("MUX2") == type_string) { - return CIRCUIT_MODEL_GATE_MUX2; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_GATE_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_GATE_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_GATE_TYPES; @@ -171,40 +111,10 @@ e_circuit_model_gate_type string_to_gate_type(const std::string& type_string) { *******************************************************************/ static e_circuit_model_port_type string_to_circuit_model_port_type(const std::string& type_string) { - if (std::string("input") == type_string) { - return CIRCUIT_MODEL_PORT_INPUT; - } - - if (std::string("output") == type_string) { - return CIRCUIT_MODEL_PORT_OUTPUT; - } - - if (std::string("clock") == type_string) { - return CIRCUIT_MODEL_PORT_CLOCK; - } - - if (std::string("sram") == type_string) { - return CIRCUIT_MODEL_PORT_SRAM; - } - - if (std::string("bl") == type_string) { - return CIRCUIT_MODEL_PORT_BL; - } - - if (std::string("wl") == type_string) { - return CIRCUIT_MODEL_PORT_WL; - } - - if (std::string("blb") == type_string) { - return CIRCUIT_MODEL_PORT_BLB; - } - - if (std::string("wlb") == type_string) { - return CIRCUIT_MODEL_PORT_WLB; - } - - if (std::string("inout") == type_string) { - return CIRCUIT_MODEL_PORT_INOUT; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_PORT_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_PORT_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_PORT_TYPES; @@ -215,12 +125,10 @@ e_circuit_model_port_type string_to_circuit_model_port_type(const std::string& t *******************************************************************/ static e_wire_model_type string_to_wire_model_type(const std::string& type_string) { - if (std::string("pi") == type_string) { - return WIRE_MODEL_PI; - } - - if (std::string("t") == type_string) { - return WIRE_MODEL_T; + for (size_t itype = 0; itype < NUM_WIRE_MODEL_TYPES; ++itype) { + if (std::string(WIRE_MODEL_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_WIRE_MODEL_TYPES; @@ -231,12 +139,10 @@ e_wire_model_type string_to_wire_model_type(const std::string& type_string) { *******************************************************************/ static e_circuit_model_delay_type string_to_circuit_model_delay_type(const std::string& type_string) { - if (std::string("rise") == type_string) { - return CIRCUIT_MODEL_DELAY_RISE; - } - - if (std::string("fall") == type_string) { - return CIRCUIT_MODEL_DELAY_FALL; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_DELAY_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_DELAY_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_DELAY_TYPES; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp b/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp index 2daedbd39..04833d33a 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp @@ -23,20 +23,11 @@ *******************************************************************/ static e_config_protocol_type string_to_config_protocol_type(const std::string& type_string) { - if (std::string("standalone") == type_string) { - return CONFIG_MEM_STANDALONE; - } - - if (std::string("scan_chain") == type_string) { - return CONFIG_MEM_SCAN_CHAIN; - } - - if (std::string("memory_bank") == type_string) { - return CONFIG_MEM_MEMORY_BANK; - } - - if (std::string("frame_based") == type_string) { - return CONFIG_MEM_FRAME_BASED; + + for (size_t itype = 0; itype < NUM_CONFIG_PROTOCOL_TYPES; ++itype) { + if (std::string(CONFIG_PROTOCOL_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CONFIG_PROTOCOL_TYPES; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp b/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp index 6007a14bf..cf8bc11b9 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp @@ -23,12 +23,10 @@ *******************************************************************/ static e_sim_accuracy_type string_to_sim_accuracy_type(const std::string& type_string) { - if (std::string("frac") == type_string) { - return SIM_ACCURACY_FRAC; - } - - if (std::string("abs") == type_string) { - return SIM_ACCURACY_ABS; + for (size_t itype = 0; itype < NUM_SIM_ACCURACY_TYPES; ++itype) { + if (std::string(SIM_ACCURACY_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_SIM_ACCURACY_TYPES; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp index e2871a638..9c5c2b132 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp @@ -23,12 +23,10 @@ *******************************************************************/ static e_tech_lib_model_type string_to_device_model_type(const std::string& type_string) { - if (std::string("transistor") == type_string) { - return TECH_LIB_MODEL_TRANSISTOR; - } - - if (std::string("rram") == type_string) { - return TECH_LIB_MODEL_RRAM; + for (size_t itype = 0; itype < NUM_TECH_LIB_MODEL_TYPES; ++itype) { + if (std::string(TECH_LIB_MODEL_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_TECH_LIB_MODEL_TYPES; @@ -39,12 +37,10 @@ e_tech_lib_model_type string_to_device_model_type(const std::string& type_string *******************************************************************/ static e_tech_lib_type string_to_tech_lib_type(const std::string& type_string) { - if (std::string("industry") == type_string) { - return TECH_LIB_INDUSTRY; - } - - if (std::string("academia") == type_string) { - return TECH_LIB_ACADEMIA; + for (size_t itype = 0; itype < NUM_TECH_LIB_TYPES; ++itype) { + if (std::string(TECH_LIB_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_TECH_LIB_TYPES;