From e8f9deeeaf0730ffb964940e76acff3161ec9697 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 16:12:20 -0700 Subject: [PATCH] [core] fixed a critical bug on computing pin index for subtile in clock taps --- openfpga/src/utils/openfpga_physical_tile_utils.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 1cce2eeee..ee3b3b5db 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -205,8 +205,9 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, /* Reach here, we get the port we want, return the accumulated index */ size_t accumulated_pin_idx = sub_tile_port.absolute_first_pin_index + - sub_tile.num_phy_pins * (tile_info.get_lsb() - sub_tile.capacity.low) + + (sub_tile.num_phy_pins / sub_tile.capacity.total()) * (tile_info.get_lsb() - sub_tile.capacity.low) + pin_info.get_lsb(); + VTR_LOG("Pin index: %lu\n", accumulated_pin_idx); return accumulated_pin_idx; } }